From patchwork Mon Jul 24 14:52:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jonas Karlman X-Patchwork-Id: 705854 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D58AC001DF for ; Mon, 24 Jul 2023 14:54:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229670AbjGXOyy (ORCPT ); Mon, 24 Jul 2023 10:54:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34608 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231787AbjGXOw5 (ORCPT ); Mon, 24 Jul 2023 10:52:57 -0400 Received: from s.wrqvtbkv.outbound-mail.sendgrid.net (s.wrqvtbkv.outbound-mail.sendgrid.net [149.72.123.24]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 59E7F10D9 for ; Mon, 24 Jul 2023 07:52:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=from:subject:mime-version:to:cc:content-transfer-encoding: content-type:cc:content-type:from:subject:to; s=s1; bh=WcPMS8VJ8wZGKcidpFy/HqVz+nWN87bUiNsDE1gwuRs=; b=jmjEZFV8G9PUpRXSheQcL4plISa3RZzSmTOYznoXHVGXvcMsEoC4Nop7o+OWT+M1NHHG qz3Wp+H26cYeIadd/VX8l+mX2z2ABk7ZLqlmsu7fZlhlc/Mgx26C4piKBhgFYm5+Z5d/ds 3NLFVWffSas7TqKKdLDV5Q0IbYYpNXfwPMXHbqPGdkN7JLgPoW/6w5LZg0L1ptxRi8CAga S8oNOhXMRdcBjGocoAQTDja6qLU3zXYsyisBt0Mhf0usuM879s6tu/aGRk+isP8frKObvj obIDbfudqTnJGJPeCkW0mGL/FsjjH1xi+qfem5jLW6AMqjfDZOOk+DBwWV+ulonw== Received: by filterdrecv-8684c58db7-nfltn with SMTP id filterdrecv-8684c58db7-nfltn-1-64BE901F-40 2023-07-24 14:52:16.172047943 +0000 UTC m=+6448424.450220586 Received: from bionic.localdomain (unknown) by geopod-ismtpd-8 (SG) with ESMTP id MTXJzVVRT-imukorVRJulQ Mon, 24 Jul 2023 14:52:15.522 +0000 (UTC) From: Jonas Karlman Subject: [PATCH] arm64: dts: rockchip: Fix regulators and enable SATA on Radxa E25 Date: Mon, 24 Jul 2023 14:52:16 +0000 (UTC) Message-ID: <20230724145213.3833099-1-jonas@kwiboo.se> X-Mailer: git-send-email 2.41.0 MIME-Version: 1.0 X-SG-EID: TdbjyGynYnRZWhH+7lKUQJL+ZxmxpowvO2O9SQF5CwCVrYgcwUXgU5DKUU3QxAfZekEeQsTe+RrMu3cja6a0hxdxYYdTXqyX82wfIRa/GfuQUGNsOvlZGB3QHxCYxiOjHZP07t/uVIOpTg7CNYgQHfx/yVh5KOiYjmJ/l+SMjKTYrHtAISoQvqpeJHhR+R8NSsw1P3Y9y9+OqBzQhwtARsWV/tu5E+6diQv0m8TixXNgC01YZlOjhrEvCI+zi3jO To: Heiko Stuebner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chukun Pan Cc: FUKAUMI Naoki , Jonas Karlman , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org X-Entity-ID: P7KYpSJvGCELWjBME/J5tg== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Despite its name, the regulator vcc3v3_pcie30x1 has nothing to do with pcie30x1. Instead, it supply power to VBAT1-5 on the M.2 KEY B port as seen on page 8 of the schematic [1]. pcie30x1 is used for the mini PCIe slot, and as seen on page 9 the vcc3v3_minipcie regulator is instead related to pcie30x1. The M.2 KEY B port can be used for WWAN USB2 modules or SATA drives. Use correct regulator vcc3v3_minipcie for pcie30x1 and enable sata1 node to fix use of SATA drives on the M.2 slot. [1] https://dl.radxa.com/cm3p/e25/radxa-e25-v1.4-sch.pdf Fixes: 2bf2f4d9f673 ("arm64: dts: rockchip: Add Radxa CM3I E25") Signed-off-by: Jonas Karlman --- .../boot/dts/rockchip/rk3568-radxa-e25.dts | 24 ++++++++++++------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts index 63c4bd873188..72ad74c38a2b 100644 --- a/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts +++ b/arch/arm64/boot/dts/rockchip/rk3568-radxa-e25.dts @@ -47,6 +47,9 @@ vbus_typec: vbus-typec-regulator { vin-supply = <&vcc5v0_sys>; }; + /* actually fed by vcc5v0_sys, dependent + * on pi6c clock generator + */ vcc3v3_minipcie: vcc3v3-minipcie-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -54,9 +57,9 @@ vcc3v3_minipcie: vcc3v3-minipcie-regulator { pinctrl-names = "default"; pinctrl-0 = <&minipcie_enable_h>; regulator-name = "vcc3v3_minipcie"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - vin-supply = <&vcc5v0_sys>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + vin-supply = <&vcc3v3_pi6c_05>; }; vcc3v3_ngff: vcc3v3-ngff-regulator { @@ -71,9 +74,6 @@ vcc3v3_ngff: vcc3v3-ngff-regulator { vin-supply = <&vcc5v0_sys>; }; - /* actually fed by vcc5v0_sys, dependent - * on pi6c clock generator - */ vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator { compatible = "regulator-fixed"; enable-active-high; @@ -83,7 +83,7 @@ vcc3v3_pcie30x1: vcc3v3-pcie30x1-regulator { regulator-name = "vcc3v3_pcie30x1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; - vin-supply = <&vcc3v3_pi6c_05>; + vin-supply = <&vcc5v0_sys>; }; vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { @@ -99,6 +99,10 @@ vcc3v3_pi6c_05: vcc3v3-pi6c-05-regulator { }; }; +&combphy1 { + phy-supply = <&vcc3v3_pcie30x1>; +}; + &pcie2x1 { pinctrl-names = "default"; pinctrl-0 = <&pcie20_reset_h>; @@ -117,7 +121,7 @@ &pcie3x1 { pinctrl-names = "default"; pinctrl-0 = <&pcie30x1m0_pins>; reset-gpios = <&gpio0 RK_PC3 GPIO_ACTIVE_HIGH>; - vpcie3v3-supply = <&vcc3v3_pcie30x1>; + vpcie3v3-supply = <&vcc3v3_minipcie>; status = "okay"; }; @@ -178,6 +182,10 @@ &pwm12 { status = "okay"; }; +&sata1 { + status = "okay"; +}; + &sdmmc0 { bus-width = <4>; cap-sd-highspeed;