From patchwork Thu Jul 20 17:36:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 704901 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E9AA3EB64DA for ; Thu, 20 Jul 2023 17:36:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231807AbjGTRgx (ORCPT ); Thu, 20 Jul 2023 13:36:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36396 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231205AbjGTRgu (ORCPT ); Thu, 20 Jul 2023 13:36:50 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A501E53; Thu, 20 Jul 2023 10:36:48 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-215-153.ewe-ip-backbone.de [91.248.215.153]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id E3555660708D; Thu, 20 Jul 2023 18:36:46 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1689874607; bh=zUejJZFS4thyPHrNS+i30eUloFjH4qgrqPO4Coui+ks=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GUqkEaoEh8FvbKRvUose4pIR1gzp03yuE2XNbw0FPHANKQq7W2zmaVT2z3rmbMwB8 BpsmmEM3XOf/Kj1f7+NBiiN7T/CbbfQyVH9z5QvJjgmfQzjZDdHiXJohRxdkqGDeYk JnsfAI7TZWwQPrdN1YeLhz+uwGwHppMTl6XZtyi4IFTghBRtIYuke6C6hmsbjqn5rk fJjQAMj7MD8xhqJM1RvPm+mJ/PKbr0gVzzB5P4CVrPW0+7spslXLbb4NKjB8DATaWN fsFaQjokiDWab5J78B0JbN/WbAoQuXPX3+s7n0xvVM1cG0xvX/l5DpBR49w/jm90Xr d+3hFH6ARVMgA== Received: by jupiter.universe (Postfix, from userid 1000) id E5A01480E64; Thu, 20 Jul 2023 19:36:44 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner , Greg Kroah-Hartman Cc: Thinh Nguyen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-rockchip@lists.infradead.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v2 1/3] dt-bindings: usb: add rk3588 compatible to rockchip,dwc3 Date: Thu, 20 Jul 2023 19:36:41 +0200 Message-Id: <20230720173643.69553-2-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230720173643.69553-1-sebastian.reichel@collabora.com> References: <20230720173643.69553-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org RK3588 has three DWC3 controllers. Two of them are fully functional in host, device and OTG mode including USB2 support. They are connected to dedicated PHYs, that also support USB-C's DisplayPort alternate mode. The third controller is connected to one of the combphy's shared with PCIe and SATA. It can only be used in host mode and does not support USB2. Compared to the other controllers this one needs some extra clocks. Signed-off-by: Sebastian Reichel --- .../devicetree/bindings/usb/rockchip,dwc3.yaml | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml index 291844c8f3e1..cbc3e55e05e1 100644 --- a/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml +++ b/Documentation/devicetree/bindings/usb/rockchip,dwc3.yaml @@ -30,6 +30,7 @@ select: enum: - rockchip,rk3328-dwc3 - rockchip,rk3568-dwc3 + - rockchip,rk3588-dwc3 required: - compatible @@ -39,6 +40,7 @@ properties: - enum: - rockchip,rk3328-dwc3 - rockchip,rk3568-dwc3 + - rockchip,rk3588-dwc3 - const: snps,dwc3 reg: @@ -58,7 +60,9 @@ properties: Master/Core clock, must to be >= 62.5 MHz for SS operation and >= 30MHz for HS operation - description: - Controller grf clock + Controller grf clock OR UTMI clock + - description: + PIPE clock clock-names: minItems: 3 @@ -66,7 +70,10 @@ properties: - const: ref_clk - const: suspend_clk - const: bus_clk - - const: grf_clk + - enum: + - grf_clk + - utmi + - const: pipe power-domains: maxItems: 1 From patchwork Thu Jul 20 17:36:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 705597 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 91A8FC04FDF for ; Thu, 20 Jul 2023 17:36:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231669AbjGTRgw (ORCPT ); Thu, 20 Jul 2023 13:36:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36394 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231136AbjGTRgu (ORCPT ); Thu, 20 Jul 2023 13:36:50 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B1241BB; Thu, 20 Jul 2023 10:36:48 -0700 (PDT) Received: from jupiter.universe (dyndsl-091-248-215-153.ewe-ip-backbone.de [91.248.215.153]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: sre) by madras.collabora.co.uk (Postfix) with ESMTPSA id DC7C2660708B; Thu, 20 Jul 2023 18:36:46 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1689874607; bh=x+aSJIr60rE8FgDa2xnKptMGufUUikneuDiI3dxwTPA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=n4AMs+zAwaq0pUK8X1771cErKK7Qn8Pa9yTCbLyI0ahf6aUsHLwUrPLhfOWk59Ypq Q7jkTCqIBDbKloXHLAvwxoWWBuUB9JFhH7/zA6hArPArEYUrIRf6tizPUzIutUvts3 jSoKyDs5y47jDLb2BtEwGez4Hq6G4uzu/889EX1KJ2XUV63ngj/3XImThTd2Nn3k6J G/FYbqL880cbWlUJzH100qujbo+vSVNRZfNI1HPgYu22ya3hb6hKYz6p7JurCGTVVw CCER8yzSjeifkdKyMGqgFvQ0rUAYbyLH/azEyx3MNnTu6NH78JBmhEfj7zmx97KG3w s+i3j0h6psbnA== Received: by jupiter.universe (Postfix, from userid 1000) id E76EA480E65; Thu, 20 Jul 2023 19:36:44 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner , Greg Kroah-Hartman Cc: Thinh Nguyen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-rockchip@lists.infradead.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v2 2/3] usb: dwc3: add optional PHY interface clocks Date: Thu, 20 Jul 2023 19:36:42 +0200 Message-Id: <20230720173643.69553-3-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230720173643.69553-1-sebastian.reichel@collabora.com> References: <20230720173643.69553-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org On Rockchip RK3588 one of the DWC3 cores is integrated weirdly and requires two extra clocks to be enabled. Without these extra clocks hot-plugging USB devices is broken. Signed-off-by: Sebastian Reichel --- drivers/usb/dwc3/core.c | 26 ++++++++++++++++++++++++++ drivers/usb/dwc3/core.h | 4 ++++ 2 files changed, 30 insertions(+) diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index f6689b731718..0618fcc4d0af 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -817,8 +817,20 @@ static int dwc3_clk_enable(struct dwc3 *dwc) if (ret) goto disable_ref_clk; + ret = clk_prepare_enable(dwc->utmi_clk); + if (ret) + goto disable_susp_clk; + + ret = clk_prepare_enable(dwc->pipe_clk); + if (ret) + goto disable_utmi_clk; + return 0; +disable_utmi_clk: + clk_disable_unprepare(dwc->utmi_clk); +disable_susp_clk: + clk_disable_unprepare(dwc->susp_clk); disable_ref_clk: clk_disable_unprepare(dwc->ref_clk); disable_bus_clk: @@ -828,6 +840,8 @@ static int dwc3_clk_enable(struct dwc3 *dwc) static void dwc3_clk_disable(struct dwc3 *dwc) { + clk_disable_unprepare(dwc->pipe_clk); + clk_disable_unprepare(dwc->utmi_clk); clk_disable_unprepare(dwc->susp_clk); clk_disable_unprepare(dwc->ref_clk); clk_disable_unprepare(dwc->bus_clk); @@ -1764,6 +1778,18 @@ static int dwc3_get_clocks(struct dwc3 *dwc) } } + dwc->utmi_clk = devm_clk_get_optional(dev, "utmi"); + if (IS_ERR(dwc->utmi_clk)) { + return dev_err_probe(dev, PTR_ERR(dwc->utmi_clk), + "could not get utmi clock\n"); + } + + dwc->pipe_clk = devm_clk_get_optional(dev, "pipe"); + if (IS_ERR(dwc->pipe_clk)) { + return dev_err_probe(dev, PTR_ERR(dwc->pipe_clk), + "could not get pipe clock\n"); + } + return 0; } diff --git a/drivers/usb/dwc3/core.h b/drivers/usb/dwc3/core.h index 8b1295e4dcdd..fa49a87025cf 100644 --- a/drivers/usb/dwc3/core.h +++ b/drivers/usb/dwc3/core.h @@ -994,6 +994,8 @@ struct dwc3_scratchpad_array { * @bus_clk: clock for accessing the registers * @ref_clk: reference clock * @susp_clk: clock used when the SS phy is in low power (S3) state + * @utmi_clk: clock used for USB2 PHY communication + * @pipe_clk: clock used for USB3 PHY communication * @reset: reset control * @regs: base address for our registers * @regs_size: address space size @@ -1159,6 +1161,8 @@ struct dwc3 { struct clk *bus_clk; struct clk *ref_clk; struct clk *susp_clk; + struct clk *utmi_clk; + struct clk *pipe_clk; struct reset_control *reset; From patchwork Thu Jul 20 17:36:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sebastian Reichel X-Patchwork-Id: 705598 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C8C8C0015E for ; Thu, 20 Jul 2023 17:36:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231407AbjGTRgu (ORCPT ); Thu, 20 Jul 2023 13:36:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36390 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230027AbjGTRgt (ORCPT ); Thu, 20 Jul 2023 13:36:49 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 82B50CC; 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Thu, 20 Jul 2023 19:36:44 +0200 (CEST) From: Sebastian Reichel To: Heiko Stuebner , Greg Kroah-Hartman Cc: Thinh Nguyen , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-rockchip@lists.infradead.org, linux-usb@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Sebastian Reichel , kernel@collabora.com Subject: [PATCH v2 3/3] arm64: dts: rockchip: rk3588s: Add USB3 host controller Date: Thu, 20 Jul 2023 19:36:43 +0200 Message-Id: <20230720173643.69553-4-sebastian.reichel@collabora.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230720173643.69553-1-sebastian.reichel@collabora.com> References: <20230720173643.69553-1-sebastian.reichel@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org RK3588 has three USB3 controllers. This adds the host-only controller, which is using the naneng-combphy shared with PCIe and SATA. The other two are dual-role and using a different PHY that is not yet supported upstream. Signed-off-by: Sebastian Reichel --- arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi index b9b509257aaa..5cda58ea52e2 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588s.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588s.dtsi @@ -443,6 +443,27 @@ usb_host1_ohci: usb@fc8c0000 { status = "disabled"; }; + usb_host2_xhci: usb@fcd00000 { + compatible = "rockchip,rk3588-dwc3", "snps,dwc3"; + reg = <0x0 0xfcd00000 0x0 0x400000>; + interrupts = ; + clocks = <&cru REF_CLK_USB3OTG2>, <&cru SUSPEND_CLK_USB3OTG2>, + <&cru ACLK_USB3OTG2>, <&cru CLK_UTMI_OTG2>, + <&cru CLK_PIPEPHY2_PIPE_U3_G>; + clock-names = "ref_clk", "suspend_clk", "bus_clk", "utmi", "pipe"; + dr_mode = "host"; + phys = <&combphy2_psu PHY_TYPE_USB3>; + phy-names = "usb3-phy"; + phy_type = "utmi_wide"; + resets = <&cru SRST_A_USB3OTG2>; + snps,dis_enblslpm_quirk; + snps,dis-u2-freeclk-exists-quirk; + snps,dis-del-phy-power-chg-quirk; + snps,dis-tx-ipgap-linecheck-quirk; + snps,dis_rxdet_inp3_quirk; + status = "disabled"; + }; + sys_grf: syscon@fd58c000 { compatible = "rockchip,rk3588-sys-grf", "syscon"; reg = <0x0 0xfd58c000 0x0 0x1000>;