From patchwork Thu Jul 20 18:38:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 704750 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A5E66EB64DD for ; Thu, 20 Jul 2023 18:39:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232120AbjGTSjQ (ORCPT ); Thu, 20 Jul 2023 14:39:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41086 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232119AbjGTSjP (ORCPT ); Thu, 20 Jul 2023 14:39:15 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9B8242D50; Thu, 20 Jul 2023 11:39:11 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 38C0561BF4; Thu, 20 Jul 2023 18:39:11 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D1B13C433CC; Thu, 20 Jul 2023 18:39:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689878350; bh=cJdsEMWu4Vw4UDfbXEhrIi77kKUyxBMQ+oaGSCuCK3E=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=YZkcJhFTmw1HPNCUbq/w1IfKEsEptFEJD1W2JPuwWxGr7tFO9SQCTfZMaEDtHuq8l e4zUx/zO+3w1TccNL5Y+8tenapCYOzqcq6IKH+pa2I0q5vpqoCTRcN3Rlf7hqUl2Lb Fcs6Fw1RgUL1heKymdHm3vK1/IkTiXJkJgqFjQR1hMijVuVwprGZ02lV7O0s9EHviS 1tJu7D1NntfhigBfbxuXejuLWgegfJDnIpnnSS+OGTI+rvKuIe1OrOmwg0BaZcwPVz SDFuCMKGoQa75D8SWoNqk6tzkMO6XEa1p6cPZjyMWqcGLUL/KwnISz/HWfVhEjTzW+ m5LAliREjPL+Q== From: Mark Brown Date: Thu, 20 Jul 2023 19:38:58 +0100 Subject: [PATCH v2 1/3] arm64/fpsimd: Ensure SME storage is allocated after SVE VL changes MIME-Version: 1.0 Message-Id: <20230720-arm64-fix-sve-sme-vl-change-v2-1-8eea06b82d57@kernel.org> References: <20230720-arm64-fix-sve-sme-vl-change-v2-0-8eea06b82d57@kernel.org> In-Reply-To: <20230720-arm64-fix-sve-sme-vl-change-v2-0-8eea06b82d57@kernel.org> To: Catalin Marinas , Will Deacon , Shuah Khan Cc: David Spickett , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown , stable@vger.kernel.org X-Mailer: b4 0.13-dev-099c9 X-Developer-Signature: v=1; a=openpgp-sha256; l=3126; i=broonie@kernel.org; h=from:subject:message-id; bh=cJdsEMWu4Vw4UDfbXEhrIi77kKUyxBMQ+oaGSCuCK3E=; b=owEBbQGS/pANAwAKASTWi3JdVIfQAcsmYgBkuX9H8a1ZEjatBHUy3+YyrBKN9Ns5zmE97HZq59se mG1hfjuJATMEAAEKAB0WIQSt5miqZ1cYtZ/in+ok1otyXVSH0AUCZLl/RwAKCRAk1otyXVSH0BFLB/ 48MuNQeHejkUjg+G0TolCglEKFMd2HtiKuI+aYs/va+ARg5B5tGns4k2GfNlWF3F3MncLnUHAh6pi0 uoZE8qR/HEHBQHh4ls8cAgx+zwm0BKVdRn85HEjCBA64N9Acm6AxpYS7OqZSq5gf736VUDI3tv0kTW hGf7qZpF95H28Wey0JMlDoHhmIgbniieL0gyklP4t5Zdvo0YwF79VKAXd1Ck/CB6G4kQLhcWvN94tU s9H+8v0mJHQjSzZntWYNYoFykVM1cQjTzmnXhyKy6USVDT1HWfVoPq6b6IhcfgTCMLvL6GxSCurZAz 3ee2zR926o69yQ3TBwXC2+a2sbrtUw X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org When we reconfigure the SVE vector length we discard the backing storage for the SVE vectors and then reallocate on next SVE use, leaving the SME specific state alone. This means that we do not enable SME traps if they were already disabled. That means that userspace code can enter streaming mode without trapping, putting the task in a state where if we try to save the state of the task we will fault. Since the ABI does not specify that changing the SVE vector length disturbs SME state, and since SVE code may not be aware of SME code in the process, we shouldn't simply discard any ZA state. Instead immediately reallocate the storage for SVE, and disable SME if we change the SVE vector length while there is no SME state active. Disabling SME traps on SVE vector length changes would make the overall code more complex since we would have a state where we have valid SME state stored but might get a SME trap. Fixes: 9e4ab6c89109 ("arm64/sme: Implement vector length configuration prctl()s") Reported-by: David Spickett Signed-off-by: Mark Brown Cc: stable@vger.kernel.org --- arch/arm64/kernel/fpsimd.c | 33 +++++++++++++++++++++++++-------- 1 file changed, 25 insertions(+), 8 deletions(-) diff --git a/arch/arm64/kernel/fpsimd.c b/arch/arm64/kernel/fpsimd.c index 7a1aeb95d7c3..89d54a5242d1 100644 --- a/arch/arm64/kernel/fpsimd.c +++ b/arch/arm64/kernel/fpsimd.c @@ -847,6 +847,8 @@ void sve_sync_from_fpsimd_zeropad(struct task_struct *task) int vec_set_vector_length(struct task_struct *task, enum vec_type type, unsigned long vl, unsigned long flags) { + bool free_sme = false; + if (flags & ~(unsigned long)(PR_SVE_VL_INHERIT | PR_SVE_SET_VL_ONEXEC)) return -EINVAL; @@ -897,21 +899,36 @@ int vec_set_vector_length(struct task_struct *task, enum vec_type type, task->thread.fp_type = FP_STATE_FPSIMD; } - if (system_supports_sme() && type == ARM64_VEC_SME) { - task->thread.svcr &= ~(SVCR_SM_MASK | - SVCR_ZA_MASK); - clear_thread_flag(TIF_SME); + if (system_supports_sme()) { + if (type == ARM64_VEC_SME || + !(task->thread.svcr & (SVCR_SM_MASK | SVCR_ZA_MASK))) { + /* + * We are changing the SME VL or weren't using + * SME anyway, discard the state and force a + * reallocation. + */ + task->thread.svcr &= ~(SVCR_SM_MASK | + SVCR_ZA_MASK); + clear_thread_flag(TIF_SME); + free_sme = true; + } } if (task == current) put_cpu_fpsimd_context(); /* - * Force reallocation of task SVE and SME state to the correct - * size on next use: + * Free the changed states if they are not in use, SME will be + * reallocated to the correct size on next use and we just + * allocate SVE now in case it is needed for use in streaming + * mode. */ - sve_free(task); - if (system_supports_sme() && type == ARM64_VEC_SME) + if (system_supports_sve()) { + sve_free(task); + sve_alloc(task, true); + } + + if (free_sme) sme_free(task); task_set_vl(task, type, vl); From patchwork Thu Jul 20 18:39:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mark Brown X-Patchwork-Id: 704749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4391EB64DD for ; Thu, 20 Jul 2023 18:39:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232145AbjGTSjZ (ORCPT ); Thu, 20 Jul 2023 14:39:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41272 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232141AbjGTSjY (ORCPT ); Thu, 20 Jul 2023 14:39:24 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 27C90270C; Thu, 20 Jul 2023 11:39:18 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B7EC761BFD; Thu, 20 Jul 2023 18:39:17 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id D507EC433C7; Thu, 20 Jul 2023 18:39:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689878357; bh=rXmOaMmqlk7QrELiC/kSDYYNiucDsBT8D5q7ohFdQ7s=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=mtgFWNoVWqppKfmmwXxHY8o8mfruxBcpLKPaSxviOeFSB2G6+jMlgOJ78/GJK3zyM YQivuehx4s4SjWWsN4xM6sAZEmyXkgNLlOCVKMv5/xVfMtIakGE6/QZZ2mrU4UynjF tKKo//JJKRRtRb7kfd4cL551+M2efF1R39kVXMKFbpLfzwSMUw/OP4XcFSU9W8/nNo vAOm8V2nd41dZcex48k+lsUx8u9tcNB+lr5v0KU8du4AY9lF1lJ4lK+1YMQIian7P4 6MW26EsuCRI0e8fp0Wt5lWv/DJp16stqfeaB6fGqRnqZHFrOpparJUO+S4O++RMeRR mQmFpyuK9SXcQ== From: Mark Brown Date: Thu, 20 Jul 2023 19:39:00 +0100 Subject: [PATCH v2 3/3] kselftest/arm64: Validate that changing one VL type does not affect another MIME-Version: 1.0 Message-Id: <20230720-arm64-fix-sve-sme-vl-change-v2-3-8eea06b82d57@kernel.org> References: <20230720-arm64-fix-sve-sme-vl-change-v2-0-8eea06b82d57@kernel.org> In-Reply-To: <20230720-arm64-fix-sve-sme-vl-change-v2-0-8eea06b82d57@kernel.org> To: Catalin Marinas , Will Deacon , Shuah Khan Cc: David Spickett , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org, Mark Brown X-Mailer: b4 0.13-dev-099c9 X-Developer-Signature: v=1; a=openpgp-sha256; l=1868; i=broonie@kernel.org; h=from:subject:message-id; bh=rXmOaMmqlk7QrELiC/kSDYYNiucDsBT8D5q7ohFdQ7s=; b=owGbwMvMwMWocq27KDak/QLjabUkhpSd9R4iIrrWIkXKwQIKwffTPk6wM8nqKk9d36291sEiQZGh RbuT0ZiFgZGLQVZMkWXts4xV6eESW+c/mv8KZhArE8gUBi5OAZjItzvs/wu9qy0kFdUf+G5IsXo2/7 hA/Zn8hGUznl1ZPTH9wTmOLVdtiw/kbM9N97+d5+DiXm8a6/TobS7388Be7ldpHnN0dyVNim351vDA WqKm+F/G2X3MsWyJxz9HX5zkW7pn0i03lxcy880MNniqfGGxDs7qibDhvLnvuv5tJVnG6sSsN05Tvq fJcabuT4uY0G9hfKT9xgSn74s2X/tdqdapw/J7eYjvi3vGwuY62bc1ZQVvepYWpLX32+zYvbr9KacP u8gNfevc8sqUee8MqoKOGG6Yaxr3xlZnayjTMyMdnqYVRdZH+jQbNXtN+BS4xPXm75nPVmG++OfPu4 KnZWZU9m3ZG8tzRNjlQ8wdDi4A X-Developer-Key: i=broonie@kernel.org; a=openpgp; fpr=3F2568AAC26998F9E813A1C5C3F436CA30F5D8EB Precedence: bulk List-ID: X-Mailing-List: linux-kselftest@vger.kernel.org On a system with both SVE and SME when we change one of the VLs this should not result in a change in the other VL. Add a check that this is in fact the case to vec-syscfg. Signed-off-by: Mark Brown --- tools/testing/selftests/arm64/fp/vec-syscfg.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/tools/testing/selftests/arm64/fp/vec-syscfg.c b/tools/testing/selftests/arm64/fp/vec-syscfg.c index 58ea4bde5be7..5f648b97a06f 100644 --- a/tools/testing/selftests/arm64/fp/vec-syscfg.c +++ b/tools/testing/selftests/arm64/fp/vec-syscfg.c @@ -554,7 +554,8 @@ static void prctl_set_onexec(struct vec_data *data) /* For each VQ verify that setting via prctl() does the right thing */ static void prctl_set_all_vqs(struct vec_data *data) { - int ret, vq, vl, new_vl; + int ret, vq, vl, new_vl, i; + int orig_vls[ARRAY_SIZE(vec_data)]; int errors = 0; if (!data->min_vl || !data->max_vl) { @@ -563,6 +564,9 @@ static void prctl_set_all_vqs(struct vec_data *data) return; } + for (i = 0; i < ARRAY_SIZE(vec_data); i++) + orig_vls[i] = vec_data[i].rdvl(); + for (vq = SVE_VQ_MIN; vq <= SVE_VQ_MAX; vq++) { vl = sve_vl_from_vq(vq); @@ -585,6 +589,22 @@ static void prctl_set_all_vqs(struct vec_data *data) errors++; } + /* Did any other VLs change? */ + for (i = 0; i < ARRAY_SIZE(vec_data); i++) { + if (&vec_data[i] == data) + continue; + + if (!(getauxval(vec_data[i].hwcap_type) & vec_data[i].hwcap)) + continue; + + if (vec_data[i].rdvl() != orig_vls[i]) { + ksft_print_msg("%s VL changed from %d to %d\n", + vec_data[i].name, orig_vls[i], + vec_data[i].rdvl()); + errors++; + } + } + /* Was that the VL we asked for? */ if (new_vl == vl) continue;