From patchwork Mon Jul 17 06:54:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 704140 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0BC82C001B0 for ; Mon, 17 Jul 2023 06:55:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229953AbjGQGzN (ORCPT ); Mon, 17 Jul 2023 02:55:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46988 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229940AbjGQGzM (ORCPT ); Mon, 17 Jul 2023 02:55:12 -0400 Received: from mail-pf1-x431.google.com (mail-pf1-x431.google.com [IPv6:2607:f8b0:4864:20::431]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3220FE41 for ; Sun, 16 Jul 2023 23:55:11 -0700 (PDT) Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-66767d628e2so2566166b3a.2 for ; Sun, 16 Jul 2023 23:55:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689576910; x=1692168910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EIQbVzJDtQSLAjOmeG/MuTeyAG4mQGjdI8C010Z2eIw=; b=UFMVPuRT1vwBT6WcyU1rl+qgHXKkfojP83VPshcp2cwXes6ul+kRV05GZKAUFec+4h CneFfJe0sEDye/vnfoAuBBWb7u1OQ9XodxMCMi8juMsKL84ESG7j61XcHSDzHaYmeA1D aw6Xu1bQiHFPDYBRT7dVtbYPBMsKq5kmi+FA6tMVYpxMiSugjIadlhM6JmFAYfA1QAB9 TP6s1/9CwjQEnOISa0V3gOhlQoS4B8HPgfx1rNOAOwQ/7Me/tzJDe6AvC9Zrr2stkn2h Wma9tGAWzXXmjOckOWrkbCyKlHGnzdTvKo1T6EPPh+iwAKqEYtNRUQYyejXf2VxrOlVU 4wTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689576910; x=1692168910; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EIQbVzJDtQSLAjOmeG/MuTeyAG4mQGjdI8C010Z2eIw=; b=alms9XA9a8eNTfGzxCpZKrEtkc95Y+7fQKnFPe2SgZZZIzlHr11SpqUyLbqYEi54Yq Zof7x13jAgL/Rm4vsXRbVr0bafEF8rIRk++ySiivuSajoXvORTpN5C1R23sZlcG0hStu 9k7+FA2x/r6Zc9IhMUDaKUEHLAQcImFYWpB/9eIWFF45E4Tda3QLEsXNl7+gKclt0Rzz 68qkwJYGjHRStoWKtsh+ZjbQzBbr/Ef9ZTAAgEiUchHJ+AX1zO4nAVa7hpHh4unXV0CT kmq0yITQSpup5shss/afLgT9buPfN/JjrfDeDEHR4kHumv0kUmZZpzmv4jRvrVDKEQQP Gnlw== X-Gm-Message-State: ABy/qLbLYLLZCDKcxgX8LDdWzP9GOLiRnX2YlF5BqhIu3lx49uAm94+i uD63FRcAJ6AiJB2uZ7eG4dGz X-Google-Smtp-Source: APBJJlE0nveJAQFhJWfXJ2pXIKRUaR22158RQz5B6tYHzqziQIaLTWZnuEN+O69BYpxfUpKDam8nvQ== X-Received: by 2002:a05:6a00:3989:b0:67a:a4d1:e70 with SMTP id fi9-20020a056a00398900b0067aa4d10e70mr10863192pfb.16.1689576910693; Sun, 16 Jul 2023 23:55:10 -0700 (PDT) Received: from localhost.localdomain ([117.193.215.209]) by smtp.gmail.com with ESMTPSA id x7-20020a62fb07000000b006675c242548sm11196422pfm.182.2023.07.16.23.55.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Jul 2023 23:55:10 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 1/7] PCI: qcom-ep: Pass alignment restriction to the EPF core Date: Mon, 17 Jul 2023 12:24:53 +0530 Message-Id: <20230717065459.14138-2-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> References: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qcom PCIe EP controllers have 4K alignment restriction for the outbound window address. Hence, pass this info to the EPF core so that the EPF drivers can make use of this info. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 0fe7f06f2102..736be5bee458 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -706,6 +706,7 @@ static const struct pci_epc_features qcom_pcie_epc_features = { .core_init_notifier = true, .msi_capable = true, .msix_capable = false, + .align = SZ_4K, }; static const struct pci_epc_features * From patchwork Mon Jul 17 06:54:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 703776 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C663AC0015E for ; Mon, 17 Jul 2023 06:55:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230043AbjGQGzX (ORCPT ); Mon, 17 Jul 2023 02:55:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47030 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229961AbjGQGzQ (ORCPT ); Mon, 17 Jul 2023 02:55:16 -0400 Received: from mail-ot1-x32e.google.com (mail-ot1-x32e.google.com [IPv6:2607:f8b0:4864:20::32e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 710061B8 for ; Sun, 16 Jul 2023 23:55:14 -0700 (PDT) Received: by mail-ot1-x32e.google.com with SMTP id 46e09a7af769-6b9cf1997c4so1225886a34.3 for ; Sun, 16 Jul 2023 23:55:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689576913; x=1692168913; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ywAnQod/2AqwT52mE4IcwiOccI2A/vlz7fI3wixXChQ=; b=COxSewSo57T9BYc2XB2RPZ4S4/p9vHVhb/9T0vJbWnE3ejosuOiGQqop/S61n/1m3J gkiP8ON7pKLZ4ZVgLDBQauxT8OH/GamXdZYAaroBax+c+pJyxkwIDgHV4BvBvU9cz9gC ORuA9rzT+Y+pVl7xVbwIs18jJZgMBzv68WrrTbl3zb0fVEbvL9sLnd0o7OinkY7ktJHR IpPkpcEIYO0/QaLZJB1U2axaO88F7fOPuIflkBqIFtuV0HCdprTqD5/abDDBplGCj/Ux w8aGmGaoDRFuS8oyYO93MLY3hceXm7PI38z7O0T9iTutiJPqwfc8HRnO4u/bLl7wJUjM XbQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689576913; x=1692168913; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ywAnQod/2AqwT52mE4IcwiOccI2A/vlz7fI3wixXChQ=; b=B+ufxcVXd61vLRVhrtm1gC2bUU8UdtoSzkzZQtfiAttbDDwlVl6Ff0XqZx7y+uhu08 qbQc8u/nymQwwwxu7WgNQ8YrJOlddkqqID5kTDU33y8KvYCAMhFdjJsypuK8m0en7wfT S89bFEwoX9C31/g4ABw1QKvRQdDQ0t/uDQNkccHePQt4WGo6HM5rEmpq+X3AO2wKZ66L mdGwuZjx81ImLKs8Tymkx/xXHMcsJRYECse+nBPGUePGVUSLjMmJip7RSQPOysA6ES1Q hqTQYASV6SMcB7JahfL0fZ95NdDXyiQFcYevcCGZ5pR25wfVYIKRl8FL7MG9ZX/scrYn aXxw== X-Gm-Message-State: ABy/qLaQ6/t7kfwvjusfaMFWrAPps2lbOhiDybF70fVXsXjyQz7PPNxq LZ4b2CC9WC6mDw5zVRtLVvh2 X-Google-Smtp-Source: APBJJlHX3QrNZi1kF0ACqAndRyoTeRH+RwIj7l0pEb3csyqHwPIlTIViF8Yxs4dhF5BQV/6Kba6YoQ== X-Received: by 2002:a05:6358:9184:b0:134:c37f:4b64 with SMTP id j4-20020a056358918400b00134c37f4b64mr8163188rwa.30.1689576913646; Sun, 16 Jul 2023 23:55:13 -0700 (PDT) Received: from localhost.localdomain ([117.193.215.209]) by smtp.gmail.com with ESMTPSA id x7-20020a62fb07000000b006675c242548sm11196422pfm.182.2023.07.16.23.55.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Jul 2023 23:55:13 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 2/7] PCI: epf-mhi: Make use of the alignment restriction from EPF core Date: Mon, 17 Jul 2023 12:24:54 +0530 Message-Id: <20230717065459.14138-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> References: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Instead of hardcoding the alignment restriction in the EPF_MHI driver, make use of the info available from the EPF core that reflects the alignment restriction of the endpoint controller. For this purpose, let's introduce the get_align_offset() static function. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c index 9c1f5a154fbd..bb7de6884824 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -102,6 +102,11 @@ struct pci_epf_mhi { int irq; }; +static size_t get_align_offset(struct pci_epc *epc, u64 addr) +{ + return addr % epc->mem->window.page_size; +} + static int __pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, phys_addr_t *paddr, void __iomem **vaddr, size_t offset, size_t size) @@ -134,7 +139,7 @@ static int pci_epf_mhi_alloc_map(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, { struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); struct pci_epc *epc = epf_mhi->epf->epc; - size_t offset = pci_addr & (epc->mem->window.page_size - 1); + size_t offset = get_align_offset(epc, pci_addr); return __pci_epf_mhi_alloc_map(mhi_cntrl, pci_addr, paddr, vaddr, offset, size); @@ -161,7 +166,7 @@ static void pci_epf_mhi_unmap_free(struct mhi_ep_cntrl *mhi_cntrl, u64 pci_addr, struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); struct pci_epf *epf = epf_mhi->epf; struct pci_epc *epc = epf->epc; - size_t offset = pci_addr & (epc->mem->window.page_size - 1); + size_t offset = get_align_offset(epc, pci_addr); __pci_epf_mhi_unmap_free(mhi_cntrl, pci_addr, paddr, vaddr, offset, size); @@ -185,7 +190,8 @@ static int pci_epf_mhi_read_from_host(struct mhi_ep_cntrl *mhi_cntrl, u64 from, void *to, size_t size) { struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); - size_t offset = from % SZ_4K; + struct pci_epc *epc = epf_mhi->epf->epc; + size_t offset = get_align_offset(epc, from); void __iomem *tre_buf; phys_addr_t tre_phys; int ret; @@ -213,7 +219,8 @@ static int pci_epf_mhi_write_to_host(struct mhi_ep_cntrl *mhi_cntrl, void *from, u64 to, size_t size) { struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); - size_t offset = to % SZ_4K; + struct pci_epc *epc = epf_mhi->epf->epc; + size_t offset = get_align_offset(epc, to); void __iomem *tre_buf; phys_addr_t tre_phys; int ret; From patchwork Mon Jul 17 06:54:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 704139 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2011BC00528 for ; Mon, 17 Jul 2023 06:55:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230053AbjGQGzZ (ORCPT ); Mon, 17 Jul 2023 02:55:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47228 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230011AbjGQGzV (ORCPT ); Mon, 17 Jul 2023 02:55:21 -0400 Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4612E10DC for ; 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Sun, 16 Jul 2023 23:55:16 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 3/7] PCI: qcom-ep: Add eDMA support Date: Mon, 17 Jul 2023 12:24:55 +0530 Message-Id: <20230717065459.14138-4-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> References: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Qualcomm PCIe Endpoint controllers have the in-built Embedded DMA (eDMA) peripheral for offloading the data transfer between PCIe bus and memory. Let's add the support for it by enabling the eDMA IRQ in the driver. Rest of the functionality will be handled by the eDMA DMA Engine driver. Since the eDMA on Qualcomm platforms only uses a single IRQ for all channels, use 1 for edma.nr_irqs. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom-ep.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom-ep.c b/drivers/pci/controller/dwc/pcie-qcom-ep.c index 736be5bee458..1baec81183b6 100644 --- a/drivers/pci/controller/dwc/pcie-qcom-ep.c +++ b/drivers/pci/controller/dwc/pcie-qcom-ep.c @@ -74,6 +74,7 @@ #define PARF_INT_ALL_PLS_ERR BIT(15) #define PARF_INT_ALL_PME_LEGACY BIT(16) #define PARF_INT_ALL_PLS_PME BIT(17) +#define PARF_INT_ALL_EDMA BIT(22) /* PARF_BDF_TO_SID_CFG register fields */ #define PARF_BDF_TO_SID_BYPASS BIT(0) @@ -395,7 +396,7 @@ static int qcom_pcie_perst_deassert(struct dw_pcie *pci) writel_relaxed(0, pcie_ep->parf + PARF_INT_ALL_MASK); val = PARF_INT_ALL_LINK_DOWN | PARF_INT_ALL_BME | PARF_INT_ALL_PM_TURNOFF | PARF_INT_ALL_DSTATE_CHANGE | - PARF_INT_ALL_LINK_UP; + PARF_INT_ALL_LINK_UP | PARF_INT_ALL_EDMA; writel_relaxed(val, pcie_ep->parf + PARF_INT_ALL_MASK); ret = dw_pcie_ep_init_complete(&pcie_ep->pci.ep); @@ -744,6 +745,7 @@ static int qcom_pcie_ep_probe(struct platform_device *pdev) pcie_ep->pci.dev = dev; pcie_ep->pci.ops = &pci_ops; pcie_ep->pci.ep.ops = &pci_ep_ops; + pcie_ep->pci.edma.nr_irqs = 1; platform_set_drvdata(pdev, pcie_ep); ret = qcom_pcie_ep_get_resources(pdev, pcie_ep); From patchwork Mon Jul 17 06:54:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 703775 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 232FFC0015E for ; Mon, 17 Jul 2023 06:55:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230004AbjGQGzh (ORCPT ); Mon, 17 Jul 2023 02:55:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47242 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229977AbjGQGz0 (ORCPT ); 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Sun, 16 Jul 2023 23:55:19 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 4/7] PCI: epf-mhi: Add eDMA support Date: Mon, 17 Jul 2023 12:24:56 +0530 Message-Id: <20230717065459.14138-5-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> References: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for Embedded DMA (eDMA) available in the Designware PCIe IP to transfer the MHI buffers between host and the endpoint. Use of eDMA helps in achieving greater throughput as the transfers are offloaded from CPUs. For differentiating the iATU and eDMA APIs, the pci_epf_mhi_{read/write} APIs are renamed to pci_epf_mhi_iatu_{read/write} and separate eDMA specific APIs pci_epf_mhi_edma_{read/write} are introduced. Platforms that require eDMA support can pass the MHI_EPF_USE_DMA flag through pci_epf_mhi_ep_info. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 237 ++++++++++++++++++- 1 file changed, 231 insertions(+), 6 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c index bb7de6884824..abebe44d0061 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -6,8 +6,10 @@ * Author: Manivannan Sadhasivam */ +#include #include #include +#include #include #include #include @@ -16,6 +18,9 @@ #define to_epf_mhi(cntrl) container_of(cntrl, struct pci_epf_mhi, cntrl) +/* Platform specific flags */ +#define MHI_EPF_USE_DMA BIT(0) + struct pci_epf_mhi_ep_info { const struct mhi_ep_cntrl_config *config; struct pci_epf_header *epf_header; @@ -23,6 +28,7 @@ struct pci_epf_mhi_ep_info { u32 epf_flags; u32 msi_count; u32 mru; + u32 flags; }; #define MHI_EP_CHANNEL_CONFIG(ch_num, ch_name, direction) \ @@ -98,6 +104,8 @@ struct pci_epf_mhi { struct mutex lock; void __iomem *mmio; resource_size_t mmio_phys; + struct dma_chan *dma_chan_tx; + struct dma_chan *dma_chan_rx; u32 mmio_size; int irq; }; @@ -186,8 +194,8 @@ static void pci_epf_mhi_raise_irq(struct mhi_ep_cntrl *mhi_cntrl, u32 vector) vector + 1); } -static int pci_epf_mhi_read_from_host(struct mhi_ep_cntrl *mhi_cntrl, u64 from, - void *to, size_t size) +static int pci_epf_mhi_iatu_read(struct mhi_ep_cntrl *mhi_cntrl, u64 from, + void *to, size_t size) { struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); struct pci_epc *epc = epf_mhi->epf->epc; @@ -215,8 +223,8 @@ static int pci_epf_mhi_read_from_host(struct mhi_ep_cntrl *mhi_cntrl, u64 from, return 0; } -static int pci_epf_mhi_write_to_host(struct mhi_ep_cntrl *mhi_cntrl, - void *from, u64 to, size_t size) +static int pci_epf_mhi_iatu_write(struct mhi_ep_cntrl *mhi_cntrl, + void *from, u64 to, size_t size) { struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); struct pci_epc *epc = epf_mhi->epf->epc; @@ -244,6 +252,200 @@ static int pci_epf_mhi_write_to_host(struct mhi_ep_cntrl *mhi_cntrl, return 0; } +static void pci_epf_mhi_dma_callback(void *param) +{ + complete(param); +} + +static int pci_epf_mhi_edma_read(struct mhi_ep_cntrl *mhi_cntrl, u64 from, + void *to, size_t size) +{ + struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); + struct device *dma_dev = epf_mhi->epf->epc->dev.parent; + struct dma_chan *chan = epf_mhi->dma_chan_rx; + struct device *dev = &epf_mhi->epf->dev; + DECLARE_COMPLETION_ONSTACK(complete); + struct dma_async_tx_descriptor *desc; + struct dma_slave_config config = {}; + dma_cookie_t cookie; + dma_addr_t dst_addr; + int ret; + + mutex_lock(&epf_mhi->lock); + + config.direction = DMA_DEV_TO_MEM; + config.src_addr = from; + + ret = dmaengine_slave_config(chan, &config); + if (ret) { + dev_err(dev, "Failed to configure DMA channel\n"); + goto err_unlock; + } + + dst_addr = dma_map_single(dma_dev, to, size, DMA_FROM_DEVICE); + ret = dma_mapping_error(dma_dev, dst_addr); + if (ret) { + dev_err(dev, "Failed to map remote memory\n"); + goto err_unlock; + } + + desc = dmaengine_prep_slave_single(chan, dst_addr, size, DMA_DEV_TO_MEM, + DMA_CTRL_ACK | DMA_PREP_INTERRUPT); + if (!desc) { + dev_err(dev, "Failed to prepare DMA\n"); + ret = -EIO; + goto err_unmap; + } + + desc->callback = pci_epf_mhi_dma_callback; + desc->callback_param = &complete; + + cookie = dmaengine_submit(desc); + ret = dma_submit_error(cookie); + if (ret) { + dev_err(dev, "Failed to do DMA submit\n"); + goto err_unmap; + } + + dma_async_issue_pending(chan); + ret = wait_for_completion_timeout(&complete, msecs_to_jiffies(1000)); + if (!ret) { + dev_err(dev, "DMA transfer timeout\n"); + dmaengine_terminate_sync(chan); + ret = -ETIMEDOUT; + } + +err_unmap: + dma_unmap_single(dma_dev, dst_addr, size, DMA_FROM_DEVICE); +err_unlock: + mutex_unlock(&epf_mhi->lock); + + return ret; +} + +static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl *mhi_cntrl, void *from, + u64 to, size_t size) +{ + struct pci_epf_mhi *epf_mhi = to_epf_mhi(mhi_cntrl); + struct device *dma_dev = epf_mhi->epf->epc->dev.parent; + struct dma_chan *chan = epf_mhi->dma_chan_tx; + struct device *dev = &epf_mhi->epf->dev; + DECLARE_COMPLETION_ONSTACK(complete); + struct dma_async_tx_descriptor *desc; + struct dma_slave_config config = {}; + dma_cookie_t cookie; + dma_addr_t src_addr; + int ret; + + mutex_lock(&epf_mhi->lock); + + config.direction = DMA_MEM_TO_DEV; + config.dst_addr = to; + + ret = dmaengine_slave_config(chan, &config); + if (ret) { + dev_err(dev, "Failed to configure DMA channel\n"); + goto err_unlock; + } + + src_addr = dma_map_single(dma_dev, from, size, DMA_TO_DEVICE); + ret = dma_mapping_error(dma_dev, src_addr); + if (ret) { + dev_err(dev, "Failed to map remote memory\n"); + goto err_unlock; + } + + desc = dmaengine_prep_slave_single(chan, src_addr, size, DMA_MEM_TO_DEV, + DMA_CTRL_ACK | DMA_PREP_INTERRUPT); + if (!desc) { + dev_err(dev, "Failed to prepare DMA\n"); + ret = -EIO; + goto err_unmap; + } + + desc->callback = pci_epf_mhi_dma_callback; + desc->callback_param = &complete; + + cookie = dmaengine_submit(desc); + ret = dma_submit_error(cookie); + if (ret) { + dev_err(dev, "Failed to do DMA submit\n"); + goto err_unmap; + } + + dma_async_issue_pending(chan); + ret = wait_for_completion_timeout(&complete, msecs_to_jiffies(1000)); + if (!ret) { + dev_err(dev, "DMA transfer timeout\n"); + dmaengine_terminate_sync(chan); + ret = -ETIMEDOUT; + } + +err_unmap: + dma_unmap_single(dma_dev, src_addr, size, DMA_FROM_DEVICE); +err_unlock: + mutex_unlock(&epf_mhi->lock); + + return ret; +} + +struct epf_dma_filter { + struct device *dev; + u32 dma_mask; +}; + +static bool pci_epf_mhi_filter(struct dma_chan *chan, void *node) +{ + struct epf_dma_filter *filter = node; + struct dma_slave_caps caps; + + memset(&caps, 0, sizeof(caps)); + dma_get_slave_caps(chan, &caps); + + return chan->device->dev == filter->dev && filter->dma_mask & + caps.directions; +} + +static int pci_epf_mhi_dma_init(struct pci_epf_mhi *epf_mhi) +{ + struct device *dma_dev = epf_mhi->epf->epc->dev.parent; + struct device *dev = &epf_mhi->epf->dev; + struct epf_dma_filter filter; + dma_cap_mask_t mask; + + dma_cap_zero(mask); + dma_cap_set(DMA_SLAVE, mask); + + filter.dev = dma_dev; + filter.dma_mask = BIT(DMA_MEM_TO_DEV); + epf_mhi->dma_chan_tx = dma_request_channel(mask, pci_epf_mhi_filter, + &filter); + if (IS_ERR_OR_NULL(epf_mhi->dma_chan_tx)) { + dev_err(dev, "Failed to request tx channel\n"); + return -ENODEV; + } + + filter.dma_mask = BIT(DMA_DEV_TO_MEM); + epf_mhi->dma_chan_rx = dma_request_channel(mask, pci_epf_mhi_filter, + &filter); + if (IS_ERR_OR_NULL(epf_mhi->dma_chan_rx)) { + dev_err(dev, "Failed to request rx channel\n"); + dma_release_channel(epf_mhi->dma_chan_tx); + epf_mhi->dma_chan_tx = NULL; + return -ENODEV; + } + + return 0; +} + +static void pci_epf_mhi_dma_deinit(struct pci_epf_mhi *epf_mhi) +{ + dma_release_channel(epf_mhi->dma_chan_tx); + dma_release_channel(epf_mhi->dma_chan_rx); + epf_mhi->dma_chan_tx = NULL; + epf_mhi->dma_chan_rx = NULL; +} + static int pci_epf_mhi_core_init(struct pci_epf *epf) { struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); @@ -289,6 +491,14 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) struct device *dev = &epf->dev; int ret; + if (info->flags & MHI_EPF_USE_DMA) { + ret = pci_epf_mhi_dma_init(epf_mhi); + if (ret) { + dev_err(dev, "Failed to initialize DMA: %d\n", ret); + return ret; + } + } + mhi_cntrl->mmio = epf_mhi->mmio; mhi_cntrl->irq = epf_mhi->irq; mhi_cntrl->mru = info->mru; @@ -298,13 +508,20 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) mhi_cntrl->raise_irq = pci_epf_mhi_raise_irq; mhi_cntrl->alloc_map = pci_epf_mhi_alloc_map; mhi_cntrl->unmap_free = pci_epf_mhi_unmap_free; - mhi_cntrl->read_from_host = pci_epf_mhi_read_from_host; - mhi_cntrl->write_to_host = pci_epf_mhi_write_to_host; + if (info->flags & MHI_EPF_USE_DMA) { + mhi_cntrl->read_from_host = pci_epf_mhi_edma_read; + mhi_cntrl->write_to_host = pci_epf_mhi_edma_write; + } else { + mhi_cntrl->read_from_host = pci_epf_mhi_iatu_read; + mhi_cntrl->write_to_host = pci_epf_mhi_iatu_write; + } /* Register the MHI EP controller */ ret = mhi_ep_register_controller(mhi_cntrl, info->config); if (ret) { dev_err(dev, "Failed to register MHI EP controller: %d\n", ret); + if (info->flags & MHI_EPF_USE_DMA) + pci_epf_mhi_dma_deinit(epf_mhi); return ret; } @@ -314,10 +531,13 @@ static int pci_epf_mhi_link_up(struct pci_epf *epf) static int pci_epf_mhi_link_down(struct pci_epf *epf) { struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); + const struct pci_epf_mhi_ep_info *info = epf_mhi->info; struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl; if (mhi_cntrl->mhi_dev) { mhi_ep_power_down(mhi_cntrl); + if (info->flags & MHI_EPF_USE_DMA) + pci_epf_mhi_dma_deinit(epf_mhi); mhi_ep_unregister_controller(mhi_cntrl); } @@ -327,6 +547,7 @@ static int pci_epf_mhi_link_down(struct pci_epf *epf) static int pci_epf_mhi_bme(struct pci_epf *epf) { struct pci_epf_mhi *epf_mhi = epf_get_drvdata(epf); + const struct pci_epf_mhi_ep_info *info = epf_mhi->info; struct mhi_ep_cntrl *mhi_cntrl = &epf_mhi->mhi_cntrl; struct device *dev = &epf->dev; int ret; @@ -339,6 +560,8 @@ static int pci_epf_mhi_bme(struct pci_epf *epf) ret = mhi_ep_power_up(mhi_cntrl); if (ret) { dev_err(dev, "Failed to power up MHI EP: %d\n", ret); + if (info->flags & MHI_EPF_USE_DMA) + pci_epf_mhi_dma_deinit(epf_mhi); mhi_ep_unregister_controller(mhi_cntrl); } } @@ -389,6 +612,8 @@ static void pci_epf_mhi_unbind(struct pci_epf *epf) */ if (mhi_cntrl->mhi_dev) { mhi_ep_power_down(mhi_cntrl); + if (info->flags & MHI_EPF_USE_DMA) + pci_epf_mhi_dma_deinit(epf_mhi); mhi_ep_unregister_controller(mhi_cntrl); } From patchwork Mon Jul 17 06:54:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 704138 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9F8D4EB64DC for ; Mon, 17 Jul 2023 06:55:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230135AbjGQGzq (ORCPT ); Mon, 17 Jul 2023 02:55:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230039AbjGQGze (ORCPT ); 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Sun, 16 Jul 2023 23:55:22 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 5/7] PCI: epf-mhi: Add support for SM8450 Date: Mon, 17 Jul 2023 12:24:57 +0530 Message-Id: <20230717065459.14138-6-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> References: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add support for Qualcomm Snapdragon SM8450 SoC to the EPF driver. SM8450 has the dedicated PID (0x0306) and supports eDMA. Currently, it has no fixed PCI class, so it is being advertised as "PCI_CLASS_OTHERS". Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 22 +++++++++++++++++--- 1 file changed, 19 insertions(+), 3 deletions(-) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c index abebe44d0061..dc6692e2c623 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -97,6 +97,23 @@ static const struct pci_epf_mhi_ep_info sdx55_info = { .mru = 0x8000, }; +static struct pci_epf_header sm8450_header = { + .vendorid = PCI_VENDOR_ID_QCOM, + .deviceid = 0x0306, + .baseclass_code = PCI_CLASS_OTHERS, + .interrupt_pin = PCI_INTERRUPT_INTA, +}; + +static const struct pci_epf_mhi_ep_info sm8450_info = { + .config = &mhi_v1_config, + .epf_header = &sm8450_header, + .bar_num = BAR_0, + .epf_flags = PCI_BASE_ADDRESS_MEM_TYPE_32, + .msi_count = 32, + .mru = 0x8000, + .flags = MHI_EPF_USE_DMA, +}; + struct pci_epf_mhi { const struct pci_epf_mhi_ep_info *info; struct mhi_ep_cntrl mhi_cntrl; @@ -654,9 +671,8 @@ static int pci_epf_mhi_probe(struct pci_epf *epf, } static const struct pci_epf_device_id pci_epf_mhi_ids[] = { - { - .name = "sdx55", .driver_data = (kernel_ulong_t)&sdx55_info, - }, + { .name = "sdx55", .driver_data = (kernel_ulong_t)&sdx55_info }, + { .name = "sm8450", .driver_data = (kernel_ulong_t)&sm8450_info }, {}, }; From patchwork Mon Jul 17 06:54:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 703774 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E2C0FC001B0 for ; Mon, 17 Jul 2023 06:55:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230081AbjGQGz4 (ORCPT ); Mon, 17 Jul 2023 02:55:56 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230083AbjGQGzk (ORCPT ); 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Sun, 16 Jul 2023 23:55:25 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 6/7] PCI: epf-mhi: Use iATU for small transfers Date: Mon, 17 Jul 2023 12:24:58 +0530 Message-Id: <20230717065459.14138-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> References: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org For transfers below 4K, let's use iATU since using eDMA for such small transfers is not efficient. This is mainly due to the fact that setting up a eDMA transfer and waiting for its completion adds some latency. This latency is negligible for large transfers but not for the smaller ones. With this hack, there is an increase in ~50Mbps throughput on both MHI UL (Uplink) and DL (Downlink) channels. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/functions/pci-epf-mhi.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/pci/endpoint/functions/pci-epf-mhi.c b/drivers/pci/endpoint/functions/pci-epf-mhi.c index dc6692e2c623..a8feb03061aa 100644 --- a/drivers/pci/endpoint/functions/pci-epf-mhi.c +++ b/drivers/pci/endpoint/functions/pci-epf-mhi.c @@ -288,6 +288,9 @@ static int pci_epf_mhi_edma_read(struct mhi_ep_cntrl *mhi_cntrl, u64 from, dma_addr_t dst_addr; int ret; + if (size < SZ_4K) + return pci_epf_mhi_iatu_read(mhi_cntrl, from, to, size); + mutex_lock(&epf_mhi->lock); config.direction = DMA_DEV_TO_MEM; @@ -354,6 +357,9 @@ static int pci_epf_mhi_edma_write(struct mhi_ep_cntrl *mhi_cntrl, void *from, dma_addr_t src_addr; int ret; + if (size < SZ_4K) + return pci_epf_mhi_iatu_write(mhi_cntrl, from, to, size); + mutex_lock(&epf_mhi->lock); config.direction = DMA_MEM_TO_DEV; From patchwork Mon Jul 17 06:54:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 704137 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7A42EC001B0 for ; Mon, 17 Jul 2023 06:56:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230198AbjGQG4D (ORCPT ); Mon, 17 Jul 2023 02:56:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47606 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230103AbjGQGzq (ORCPT ); Mon, 17 Jul 2023 02:55:46 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CDEA219AC for ; Sun, 16 Jul 2023 23:55:29 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-6831e80080dso2642284b3a.0 for ; Sun, 16 Jul 2023 23:55:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689576928; x=1692168928; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cRwHHVBuwFdTSPfIU1R1ZLyGoM8LybFGSYGhuRMiUuk=; b=kSVx8Wk/UdV6T3ySTsoCWHjmRp7PQqIlR1Asg6XqAdVC2L3DfGAYYvNgU0CLQAGoik kb9RlF+7lRH2uctGidrXT9GDHJvclhslSq7CQuzokRMM2Xh4c0gIlwJfscGF7zU8ZGg+ utgqJrbCJttTV1GGHqw3LfBtgRcFcCItEnXulZ+5+eGxY7Qb0spCSpbE2Kp7duQqLUBJ CQY9bAntoLYs6yPGX19LWWdyTs3VX+NUg4IdORjto6yFlh7tDvr3hGq3uGCJiS6QIwqH zUlDixthW871aJxwAkTAEWYHHA2wq4SrL7eNnLKde2kZhJQYY1Uilduz+LOMMXQAbIS0 Y0Mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689576928; x=1692168928; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cRwHHVBuwFdTSPfIU1R1ZLyGoM8LybFGSYGhuRMiUuk=; b=OSZeLYq8lWTTx469k3ZTPfJFbf9XzgSMiClE8S0EhNQ4MRPqzWDDIRSDey267X/uxq 7wdJbTv8E5Xib4JBrIo3QR8QWylG4iDri23fa5g6MQwoMuWRBhxEeOyiNUpQ6MTEjNpo k7l2yrCqopXQiciKXntZqHLwOzZ6ncfPhhYpCVv4wjcZ7YuXfkX5diqWrNax+Dd5RHS/ iqGjQiNZGomg0btzCM4dHh6xGvA4kouuAJyowRFCyaAzUcVu9Ts7m7p5yDG/g6ZcIQ1V wS02PL1B1kU+3rniJ4x2f7wa7dqsC9Fs08osd7T1I/6AfITtIPyx6s/07h9Ka1drfSp/ UXnw== X-Gm-Message-State: ABy/qLZKRSVSln9dt0iq6Fa0/4Zov9XABtvA/KgQYJesy9Ok4jt/k/b3 cKY8AT0O3o8i6ITiCKnszT0P X-Google-Smtp-Source: APBJJlG4K9K281TmKA2IFNIDJX1vCI+o79+13v51XsucEfkt42YZpay+GD8qVKNI+/1HgkkDP26ObQ== X-Received: by 2002:a05:6a00:3983:b0:668:7e84:32e6 with SMTP id fi3-20020a056a00398300b006687e8432e6mr14433427pfb.29.1689576928654; Sun, 16 Jul 2023 23:55:28 -0700 (PDT) Received: from localhost.localdomain ([117.193.215.209]) by smtp.gmail.com with ESMTPSA id x7-20020a62fb07000000b006675c242548sm11196422pfm.182.2023.07.16.23.55.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 16 Jul 2023 23:55:28 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com Cc: kishon@kernel.org, bhelgaas@google.com, linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, Manivannan Sadhasivam Subject: [PATCH v2 7/7] PCI: endpoint: Add kernel-doc for pci_epc_mem_init() API Date: Mon, 17 Jul 2023 12:24:59 +0530 Message-Id: <20230717065459.14138-8-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> References: <20230717065459.14138-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add missing kernel-doc for pci_epc_mem_init() API. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/endpoint/pci-epc-mem.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pci/endpoint/pci-epc-mem.c b/drivers/pci/endpoint/pci-epc-mem.c index 7dcf6f480b82..a9c028f58da1 100644 --- a/drivers/pci/endpoint/pci-epc-mem.c +++ b/drivers/pci/endpoint/pci-epc-mem.c @@ -115,6 +115,16 @@ int pci_epc_multi_mem_init(struct pci_epc *epc, } EXPORT_SYMBOL_GPL(pci_epc_multi_mem_init); +/** + * pci_epc_mem_init() - Initialize the pci_epc_mem structure + * @epc: the EPC device that invoked pci_epc_mem_init + * @base: Physical address of the window region + * @size: Total Size of the window region + * @page_size: Page size of the window region + * + * Invoke to initialize a single pci_epc_mem structure used by the + * endpoint functions to allocate memory for mapping the PCI host memory + */ int pci_epc_mem_init(struct pci_epc *epc, phys_addr_t base, size_t size, size_t page_size) {