From patchwork Mon Jul 10 10:37:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 701760 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 898E4C0015E for ; Mon, 10 Jul 2023 10:38:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231375AbjGJKiM (ORCPT ); Mon, 10 Jul 2023 06:38:12 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45304 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233500AbjGJKiJ (ORCPT ); Mon, 10 Jul 2023 06:38:09 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2AA1CCC; Mon, 10 Jul 2023 03:38:07 -0700 (PDT) Received: from pps.filterd (m0279870.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36AABES2030520; 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Mon, 10 Jul 2023 10:38:01 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Mon, 10 Jul 2023 03:37:56 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH 1/6] dt-bindings: thermal: tsens: Add nvmem cells for calibration data Date: Mon, 10 Jul 2023 16:07:30 +0530 Message-ID: <20230710103735.1375847-2-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> References: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: scTWEqQJ8M4Gs3QxE_13-qnneS268xR7 X-Proofpoint-ORIG-GUID: scTWEqQJ8M4Gs3QxE_13-qnneS268xR7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-10_08,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 clxscore=1011 lowpriorityscore=0 adultscore=0 phishscore=0 mlxlogscore=999 bulkscore=0 malwarescore=0 impostorscore=0 mlxscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307100096 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add TSENS V2 calibration nvmem cells for IPQ5332 Signed-off-by: Praveenkumar I --- .../bindings/thermal/qcom-tsens.yaml | 26 +++++++++++++++++-- 1 file changed, 24 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 27e9e16e6455..8b7863c3989e 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -91,7 +91,7 @@ properties: maxItems: 2 nvmem-cells: - oneOf: + anyOf: - minItems: 1 maxItems: 2 description: @@ -106,9 +106,13 @@ properties: description: | Reference to nvmem cells for the calibration mode, two calibration bases and two cells per each sensor, main and backup copies, plus use_backup cell + - maxItems: 17 + description: | + V2 of TSENS, reference to nvmem cells for the calibration mode, two calibration + bases and one cell per each sensor nvmem-cell-names: - oneOf: + anyOf: - minItems: 1 items: - const: calib @@ -205,6 +209,24 @@ properties: - const: s9_p2_backup - const: s10_p1_backup - const: s10_p2_backup + - items: + - const: mode + - const: base0 + - const: base1 + - const: s0_offset + - const: s3_offset + - const: s4_offset + - const: s5_offset + - const: s6_offset + - const: s7_offset + - const: s8_offset + - const: s9_offset + - const: s10_offset + - const: s11_offset + - const: s12_offset + - const: s13_offset + - const: s14_offset + - const: s15_offset "#qcom,sensors": description: From patchwork Mon Jul 10 10:37:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 701758 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96233EB64DC for ; Mon, 10 Jul 2023 10:38:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233533AbjGJKi5 (ORCPT ); Mon, 10 Jul 2023 06:38:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45816 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232798AbjGJKiw (ORCPT ); Mon, 10 Jul 2023 06:38:52 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B72E8E3; Mon, 10 Jul 2023 03:38:29 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36A8xhIe008012; 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Mon, 10 Jul 2023 10:38:10 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Mon, 10 Jul 2023 03:38:05 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH 3/6] dt-bindings: thermal: tsens: Add ipq5332 compatible Date: Mon, 10 Jul 2023 16:07:32 +0530 Message-ID: <20230710103735.1375847-4-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> References: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: LUbr4zSV2sMbANqKIGt0_PVh6CVBKtTa X-Proofpoint-ORIG-GUID: LUbr4zSV2sMbANqKIGt0_PVh6CVBKtTa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-10_08,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 impostorscore=0 adultscore=0 spamscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 clxscore=1015 bulkscore=0 suspectscore=0 malwarescore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307100096 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org IPQ5332 uses TSENS v2.3.3 with combined interrupt. RPM is not available in the SoC, hence adding new compatible to have the sensor enablement and calibration function. Signed-off-by: Praveenkumar I --- Documentation/devicetree/bindings/thermal/qcom-tsens.yaml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 8b7863c3989e..ee57713f6131 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -68,8 +68,10 @@ properties: - const: qcom,tsens-v2 - description: v2 of TSENS with combined interrupt - enum: - - qcom,ipq8074-tsens + items: + - enum: + - qcom,ipq8074-tsens + - qcom,ipq5332-tsens - description: v2 of TSENS with combined interrupt items: @@ -289,6 +291,7 @@ allOf: contains: enum: - qcom,ipq8074-tsens + - qcom,ipq5332-tsens then: properties: interrupts: @@ -304,6 +307,7 @@ allOf: contains: enum: - qcom,ipq8074-tsens + - qcom,ipq5332-tsens - qcom,tsens-v0_1 - qcom,tsens-v1 - qcom,tsens-v2 From patchwork Mon Jul 10 10:37:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 701759 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 935ECC0015E for ; Mon, 10 Jul 2023 10:38:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231494AbjGJKia (ORCPT ); Mon, 10 Jul 2023 06:38:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45436 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232524AbjGJKi1 (ORCPT ); Mon, 10 Jul 2023 06:38:27 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5851FB; Mon, 10 Jul 2023 03:38:22 -0700 (PDT) Received: from pps.filterd (m0279869.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 36A9jTjN022183; Mon, 10 Jul 2023 10:38:16 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=qcppdkim1; bh=bfNOF/GRWeeHJbmWyRnvqYdWgqv/8yp+BQB3y1VQsOk=; b=WRL+3hqVse1KujBZ6Kz6IE+NuxM7XVgE75oqHRiIiiYbuJpyzS1omyguAPW3AVVNWKRF k7HgHrU5rPikPdj8dMmxighOV2GYOpkP49U49RzWM4WANm+M6+2Jh2n4pQ7O1lV5POms pAeBWyQqbINdKmvn2xMexhtzhRFyW0wbaOYxuD9NHQ6p1ZWWF5zSvRLK/bufCKHbcypi qWvqflpyt8hL8phL6SARCvEXdS0vi1Ind/WCJhUVclNGcGEtVnp7o2iVB845Gd7G3J4B 3HPD/5/pGeyeH88gdPvx/iAUbkufGisYiwVet+/77iSf7vLfg58nNqfAnyZvJu6H+KNy Rg== Received: from nalasppmta04.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rpxteuac2-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:38:16 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 36AAcFIl013695 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Mon, 10 Jul 2023 10:38:15 GMT Received: from hu-ipkumar-blr.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1118.30; Mon, 10 Jul 2023 03:38:10 -0700 From: Praveenkumar I To: , , , , , , , , , , , , , , CC: Subject: [PATCH 4/6] arm64: dts: qcom: ipq5332: Add tsens node Date: Mon, 10 Jul 2023 16:07:33 +0530 Message-ID: <20230710103735.1375847-5-quic_ipkumar@quicinc.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> References: <20230710103735.1375847-1-quic_ipkumar@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: Q1tzYNmWuLQ9shshDY-jcNDnomCiK-pT X-Proofpoint-ORIG-GUID: Q1tzYNmWuLQ9shshDY-jcNDnomCiK-pT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-07-10_08,2023-07-06_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 priorityscore=1501 clxscore=1011 impostorscore=0 mlxlogscore=696 bulkscore=0 spamscore=0 malwarescore=0 adultscore=0 phishscore=0 suspectscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2307100096 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org IPQ5332 has tsens v2.3.3 peripheral. This patch adds the tsense node with nvmem cells for calibration data. Signed-off-by: Praveenkumar I --- arch/arm64/boot/dts/qcom/ipq5332.dtsi | 113 ++++++++++++++++++++++++++ 1 file changed, 113 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5332.dtsi b/arch/arm64/boot/dts/qcom/ipq5332.dtsi index 8bfc2db44624..a1e3527178c0 100644 --- a/arch/arm64/boot/dts/qcom/ipq5332.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5332.dtsi @@ -150,6 +150,91 @@ qfprom: efuse@a4000 { reg = <0x000a4000 0x721>; #address-cells = <1>; #size-cells = <1>; + + tsens_mode: mode@3e1 { + reg = <0x3e1 0x1>; + bits = <0 3>; + }; + + tsens_base0: base0@3e1 { + reg = <0x3e1 0x2>; + bits = <3 10>; + }; + + tsens_base1: base1@3e2 { + reg = <0x3e2 0x2>; + bits = <5 10>; + }; + + s0_offset: s0_offset@3e4 { + reg = <0x3e4 0x1>; + bits = <0 4>; + }; + + s3_offset: s3_offset@3e5 { + reg = <0x3e5 0x1>; + bits = <4 4>; + }; + + s4_offset: s4_offset@3e6 { + reg = <0x3e6 0x1>; + bits = <0 4>; + }; + + s5_offset: s5_offset@3e6 { + reg = <0x3e6 0x1>; + bits = <4 4>; + }; + + s6_offset: s6_offset@3e8 { + reg = <0x3e8 0x1>; + bits = <0 4>; + }; + + s7_offset: s7_offset@3e8 { + reg = <0x3e8 0x1>; + bits = <4 4>; + }; + + s8_offset: s8_offset@3a4 { + reg = <0x3a4 0x1>; + bits = <0 4>; + }; + + s9_offset: s9_offset@3a4 { + reg = <0x3a4 0x1>; + bits = <4 4>; + }; + + s10_offset: s10_offset@3a5 { + reg = <0x3a5 0x1>; + bits = <0 4>; + }; + + s11_offset: s11_offset@3a5 { + reg = <0x3a5 0x1>; + bits = <4 4>; + }; + + s12_offset: s12_offset@3a6 { + reg = <0x3a6 0x1>; + bits = <0 4>; + }; + + s13_offset: s13_offset@3a6 { + reg = <0x3a6 0x1>; + bits = <4 4>; + }; + + s14_offset: s14_offset@3ad { + reg = <0x3ad 0x2>; + bits = <7 4>; + }; + + s15_offset: s0_offset@3ae { + reg = <0x3ae 0x1>; + bits = <3 4>; + }; }; rng: rng@e3000 { @@ -159,6 +244,34 @@ rng: rng@e3000 { clock-names = "core"; }; + tsens: thermal-sensor@4a9000 { + compatible = "qcom,ipq5332-tsens"; + reg = <0x4a9000 0x1000>, + <0x4a8000 0x1000>; + nvmem-cells = <&tsens_mode>, <&tsens_base0>, + <&tsens_base1>, <&s0_offset>, + <&s3_offset>, <&s4_offset>, + <&s5_offset>, <&s6_offset>, + <&s7_offset>, <&s8_offset>, + <&s9_offset>, <&s10_offset>, + <&s11_offset>, <&s12_offset>, + <&s13_offset>, <&s14_offset>, + <&s15_offset>; + nvmem-cell-names = "mode", "base0", + "base1", "s0_offset", + "s3_offset", "s4_offset", + "s5_offset", "s6_offset", + "s7_offset", "s8_offset", + "s9_offset", "s10_offset", + "s11_offset", "s12_offset", + "s13_offset", "s14_offset", + "s15_offset"; + interrupts = ; + interrupt-names = "combined"; + #qcom,sensors = <16>; + #thermal-sensor-cells = <1>; + }; + tlmm: pinctrl@1000000 { compatible = "qcom,ipq5332-tlmm"; reg = <0x01000000 0x300000>; From patchwork Mon Jul 10 10:37:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Praveenkumar I X-Patchwork-Id: 701757 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 95B22C3DA40 for ; Mon, 10 Jul 2023 10:41:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231765AbjGJKlL (ORCPT ); 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But as the SoCs does not have RPM, kernel needs to take care of sensor enablement and calibration. Hence introduced new ops and data for IPQ5332 and reused the feature_config from IPQ8074. Signed-off-by: Praveenkumar I --- drivers/thermal/qcom/tsens-v2.c | 13 +++++++++++++ drivers/thermal/qcom/tsens.c | 3 +++ drivers/thermal/qcom/tsens.h | 2 +- 3 files changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/tsens-v2.c b/drivers/thermal/qcom/tsens-v2.c index db48b1d95348..8b6e3876fd2c 100644 --- a/drivers/thermal/qcom/tsens-v2.c +++ b/drivers/thermal/qcom/tsens-v2.c @@ -237,6 +237,19 @@ struct tsens_plat_data data_ipq8074 = { .fields = tsens_v2_regfields, }; +static const struct tsens_ops ops_ipq5332_v2 = { + .init = init_common, + .get_temp = get_temp_tsens_valid, + .calibrate = tsens_v2_calibration, +}; + +struct tsens_plat_data data_ipq5332 = { + .sensors_to_en = 0xF800, + .ops = &ops_ipq5332_v2, + .feat = &ipq8074_feat, + .fields = tsens_v2_regfields, +}; + /* Kept around for backward compatibility with old msm8996.dtsi */ struct tsens_plat_data data_8996 = { .num_sensors = 13, diff --git a/drivers/thermal/qcom/tsens.c b/drivers/thermal/qcom/tsens.c index 169690355dad..e8ba2901cda8 100644 --- a/drivers/thermal/qcom/tsens.c +++ b/drivers/thermal/qcom/tsens.c @@ -1140,6 +1140,9 @@ static const struct of_device_id tsens_table[] = { }, { .compatible = "qcom,ipq8074-tsens", .data = &data_ipq8074, + }, { + .compatible = "qcom,ipq5332-tsens", + .data = &data_ipq5332, }, { .compatible = "qcom,mdm9607-tsens", .data = &data_9607, diff --git a/drivers/thermal/qcom/tsens.h b/drivers/thermal/qcom/tsens.h index f8897bc8944e..36040f9beebc 100644 --- a/drivers/thermal/qcom/tsens.h +++ b/drivers/thermal/qcom/tsens.h @@ -701,6 +701,6 @@ extern struct tsens_plat_data data_8226, data_8909, data_8916, data_8939, data_8 extern struct tsens_plat_data data_tsens_v1, data_8976, data_8956; /* TSENS v2 targets */ -extern struct tsens_plat_data data_8996, data_ipq8074, data_tsens_v2; +extern struct tsens_plat_data data_8996, data_ipq8074, data_ipq5332, data_tsens_v2; #endif /* __QCOM_TSENS_H__ */