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[209.51.188.17]) by mx.google.com with ESMTPS id n15-20020ac85b4f000000b004034ce9a8b1si15726qtw.153.2023.07.10.08.22.19 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 10 Jul 2023 08:22:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WSoQ4+jC; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qIshw-0007lm-2N; Mon, 10 Jul 2023 11:21:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qIshp-0007k6-B8 for qemu-devel@nongnu.org; Mon, 10 Jul 2023 11:21:43 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qIshl-0007ve-Es for qemu-devel@nongnu.org; Mon, 10 Jul 2023 11:21:41 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3fc0aecf107so18317165e9.2 for ; Mon, 10 Jul 2023 08:21:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1689002493; x=1691594493; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5UcR4FHg9WVcPft9HxBo42jo6Qco7ragFk7gzsy3OlA=; b=WSoQ4+jCE/H44aGUgoGWpIn8FMihv4CdBuyTu+ycFzTQUa9GUOZiu8LNvB+7X/EP+i 6Dl9sGKSCfFNCFIOJ6DIAyiH2HwCDZZ8e7IxbjHuhmq7zISjIb498yL2nbUw0ZGIOaHz dB5Gb1CTeXFEFUmMg9AtBkX97DxINzZXFkuNgysGv81cqIoxjKneePn45f5No4v0Ah3V +h+cnZPWkUSNmm4V7A1Tk932AiPZ2kO9j1+vO76fB9USjWicHQ6WjGBrXvxhJOhCykiM Z/rCsHR0Tg4aC42uZvbU+L9j9tsBcnaA9Sxe3EsACzxKSvlqFlv6ipB7W1hbYa1m2qS7 84Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1689002493; x=1691594493; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5UcR4FHg9WVcPft9HxBo42jo6Qco7ragFk7gzsy3OlA=; b=fbCBn0uyTKKLlEKGk85UtUOEljI3Kx6VesJZsPyMLdAZvui366ND7o3ed47WJK/POM 9hAfvFW/ONcTw7x6RvNSaOiNmckTlembwC6Hgdu93DqVnL/dzSGfawIwgrjWVp4U+Peo Z0lX6O575LYbSCnvEzn5Xb0DG+OpWwgHrJDiOEAI599/TLHbVQ6SBN4cvLDw53xgltG+ BlrNlrIhAnYjMRiRwaSMCbG8xaSzoxLn6C11HMX2QQhd/m6Z+mLHMw0IA0/a7fmqJlF6 OFax80LY2wnk75KR1PHNvtc1VLcObfp0twxtTjSG/rMVPsOpjgGSmR8eUSiotBbHMbO8 dM3w== X-Gm-Message-State: ABy/qLa4bb2CyJeUscn2zq/ZtxTG29+J9QYTmnXBnb8UVGWe8CLKBiGn pMZMtuG4tp0R/kqSQTBErSJF7A== X-Received: by 2002:a7b:c8cd:0:b0:3fc:5d2:1f47 with SMTP id f13-20020a7bc8cd000000b003fc05d21f47mr6559620wml.20.1689002493255; Mon, 10 Jul 2023 08:21:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v24-20020a05600c215800b003fa95f328afsm10578798wml.29.2023.07.10.08.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 08:21:32 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jean-Philippe Brucker , Richard Henderson Subject: [PATCH for-8.1 1/3] target/arm/ptw.c: Add comments to S1Translate struct fields Date: Mon, 10 Jul 2023 16:21:28 +0100 Message-Id: <20230710152130.3928330-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710152130.3928330-1-peter.maydell@linaro.org> References: <20230710152130.3928330-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Add comments to the in_* fields in the S1Translate struct that explain what they're doing. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- I figured some of this out when writing commit fcc0b0418fff, and then I found I'd forgotten it all when I was trying to fix this new bug. So this time I'm writing this down :-) --- target/arm/ptw.c | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9aaff1546a6..21749375f97 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -19,10 +19,50 @@ #endif typedef struct S1Translate { + /* + * in_mmu_idx : specifies which TTBR, TCR, etc to use for the walk. + * Together with in_space, specifies the architectural translation regime. + */ ARMMMUIdx in_mmu_idx; + /* + * in_ptw_idx: specifies which mmuidx to use for the actual + * page table descriptor load operations. This will be one of the + * ARMMMUIdx_Stage2* or one of the ARMMMUIdx_Phys_* indexes. + * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, + * this field is updated accordingly. + */ ARMMMUIdx in_ptw_idx; + /* + * in_space: the security space for this walk. This plus + * the in_mmu_idx specify the architectural translation regime. + * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, + * this field is updated accordingly. + * + * Note that the security space for the in_ptw_idx may be different + * from that for the in_mmu_idx. We do not need to explicitly track + * the in_ptw_idx security space because: + * - if the in_ptw_idx is an ARMMMUIdx_Phys_* then the mmuidx + * itself specifies the security space + * - if the in_ptw_idx is an ARMMMUIdx_Stage2* then the security + * space used for ptw reads is the same as that of the security + * space of the stage 1 translation for all cases except where + * stage 1 is Secure; in that case the only possibilities for + * the ptw read are Secure and NonSecure, and the in_ptw_idx + * value being Stage2 vs Stage2_S distinguishes those. + */ ARMSecuritySpace in_space; + /* + * in_secure: whether the translation regime is a Secure one. + * This is always equal to arm_space_is_secure(in_space). + * If a Secure ptw is "downgraded" to NonSecure by an NSTable bit, + * this field is updated accordingly. + */ bool in_secure; + /* + * in_debug: is this a QEMU debug access (gdbstub, etc)? Debug + * accesses will not update the guest page table access flags + * and will not change the state of the softmmu TLBs. + */ bool in_debug; /* * If this is stage 2 of a stage 1+2 page table walk, then this must From patchwork Mon Jul 10 15:21:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 701018 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp5236114wrs; Mon, 10 Jul 2023 08:22:20 -0700 (PDT) X-Google-Smtp-Source: APBJJlH6wX7GEjQoneS+2f7YgvE43WhH934DkaLmBCBwQ+o86CrPFdxTypFbOmYLQvjR6vUcY9Ya X-Received: by 2002:a05:620a:4089:b0:767:96e2:7dc with SMTP id f9-20020a05620a408900b0076796e207dcmr12207268qko.49.1689002540600; Mon, 10 Jul 2023 08:22:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689002540; cv=none; d=google.com; s=arc-20160816; b=ya0C1Uks0pQSgnuuKNATTj0YLX5ibJhGbNkRS7LkYQzr45MajylvAaRjU1h0Z2N0QV PZ/3air6FTcqy7yJIId5bWLlgWNumahLamWMQinvHo0KWDGuG+Mm0Pl7Eq6pv5f9E3i8 25GN4gSlcG1Lasf4VaxopSC0hvcJvtkh17Ytms7opxOqgvsBjYt9NtOBWdjC6p1TjIbH OODFYfrzzPctAsnTBnXa9Vb4w0oNrIU0wSqm8uD/XgI3/uflMVnOq3hYnXSNIfnsMOuP THDRXubaXft6Wfgu0/BTIRwOHtU3VGj0m8pYqfXw7ID/8rmycxtY9MN6HGTR3zlEvXJd SS3A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JoReB+bQetq/CZ2AVQqn0lg1rDXgEHC6Q4MrGNoc0WQ=; fh=DjFcf5x540nYnyRj+nrzzvmu8+sx0bTdo0fYzBaWDzs=; b=sh+QsszsSDstYifjyi0yXo3wPl7dTq+sIivZYEQBjvgqcBWM0mnu06ZQl9r/iy0pnR BpqRaUseXn3bpbTMIq8WPGSa4txU7XTFEAcynQWG8NX3vAxWNZBAk1QQo/ts9ppwagVm ph+pXsRvAYpsZkzXzJY6Gz6wPE+FHXwZWRNdd3fL2N0geF/v//fSIkwmDeksTFsQPUkt e4yaj0eRre9vE5elns6ZoD/KulAR6rwccgcJeloN1G7MNd5FRdN7Y4KfhQR2FurnVPls MeTRbEqv9vLidEapJMtOSRFARpw7nR/bBLVSRHMe54i91UkxJQwCuO7DmEeOpy+t+x/w 6pMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gBMAMEdp; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v24-20020a05600c215800b003fa95f328afsm10578798wml.29.2023.07.10.08.21.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 08:21:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jean-Philippe Brucker , Richard Henderson Subject: [PATCH for-8.1 2/3] target/arm: Fix S1_ptw_translate() debug path Date: Mon, 10 Jul 2023 16:21:29 +0100 Message-Id: <20230710152130.3928330-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710152130.3928330-1-peter.maydell@linaro.org> References: <20230710152130.3928330-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In commit XXX we rearranged the logic in S1_ptw_translate() so that the debug-access "call get_phys_addr_*" codepath is used both when S1 is doing ptw reads from stage 2 and when it is doing ptw reads from physical memory. However, we didn't update the calculation of s2ptw->in_space and s2ptw->in_secure to account for the "ptw reads from physical memory" case. This meant that debug accesses when in Secure state broke. Create a new function S2_security_space() which returns the correct security space to use for the ptw load, and use it to determine the correct .in_secure and .in_space fields for the stage 2 lookup for the ptw load. Reported-by: Jean-Philippe Brucker Fixes: fe4a5472ccd6 ("target/arm: Use get_phys_addr_with_struct in S1_ptw_translate") Signed-off-by: Peter Maydell Tested-by: Jean-Philippe Brucker Reviewed-by: Richard Henderson --- target/arm/ptw.c | 37 ++++++++++++++++++++++++++++++++----- 1 file changed, 32 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 21749375f97..c0b9cee5843 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -485,11 +485,39 @@ static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) } } +static ARMSecuritySpace S2_security_space(ARMSecuritySpace s1_space, + ARMMMUIdx s2_mmu_idx) +{ + /* + * Return the security space to use for stage 2 when doing + * the S1 page table descriptor load. + */ + if (regime_is_stage2(s2_mmu_idx)) { + /* + * The security space for ptw reads is almost always the same + * as that of the security space of the stage 1 translation. + * The only exception is when stage 1 is Secure; in that case + * the ptw read might be to the Secure or the NonSecure space + * (but never Realm or Root), and the s2_mmu_idx tells us which. + * Root translations are always single-stage. + */ + if (s1_space == ARMSS_Secure) { + return arm_secure_to_space(s2_mmu_idx == ARMMMUIdx_Stage2_S); + } else { + assert(s2_mmu_idx != ARMMMUIdx_Stage2_S); + assert(s1_space != ARMSS_Root); + return s1_space; + } + } else { + /* ptw loads are from phys: the mmu idx itself says which space */ + return arm_phys_to_space(s2_mmu_idx); + } +} + /* Translate a S1 pagetable walk through S2 if needed. */ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, hwaddr addr, ARMMMUFaultInfo *fi) { - ARMSecuritySpace space = ptw->in_space; bool is_secure = ptw->in_secure; ARMMMUIdx mmu_idx = ptw->in_mmu_idx; ARMMMUIdx s2_mmu_idx = ptw->in_ptw_idx; @@ -502,13 +530,12 @@ static bool S1_ptw_translate(CPUARMState *env, S1Translate *ptw, * From gdbstub, do not use softmmu so that we don't modify the * state of the cpu at all, including softmmu tlb contents. */ + ARMSecuritySpace s2_space = S2_security_space(ptw->in_space, s2_mmu_idx); S1Translate s2ptw = { .in_mmu_idx = s2_mmu_idx, .in_ptw_idx = ptw_idx_for_stage_2(env, s2_mmu_idx), - .in_secure = s2_mmu_idx == ARMMMUIdx_Stage2_S, - .in_space = (s2_mmu_idx == ARMMMUIdx_Stage2_S ? ARMSS_Secure - : space == ARMSS_Realm ? ARMSS_Realm - : ARMSS_NonSecure), + .in_secure = arm_space_is_secure(s2_space), + .in_space = s2_space, .in_debug = true, }; GetPhysAddrResult s2 = { }; From patchwork Mon Jul 10 15:21:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 701019 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp5236219wrs; Mon, 10 Jul 2023 08:22:35 -0700 (PDT) X-Google-Smtp-Source: APBJJlGMXgxZX69GRRoeauuUcnUq5chzc+jO9p77jxWIZ6v+KxsYx6r9L3cIRNkrcbn0yGTdo4jE X-Received: by 2002:a05:620a:2804:b0:75b:23a1:362e with SMTP id f4-20020a05620a280400b0075b23a1362emr14924083qkp.63.1689002554889; Mon, 10 Jul 2023 08:22:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1689002554; cv=none; d=google.com; s=arc-20160816; b=NgkMr/1kTQUJEsO2XKYXPyJl2iRjMToJ2hAnEI6gghu4o+tPSaUFvLd7ugeg/7/557 zvKHMZisKAi6g5ovAjfRnNOeIWNPc7+YWW/VoINkqtaDQ1e9eR+jbZi2Ycg+LXEawVDY fcHn6i3a7jhfiVV5ypCV9CAK/K4a/aZ0OcGJ7sQrJxiR7pi/1AEzuRkwiYlBkr5UmLM0 b1z4YMnRTgrYY02ZORYpyLfhj5AER9lvSftflQEzFvmGUPLPK5j9zb+6SqrKuWzdv4nB poN9+woby9/qeknSUteD/EHZ3eyFh/DxJPQlFpOQTbLGeoBx7sUCILFdFfCEhyQ7R5If 33FQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=d9OpS0FI8bXPcgU4kwQax5JMttcbv9wmKGoxNnD4iVQ=; fh=DjFcf5x540nYnyRj+nrzzvmu8+sx0bTdo0fYzBaWDzs=; b=roGqERAPmYouvdeZAG7g88qjW+ygsNWoKSrr4wNpbHxDjeXE4v7aWbJbgILCRm3b66 7GuKW21hZ9gtISrDp8nzKz9ShtPOEVQEMvanXNGCbTEZ7R47koMoBJqJE9B3DvHamTLy Krhus4jQUu4NdreMbXmbRLEo7NTSE8okQt0KELxy7Bx8GthkMora9vCxnlPoXo6mcEsz BUGS3eOTHLBy8qVg4S3fTIutYmZ1oJg8hzvNxqBFBbCekqbmvtAmtO9ch4UAehulutqv 2WQJtJGHzpaXX0UBbGEPxQxG2i3sNq+3VIz8UjTb1FCtF0jEa7t8VulsuyA2KM0kEjeI Z77A== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=VnD6288+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id v24-20020a05600c215800b003fa95f328afsm10578798wml.29.2023.07.10.08.21.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 10 Jul 2023 08:21:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Jean-Philippe Brucker , Richard Henderson Subject: [PATCH for-8.1 3/3] target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits Date: Mon, 10 Jul 2023 16:21:30 +0100 Message-Id: <20230710152130.3928330-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230710152130.3928330-1-peter.maydell@linaro.org> References: <20230710152130.3928330-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In get_phys_addr_twostage() the code that applies the effects of VSTCR.{SA,SW} and VTCR.{NSA,NSW} only updates result->f.attrs.secure. Now we also have f.attrs.space for FEAT_RME, we need to keep the two in sync. These bits only have an effect for Secure space translations, not for Root, so use the input in_space field to determine whether to apply them rather than the input is_secure. This doesn't actually make a difference because Root translations are never two-stage, but it's a little clearer. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- I noticed this while reading through the ptw code... --- target/arm/ptw.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index c0b9cee5843..8f94100c61f 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3118,6 +3118,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, hwaddr ipa; int s1_prot, s1_lgpgsz; bool is_secure = ptw->in_secure; + ARMSecuritySpace in_space = ptw->in_space; bool ret, ipa_secure; ARMCacheAttrs cacheattrs1; ARMSecuritySpace ipa_space; @@ -3200,11 +3201,13 @@ static bool get_phys_addr_twostage(CPUARMState *env, S1Translate *ptw, * Check if IPA translates to secure or non-secure PA space. * Note that VSTCR overrides VTCR and {N}SW overrides {N}SA. */ - result->f.attrs.secure = - (is_secure - && !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)) - && (ipa_secure - || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW)))); + if (in_space == ARMSS_Secure) { + result->f.attrs.secure = + !(env->cp15.vstcr_el2 & (VSTCR_SA | VSTCR_SW)) + && (ipa_secure + || !(env->cp15.vtcr_el2 & (VTCR_NSA | VTCR_NSW))); + result->f.attrs.space = arm_secure_to_space(result->f.attrs.secure); + } return false; }