From patchwork Wed Jun 26 14:46:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167806 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp870527ock; Wed, 26 Jun 2019 07:47:16 -0700 (PDT) X-Google-Smtp-Source: APXvYqxos+H5huphcST0W359plL4nAHdfuB6jSd7+8rzWFjp1k2paMIW4Dj0KYoIF48UvOCA6lL8 X-Received: by 2002:a17:90a:b30a:: with SMTP id d10mr5284101pjr.8.1561560436311; Wed, 26 Jun 2019 07:47:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560436; cv=none; d=google.com; s=arc-20160816; b=WvupYVqk0erxK9vkNteXQY7BgOqn7wJVpn8j43F9M3ofcKX9iYgiH84dXl3tTGV89p 2qRUBRevOOgFNdNQ8arL8xPmdnMvAQMdpOoPFZdgLqXP3uV90cPfK6nhznqo8AFOPNld 4GWq7QvbAO+eITVwH1Y25HiWdBQoh7V7pWyD3cPbBJ/gUcmalM8kK67rZlHYt0SmLFBe 1ZCARSwVGcouDP6gylNtZTTckvxhcBUzJdv54k0V70u5P1h1TODzqo8/38xATfOEVWb6 f4XLPe0kOEW8+N/CzoZ7/NPLHAyVtgqrNXvnyvVbXiuZFERs3EV0/Wgkg0NUpS29kGny iadw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=hAqxSgIO55AtglPI4y9BMkAp6zehdCTsbn3850+kcK0=; b=htxIDY+qHvvWJ3Pa/enn8sTGigc8EYIdva++lO2EnKSS2gmOwDIEAnWG+Ukve8cTti eF2jY9kKh4z4z21QAJEfcJYdqLvkJoSx//D3ULh/UZOZmGuKZPGEDPncKuLrD5UVuUFw bP0CFzSipJYEhZTYXcKju87MClbR5QhkIaPg03DOnBDSKnWq4ABkZki8IUcauYeuB7AH aLIhCjZ4ufn+zjcbMnj4kZ40Hmmg6WkQ+i8qif/4hOZYHVADZ4+G2vqBJVz9uVYSIVx6 A+y8u468S1IxUGqKSXLxg/b8ei/SXdqBDoaYFkb8j2iEwTwnFGSzkCIYWP0eYjbYZg2k 9KwQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=I8is5qvO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.10 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:11 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Neil Armstrong , Kevin Hilman , linux-arm-kernel@lists.infradead.org (moderated list:ARM/Amlogic Meson SoC support), linux-amlogic@lists.infradead.org (open list:ARM/Amlogic Meson SoC support) Subject: [PATCH 01/25] clocksource/drivers/timer-meson6: Update with SPDX Licence identifier Date: Wed, 26 Jun 2019 16:46:27 +0200 Message-Id: <20190626144651.16742-1-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: References: Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Neil Armstrong Comply with the licensing rules defined in the documentation. Signed-off-by: Neil Armstrong Reviewed-by: Martin Blumenstingl Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-meson6.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-meson6.c b/drivers/clocksource/timer-meson6.c index 84bd9479c3f8..9e8b467c71da 100644 --- a/drivers/clocksource/timer-meson6.c +++ b/drivers/clocksource/timer-meson6.c @@ -1,13 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* * Amlogic Meson6 SoCs timer handling. * * Copyright (C) 2014 Carlo Caione * * Based on code from Amlogic, Inc - * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include From patchwork Wed Jun 26 14:46:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167807 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp870578ock; Wed, 26 Jun 2019 07:47:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqz/zR7H1/4I154H5GgWqtdTWLBmOiWwz3sRU0UurA/MxTXmqjpAL4xCmlLu1goKGGW0Snan X-Received: by 2002:a17:90a:32ed:: with SMTP id l100mr5163616pjb.11.1561560440252; Wed, 26 Jun 2019 07:47:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560440; cv=none; d=google.com; s=arc-20160816; b=ZsbiNF8D0Fq2T1oqYfaAqjQuimMps+FEldEJ9Nf05zIG0N3WzqkaD32edk/+OzFgp0 NNIFujpmYdzwv6xSVaRPZbqK9uQhL1s9tJOiBD39ZJcZ2tVJtzZ1RWo93YlYVvczLBrr PW0ql66f/0vMZw1w7uPlEXKDIO07cFXG/8AhjVpAkDO9ieH76MeiCDYXPMnnQgM9R/k6 z9+Gv0aofpu3/KjB24WB18Nt2NhiNIQ5poeRT2pA0OcMtsUrfh5cHBusibefN05ERjfb BoDLWASpWITKzhq4y5JXD+WQ3ltKmTgpZoEzfVLd3wAPhCICmsPdOm2n0aVf5wj7zjJs uMkQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=WDX9H0FW6Px0pSdZdykt6dt3zN2IzeMqp5Ci6/xL3gc=; b=wGc8Thr0bBe7t7C0pxGfPwilkG2ix7u9Oj+4gLJW2IC9WzcOdZhHFab57wAdnAJZ9j hgJTlWD6E8LbX+XD+cOxsf3bmJCDGW/OQpTWSaG3QWF68m2PS1FD5gDww5Z2fD3ayXOh PgXsYE/AhpMY1zBD56GBUSC8qnBxKY0a+29e7hDUHUI/XL3vEXpdVfVWg3OeuzqCuYHw h01Ve98/vcAgArP+a+qW8TEZtBz80+aBKBkjOybRlZvLyvFpjBjPNCYqsZHYuYtuNZ6K zxk/acsX0M4DBJIundW05Zi6LQmq2eoREIlo+SNhibpWc1bhq/+admbwJNOVYuXdcScL 6Z+A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="o/YR4KLn"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.12 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:13 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Linus Walleij , Linus Walleij , Imre Kaloz , Krzysztof Halasa , linux-arm-kernel@lists.infradead.org (moderated list:ARM/INTEL IXP4XX ARM ARCHITECTURE) Subject: [PATCH 02/25] clocksource/drivers/ixp4xx: Implement delay timer Date: Wed, 26 Jun 2019 16:46:28 +0200 Message-Id: <20190626144651.16742-2-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Linus Walleij This adds delay timer functionality to the IXP4xx timer driver. Signed-off-by: Linus Walleij Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-ixp4xx.c | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-ixp4xx.c b/drivers/clocksource/timer-ixp4xx.c index 5c2190b654cd..9396745e1c17 100644 --- a/drivers/clocksource/timer-ixp4xx.c +++ b/drivers/clocksource/timer-ixp4xx.c @@ -75,14 +75,19 @@ to_ixp4xx_timer(struct clock_event_device *evt) return container_of(evt, struct ixp4xx_timer, clkevt); } -static u64 notrace ixp4xx_read_sched_clock(void) +static unsigned long ixp4xx_read_timer(void) { return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET); } +static u64 notrace ixp4xx_read_sched_clock(void) +{ + return ixp4xx_read_timer(); +} + static u64 ixp4xx_clocksource_read(struct clocksource *c) { - return __raw_readl(local_ixp4xx_timer->base + IXP4XX_OSTS_OFFSET); + return ixp4xx_read_timer(); } static irqreturn_t ixp4xx_timer_interrupt(int irq, void *dev_id) @@ -224,6 +229,13 @@ static __init int ixp4xx_timer_register(void __iomem *base, sched_clock_register(ixp4xx_read_sched_clock, 32, timer_freq); +#ifdef CONFIG_ARM + /* Also use this timer for delays */ + tmr->delay_timer.read_current_timer = ixp4xx_read_timer; + tmr->delay_timer.freq = timer_freq; + register_current_timer_delay(&tmr->delay_timer); +#endif + return 0; } From patchwork Wed Jun 26 14:46:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167808 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp870639ock; Wed, 26 Jun 2019 07:47:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqxswgRZwkhSTzvAwA/6sROcne7ECDhGAvzUMd6OAp6wjFnjibFHYmUvz4iJ6uQefh8MyT9T X-Received: by 2002:a17:902:ba82:: with SMTP id k2mr6114471pls.323.1561560443274; Wed, 26 Jun 2019 07:47:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560443; cv=none; d=google.com; s=arc-20160816; b=Q3L9/KLAzZJ2qfoBJUNaosYJKhUTzXdTUqjn4lrSC3zBsTFUqXlN64Oj0CbwubTE5A TRlmJGag3gdl7JaKFtDHAzJw9Ze7oW3Kd9qoAGEQ615LgRImTUD3WSaCWWaQSW5VPecf vC3h+xlqDIsOTJmuKAbNcWwAtyOrzhlcVQuA8s3fy/XiLAmsyeJrl1YLRl27suZCPCYk RYyIa7PL9KwrzdakkUIlLZNNYHVUBiH5+LtrJoEEsuETvHHiPZ3rwoi1W41iUw5DNOJT vtbjZEOlNC1KhjhsnD16s6o+8tPOWa1TQhr8ttlMTMxhW6MoToZChs6hiODHyXNgGtdC jI6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=fNYOymAKKEH/tI650TaMtzoROF9PuK3S14KyC5Y7dck=; b=HFd5HFIJm47DHgyl1wgYzbb86HW1CPF3RKCqh120nP06J3rNQiOUgyfMyU5RKDfzPZ v8RdJl5CeVMoeXwgfCFGyDdI4C11iwm7n70nUev0ftm6o3kFoqpaI5Q6LRGdwDr1oXYK jEoDj4pCi4uuQwxuf0BGGUKP1f6fXfknIJhWw9nLitQV01p94RWoxQr6+AIpiaFIELjr 2xon5k2re/oB3mEWqioaYNWSch0bmxNcA6CYMK6Let0+FdiiYHydDu7fnwJJkqPHnN6J qV7xDkGYXm30+xP4B/3iM1/a5ObI/zaSLnbavpBbCXHStzxP6wNqHWyCLxP1bVMnbmq/ i0AQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=h2BSh+mB; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:14 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Masahiro Yamada , Vineet Gupta , linux-snps-arc@lists.infradead.org (open list:SYNOPSYS ARC ARCHITECTURE) Subject: [PATCH 03/25] clocksource/drivers/arc_timer: Use BIT() instead of _BITUL() Date: Wed, 26 Jun 2019 16:46:29 +0200 Message-Id: <20190626144651.16742-3-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Masahiro Yamada This is in-kernel C code, so there is no reason to use _BITUL(). Replace it with equivalent BIT(). I added #include explicitly although it has been included by other headers eventually. Signed-off-by: Masahiro Yamada Signed-off-by: Daniel Lezcano --- drivers/clocksource/arc_timer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/clocksource/arc_timer.c b/drivers/clocksource/arc_timer.c index b28970ca4a7a..b1f21bf3b83c 100644 --- a/drivers/clocksource/arc_timer.c +++ b/drivers/clocksource/arc_timer.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include @@ -142,7 +143,7 @@ static u64 arc_read_rtc(struct clocksource *cs) l = read_aux_reg(AUX_RTC_LOW); h = read_aux_reg(AUX_RTC_HIGH); status = read_aux_reg(AUX_RTC_CTRL); - } while (!(status & _BITUL(31))); + } while (!(status & BIT(31))); return (((u64)h) << 32) | l; } From patchwork Wed Jun 26 14:46:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167809 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp870677ock; Wed, 26 Jun 2019 07:47:25 -0700 (PDT) X-Google-Smtp-Source: APXvYqymmASdoiB2iX8kMLw1532c3FpOC2zDQXnlczObNr0TEBqUCBVg6pwLG3qU7tTZ6PGy3mJj X-Received: by 2002:a17:902:a60d:: with SMTP id u13mr6006520plq.144.1561560445809; Wed, 26 Jun 2019 07:47:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560445; cv=none; d=google.com; s=arc-20160816; b=lICcw3TiOQax4essEPBHoeE8Ph3g/6pYD4Eq2m3b5hplDL+p8oVVxaI5v01H5Whw5H dUqHuhSua4742ne4+W+9bePY7cUv+otaYxhmeQ3OdmsOobIPeeOSry6jgXrB82AaLqCp OfLeV0XsBrCVAyYh5KIYXarq7+KOJTd2ACAal87jm20mcE+VIKeS5MbgC/gMIsWajnjT AtN4N23im0p3M4YUgcRgkB7SSFtPD0KOTkmU25e+3yS6ftiGHSBbaAeY3VEBgb8u+N5K vrh6CjCFBPDeuNGAyP0WA3EYmcuu+M6KYRNxeJoiM9tgJ5H9tCxFwC2G1cTEKPZX3JLa Y/lQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=GnURz9uBDl/JIVDRIJyHSxWewLcsuwU4f5F+HbyZmEk=; b=yqlC597C39TYi7NpHBit8IXOPehRGve6N6ykmQQauY50HD03GBVT315OoMXckkGzWT WVhHf+GXI1ZHr3TUpxGlbTJWDJdKkcmf/0we6z83lDvPTulUAn8SNYAOl6Hx8FUvRHou oQGc23UuPB/NDRbuuSz9EmJ6XJNYKD3pbxcn+Hgw43bYchtOoDgZ7MK30VlIOkLJwLRL if7AFJsDNJ4sCMPwJt3EqeLZQp0wuVt9V4VH1Ma+EsWcNBM9GGExx0k9JQg98Ho1UXiL il6zerkRTqrmfTEypCqJb5zj4q+oLDIsbPjRg70Ifdc8qS1vV2PyEOpUlMKWmnDPdTWS 1o3A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KQ5btisT; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:17 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Marek Szyprowski , Kukjin Kim , Krzysztof Kozlowski , Will Deacon , Palmer Dabbelt , Borislav Petkov , "Rafael J. Wysocki" , Lucas Stach , "Kulkarni, Ganapatrao" , Peter Zijlstra , Guo Ren , Joseph Lo , Anju T Sudhakar , Hoan Tran , linux-arm-kernel@lists.infradead.org (moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES), linux-samsung-soc@vger.kernel.org (moderated list:ARM/SAMSUNG EXYNOS ARM ARCHITECTURES) Subject: [PATCH 04/25] clocksource/drivers/exynos_mct: Increase priority over ARM arch timer Date: Wed, 26 Jun 2019 16:46:30 +0200 Message-Id: <20190626144651.16742-4-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Marek Szyprowski Exynos SoCs based on CA7/CA15 have 2 timer interfaces: custom Exynos MCT (Multi Core Timer) and standard ARM Architected Timers. There are use cases, where both timer interfaces are used simultanously. One of such examples is using Exynos MCT for the main system timer and ARM Architected Timers for the KVM and virtualized guests (KVM requires arch timers). Exynos Multi-Core Timer driver (exynos_mct) must be however started before ARM Architected Timers (arch_timer), because they both share some common hardware blocks (global system counter) and turning on MCT is needed to get ARM Architected Timer working properly. To ensure selecting Exynos MCT as the main system timer, increase MCT timer rating. To ensure proper starting order of both timers during suspend/resume cycle, increase MCT hotplug priority over ARM Archictected Timers. Signed-off-by: Marek Szyprowski Reviewed-by: Krzysztof Kozlowski Reviewed-by: Chanwoo Choi Signed-off-by: Daniel Lezcano --- drivers/clocksource/exynos_mct.c | 4 ++-- include/linux/cpuhotplug.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/exynos_mct.c b/drivers/clocksource/exynos_mct.c index 34bd250d46c6..6aa10cbc1d59 100644 --- a/drivers/clocksource/exynos_mct.c +++ b/drivers/clocksource/exynos_mct.c @@ -209,7 +209,7 @@ static void exynos4_frc_resume(struct clocksource *cs) static struct clocksource mct_frc = { .name = "mct-frc", - .rating = 400, + .rating = 450, /* use value higher than ARM arch timer */ .read = exynos4_frc_read, .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS, @@ -464,7 +464,7 @@ static int exynos4_mct_starting_cpu(unsigned int cpu) evt->set_state_oneshot_stopped = set_state_shutdown; evt->tick_resume = set_state_shutdown; evt->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT; - evt->rating = 450; + evt->rating = 500; /* use value higher than ARM arch timer */ exynos4_mct_write(TICK_BASE_CNT, mevt->base + MCT_L_TCNTB_OFFSET); diff --git a/include/linux/cpuhotplug.h b/include/linux/cpuhotplug.h index 5c6062206760..87c211adf49e 100644 --- a/include/linux/cpuhotplug.h +++ b/include/linux/cpuhotplug.h @@ -116,10 +116,10 @@ enum cpuhp_state { CPUHP_AP_PERF_ARM_ACPI_STARTING, CPUHP_AP_PERF_ARM_STARTING, CPUHP_AP_ARM_L2X0_STARTING, + CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, CPUHP_AP_ARM_ARCH_TIMER_STARTING, CPUHP_AP_ARM_GLOBAL_TIMER_STARTING, CPUHP_AP_JCORE_TIMER_STARTING, - CPUHP_AP_EXYNOS4_MCT_TIMER_STARTING, CPUHP_AP_ARM_TWD_STARTING, CPUHP_AP_QCOM_TIMER_STARTING, CPUHP_AP_TEGRA_TIMER_STARTING, From patchwork Wed Jun 26 14:46:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167810 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp870714ock; Wed, 26 Jun 2019 07:47:28 -0700 (PDT) X-Google-Smtp-Source: APXvYqz5q1QiltUjCq18Fwos0GhJdrI7vltUcXX9cIlq6aFiMPemKcvxMNiL+sj0axnUYi3PTK0w X-Received: by 2002:a17:90a:4f0e:: with SMTP id p14mr5052093pjh.40.1561560447893; Wed, 26 Jun 2019 07:47:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560447; cv=none; d=google.com; s=arc-20160816; b=g87HV4aS7wvXshViYL+5w2fzOPMEEnwJEppeqgB0quFRYEUaaE0syy/vn37RCAjLuL TeT3GKadLIsUVTLCxeOdN2CaYTU9j33wa1P3QccKg/X4N0r+AKoeRYuy81zs/t0dQ++p F3p6FdOf36rq6MezzFEfpnKQzBYTm+SShpE0I5pa/rZMf9BvlI96MbNyZ0i9mvlRZj/8 HUvR5wg6CAH/2C/rwhvqFAJiZCryMvhMOFXlb64hxVS4fJ4ksQ8WmSf2DoGpmRIUEXLY NMjd5RsVkp5/fYaSmpX+PtTrPDH4H/V6qfihICTi7W83mZZUb0xT3cOfuSaqp9DyWUmM F8EA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=pCTMtso5AmHagoM0kbPRWJWMA6Wb3OobegULM1kp5BM=; b=UH5b3q1HSZcwzfeYCFQ8JFn4ywAkBDGCODebOiT97G7PC+XWWokdgfeV6ebapMZwO9 crInf8yLSqhqO01MbSToLq0NXsbgcTXtFsh9mmmGFK8Dm5y/1vRKpJUOFmLZwEwS3QO2 YUuWB9kMVHYcQis7okoFTiYP08II709dkMuHP2nTCGLpXqCd9/2NX4bBXinKYtrM+AOb DmBshg4u41cLik8cKC1vGPxvzbN03QWz+emFXgf3N08ulAnoGboHsZd6OLQaiYgNeYrx C0BE+fqg/8eWR9MRHejkUveLK2OSrGg0YJIKWNJ0D+jdxDgbt8mK6T/fsxviEXr2PIyg awcA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aTMI536E; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.18 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:19 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 05/25] clocksource/drivers/tegra: Support per-CPU timers on all Tegra's Date: Wed, 26 Jun 2019 16:46:31 +0200 Message-Id: <20190626144651.16742-5-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko Assign TMR1-4 per-CPU core on 32bit Tegra's in a way it is done for Tegra210. In a result each core can handle its own timer events, less code is unique to ARM64 and Tegra's clock events driver now has higher rating on all Tegra's, replacing the ARM's TWD timer which isn't very accurate due to the clock rate jitter caused by CPU frequency scaling. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 120 ++++++++++------------------ 1 file changed, 43 insertions(+), 77 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 1e7ece279730..4b30ba6228c1 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -40,13 +40,18 @@ #define TIMER_PCR_INTR_CLR BIT(30) #ifdef CONFIG_ARM -#define TIMER_CPU0 0x50 /* TIMER3 */ +#define TIMER_CPU0 0x00 /* TIMER1 */ +#define TIMER_CPU2 0x50 /* TIMER3 */ +#define TIMER1_IRQ_IDX 0 +#define IRQ_IDX_FOR_CPU(cpu) (TIMER1_IRQ_IDX + cpu) +#define TIMER_BASE_FOR_CPU(cpu) \ + (((cpu) & 1) * 8 + ((cpu) < 2 ? TIMER_CPU0 : TIMER_CPU2)) #else #define TIMER_CPU0 0x90 /* TIMER10 */ #define TIMER10_IRQ_IDX 10 #define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) -#endif #define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8) +#endif static u32 usec_config; static void __iomem *timer_reg_base; @@ -109,7 +114,6 @@ static void tegra_timer_resume(struct clock_event_device *evt) writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); } -#ifdef CONFIG_ARM64 static DEFINE_PER_CPU(struct timer_of, tegra_to) = { .flags = TIMER_OF_CLOCK | TIMER_OF_BASE, @@ -150,33 +154,8 @@ static int tegra_timer_stop(unsigned int cpu) return 0; } -#else /* CONFIG_ARM */ -static struct timer_of tegra_to = { - .flags = TIMER_OF_CLOCK | TIMER_OF_BASE | TIMER_OF_IRQ, - - .clkevt = { - .name = "tegra_timer", - .rating = 300, - .features = CLOCK_EVT_FEAT_ONESHOT | - CLOCK_EVT_FEAT_PERIODIC | - CLOCK_EVT_FEAT_DYNIRQ, - .set_next_event = tegra_timer_set_next_event, - .set_state_shutdown = tegra_timer_shutdown, - .set_state_periodic = tegra_timer_set_periodic, - .set_state_oneshot = tegra_timer_shutdown, - .tick_resume = tegra_timer_shutdown, - .suspend = tegra_timer_suspend, - .resume = tegra_timer_resume, - .cpumask = cpu_possible_mask, - }, - - .of_irq = { - .index = 2, - .flags = IRQF_TIMER | IRQF_TRIGGER_HIGH, - .handler = tegra_timer_isr, - }, -}; +#ifdef CONFIG_ARM static u64 notrace tegra_read_sched_clock(void) { return readl(timer_reg_base + TIMERUS_CNTR_1US); @@ -213,10 +192,12 @@ static struct clocksource suspend_rtc_clocksource = { }; #endif -static int tegra_timer_common_init(struct device_node *np, struct timer_of *to) +static int tegra_init_timer(struct device_node *np, bool tegra20) { - int ret = 0; + struct timer_of *to; + int cpu, ret; + to = this_cpu_ptr(&tegra_to); ret = timer_of_init(np, to); if (ret < 0) goto out; @@ -258,29 +239,19 @@ static int tegra_timer_common_init(struct device_node *np, struct timer_of *to) goto out; } - writel(usec_config, timer_of_base(to) + TIMERUS_USEC_CFG); - -out: - return ret; -} - -#ifdef CONFIG_ARM64 -static int __init tegra_init_timer(struct device_node *np) -{ - int cpu, ret = 0; - struct timer_of *to; - - to = this_cpu_ptr(&tegra_to); - ret = tegra_timer_common_init(np, to); - if (ret < 0) - goto out; + writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); for_each_possible_cpu(cpu) { - struct timer_of *cpu_to; + struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); + + /* + * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the + * parent clock. + */ + if (tegra20) + cpu_to->of_clk.rate = 1000000; - cpu_to = per_cpu_ptr(&tegra_to, cpu); cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu); - cpu_to->of_clk.rate = timer_of_rate(to); cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->clkevt.irq = irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu)); @@ -322,43 +293,39 @@ static int __init tegra_init_timer(struct device_node *np) timer_of_cleanup(to); return ret; } + +#ifdef CONFIG_ARM64 +static int __init tegra210_init_timer(struct device_node *np) +{ + return tegra_init_timer(np, false); +} +TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); #else /* CONFIG_ARM */ -static int __init tegra_init_timer(struct device_node *np) +static int __init tegra20_init_timer(struct device_node *np) { - int ret = 0; + struct timer_of *to; + int err; - ret = tegra_timer_common_init(np, &tegra_to); - if (ret < 0) - goto out; + err = tegra_init_timer(np, true); + if (err) + return err; - tegra_to.of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(0); - tegra_to.of_clk.rate = 1000000; /* microsecond timer */ + to = this_cpu_ptr(&tegra_to); sched_clock_register(tegra_read_sched_clock, 32, - timer_of_rate(&tegra_to)); - ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", timer_of_rate(&tegra_to), + timer_of_rate(to)); + err = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, + "timer_us", timer_of_rate(to), 300, 32, clocksource_mmio_readl_up); - if (ret) { - pr_err("Failed to register clocksource\n"); - goto out; - } + if (err) + pr_err("Failed to register clocksource: %d\n", err); tegra_delay_timer.read_current_timer = tegra_delay_timer_read_counter_long; - tegra_delay_timer.freq = timer_of_rate(&tegra_to); + tegra_delay_timer.freq = timer_of_rate(to); register_current_timer_delay(&tegra_delay_timer); - clockevents_config_and_register(&tegra_to.clkevt, - timer_of_rate(&tegra_to), - 0x1, - 0x1fffffff); - - return ret; -out: - timer_of_cleanup(&tegra_to); - - return ret; + return 0; } static int __init tegra20_init_rtc(struct device_node *np) @@ -374,6 +341,5 @@ static int __init tegra20_init_rtc(struct device_node *np) return 0; } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); #endif -TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra_init_timer); -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra_init_timer); From patchwork Wed Jun 26 14:46:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167830 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp872552ock; Wed, 26 Jun 2019 07:49:10 -0700 (PDT) X-Google-Smtp-Source: APXvYqyOMNANfcp5jKGb2Zf6v6wzz2Mk+B7gVZ4871ShgmDvqPJYK1ZHxdFnRiw3/F3sQ6IZFVrV X-Received: by 2002:a17:902:724:: with SMTP id 33mr5810047pli.49.1561560549902; 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:20 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 06/25] clocksource/drivers/tegra: Unify timer code Date: Wed, 26 Jun 2019 16:46:32 +0200 Message-Id: <20190626144651.16742-6-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko Tegra132 is 64bit platform and it has the tegra20-timer hardware unit. Right now the corresponding timer code isn't compiled for ARM64, remove ifdef'iness from the code and compile tegra20-timer for both 32 and 64 bit platforms. Also note that like the older generations, Tegra210 has the microseconds counter, hence the timer_us clocksource is now made available for Tegra210 as well. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 111 +++++++++++++++------------- 1 file changed, 60 insertions(+), 51 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 4b30ba6228c1..acd68c77fa91 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -21,10 +21,6 @@ #include "timer-of.h" -#ifdef CONFIG_ARM -#include -#endif - #define RTC_SECONDS 0x08 #define RTC_SHADOW_SECONDS 0x0c #define RTC_MILLISECONDS 0x10 @@ -39,25 +35,17 @@ #define TIMER_PCR 0x4 #define TIMER_PCR_INTR_CLR BIT(30) -#ifdef CONFIG_ARM -#define TIMER_CPU0 0x00 /* TIMER1 */ -#define TIMER_CPU2 0x50 /* TIMER3 */ +#define TIMER1_BASE 0x00 +#define TIMER2_BASE 0x08 +#define TIMER3_BASE 0x50 +#define TIMER4_BASE 0x58 +#define TIMER10_BASE 0x90 + #define TIMER1_IRQ_IDX 0 -#define IRQ_IDX_FOR_CPU(cpu) (TIMER1_IRQ_IDX + cpu) -#define TIMER_BASE_FOR_CPU(cpu) \ - (((cpu) & 1) * 8 + ((cpu) < 2 ? TIMER_CPU0 : TIMER_CPU2)) -#else -#define TIMER_CPU0 0x90 /* TIMER10 */ #define TIMER10_IRQ_IDX 10 -#define IRQ_IDX_FOR_CPU(cpu) (TIMER10_IRQ_IDX + cpu) -#define TIMER_BASE_FOR_CPU(cpu) (TIMER_CPU0 + (cpu) * 8) -#endif static u32 usec_config; static void __iomem *timer_reg_base; -#ifdef CONFIG_ARM -static struct delay_timer tegra_delay_timer; -#endif static int tegra_timer_set_next_event(unsigned long cycles, struct clock_event_device *evt) @@ -155,17 +143,23 @@ static int tegra_timer_stop(unsigned int cpu) return 0; } -#ifdef CONFIG_ARM static u64 notrace tegra_read_sched_clock(void) { return readl(timer_reg_base + TIMERUS_CNTR_1US); } +#ifdef CONFIG_ARM static unsigned long tegra_delay_timer_read_counter_long(void) { return readl(timer_reg_base + TIMERUS_CNTR_1US); } +static struct delay_timer tegra_delay_timer = { + .read_current_timer = tegra_delay_timer_read_counter_long, + .freq = 1000000, +}; +#endif + static struct timer_of suspend_rtc_to = { .flags = TIMER_OF_BASE | TIMER_OF_CLOCK, }; @@ -190,9 +184,34 @@ static struct clocksource suspend_rtc_clocksource = { .mask = CLOCKSOURCE_MASK(32), .flags = CLOCK_SOURCE_IS_CONTINUOUS | CLOCK_SOURCE_SUSPEND_NONSTOP, }; -#endif -static int tegra_init_timer(struct device_node *np, bool tegra20) +static inline unsigned int tegra_base_for_cpu(int cpu, bool tegra20) +{ + if (tegra20) { + switch (cpu) { + case 0: + return TIMER1_BASE; + case 1: + return TIMER2_BASE; + case 2: + return TIMER3_BASE; + default: + return TIMER4_BASE; + } + } + + return TIMER10_BASE + cpu * 8; +} + +static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20) +{ + if (tegra20) + return TIMER1_IRQ_IDX + cpu; + + return TIMER10_IRQ_IDX + cpu; +} + +static int __init tegra_init_timer(struct device_node *np, bool tegra20) { struct timer_of *to; int cpu, ret; @@ -243,6 +262,8 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) for_each_possible_cpu(cpu) { struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); + unsigned int base = tegra_base_for_cpu(cpu, tegra20); + unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20); /* * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the @@ -251,10 +272,10 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) if (tegra20) cpu_to->of_clk.rate = 1000000; - cpu_to->of_base.base = timer_reg_base + TIMER_BASE_FOR_CPU(cpu); + cpu_to = per_cpu_ptr(&tegra_to, cpu); + cpu_to->of_base.base = timer_reg_base + base; cpu_to->clkevt.cpumask = cpumask_of(cpu); - cpu_to->clkevt.irq = - irq_of_parse_and_map(np, IRQ_IDX_FOR_CPU(cpu)); + cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); if (!cpu_to->clkevt.irq) { pr_err("%s: can't map IRQ for CPU%d\n", __func__, cpu); @@ -274,6 +295,18 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) } } + sched_clock_register(tegra_read_sched_clock, 32, 1000000); + + ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, + "timer_us", 1000000, + 300, 32, clocksource_mmio_readl_up); + if (ret) + pr_err("failed to register clocksource: %d\n", ret); + +#ifdef CONFIG_ARM + register_current_timer_delay(&tegra_delay_timer); +#endif + cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, tegra_timer_stop); @@ -294,39 +327,17 @@ static int tegra_init_timer(struct device_node *np, bool tegra20) return ret; } -#ifdef CONFIG_ARM64 static int __init tegra210_init_timer(struct device_node *np) { return tegra_init_timer(np, false); } TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); -#else /* CONFIG_ARM */ + static int __init tegra20_init_timer(struct device_node *np) { - struct timer_of *to; - int err; - - err = tegra_init_timer(np, true); - if (err) - return err; - - to = this_cpu_ptr(&tegra_to); - - sched_clock_register(tegra_read_sched_clock, 32, - timer_of_rate(to)); - err = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", timer_of_rate(to), - 300, 32, clocksource_mmio_readl_up); - if (err) - pr_err("Failed to register clocksource: %d\n", err); - - tegra_delay_timer.read_current_timer = - tegra_delay_timer_read_counter_long; - tegra_delay_timer.freq = timer_of_rate(to); - register_current_timer_delay(&tegra_delay_timer); - - return 0; + return tegra_init_timer(np, true); } +TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); static int __init tegra20_init_rtc(struct device_node *np) { @@ -341,5 +352,3 @@ static int __init tegra20_init_rtc(struct device_node *np) return 0; } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); -TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); -#endif From patchwork Wed Jun 26 14:46:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167811 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp870753ock; Wed, 26 Jun 2019 07:47:30 -0700 (PDT) X-Google-Smtp-Source: APXvYqzW4kjCWznXd5uvNDopyZRPvYTUbMyW1zz5K9hSBWo7xj4E6PjVD5sS9HaE3gWvObFSAjT4 X-Received: by 2002:a17:90b:f0e:: with SMTP id br14mr5161395pjb.117.1561560450719; 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:23 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 07/25] clocksource/drivers/tegra: Reset hardware state on init Date: Wed, 26 Jun 2019 16:46:33 +0200 Message-Id: <20190626144651.16742-7-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko Reset timer's hardware state to ensure that initially it is in a predictable state. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 3 +++ 1 file changed, 3 insertions(+) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index acd68c77fa91..3e4f12aee8df 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -123,6 +123,9 @@ static int tegra_timer_setup(unsigned int cpu) { struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); + writel(0, timer_of_base(to) + TIMER_PTV); + writel(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); + irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); enable_irq(to->clkevt.irq); From patchwork Wed Jun 26 14:46:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167812 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp870807ock; Wed, 26 Jun 2019 07:47:34 -0700 (PDT) X-Google-Smtp-Source: APXvYqxO59lq0VHpn+1tlBPbR0ccw3tLuaq/FjGTLTDS6IOsKIkJKCYzSi8TUWNOJn5fktz0Opqe X-Received: by 2002:a17:902:42d:: with SMTP id 42mr5699534ple.228.1561560453947; Wed, 26 Jun 2019 07:47:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560453; cv=none; d=google.com; s=arc-20160816; b=YlttfiTGIOMt53aF18n11bYhJA90jL50K7kAIKGPm5vTiL9Da3Z6YgRckSELV9hKEy PujXYvNR50htgSKZuHheX6IGLULTYDLWPSuqujAixbDXEqtsDVaqnvxwEjDWQFdy3S6x IPo2dMER7nQFDXdUdV/EMsqKqAr7LqTc1B2+csM/pPDEQVlHDf2FtP0hhQjr10x5WKza VhtFwF0Emdm4aus8xEnyTic6rnMMcny6uf2jyk4/gvZkAEfEmaou6k8lX3gA1WCf5oXN XxPVJNf7lDBMjK7gAQX9C9SdtEPaFUsOO1BId1DeB+YwJc43dm9JHf9az73piPWOjMMQ KAHg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=g8xq5QdzKn63u1M0EUnZlEgWbt3e6x6fUijd7UtCicQ=; b=0Sk17w1srqPdP2CwYaWCROcCHOpKbkY6EHw4altYNNJZhBotL3Um0jwa1g4NaUm3Xy S1Po1JhqUADxUVOiyj6EkTr8wVSjwL+EyA7GgBCxrqi7T/VB2WRtH7pY7ZWHdcVIqR0K /FyuDCcIqJSZbiH3ipKkDkRL9hbH9eYDPjF9+A0nHpLSX2znERWjVjAanjegxzGINIbr woK/V1ucVOcmwzG7g+CdCgbEODMhrb8g1J6PcPQFsq6EwpJDCMaEWtOqaEuOK/1zxKhk msZJMc4DUV7ZVNsv0qnQkh653vvbho4/60EtxfXWGeV5jHLASqdiYhEZ5O4O9XFhH3b2 id9A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UVaPVeuQ; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:24 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 08/25] clocksource/drivers/tegra: Replace readl/writel with relaxed versions Date: Wed, 26 Jun 2019 16:46:34 +0200 Message-Id: <20190626144651.16742-8-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko The readl/writel functions are inserting memory barrier to ensure that outstanding memory writes are completed, this results in L2 cache syncing being done on Tegra20 and Tegra30 which isn't a very cheap operation. Replace all readl/writel occurrences in the code with the relaxed versions since there is no need for the memory-access syncing. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 35 +++++++++++++++-------------- 1 file changed, 18 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 3e4f12aee8df..276b55f6ada0 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -52,9 +52,9 @@ static int tegra_timer_set_next_event(unsigned long cycles, { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PTV_EN | - ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ - reg_base + TIMER_PTV); + writel_relaxed(TIMER_PTV_EN | + ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ + reg_base + TIMER_PTV); return 0; } @@ -63,7 +63,7 @@ static int tegra_timer_shutdown(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(0, reg_base + TIMER_PTV); + writel_relaxed(0, reg_base + TIMER_PTV); return 0; } @@ -72,9 +72,9 @@ static int tegra_timer_set_periodic(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PTV_EN | TIMER_PTV_PER | - ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), - reg_base + TIMER_PTV); + writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | + ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), + reg_base + TIMER_PTV); return 0; } @@ -84,7 +84,7 @@ static irqreturn_t tegra_timer_isr(int irq, void *dev_id) struct clock_event_device *evt = (struct clock_event_device *)dev_id; void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); evt->event_handler(evt); return IRQ_HANDLED; @@ -94,12 +94,12 @@ static void tegra_timer_suspend(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); + writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); } static void tegra_timer_resume(struct clock_event_device *evt) { - writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); + writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); } static DEFINE_PER_CPU(struct timer_of, tegra_to) = { @@ -123,8 +123,8 @@ static int tegra_timer_setup(unsigned int cpu) { struct timer_of *to = per_cpu_ptr(&tegra_to, cpu); - writel(0, timer_of_base(to) + TIMER_PTV); - writel(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); + writel_relaxed(0, timer_of_base(to) + TIMER_PTV); + writel_relaxed(TIMER_PCR_INTR_CLR, timer_of_base(to) + TIMER_PCR); irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); enable_irq(to->clkevt.irq); @@ -148,13 +148,13 @@ static int tegra_timer_stop(unsigned int cpu) static u64 notrace tegra_read_sched_clock(void) { - return readl(timer_reg_base + TIMERUS_CNTR_1US); + return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US); } #ifdef CONFIG_ARM static unsigned long tegra_delay_timer_read_counter_long(void) { - return readl(timer_reg_base + TIMERUS_CNTR_1US); + return readl_relaxed(timer_reg_base + TIMERUS_CNTR_1US); } static struct delay_timer tegra_delay_timer = { @@ -175,8 +175,9 @@ static struct timer_of suspend_rtc_to = { */ static u64 tegra_rtc_read_ms(struct clocksource *cs) { - u32 ms = readl(timer_of_base(&suspend_rtc_to) + RTC_MILLISECONDS); - u32 s = readl(timer_of_base(&suspend_rtc_to) + RTC_SHADOW_SECONDS); + void __iomem *reg_base = timer_of_base(&suspend_rtc_to); + u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS); + u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS); return (u64)s * MSEC_PER_SEC + ms; } @@ -261,7 +262,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) goto out; } - writel(usec_config, timer_reg_base + TIMERUS_USEC_CFG); + writel_relaxed(usec_config, timer_reg_base + TIMERUS_USEC_CFG); for_each_possible_cpu(cpu) { struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.25 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:26 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 09/25] clocksource/drivers/tegra: Release all IRQ's on request_irq() error Date: Wed, 26 Jun 2019 16:46:35 +0200 Message-Id: <20190626144651.16742-9-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko Release all requested IRQ's on the request error to properly clean up allocated resources. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 276b55f6ada0..e2ef6b8211a5 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -284,7 +284,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) pr_err("%s: can't map IRQ for CPU%d\n", __func__, cpu); ret = -EINVAL; - goto out; + goto out_irq; } irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); @@ -294,7 +294,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) if (ret) { pr_err("%s: cannot setup irq %d for CPU%d\n", __func__, cpu_to->clkevt.irq, cpu); - ret = -EINVAL; + irq_dispose_mapping(cpu_to->clkevt.irq); + cpu_to->clkevt.irq = 0; goto out_irq; } } From patchwork Wed Jun 26 14:46:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167828 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp872202ock; Wed, 26 Jun 2019 07:48:51 -0700 (PDT) X-Google-Smtp-Source: APXvYqy0m22btg0jNcwqcxvPWYuuzVDGL2waf0eFW2xjSaPbbf1hngG1ttl3IUKWrUfXormsFfvU X-Received: by 2002:a17:902:7c90:: with SMTP id y16mr6022627pll.238.1561560531525; Wed, 26 Jun 2019 07:48:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560531; cv=none; d=google.com; s=arc-20160816; b=QS6Ebjviryu4P1BqPEsV60KZ1tYE+0WnL9ReRensOJf4naJweeiW9noxv2oUkrfXRY 3Poy+EnllEhHpSsW5Y0TqTwtU83WOT7V9edpA+IBFa9gLqlyR3ev/wsDqoh5tbhZPmd4 6GHmR82D4N1Yztgnh4Tgik4O8qtHz4rtUAEIe52Xbk26l985oORrINmbNxFW3bFe2GH5 qUTQrf28MKT/tar+/ND1IWeFMcg9t+CBLDg9rAnSynmuiui6vewvPWb3UnZFIpczp40S T3vxt+PrBJLW9YUUfde6L2ImVVB8p3vfjIXkcZ1EuUEB5WIusoHrdpMGI48WpGSItO3/ 2bAQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Y/jkAn3vCT4++dqCh3VgpJih6azC2n9WMcpnAYjdo7g=; b=OWc45s8aI2iq13NH0cqcHxU+c+pFi31PMLoJXgHfCHuTAf8BKFNTtPf7DogDAFFkLw B1F4T3MpivLPHTdS11vUUfd/vNIyLdB30fwY4fmiirlp0/YXbQAdiDjZFf1yvKB7f5wj r3EXEMiKyBQUX16MEjm95uJ1E3bNebd2wbFZmxhkO65VgryW7BNzNvDPTyErZbA4tLgt EdFXmIK3VaaMGYVm9M9rgfizF1BZ4+mqrD77VWDdW9G7RsygQRU2YMh+9UEUV6K9o7p7 ExCMKdBovhJvwufL9b90B5Fj5vP6hjK86M/D6z5UDycmpBAkpaa2wn8sdU0Ci119Cpd4 nwHA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=zCRa4KiG; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:27 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 10/25] clocksource/drivers/tegra: Minor code clean up Date: Wed, 26 Jun 2019 16:46:36 +0200 Message-Id: <20190626144651.16742-10-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko Correct typo and use proper upper casing for acronyms in the comments, use common style for error messages, prepend error messages with "tegra-timer:", add error message for cpuhp_setup_state() failure and clean up whitespaces in the code to fix checkpatch warnings. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 43 ++++++++++++++++------------- 1 file changed, 24 insertions(+), 19 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index e2ef6b8211a5..6a3704142f31 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -6,6 +6,8 @@ * Colin Cross */ +#define pr_fmt(fmt) "tegra-timer: " fmt + #include #include #include @@ -21,13 +23,13 @@ #include "timer-of.h" -#define RTC_SECONDS 0x08 -#define RTC_SHADOW_SECONDS 0x0c -#define RTC_MILLISECONDS 0x10 +#define RTC_SECONDS 0x08 +#define RTC_SHADOW_SECONDS 0x0c +#define RTC_MILLISECONDS 0x10 -#define TIMERUS_CNTR_1US 0x10 -#define TIMERUS_USEC_CFG 0x14 -#define TIMERUS_CNTR_FREEZE 0x4c +#define TIMERUS_CNTR_1US 0x10 +#define TIMERUS_USEC_CFG 0x14 +#define TIMERUS_CNTR_FREEZE 0x4c #define TIMER_PTV 0x0 #define TIMER_PTV_EN BIT(31) @@ -48,7 +50,7 @@ static u32 usec_config; static void __iomem *timer_reg_base; static int tegra_timer_set_next_event(unsigned long cycles, - struct clock_event_device *evt) + struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); @@ -169,15 +171,17 @@ static struct timer_of suspend_rtc_to = { /* * tegra_rtc_read - Reads the Tegra RTC registers - * Care must be taken that this funciton is not called while the + * Care must be taken that this function is not called while the * tegra_rtc driver could be executing to avoid race conditions * on the RTC shadow register */ static u64 tegra_rtc_read_ms(struct clocksource *cs) { void __iomem *reg_base = timer_of_base(&suspend_rtc_to); + u32 ms = readl_relaxed(reg_base + RTC_MILLISECONDS); u32 s = readl_relaxed(reg_base + RTC_SHADOW_SECONDS); + return (u64)s * MSEC_PER_SEC + ms; } @@ -222,7 +226,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) to = this_cpu_ptr(&tegra_to); ret = timer_of_init(np, to); - if (ret < 0) + if (ret) goto out; timer_reg_base = timer_of_base(to); @@ -281,8 +285,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); if (!cpu_to->clkevt.irq) { - pr_err("%s: can't map IRQ for CPU%d\n", - __func__, cpu); + pr_err("failed to map irq for cpu%d\n", cpu); ret = -EINVAL; goto out_irq; } @@ -292,8 +295,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) IRQF_TIMER | IRQF_NOBALANCING, cpu_to->clkevt.name, &cpu_to->clkevt); if (ret) { - pr_err("%s: cannot setup irq %d for CPU%d\n", - __func__, cpu_to->clkevt.irq, cpu); + pr_err("failed to set up irq for cpu%d: %d\n", + cpu, ret); irq_dispose_mapping(cpu_to->clkevt.irq); cpu_to->clkevt.irq = 0; goto out_irq; @@ -312,11 +315,14 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) register_current_timer_delay(&tegra_delay_timer); #endif - cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, - "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, - tegra_timer_stop); + ret = cpuhp_setup_state(CPUHP_AP_TEGRA_TIMER_STARTING, + "AP_TEGRA_TIMER_STARTING", tegra_timer_setup, + tegra_timer_stop); + if (ret) + pr_err("failed to set up cpu hp state: %d\n", ret); return ret; + out_irq: for_each_possible_cpu(cpu) { struct timer_of *cpu_to; @@ -329,6 +335,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) } out: timer_of_cleanup(to); + return ret; } @@ -352,8 +359,6 @@ static int __init tegra20_init_rtc(struct device_node *np) if (ret) return ret; - clocksource_register_hz(&suspend_rtc_clocksource, 1000); - - return 0; + return clocksource_register_hz(&suspend_rtc_clocksource, 1000); } TIMER_OF_DECLARE(tegra20_rtc, "nvidia,tegra20-rtc", tegra20_init_rtc); From patchwork Wed Jun 26 14:46:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167827 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp872103ock; 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.28 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:28 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko Subject: [PATCH 11/25] clocksource/drivers/tegra: Support COMPILE_TEST universally Date: Wed, 26 Jun 2019 16:46:37 +0200 Message-Id: <20190626144651.16742-11-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko Remove build dependency on ARM for compile-testing to allow non-arch specific build-bots (like Intel's test robot) to compile the driver and report about problems. Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index 3300739edce4..d17a347e813a 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -140,7 +140,7 @@ config TEGRA_TIMER bool "Tegra timer driver" if COMPILE_TEST select CLKSRC_MMIO select TIMER_OF - depends on ARM || ARM64 + depends on ARCH_TEGRA || COMPILE_TEST help Enables support for the Tegra driver. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.29 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:30 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Thierry Reding , Jonathan Hunter , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 12/25] clocksource/drivers/tegra: Lower clocksource rating for some Tegra's Date: Wed, 26 Jun 2019 16:46:38 +0200 Message-Id: <20190626144651.16742-12-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko Arch-timer is more preferable for a range of Tegra SoC generations as it has higher precision and is not affect by any kind of problems. Pointed-out-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra20.c | 30 +++++++++++++++++++++++++---- 1 file changed, 26 insertions(+), 4 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra20.c index 6a3704142f31..ed1454000ea9 100644 --- a/drivers/clocksource/timer-tegra20.c +++ b/drivers/clocksource/timer-tegra20.c @@ -109,7 +109,6 @@ static DEFINE_PER_CPU(struct timer_of, tegra_to) = { .clkevt = { .name = "tegra_timer", - .rating = 460, .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, .set_next_event = tegra_timer_set_next_event, .set_state_shutdown = tegra_timer_shutdown, @@ -219,7 +218,8 @@ static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20) return TIMER10_IRQ_IDX + cpu; } -static int __init tegra_init_timer(struct device_node *np, bool tegra20) +static int __init tegra_init_timer(struct device_node *np, bool tegra20, + int rating) { struct timer_of *to; int cpu, ret; @@ -282,6 +282,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) cpu_to = per_cpu_ptr(&tegra_to, cpu); cpu_to->of_base.base = timer_reg_base + base; + cpu_to->clkevt.rating = rating; cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); if (!cpu_to->clkevt.irq) { @@ -341,13 +342,34 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20) static int __init tegra210_init_timer(struct device_node *np) { - return tegra_init_timer(np, false); + /* + * Arch-timer can't survive across power cycle of CPU core and + * after CPUPORESET signal due to a system design shortcoming, + * hence tegra-timer is more preferable on Tegra210. + */ + return tegra_init_timer(np, false, 460); } TIMER_OF_DECLARE(tegra210_timer, "nvidia,tegra210-timer", tegra210_init_timer); static int __init tegra20_init_timer(struct device_node *np) { - return tegra_init_timer(np, true); + int rating; + + /* + * Tegra20 and Tegra30 have Cortex A9 CPU that has a TWD timer, + * that timer runs off the CPU clock and hence is subjected to + * a jitter caused by DVFS clock rate changes. Tegra-timer is + * more preferable for older Tegra's, while later SoC generations + * have arch-timer as a main per-CPU timer and it is not affected + * by DVFS changes. + */ + if (of_machine_is_compatible("nvidia,tegra20") || + of_machine_is_compatible("nvidia,tegra30")) + rating = 460; + else + rating = 330; + + return tegra_init_timer(np, true, rating); } TIMER_OF_DECLARE(tegra20_timer, "nvidia,tegra20-timer", tegra20_init_timer); From patchwork Wed Jun 26 14:46:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167815 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp870972ock; Wed, 26 Jun 2019 07:47:43 -0700 (PDT) X-Google-Smtp-Source: APXvYqykR4BO8/2/K4XO0upgTgJHXlLvsL9YmB7gBZPrY3v20IsEZwOPgAXleJdbFG1DehFOqDGG X-Received: by 2002:a17:902:be12:: with SMTP id r18mr5594615pls.341.1561560462981; Wed, 26 Jun 2019 07:47:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560462; cv=none; d=google.com; s=arc-20160816; b=DargGwHhzvalbwU+yM4g1ZvAA2roVs6jNKMJ9dkEs5oZl2nMgXNYg99VUfIexVaWyK LQ+Ss9J8QsnlLjUR0dCUvbARt9u/cYNp0ohICOucs+xgz/2yLfhSCMqOzofI/ciBHMJI pEg0kjXRmiEQvb+WAY0ihGE7VpaMRDpGEuE1+BANI44SsbJvd9m9cM3XlNq1+CgxKhd1 rtLAXzBxyUxkqP8dXihePvRtAp5aXYeWYbTN5ydlccmULWSbTkD0L6AdRQTfKrg5WEp2 mYbvyLxQFtusjVBhi48Ezy0rCJJ8ZST8ZfuortUV/4WBGxmeyPl3Csq8ZwefgFgPmkuu xWdw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=JvEiCBwyt/FKczphOvHNL3YMIgGxDxP9ixu7/5tHp7M=; b=Fa5QaWzl9aoHyvMAKfQ4W2CqGiUIasywRxispEEhaFE/SOPmuEbFmqtJ5ZzPNouUxM zXY6cayK/uNFQeyAj8bzKe/axv5WKuNYoxafMQ42KH3Jo/9g3SjDkmTwE8zCT5HuXpJ8 VLN8GyeAXbyNGdXNiae+LtyzpxhJ59/xVA/s/X5DMCgv7wRB8HnhWdyn0PCI3Jt2gBER bUdzVucw3sKGnKyJWObiHvVl5Kie8mej14aXCk38PEHUUFZBxStnnn0dCulEit47TGWc vFJOeIKEExxCP0QL5FGbfmmGnAoUOQ/mlNdbI3e5fYJ3WlDLImDa5yG6U/rlr3LNwENQ 8jyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=u+jbMOKd; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.31 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:32 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko Subject: [PATCH 13/25] clocksource/drivers/tegra: Rename timer-tegra20.c to timer-tegra.c Date: Wed, 26 Jun 2019 16:46:39 +0200 Message-Id: <20190626144651.16742-13-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko Rename driver's source file to better reflect that it's not specific to older SoC generations. Suggested-by: Daniel Lezcano Signed-off-by: Dmitry Osipenko Acked-By: Peter De Schrijver Signed-off-by: Daniel Lezcano --- drivers/clocksource/Makefile | 2 +- drivers/clocksource/{timer-tegra20.c => timer-tegra.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename drivers/clocksource/{timer-tegra20.c => timer-tegra.c} (100%) -- 2.17.1 diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 236858fa7fbf..4145b21eaed3 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -36,7 +36,7 @@ obj-$(CONFIG_U300_TIMER) += timer-u300.o obj-$(CONFIG_SUN4I_TIMER) += timer-sun4i.o obj-$(CONFIG_SUN5I_HSTIMER) += timer-sun5i.o obj-$(CONFIG_MESON6_TIMER) += timer-meson6.o -obj-$(CONFIG_TEGRA_TIMER) += timer-tegra20.o +obj-$(CONFIG_TEGRA_TIMER) += timer-tegra.o obj-$(CONFIG_VT8500_TIMER) += timer-vt8500.o obj-$(CONFIG_NSPIRE_TIMER) += timer-zevio.o obj-$(CONFIG_BCM_KONA_TIMER) += bcm_kona_timer.o diff --git a/drivers/clocksource/timer-tegra20.c b/drivers/clocksource/timer-tegra.c similarity index 100% rename from drivers/clocksource/timer-tegra20.c rename to drivers/clocksource/timer-tegra.c From patchwork Wed Jun 26 14:46:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167816 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp871039ock; Wed, 26 Jun 2019 07:47:46 -0700 (PDT) X-Google-Smtp-Source: APXvYqwotjqI61k4SqrhLomBgLMfJzdeZw+cxTzRLWTJavhjX7eT9B/pPiA575O1uUowtfVQm+ys X-Received: by 2002:a63:4556:: with SMTP id u22mr3378468pgk.444.1561560466802; Wed, 26 Jun 2019 07:47:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560466; cv=none; d=google.com; s=arc-20160816; b=f4Gh8F9tczNE/2y6VUt4sFs+ZDFPFOAvHM44QZ4H5jmz5tyq2m4XtvDciGjGJxP8LO /xO24DFkBDAUDdEtT85iDYAk/E+UylmMquRWGiJuY7orInGQ/vQGUvSB0SOag5No0LX3 VJLH+m+BWj7aHX8T2RSkmXzDEWRWR4+xfE//LRkqnkXDtMBnzhX4nqlqWkPlScWja2Bi GafH98dBVfotxEDZxjV3/3WUHXg/I3SRPpjoUGflP/VnB7U3Xt3EtD5MR5NXT61k09tF EaRIpJa8tBgHNvvsSjHhKApBmQwI9uACRnApYozG051nWW3WtWG7AQTbbQzT2VDRjFV9 bsTg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=cbSVQ22cXPOUgxve/+oaGWixu1F5XT9Nb/A3w74S+UE=; b=v7I8UlfBRGj6ghEFBtoXt0jBApIIAXZi6nJ2QR/JrClicGJ2/ApONbqXPYgtMIHR39 MmYxXYcppJD0/3xxPxT8K+2rhpq6WE6sJQHRDiUCvWwSkt5pczGhW750FvAsGSnZ/buZ HabpA/TZ/s/3xrVZw7Nf6ThOs7d1byadD6eo08oi0LdV35W9Eb9jVaWh4IWaV8ZYttsS IXbSuhFFLyFBXnXxLnedgtKyYRWq7VJPwQGWcBEggasR42Xf7qBHqnJqLcIG9ppYdGg+ gLtgKbkp4AfRYGuZJCiPiSva/AouUecIRRDKNwFmccILIj6wtFEHlaII3UZcsBpaT4qy Eqhw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ADrxohoq; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:37 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Andrew Murray , Mark Rutland , Will Deacon , Marc Zyngier , Russell King , Catalin Marinas , linux-arm-kernel@lists.infradead.org (moderated list:ARM ARCHITECTED TIMER DRIVER) Subject: [PATCH 15/25] clocksource/drivers/arm_arch_timer: Extract elf_hwcap use to arch-helper Date: Wed, 26 Jun 2019 16:46:41 +0200 Message-Id: <20190626144651.16742-15-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Andrew Murray Different mechanisms are used to test and set elf_hwcaps between ARM and ARM64, this results in the use of ifdeferry in this file when setting/testing for the EVTSTRM hwcap. Let's improve readability by extracting this to an arch helper. Signed-off-by: Andrew Murray Acked-by: Mark Rutland Acked-by: Will Deacon Signed-off-by: Daniel Lezcano --- arch/arm/include/asm/arch_timer.h | 10 ++++++++++ arch/arm64/include/asm/arch_timer.h | 13 +++++++++++++ drivers/clocksource/arm_arch_timer.c | 15 ++------------- 3 files changed, 25 insertions(+), 13 deletions(-) -- 2.17.1 diff --git a/arch/arm/include/asm/arch_timer.h b/arch/arm/include/asm/arch_timer.h index 4b66ecd6be99..99175812d903 100644 --- a/arch/arm/include/asm/arch_timer.h +++ b/arch/arm/include/asm/arch_timer.h @@ -4,6 +4,7 @@ #include #include +#include #include #include #include @@ -124,6 +125,15 @@ static inline void arch_timer_set_cntkctl(u32 cntkctl) isb(); } +static inline void arch_timer_set_evtstrm_feature(void) +{ + elf_hwcap |= HWCAP_EVTSTRM; +} + +static inline bool arch_timer_have_evtstrm_feature(void) +{ + return elf_hwcap & HWCAP_EVTSTRM; +} #endif #endif diff --git a/arch/arm64/include/asm/arch_timer.h b/arch/arm64/include/asm/arch_timer.h index 50b3ab7ded4f..a847a3ee6cab 100644 --- a/arch/arm64/include/asm/arch_timer.h +++ b/arch/arm64/include/asm/arch_timer.h @@ -20,6 +20,7 @@ #define __ASM_ARCH_TIMER_H #include +#include #include #include @@ -240,4 +241,16 @@ static inline int arch_timer_arch_init(void) return 0; } +static inline void arch_timer_set_evtstrm_feature(void) +{ + cpu_set_named_feature(EVTSTRM); +#ifdef CONFIG_COMPAT + compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM; +#endif +} + +static inline bool arch_timer_have_evtstrm_feature(void) +{ + return cpu_have_named_feature(EVTSTRM); +} #endif diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 5c69c9a9a6a4..3c8afcd3444c 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -804,14 +804,7 @@ static void arch_timer_evtstrm_enable(int divider) cntkctl |= (divider << ARCH_TIMER_EVT_TRIGGER_SHIFT) | ARCH_TIMER_VIRT_EVT_EN; arch_timer_set_cntkctl(cntkctl); -#ifdef CONFIG_ARM64 - cpu_set_named_feature(EVTSTRM); -#else - elf_hwcap |= HWCAP_EVTSTRM; -#endif -#ifdef CONFIG_COMPAT - compat_elf_hwcap |= COMPAT_HWCAP_EVTSTRM; -#endif + arch_timer_set_evtstrm_feature(); cpumask_set_cpu(smp_processor_id(), &evtstrm_available); } @@ -1040,11 +1033,7 @@ static int arch_timer_cpu_pm_notify(struct notifier_block *self, } else if (action == CPU_PM_ENTER_FAILED || action == CPU_PM_EXIT) { arch_timer_set_cntkctl(__this_cpu_read(saved_cntkctl)); -#ifdef CONFIG_ARM64 - if (cpu_have_named_feature(EVTSTRM)) -#else - if (elf_hwcap & HWCAP_EVTSTRM) -#endif + if (arch_timer_have_evtstrm_feature()) cpumask_set_cpu(smp_processor_id(), &evtstrm_available); } return NOTIFY_OK; From patchwork Wed Jun 26 14:46:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167817 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp871101ock; Wed, 26 Jun 2019 07:47:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqxe8v7KFe01tVpIBDn8K8J/pR8ld9nejIjoUOGJdC57bHj3Oqo+0Z63M6vtRDgSaSjcDTX+ X-Received: by 2002:a63:4d51:: with SMTP id n17mr3202461pgl.449.1561560469746; Wed, 26 Jun 2019 07:47:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560469; cv=none; d=google.com; s=arc-20160816; b=w5MfLrjobEs3xLRyatjTrZYYbSWx7zKsBIfkZ5LltHhdJ2iJrMGQBBY9fhTXGnje9H O8dqHlx1VVoDCe4bMLKEHnh6cAjm/1WDY1X8g0c50vFlZ9PnNxxT/F3YUSeuwSjmEEHc Dmta3q41xBOoVJrqpVX2MkHkqJQXRLXeYVEuNHRPqWIykvWEllgI7nmVAT5qmnp1Walr 3IHwwVCFXiXBXo2LtHD9NosjN8iXFnuIh/erY74UGLdgIqYIOxReCWXOIsYbJg+/MTOd fQdVMa8l53QFZxJ/e2M/CGHsu/ebrHdDT0cFtwgnQNqDxXCMKzIAlw4n56JUlYOCG2xu KQhw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=OvrcN7nx43BK8pLnR/sB9l6LAwke86j5KsajSpQYjKA=; b=sKD8C5CApOZpQgCG7QB7+q6nAMLXA0KSx5c7Uo1HVRJ+bG5MZV0qUjCNyjeUD3EEGj eBeBywUeUjpsxNamZsw+9EitwTOFf7bCOodYGI7H9ZpCpnCzUp7Ayisg9bk4ehrYSGZW Xj41onXn7j1MG139W6Wtzj64LY47g2W7tR4hLXuCODKSnngcuO1pIm9aGxckT2RgHpjw 8Fb9EV+gKcV5euVr6yzEBxDCrnO/ffpSzDUfUi87bNLIMXV09ZctUR0YrDqbBXluxhbL 9ytBrWzBq1HfKQan7xNxrdIkYeJWgSgRpdAZX9881Fqug32MY82eQAUhWCQPu8ISDMbS AkvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mCICVFSv; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.38 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:39 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 16/25] clocksource/drivers/tegra: Restore timer rate on Tegra210 Date: Wed, 26 Jun 2019 16:46:42 +0200 Message-Id: <20190626144651.16742-16-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko The clocksource rate is initialized only for the first per-CPU clocksource and then that rate shall be replicated for the rest of clocksource's because they are initialized manually in the code. Fixes: 3be2a85a0b61 ("clocksource/drivers/tegra: Support per-CPU timers on all Tegra's") Acked-by: Jon Hunter Tested-by: Jon Hunter Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index ed1454000ea9..880ba67ca7ee 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -279,6 +279,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, */ if (tegra20) cpu_to->of_clk.rate = 1000000; + else + cpu_to->of_clk.rate = timer_of_rate(to); cpu_to = per_cpu_ptr(&tegra_to, cpu); cpu_to->of_base.base = timer_reg_base + base; From patchwork Wed Jun 26 14:46:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167818 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp871154ock; Wed, 26 Jun 2019 07:47:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqy6fehSG39e7xQYP6maKIfizdjJP/DalF8ZcmH53HrvZQd9KDqaRQsDwNZ0Lo52nXxMMefG X-Received: by 2002:a17:90a:cd03:: with SMTP id d3mr4981307pju.127.1561560472587; Wed, 26 Jun 2019 07:47:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560472; cv=none; d=google.com; s=arc-20160816; b=WnU8TF6nViWZnVIF1QeqtC3J8i3wfRUGwo3mN8/cQl6thR/qLdqXhC4rAnppw5ZKas H6k5PTP/xZ6qKfYd8G50vgFqomZFXSdi/zKhix/svIu9mmFsfc8DMWvJer0DwoSmrNAO +3lf3v+9AU5s9Jk0kbE5az11DeuQsh4eFhVzln4r13EXpL+oH4yW7Rlfk4bkawOmQK3s ju5SevMFa/nxw3pjcjOIVpGr0/LfbASzhmL1WC1vdYZT5qmmjAQOw2cHdGJ+Z7zNamod G65bR8JxhOwfhCxoEMN2++JqGbMyh2Uu7LTr2qx7x3N1flI/LTh/B899H5ISitiZmHse BiUw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=yqfHGm0TnB/EluOWXQT4ZbDAqP2xMCI6PrNJ2MlYeVk=; b=JbW1T7FyuNW/BvteSNF5yz8urLlK4byMvGp9z6aIvEGU0fPqtl0nsD65Vrl2AHpx9Q 1q88MZI8LH6VfE+55zJnTdrUriTMFLVVXwAtZheGhUyUWujDvqutfg5nG3RhsAVtdDI9 RHOQ1czMz6PVUyl/Fdk/WWiYP+cSsgCpfNTMuNz519L0UevOtsUYy+vpDYECV+TGsX7f 4Ck+aRyRTHFQSLC82kmo0p++vvKTwssESJBwulxgFla4Jd9eIy0wXPNhxRXX9jNizWLt m/vOhW5UqGz+/BNJTv1BOWEkde4TP474kCDUUlHtbykmKe8HRzvXQa52kpD+ZKT7okAb sDdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a71rNY30; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:40 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 17/25] clocksource/drivers/tegra: Remove duplicated use of per_cpu_ptr Date: Wed, 26 Jun 2019 16:46:43 +0200 Message-Id: <20190626144651.16742-17-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko It was left unnoticed by accident, which means that the code could be cleaned up a tad more. Acked-by: Jon Hunter Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 42 ++++++++++++++++++------------- 1 file changed, 25 insertions(+), 17 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index 880ba67ca7ee..f172a57cc5fe 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -218,6 +218,19 @@ static inline unsigned int tegra_irq_idx_for_cpu(int cpu, bool tegra20) return TIMER10_IRQ_IDX + cpu; } +static inline unsigned long tegra_rate_for_timer(struct timer_of *to, + bool tegra20) +{ + /* + * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the + * parent clock. + */ + if (tegra20) + return 1000000; + + return timer_of_rate(to); +} + static int __init tegra_init_timer(struct device_node *np, bool tegra20, int rating) { @@ -270,32 +283,27 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, for_each_possible_cpu(cpu) { struct timer_of *cpu_to = per_cpu_ptr(&tegra_to, cpu); + unsigned long flags = IRQF_TIMER | IRQF_NOBALANCING; + unsigned long rate = tegra_rate_for_timer(to, tegra20); unsigned int base = tegra_base_for_cpu(cpu, tegra20); unsigned int idx = tegra_irq_idx_for_cpu(cpu, tegra20); + unsigned int irq = irq_of_parse_and_map(np, idx); - /* - * TIMER1-9 are fixed to 1MHz, TIMER10-13 are running off the - * parent clock. - */ - if (tegra20) - cpu_to->of_clk.rate = 1000000; - else - cpu_to->of_clk.rate = timer_of_rate(to); - - cpu_to = per_cpu_ptr(&tegra_to, cpu); - cpu_to->of_base.base = timer_reg_base + base; - cpu_to->clkevt.rating = rating; - cpu_to->clkevt.cpumask = cpumask_of(cpu); - cpu_to->clkevt.irq = irq_of_parse_and_map(np, idx); - if (!cpu_to->clkevt.irq) { + if (!irq) { pr_err("failed to map irq for cpu%d\n", cpu); ret = -EINVAL; goto out_irq; } + cpu_to->clkevt.irq = irq; + cpu_to->clkevt.rating = rating; + cpu_to->clkevt.cpumask = cpumask_of(cpu); + cpu_to->of_base.base = timer_reg_base + base; + cpu_to->of_clk.rate = rate; + irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); - ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, - IRQF_TIMER | IRQF_NOBALANCING, + + ret = request_irq(cpu_to->clkevt.irq, tegra_timer_isr, flags, cpu_to->clkevt.name, &cpu_to->clkevt); if (ret) { pr_err("failed to set up irq for cpu%d: %d\n", From patchwork Wed Jun 26 14:46:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167826 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp871968ock; Wed, 26 Jun 2019 07:48:39 -0700 (PDT) X-Google-Smtp-Source: APXvYqyhsJ3l7utyaBlM5xjom0IXZaSzXRBfMsHCaiqE7M4GuSELAYzbKAOeqjJ1kWIN+RZdipij X-Received: by 2002:a63:b547:: with SMTP id u7mr3426430pgo.322.1561560519346; Wed, 26 Jun 2019 07:48:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560519; cv=none; d=google.com; s=arc-20160816; b=C5JlR9XcNQnsbKLpv16KErIZHCpTvzDrKkuvHf3AWaB82VaHs+jgDEjqShMulzIFXo jIFjcVWFLVsfq+slOuXllTzUZemSvtybHyJ9pLqWsGGO78H6pjinZLj9V8EfQJgKwzDI Mcf2HkKWXaNWei9wAKZOsnHtU90pwoZrTFtwAjzQyORhjCTKxd3OQSwEpdD/4UHUqy9n FeoEm980AETH2C9Ex/hpex2sQ3TTYXu9Q8OCBWS5GEUoZWFMWnxuavZu70om2gSGGI60 PyQW2ZlVoii/2CtWkRYuavfi/PwLCrFNHbff0+4I/OC6nY1EKcEmP1He5aAGXjnp08QB +2pQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=4IAtyPcsTx9RzQZd9Z8HcSfwjywt5ILpbuYeShXpAGo=; b=sl9RkO+JhzrOxeJ4z8Z6afCNUoGgOVbMji2B1Ll2djWkVLbUQO2a0fLQlesgE2jsaE WUUzXx7Me6VW8+VVY+kJqOnEFtRfg+fE3I0vaXSt4oPqa41HLb0AXEZeNo2HCfuNx0l9 KPImb0bUk4ls0WKsiJaVeCiTZJSTHIRQkcIeDe9xhH17prUzwd5L05bIwz8rmwGeicfO SnaJkbs+TgPXoyVfCOit7XtYILhw+2lCuALmxOxAQH8o0ND8JVQ+PY/5zjGyvNd8WFbo o3oV6qhjX6TgmQtWTReP3PRG+ONeLl/7ys8gtQr9C6Mlho7RQJbP9Gd8ZKA9uIMHzO07 tKGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=DxmMYVPx; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.41 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:41 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 18/25] clocksource/drivers/tegra: Set and use timer's period Date: Wed, 26 Jun 2019 16:46:44 +0200 Message-Id: <20190626144651.16742-18-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko The of_clk structure has a period field that is set up initially by timer_of_clk_init(), that period value need to be adjusted for a case of TIMER1-9 that are running at a fixed rate that doesn't match the clock's rate. Note that the period value is currently used only by some of the clocksource drivers internally and hence this is just a minor cleanup change that doesn't fix anything. Signed-off-by: Dmitry Osipenko Acked-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index f172a57cc5fe..41257f89a216 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -73,9 +73,9 @@ static int tegra_timer_shutdown(struct clock_event_device *evt) static int tegra_timer_set_periodic(struct clock_event_device *evt) { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); + unsigned long period = timer_of_period(to_timer_of(evt)); - writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | - ((timer_of_rate(to_timer_of(evt)) / HZ) - 1), + writel_relaxed(TIMER_PTV_EN | TIMER_PTV_PER | (period - 1), reg_base + TIMER_PTV); return 0; @@ -299,6 +299,7 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, cpu_to->clkevt.rating = rating; cpu_to->clkevt.cpumask = cpumask_of(cpu); cpu_to->of_base.base = timer_reg_base + base; + cpu_to->of_clk.period = rate / HZ; cpu_to->of_clk.rate = rate; irq_set_status_flags(cpu_to->clkevt.irq, IRQ_NOAUTOEN); From patchwork Wed Jun 26 14:46:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167819 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp871217ock; Wed, 26 Jun 2019 07:47:56 -0700 (PDT) X-Google-Smtp-Source: APXvYqyxrZiLfFMUzOmtRMUx9hThAAZ7SXSk0iQQZG7ddpTppx6M5nspv8+HQ+/Y6jVHXYpkgGu7 X-Received: by 2002:a17:90a:2305:: with SMTP id f5mr5439008pje.128.1561560476485; Wed, 26 Jun 2019 07:47:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560476; cv=none; d=google.com; s=arc-20160816; b=gYVFflDHFlhkGhodgcqgolzCltnRlnmurEKEHSTKJoHB50q02m9qcGf+fc+gSAhQRX 3lQg4nqRLDUGd3iB3jeQqZAt0WNTazW1wYEjx5Rm8ewVx38pz3oojGs/z/kIjRRsUNFa r6b2BhX1OuoqLeF+E1rTOKqct1/o/X2vGevJ9W1jeZbR5tOC0UbdHr29zgR13LhiK32B lkhf2fFHock2abraPjXpvDRPvqmv8gF2jb44eBjcyViNkoXIKeFdyS3hRPjy3R6jhzd5 eE4tSa97GOzT1CYGh0I8ptAiJjXbbMsEhN9QMQxZAvs0LUX8dJCLk7YoeyUWmF9YRbiF dunQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=DAchjLoGp53ThJdxxXYtoXfJ80Q4DYb4SAa6+caQEjY=; b=y87QYLjQ4hVIAZv/nHIFCqxb+z6HAh3o83rogapltJvYnU57JRec3trbJA8Zqtgk/t GXvOkFyMfzmkXVvQATyayRhv2c5t9ztSrz60Edq5G8QG2R1GzNCSR/2VEZnof1N+xNEZ yxvKdShWTb/qoyJnMVca1SG/zxpGrmXZkzp6FW2o5fmQplo+oPIn47pr9eBMuD+3GKrq Lk9DvdHbKRZo8mAZe2W/EWah0NThgXjQCLj6LF+TTwjrdMsYjCWGS23CnD0qzUW2a9M3 MXqvqrwIVqZ0lnqXUUnw5gAtDXE7kYPJcG08XPYc1gQ1oyrhF6026kDyrhjGo47UlKbz Ny8w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xiqkyqpU; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.42 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:43 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 19/25] clocksource/drivers/tegra: Drop unneeded typecasting in one place Date: Wed, 26 Jun 2019 16:46:45 +0200 Message-Id: <20190626144651.16742-19-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko There is no need to cast void because kernel allows to do that without a warning message from a compiler. Acked-by: Jon Hunter Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index 41257f89a216..f7a09d88dacb 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -83,7 +83,7 @@ static int tegra_timer_set_periodic(struct clock_event_device *evt) static irqreturn_t tegra_timer_isr(int irq, void *dev_id) { - struct clock_event_device *evt = (struct clock_event_device *)dev_id; + struct clock_event_device *evt = dev_id; void __iomem *reg_base = timer_of_base(to_timer_of(evt)); writel_relaxed(TIMER_PCR_INTR_CLR, reg_base + TIMER_PCR); From patchwork Wed Jun 26 14:46:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167820 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp871258ock; Wed, 26 Jun 2019 07:47:59 -0700 (PDT) X-Google-Smtp-Source: APXvYqw2+Ahfh8uuiyXal1KObOH8cU8V3Kir+Ri2YQu3125sKoA+GDpR6C9XZU0zwG/Q1UzLSkJL X-Received: by 2002:a63:c302:: with SMTP id c2mr3176400pgd.300.1561560479173; Wed, 26 Jun 2019 07:47:59 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560479; cv=none; d=google.com; s=arc-20160816; b=vn/R1/Q9rEvdwUpFxlFlwoiudCh2YnHBjB+9HR+8E2h6dLkrgALvYiJhl6mHP4XcMc L0qO5XZVexh4te32Cq6xLliTlvw1pUEvtgQQMwKSXJdYRdGSrZIKOGvEx2GQG65o2WTy 1xQK0hP1yQ4L8dOCk3WRaa/XZJUbdwdPHKsUakwQse5pWqshgOwfPkCdanRvG77Lc1f7 4lgPzbtfV7QQxJx8MbO3li43qcbKJ7MBCKfLBeKbDY9jaNssd+W+0X65fP3ZE/T0A3f2 AbYsZeN3oXGD2j9pkJso/pXa4rh9ISTTBpMm7mLo9fPoNQ37hB8W+4LAzAPU/VzqA9at l+Tw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=v71fsQ7QyhP31JuRKVVsI8LiqKCJEYn7OMik1mGoLt0=; b=lk/pf0jPeXEsQ36y5rbrs5cehPVjLLhqW4JpUSm43p1/jm4R4NzlBJs5PKIBxFBC0E WgiPVr4bGAKQTtvX2a+AignGXdsX4hRCoBBepH3JV3wTHrCsJ6K+FRex3bKnSej8njCw 38SsVP0me9wuopgpv3nnhVp3csjHCVY/wxqVo1rE5Htbwr/cV+SpkjNmhqi5a7v8s58q A3pBTdogSz2Bnxvhpz4IPuvhegKGkFolhwVmUenEFEmNQiLIFnedcpuE2gR8ohrJkXHc saVwKXUq2Y/sEw6/vOdMRLJjv9+JyFRQeGPVPKSVwUoCFPNRxb+o0LqQbhdbn1n8MG3l jrjA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Nqrwya3T; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:44 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 20/25] clocksource/drivers/tegra: Add verbose definition for 1MHz constant Date: Wed, 26 Jun 2019 16:46:46 +0200 Message-Id: <20190626144651.16742-20-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko Convert all 1MHz literals to a verbose constant for better readability. Suggested-by: Daniel Lezcano Acked-by: Jon Hunter Signed-off-by: Dmitry Osipenko Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index f7a09d88dacb..cc90f22c559b 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -46,6 +46,8 @@ #define TIMER1_IRQ_IDX 0 #define TIMER10_IRQ_IDX 10 +#define TIMER_1MHz 1000000 + static u32 usec_config; static void __iomem *timer_reg_base; @@ -160,7 +162,7 @@ static unsigned long tegra_delay_timer_read_counter_long(void) static struct delay_timer tegra_delay_timer = { .read_current_timer = tegra_delay_timer_read_counter_long, - .freq = 1000000, + .freq = TIMER_1MHz, }; #endif @@ -226,7 +228,7 @@ static inline unsigned long tegra_rate_for_timer(struct timer_of *to, * parent clock. */ if (tegra20) - return 1000000; + return TIMER_1MHz; return timer_of_rate(to); } @@ -315,11 +317,11 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, } } - sched_clock_register(tegra_read_sched_clock, 32, 1000000); + sched_clock_register(tegra_read_sched_clock, 32, TIMER_1MHz); ret = clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, - "timer_us", 1000000, - 300, 32, clocksource_mmio_readl_up); + "timer_us", TIMER_1MHz, 300, 32, + clocksource_mmio_readl_up); if (ret) pr_err("failed to register clocksource: %d\n", ret); From patchwork Wed Jun 26 14:46:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167825 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp871876ock; Wed, 26 Jun 2019 07:48:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqwGe46BklkU02pZormHi5u9RJmfKFc8sLWjlbBehNrm2M9ymEizPGpv/r4xq7uVV4sDOFYX X-Received: by 2002:a17:902:9a87:: with SMTP id w7mr5880627plp.221.1561560513794; Wed, 26 Jun 2019 07:48:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560513; cv=none; d=google.com; s=arc-20160816; b=PsDpvEM+okYRrLg+wWSICjscXujyKGKeDVYyl3D+hv5dTsH0xn+a0sbfKPg4zQ6784 gPWZfZ0SsXDOxv1DGZJ6mupu37hK+odwA28TfLxhr3DkT0WUkjm2Dg9dlELnmzM7lSkb rHoB3LRvftf7+c/T7pH7/R1ZWezvu17QV79SUAZL2O3prfRg2KIhLaLtTj3Yx/sAFVP3 bYcar8uNwWMQuUz9BR4ZSwq7t5mN9zGWM8zTK3cUz04PsKUlBeKN/m+w2NXV7S4SYLxO 3HnHX6NHYNKanVsKghbuWFmJrzXW0ODNWWJG6reOG+nfjzzzPTyfD2FGumtBGhKFJx6Z rRUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=JJjc1JQr3nhAuAaXUtH5dZp0geSFnyJ4aiNQzKjFRos=; b=UswwYY2jqFK3ixuLui91zvfDTELbfN0xCx2J51BlYtxIhbhkW5WTquOS81mAj5FBqq CedlemK5E/YmGhW+bN8lWthyr0NIommz2S77pFoHhIiBnGYgnWJzUQMj9q6HrJBBvcLq Ph+AWnekHqctQh2aBzcRJdJgwrwtCrPq14AD4aAefQ0yyOFpP5ot+QmbBfx9LmQn38UJ F9UGgK9Qr3cQ+yplCFDcAsbqMytw+y9CuXo53/EujUyon46NJk+HixBhpbsgKcTD6iwB pn22TaJeWquT+VBkQ2XIbq03y0RsMt+nNgtWQkhrQtd0bMV3qDd2W7bzxVx2ax0CIKB+ 4UBQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SE0BjstO; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.46 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:46 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 21/25] clocksource/drivers/tegra: Restore base address before cleanup Date: Wed, 26 Jun 2019 16:46:47 +0200 Message-Id: <20190626144651.16742-21-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko We're adjusting the timer's base for each per-CPU timer to point to the actual start of the timer since device-tree defines a compound registers range that includes all of the timers. In this case the original base need to be restore before calling iounmap to unmap the proper address. Signed-off-by: Dmitry Osipenko Acked-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 2 ++ 1 file changed, 2 insertions(+) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index cc90f22c559b..8e70f38f1898 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -347,6 +347,8 @@ static int __init tegra_init_timer(struct device_node *np, bool tegra20, irq_dispose_mapping(cpu_to->clkevt.irq); } } + + to->of_base.base = timer_reg_base; out: timer_of_cleanup(to); From patchwork Wed Jun 26 14:46:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167824 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp871645ock; Wed, 26 Jun 2019 07:48:20 -0700 (PDT) X-Google-Smtp-Source: APXvYqyl1PdT5TKl4ixh0lQSWPEG7sVB9EHNcacXbcShSVaixslIigmzEaio+hAeVupnO7tTuYHy X-Received: by 2002:a63:9548:: with SMTP id t8mr3345101pgn.256.1561560500329; Wed, 26 Jun 2019 07:48:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560500; cv=none; d=google.com; s=arc-20160816; b=czwWVHNumFvw47hTe9WFeYgSB+SzmNWRgpFX5b6uahyeja+jfDrobts18st1LdHNE8 8mdKR/8yVDoJjyLrcb4tTJuxvxklRJpoZPVLNMCsJztHIx0ZhvN6J+QExMFldnnygPPH HKEj+JkUp+XTmXrEeHxGVTvO9CtJiMBw6MhN7FIfaDylsNjg/MTTbuqb2Y7ZeJdMdaHg jje4Vo8Je1zo104GYpZNgHJ+c+D3DTaKhoNk/7ag5+DCJ0tZfcw7D7BazfQImtzm8tzE XeYvupfu/iPpXsbWaCU9JgXQ76xtNe5/v2Wo0yznG4axHOLDM7TikqhoB5KJAXVdtSYs HeoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=NrTLjCEQJCPZZPBocCnR2gGFul+oEek89zztJZXdth0=; b=SBApKgotm3L831siGi6CQ6Ofe0QB22If5hkdrsbNHZng6GGJhZae2MoOE5UeJ3IwGN O0PWZMKObBVa+q5CRwB/CBGjyp550uU1tr1TNvPDmPAbw4r7PT5cf31tkoTm0DQbdarc H2lvOr3JtMR2DXFN3nCkaaNpDo6J7F/hI1nnWqSuHsFRULEyDQpBoqkI2CW0Rok1kqF/ dko8oZgDbYa/obrv0Ih/4mqElMGGlak0YFoXJSjMBQYVh0qq1qW5IqS8BAkzBLpHKjPu QOg5GipGxqP0+gks/pTPGEFGdWI0FccLTe6QKrParJpMiimAvx/t099A7d3eXiIsZMQ1 KhIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=h57Q8Ma7; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.47 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:48 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 22/25] clocksource/drivers/tegra: Cycles can't be 0 Date: Wed, 26 Jun 2019 16:46:48 +0200 Message-Id: <20190626144651.16742-22-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko Tegra's timer uses n+1 scheme for the counter, i.e. timer will fire after one tick if 0 is loaded. The minimum and maximum numbers of oneshot ticks are defined by clockevents_config_and_register(min, max) invocation and the min value is set to 1 tick. Hence "cycles" value can't ever be 0, unless it's a bug in clocksource core. Signed-off-by: Dmitry Osipenko Acked-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index 8e70f38f1898..a907e71065bd 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -56,9 +56,16 @@ static int tegra_timer_set_next_event(unsigned long cycles, { void __iomem *reg_base = timer_of_base(to_timer_of(evt)); - writel_relaxed(TIMER_PTV_EN | - ((cycles > 1) ? (cycles - 1) : 0), /* n+1 scheme */ - reg_base + TIMER_PTV); + /* + * Tegra's timer uses n+1 scheme for the counter, i.e. timer will + * fire after one tick if 0 is loaded. + * + * The minimum and maximum numbers of oneshot ticks are defined + * by clockevents_config_and_register(1, 0x1fffffff + 1) invocation + * below in the code. Hence the cycles (ticks) can't be outside of + * a range supportable by hardware. + */ + writel_relaxed(TIMER_PTV_EN | (cycles - 1), reg_base + TIMER_PTV); return 0; } From patchwork Wed Jun 26 14:46:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167822 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp871339ock; Wed, 26 Jun 2019 07:48:04 -0700 (PDT) X-Google-Smtp-Source: APXvYqzkPQwxcxOSm5gTwNCVpv4CF8CAcHxmkrJbgfSJS8OTG4AOPIw0A+XJ3zyhfS+0Cjz+RVny X-Received: by 2002:a17:902:b284:: with SMTP id u4mr6159317plr.36.1561560484763; Wed, 26 Jun 2019 07:48:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560484; cv=none; d=google.com; s=arc-20160816; b=wtQfmPLT7psXsVHvCrta9Nmlw9kX92LJ4Si8hlswfygQKaFmf0HmKQyLi4EwJ9E/v1 /ZnQf1RqItA/WVhE35jB74n0T9/puv7YiwurRuZyNPsbDeXWayNgEp9NVunzPnMRY9Oc QwtNFqxv3kZ4Rh8STkmug95yptI+EaEw8ie07OU0DrhSoxWOAC6H564y9XVp95qeNbhH GXix72zRTe6zPDURw7RTxKtm5gx3MnJSubyhCWVLQHGSgvF+HTsHKNZJyR3I/td6bVSu ZN5wDLaaOft5LCyIrNF+JbI7RWWwW1n71GjUNNDj4PXtlrQ62KyklF+HMiCjLLyjKsIv IZGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=nq1XbTkt1vTkv4HhT7D+cz8CUmDBD84eY2DPwK+R49I=; b=Bw2+7v/SCckjqPIfFFvxL3U5hGyUSR/K0eS6N3+vZIkN2fNe2qhg7zgasLX1Af3jPR GBVuQvcwckZhBswDAa1mL8AuDFd/cxY3WTZwuXwfopJUdJR+m9fGgccgt6jsQZVRgv+C uljeDysjs6t2mhDSAziYeMDWVttFYUQup34yDDC2cMDczIM70GdwV/g0oJgs4K9k/kP5 /kLEEuy3GBzto7ebqodyBtLwrzYD3f3WmlpzQf8Ci1zm5vDpU5DZFtYzBUMJwXNvQLRy qpsGsxEuq6P7HKJYyTQ0lW8Zg6M3SZf6NIvXtTAXjq+NccBHdIfMAx0Jk5suZ7U8pUKi 2QGg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hjvzg9a9; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:50 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Dmitry Osipenko , Jon Hunter , Thierry Reding , Thierry Reding , linux-tegra@vger.kernel.org (open list:TEGRA ARCHITECTURE SUPPORT) Subject: [PATCH 23/25] clocksource/drivers/tegra: Set up maximum-ticks limit properly Date: Wed, 26 Jun 2019 16:46:49 +0200 Message-Id: <20190626144651.16742-23-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Dmitry Osipenko Tegra's timer has 29 bits for the counter and for the "load" register which sets counter to a load-value. The counter's value is lower than the actual value by 1 because it starts to decrement after one tick, hence the maximum number of ticks that hardware can handle equals to 29 bits + 1. Signed-off-by: Dmitry Osipenko Acked-by: Jon Hunter Acked-by: Thierry Reding Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-tegra.c | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) -- 2.17.1 diff --git a/drivers/clocksource/timer-tegra.c b/drivers/clocksource/timer-tegra.c index a907e71065bd..e9635c25eef4 100644 --- a/drivers/clocksource/timer-tegra.c +++ b/drivers/clocksource/timer-tegra.c @@ -139,9 +139,17 @@ static int tegra_timer_setup(unsigned int cpu) irq_force_affinity(to->clkevt.irq, cpumask_of(cpu)); enable_irq(to->clkevt.irq); + /* + * Tegra's timer uses n+1 scheme for the counter, i.e. timer will + * fire after one tick if 0 is loaded and thus minimum number of + * ticks is 1. In result both of the clocksource's tick limits are + * higher than a minimum and maximum that hardware register can + * take by 1, this is then taken into account by set_next_event + * callback. + */ clockevents_config_and_register(&to->clkevt, timer_of_rate(to), 1, /* min */ - 0x1fffffff); /* 29 bits */ + 0x1fffffff + 1); /* max 29 bits + 1 */ return 0; } From patchwork Wed Jun 26 14:46:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167821 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp871321ock; Wed, 26 Jun 2019 07:48:03 -0700 (PDT) X-Google-Smtp-Source: APXvYqxZMJLDSvhVvRX/NbzP3+4xCPPyH4XbK0/YlkX9QF73/toDPUcIXQdbjWZfF3UOqbUWqk6d X-Received: by 2002:a65:45c1:: with SMTP id m1mr3493822pgr.260.1561560483489; Wed, 26 Jun 2019 07:48:03 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560483; cv=none; d=google.com; s=arc-20160816; b=tbFxlrtE8rk7O5Z1mQA3fYM8FE5v6V274EwFVVuDFmOKLJIknK/80e7ezsnn2UsVvv zrG+uYkcQkUSgZkc23iXpIrM/87uIze6QTyY/H0VDgui9Cqig5gUQG047v2YyuxP09DH HcRg4h90JOjC86ZHZjjTvFk0dg18eNoWjRfK3nodGFa/8X58lEY342h5f60TMvc8Pqiq MikWMfrRSdVaoOZFz4iBOrtRk1I/DN9r4o95dlAfqYwnQ8XyWMyUbMG8t3OLw97BG6r6 ghKMmg3fPCv2LAAf/iWp1HyYgzz6eGFqslerBTBxmtp7gypxOwhI43bWEyXAXTC4pJ4w SpaQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=Dy8jnockowGt8dviHenRA8qAp72zLWbVdawq1Q1woVo=; b=QTvVzTGSfBx2Cv9+AG+kwKVTespukwm7lUeYOA/4rKQlDR4QypuQsNd9xsAuGP9GeZ 7GKyv8MP8rd8IH11277swTRZepjTFe3HwT7F9P39F9edS3aSnW7ASmqPuCMW3sxxtve/ 97r3CBMWuVIZRWB/zkNA77Zy8XHyP/FFAqY/lf+cyRizBFrGPw4GuVAvLkFDA3ua385c SmHzn6rpyE4Uf+KEl3C3bQDXvfKQL/uNHE6n95+Q9KtXUgMj+kjqnUgylZ3SOPFcqzK6 Zdlj9t7+ZQsxF01yXMvwh0mGCb/m8gml1fcOyvMLgoRioAEvqs9k1o9UxL1NxS8GAXiE gaPQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="vfdE/2zv"; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.54 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:54 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH 24/25] clocksource/drivers/davinci: Add support for clockevents Date: Wed, 26 Jun 2019 16:46:50 +0200 Message-Id: <20190626144651.16742-24-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bartosz Golaszewski Currently the clocksource and clockevent support for davinci platforms lives in mach-davinci. It hard-codes many things, uses global variables, implements functionalities unused by any platform and has code fragments scattered across many (often unrelated) files. Implement a new, modern and simplified timer driver and put it into drivers/clocksource. We still need to support legacy board files so export a config structure and a function that allows machine code to register the timer. The timer we're using is 64-bit but can be programmed in dual 32-bit mode (both chained and unchained). On all davinci SoCs except for da830 we're using both halves. Lower half for clockevents and upper half for clocksource. On da830 we're using the lower half for both with the help of a compare register. This patch contains the core code and support for clockevent. The clocksource code will be included in a subsequent patch. Signed-off-by: Bartosz Golaszewski Signed-off-by: Daniel Lezcano --- drivers/clocksource/Kconfig | 5 + drivers/clocksource/Makefile | 1 + drivers/clocksource/timer-davinci.c | 284 ++++++++++++++++++++++++++++ include/clocksource/timer-davinci.h | 44 +++++ 4 files changed, 334 insertions(+) create mode 100644 drivers/clocksource/timer-davinci.c create mode 100644 include/clocksource/timer-davinci.h -- 2.17.1 diff --git a/drivers/clocksource/Kconfig b/drivers/clocksource/Kconfig index e9936992934a..5e9317dc3d39 100644 --- a/drivers/clocksource/Kconfig +++ b/drivers/clocksource/Kconfig @@ -43,6 +43,11 @@ config BCM_KONA_TIMER help Enables the support for the BCM Kona mobile timer driver. +config DAVINCI_TIMER + bool "Texas Instruments DaVinci timer driver" if COMPILE_TEST + help + Enables the support for the TI DaVinci timer driver. + config DIGICOLOR_TIMER bool "Digicolor timer driver" if COMPILE_TEST select CLKSRC_MMIO diff --git a/drivers/clocksource/Makefile b/drivers/clocksource/Makefile index 0939886b305f..5582252efb31 100644 --- a/drivers/clocksource/Makefile +++ b/drivers/clocksource/Makefile @@ -15,6 +15,7 @@ obj-$(CONFIG_SH_TIMER_TMU) += sh_tmu.o obj-$(CONFIG_EM_TIMER_STI) += em_sti.o obj-$(CONFIG_CLKBLD_I8253) += i8253.o obj-$(CONFIG_CLKSRC_MMIO) += mmio.o +obj-$(CONFIG_DAVINCI_TIMER) += timer-davinci.o obj-$(CONFIG_DIGICOLOR_TIMER) += timer-digicolor.o obj-$(CONFIG_OMAP_DM_TIMER) += timer-ti-dm.o obj-$(CONFIG_DW_APB_TIMER) += dw_apb_timer.o diff --git a/drivers/clocksource/timer-davinci.c b/drivers/clocksource/timer-davinci.c new file mode 100644 index 000000000000..246a5564495d --- /dev/null +++ b/drivers/clocksource/timer-davinci.c @@ -0,0 +1,284 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * TI DaVinci clocksource driver + * + * Copyright (C) 2019 Texas Instruments + * Author: Bartosz Golaszewski + * (with tiny parts adopted from code by Kevin Hilman ) + */ + +#include +#include +#include +#include +#include +#include +#include + +#include + +#undef pr_fmt +#define pr_fmt(fmt) "%s: " fmt "\n", __func__ + +#define DAVINCI_TIMER_REG_TIM12 0x10 +#define DAVINCI_TIMER_REG_TIM34 0x14 +#define DAVINCI_TIMER_REG_PRD12 0x18 +#define DAVINCI_TIMER_REG_PRD34 0x1c +#define DAVINCI_TIMER_REG_TCR 0x20 +#define DAVINCI_TIMER_REG_TGCR 0x24 + +#define DAVINCI_TIMER_TIMMODE_MASK GENMASK(3, 2) +#define DAVINCI_TIMER_RESET_MASK GENMASK(1, 0) +#define DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED BIT(2) +#define DAVINCI_TIMER_UNRESET GENMASK(1, 0) + +#define DAVINCI_TIMER_ENAMODE_MASK GENMASK(1, 0) +#define DAVINCI_TIMER_ENAMODE_DISABLED 0x00 +#define DAVINCI_TIMER_ENAMODE_ONESHOT BIT(0) +#define DAVINCI_TIMER_ENAMODE_PERIODIC BIT(1) + +#define DAVINCI_TIMER_ENAMODE_SHIFT_TIM12 6 +#define DAVINCI_TIMER_ENAMODE_SHIFT_TIM34 22 + +#define DAVINCI_TIMER_MIN_DELTA 0x01 +#define DAVINCI_TIMER_MAX_DELTA 0xfffffffe + +#define DAVINCI_TIMER_TGCR_DEFAULT \ + (DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED | DAVINCI_TIMER_UNRESET) + +struct davinci_clockevent { + struct clock_event_device dev; + void __iomem *base; + unsigned int cmp_off; +}; + +static struct davinci_clockevent * +to_davinci_clockevent(struct clock_event_device *clockevent) +{ + return container_of(clockevent, struct davinci_clockevent, dev); +} + +static unsigned int +davinci_clockevent_read(struct davinci_clockevent *clockevent, + unsigned int reg) +{ + return readl_relaxed(clockevent->base + reg); +} + +static void davinci_clockevent_write(struct davinci_clockevent *clockevent, + unsigned int reg, unsigned int val) +{ + writel_relaxed(val, clockevent->base + reg); +} + +static void davinci_tim12_shutdown(void __iomem *base) +{ + unsigned int tcr; + + tcr = DAVINCI_TIMER_ENAMODE_DISABLED << + DAVINCI_TIMER_ENAMODE_SHIFT_TIM12; + /* + * This function is only ever called if we're using both timer + * halves. In this case TIM34 runs in periodic mode and we must + * not modify it. + */ + tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC << + DAVINCI_TIMER_ENAMODE_SHIFT_TIM34; + + writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); +} + +static void davinci_tim12_set_oneshot(void __iomem *base) +{ + unsigned int tcr; + + tcr = DAVINCI_TIMER_ENAMODE_ONESHOT << + DAVINCI_TIMER_ENAMODE_SHIFT_TIM12; + /* Same as above. */ + tcr |= DAVINCI_TIMER_ENAMODE_PERIODIC << + DAVINCI_TIMER_ENAMODE_SHIFT_TIM34; + + writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); +} + +static int davinci_clockevent_shutdown(struct clock_event_device *dev) +{ + struct davinci_clockevent *clockevent; + + clockevent = to_davinci_clockevent(dev); + + davinci_tim12_shutdown(clockevent->base); + + return 0; +} + +static int davinci_clockevent_set_oneshot(struct clock_event_device *dev) +{ + struct davinci_clockevent *clockevent = to_davinci_clockevent(dev); + + davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0); + + davinci_tim12_set_oneshot(clockevent->base); + + return 0; +} + +static int +davinci_clockevent_set_next_event_std(unsigned long cycles, + struct clock_event_device *dev) +{ + struct davinci_clockevent *clockevent = to_davinci_clockevent(dev); + + davinci_clockevent_shutdown(dev); + + davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_TIM12, 0x0); + davinci_clockevent_write(clockevent, DAVINCI_TIMER_REG_PRD12, cycles); + + davinci_clockevent_set_oneshot(dev); + + return 0; +} + +static int +davinci_clockevent_set_next_event_cmp(unsigned long cycles, + struct clock_event_device *dev) +{ + struct davinci_clockevent *clockevent = to_davinci_clockevent(dev); + unsigned int curr_time; + + curr_time = davinci_clockevent_read(clockevent, + DAVINCI_TIMER_REG_TIM12); + davinci_clockevent_write(clockevent, + clockevent->cmp_off, curr_time + cycles); + + return 0; +} + +static irqreturn_t davinci_timer_irq_timer(int irq, void *data) +{ + struct davinci_clockevent *clockevent = data; + + if (!clockevent_state_oneshot(&clockevent->dev)) + davinci_tim12_shutdown(clockevent->base); + + clockevent->dev.event_handler(&clockevent->dev); + + return IRQ_HANDLED; +} + +static void davinci_timer_init(void __iomem *base) +{ + /* Set clock to internal mode and disable it. */ + writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TCR); + /* + * Reset both 32-bit timers, set no prescaler for timer 34, set the + * timer to dual 32-bit unchained mode, unreset both 32-bit timers. + */ + writel_relaxed(DAVINCI_TIMER_TGCR_DEFAULT, + base + DAVINCI_TIMER_REG_TGCR); + /* Init both counters to zero. */ + writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12); + writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34); +} + +int __init davinci_timer_register(struct clk *clk, + const struct davinci_timer_cfg *timer_cfg) +{ + struct davinci_clockevent *clockevent; + unsigned int tick_rate; + void __iomem *base; + int rv; + + rv = clk_prepare_enable(clk); + if (rv) { + pr_err("Unable to prepare and enable the timer clock"); + return rv; + } + + if (!request_mem_region(timer_cfg->reg.start, + resource_size(&timer_cfg->reg), + "davinci-timer")) { + pr_err("Unable to request memory region"); + return -EBUSY; + } + + base = ioremap(timer_cfg->reg.start, resource_size(&timer_cfg->reg)); + if (!base) { + pr_err("Unable to map the register range"); + return -ENOMEM; + } + + davinci_timer_init(base); + tick_rate = clk_get_rate(clk); + + clockevent = kzalloc(sizeof(*clockevent), GFP_KERNEL | __GFP_NOFAIL); + if (!clockevent) { + pr_err("Error allocating memory for clockevent data"); + return -ENOMEM; + } + + clockevent->dev.name = "tim12"; + clockevent->dev.features = CLOCK_EVT_FEAT_ONESHOT; + clockevent->dev.cpumask = cpumask_of(0); + clockevent->base = base; + + if (timer_cfg->cmp_off) { + clockevent->cmp_off = timer_cfg->cmp_off; + clockevent->dev.set_next_event = + davinci_clockevent_set_next_event_cmp; + } else { + clockevent->dev.set_next_event = + davinci_clockevent_set_next_event_std; + clockevent->dev.set_state_oneshot = + davinci_clockevent_set_oneshot; + clockevent->dev.set_state_shutdown = + davinci_clockevent_shutdown; + } + + rv = request_irq(timer_cfg->irq[DAVINCI_TIMER_CLOCKEVENT_IRQ].start, + davinci_timer_irq_timer, IRQF_TIMER, + "clockevent/tim12", clockevent); + if (rv) { + pr_err("Unable to request the clockevent interrupt"); + return rv; + } + + clockevents_config_and_register(&clockevent->dev, tick_rate, + DAVINCI_TIMER_MIN_DELTA, + DAVINCI_TIMER_MAX_DELTA); + + return 0; +} + +static int __init of_davinci_timer_register(struct device_node *np) +{ + struct davinci_timer_cfg timer_cfg = { }; + struct clk *clk; + int rv; + + rv = of_address_to_resource(np, 0, &timer_cfg.reg); + if (rv) { + pr_err("Unable to get the register range for timer"); + return rv; + } + + rv = of_irq_to_resource_table(np, timer_cfg.irq, + DAVINCI_TIMER_NUM_IRQS); + if (rv != DAVINCI_TIMER_NUM_IRQS) { + pr_err("Unable to get the interrupts for timer"); + return rv; + } + + clk = of_clk_get(np, 0); + if (IS_ERR(clk)) { + pr_err("Unable to get the timer clock"); + return PTR_ERR(clk); + } + + rv = davinci_timer_register(clk, &timer_cfg); + if (rv) + clk_put(clk); + + return rv; +} +TIMER_OF_DECLARE(davinci_timer, "ti,da830-timer", of_davinci_timer_register); diff --git a/include/clocksource/timer-davinci.h b/include/clocksource/timer-davinci.h new file mode 100644 index 000000000000..1dcc1333fbc8 --- /dev/null +++ b/include/clocksource/timer-davinci.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * TI DaVinci clocksource driver + * + * Copyright (C) 2019 Texas Instruments + * Author: Bartosz Golaszewski + */ + +#ifndef __TIMER_DAVINCI_H__ +#define __TIMER_DAVINCI_H__ + +#include +#include + +enum { + DAVINCI_TIMER_CLOCKEVENT_IRQ, + DAVINCI_TIMER_CLOCKSOURCE_IRQ, + DAVINCI_TIMER_NUM_IRQS, +}; + +/** + * struct davinci_timer_cfg - davinci clocksource driver configuration struct + * @reg: register range resource + * @irq: clockevent and clocksource interrupt resources + * @cmp_off: if set - it specifies the compare register used for clockevent + * + * Note: if the compare register is specified, the driver will use the bottom + * clock half for both clocksource and clockevent and the compare register + * to generate event irqs. The user must supply the correct compare register + * interrupt number. + * + * This is only used by da830 the DSP of which uses the top half. The timer + * driver still configures the top half to run in free-run mode. + */ +struct davinci_timer_cfg { + struct resource reg; + struct resource irq[DAVINCI_TIMER_NUM_IRQS]; + unsigned int cmp_off; +}; + +int __init davinci_timer_register(struct clk *clk, + const struct davinci_timer_cfg *data); + +#endif /* __TIMER_DAVINCI_H__ */ From patchwork Wed Jun 26 14:46:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Lezcano X-Patchwork-Id: 167823 Delivered-To: patch@linaro.org Received: by 2002:ac9:6410:0:0:0:0:0 with SMTP id r16csp871417ock; Wed, 26 Jun 2019 07:48:08 -0700 (PDT) X-Google-Smtp-Source: APXvYqx8/z9PTFT58OELMflNP9dAPqNW51bz/1qfAhkFc9pG6PoYz6S7F+4LpjZHJJZKIDbkasd1 X-Received: by 2002:a17:902:76c6:: with SMTP id j6mr5880950plt.263.1561560488497; Wed, 26 Jun 2019 07:48:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1561560488; cv=none; d=google.com; s=arc-20160816; b=y91cWMkvRyPjMYtoaTJVBRMCh9v+nExVWmrin1dDp5TAGTxNZs7QSM5/thPfeS/JNG UPX73/E/iDOrvrKi9vsGY0ixsf5GDQ4NRQscT3PKZCEaA38FGFD17I7jpVZ+vtpl7u98 Z1+Wxa8Lh8PCbjRWUM/rAIv3g7QVLBc3jfq+MwFtaDAJ5Vi5Pl5uMQdoPCZRT27dxRhD Z4m3pxDlxX7Fn2egpbJcx9+IQQZiejLoUXCQ1iZ718ZwTjLbpdhMLfe56G/3ygPQ1Xdn jAxIfoAFKXxShlqDFh3DLo0iwEK1It4+RXQK86fZ/hoM49SsWGcej1P+2MSRaviBlpse 4/6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:references:in-reply-to:message-id:date :subject:cc:to:from:dkim-signature; bh=pZpH6RCNGAxgK3hStX/EjA5VCFJvxP+EAUqW2EeEzuo=; b=C1Vb+JZLkBiHbP0viGgAV73N7H6jxzIuOSgNyS4EjMeW38I4qF9Po8UP7ReOJtkTwd 0DaebELe6OcZLVd4T8xeY2sA5GT+6bhXW0Sl3ZRyhsgNn5j9u7AfNQH4smgFyN3JnNDj uDGVSSOQd0N55zSHhMpowlFBCbWgNkdgqC5GB9UX8QlHal0LfVC+j0E3Rg/x6zibPrs/ xdNKfmjuDqT73N0TtACIdFgl3r07b01V22Xo3GTHNH38eeBDxgVxFmcTvGMU1uoVDMr4 tRbdHQWNjOtEix3oMQENA3g91hLXmLptgZOO3VonJedtLeYnfc4hGu7NdniNbgzVz/re E8Sg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BpPX0SlV; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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[77.130.92.26]) by smtp.gmail.com with ESMTPSA id h84sm2718557wmf.43.2019.06.26.07.47.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 26 Jun 2019 07:47:55 -0700 (PDT) From: Daniel Lezcano To: tglx@linutronix.de Cc: linux-kernel@vger.kernel.org, Bartosz Golaszewski Subject: [PATCH 25/25] clocksource/drivers/davinci: Add support for clocksource Date: Wed, 26 Jun 2019 16:46:51 +0200 Message-Id: <20190626144651.16742-25-daniel.lezcano@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190626144651.16742-1-daniel.lezcano@linaro.org> References: <20190626144651.16742-1-daniel.lezcano@linaro.org> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org From: Bartosz Golaszewski Extend the davinci-timer driver to also register a clock source. Signed-off-by: Bartosz Golaszewski Signed-off-by: Daniel Lezcano --- drivers/clocksource/timer-davinci.c | 85 +++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) -- 2.17.1 diff --git a/drivers/clocksource/timer-davinci.c b/drivers/clocksource/timer-davinci.c index 246a5564495d..62745c962049 100644 --- a/drivers/clocksource/timer-davinci.c +++ b/drivers/clocksource/timer-davinci.c @@ -43,6 +43,8 @@ #define DAVINCI_TIMER_MIN_DELTA 0x01 #define DAVINCI_TIMER_MAX_DELTA 0xfffffffe +#define DAVINCI_TIMER_CLKSRC_BITS 32 + #define DAVINCI_TIMER_TGCR_DEFAULT \ (DAVINCI_TIMER_TIMMODE_32BIT_UNCHAINED | DAVINCI_TIMER_UNRESET) @@ -52,6 +54,16 @@ struct davinci_clockevent { unsigned int cmp_off; }; +/* + * This must be globally accessible by davinci_timer_read_sched_clock(), so + * let's keep it here. + */ +static struct { + struct clocksource dev; + void __iomem *base; + unsigned int tim_off; +} davinci_clocksource; + static struct davinci_clockevent * to_davinci_clockevent(struct clock_event_device *clockevent) { @@ -166,6 +178,53 @@ static irqreturn_t davinci_timer_irq_timer(int irq, void *data) return IRQ_HANDLED; } +static u64 notrace davinci_timer_read_sched_clock(void) +{ + return readl_relaxed(davinci_clocksource.base + + davinci_clocksource.tim_off); +} + +static u64 davinci_clocksource_read(struct clocksource *dev) +{ + return davinci_timer_read_sched_clock(); +} + +/* + * Standard use-case: we're using tim12 for clockevent and tim34 for + * clocksource. The default is making the former run in oneshot mode + * and the latter in periodic mode. + */ +static void davinci_clocksource_init_tim34(void __iomem *base) +{ + int tcr; + + tcr = DAVINCI_TIMER_ENAMODE_PERIODIC << + DAVINCI_TIMER_ENAMODE_SHIFT_TIM34; + tcr |= DAVINCI_TIMER_ENAMODE_ONESHOT << + DAVINCI_TIMER_ENAMODE_SHIFT_TIM12; + + writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM34); + writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD34); + writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); +} + +/* + * Special use-case on da830: the DSP may use tim34. We're using tim12 for + * both clocksource and clockevent. We set tim12 to periodic and don't touch + * tim34. + */ +static void davinci_clocksource_init_tim12(void __iomem *base) +{ + unsigned int tcr; + + tcr = DAVINCI_TIMER_ENAMODE_PERIODIC << + DAVINCI_TIMER_ENAMODE_SHIFT_TIM12; + + writel_relaxed(0x0, base + DAVINCI_TIMER_REG_TIM12); + writel_relaxed(UINT_MAX, base + DAVINCI_TIMER_REG_PRD12); + writel_relaxed(tcr, base + DAVINCI_TIMER_REG_TCR); +} + static void davinci_timer_init(void __iomem *base) { /* Set clock to internal mode and disable it. */ @@ -247,6 +306,32 @@ int __init davinci_timer_register(struct clk *clk, DAVINCI_TIMER_MIN_DELTA, DAVINCI_TIMER_MAX_DELTA); + davinci_clocksource.dev.rating = 300; + davinci_clocksource.dev.read = davinci_clocksource_read; + davinci_clocksource.dev.mask = + CLOCKSOURCE_MASK(DAVINCI_TIMER_CLKSRC_BITS); + davinci_clocksource.dev.flags = CLOCK_SOURCE_IS_CONTINUOUS; + davinci_clocksource.base = base; + + if (timer_cfg->cmp_off) { + davinci_clocksource.dev.name = "tim12"; + davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM12; + davinci_clocksource_init_tim12(base); + } else { + davinci_clocksource.dev.name = "tim34"; + davinci_clocksource.tim_off = DAVINCI_TIMER_REG_TIM34; + davinci_clocksource_init_tim34(base); + } + + rv = clocksource_register_hz(&davinci_clocksource.dev, tick_rate); + if (rv) { + pr_err("Unable to register clocksource"); + return rv; + } + + sched_clock_register(davinci_timer_read_sched_clock, + DAVINCI_TIMER_CLKSRC_BITS, tick_rate); + return 0; }