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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id l5-20020a2e8685000000b002b6ee99fff2sm756803lji.34.2023.07.07.05.30.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 05:30:28 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jonathan Cameron , Lars-Peter Clausen , linux-iio@vger.kernel.org Subject: [PATCH v2 1/8] dt-bindings: iio: adc: qcom, spmi-adc7: use predefined channel ids Date: Fri, 7 Jul 2023 15:30:20 +0300 Message-Id: <20230707123027.1510723-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> References: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Each of qcom,spmi-adc7-pm*.h headers define a set of ADC channels that can be used for monitoring on thie particular chip. Switch them to use channel IDs defined in the dt-bindings/iio/qcom,spmi-vadc.h header instead of specifying the numeric IDs. Suggested-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov Reviewed-by: Krzysztof Kozlowski --- .../dt-bindings/iio/qcom,spmi-adc7-pm8350.h | 88 +++++++------ .../dt-bindings/iio/qcom,spmi-adc7-pm8350b.h | 124 +++++++++--------- .../dt-bindings/iio/qcom,spmi-adc7-pmk8350.h | 50 +++---- .../dt-bindings/iio/qcom,spmi-adc7-pmr735a.h | 22 ++-- .../dt-bindings/iio/qcom,spmi-adc7-pmr735b.h | 22 ++-- 5 files changed, 158 insertions(+), 148 deletions(-) diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h index 09fd169ad18e..5d98f7d48a1e 100644 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350.h @@ -6,58 +6,60 @@ #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H #define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H +#include + /* ADC channels for PM8350_ADC for PMIC7 */ -#define PM8350_ADC7_REF_GND(sid) ((sid) << 8 | 0x0) -#define PM8350_ADC7_1P25VREF(sid) ((sid) << 8 | 0x01) -#define PM8350_ADC7_VREF_VADC(sid) ((sid) << 8 | 0x02) -#define PM8350_ADC7_DIE_TEMP(sid) ((sid) << 8 | 0x03) - -#define PM8350_ADC7_AMUX_THM1(sid) ((sid) << 8 | 0x04) -#define PM8350_ADC7_AMUX_THM2(sid) ((sid) << 8 | 0x05) -#define PM8350_ADC7_AMUX_THM3(sid) ((sid) << 8 | 0x06) -#define PM8350_ADC7_AMUX_THM4(sid) ((sid) << 8 | 0x07) -#define PM8350_ADC7_AMUX_THM5(sid) ((sid) << 8 | 0x08) -#define PM8350_ADC7_GPIO1(sid) ((sid) << 8 | 0x0a) -#define PM8350_ADC7_GPIO2(sid) ((sid) << 8 | 0x0b) -#define PM8350_ADC7_GPIO3(sid) ((sid) << 8 | 0x0c) -#define PM8350_ADC7_GPIO4(sid) ((sid) << 8 | 0x0d) +#define PM8350_ADC7_REF_GND(sid) ((sid) << 8 | ADC7_REF_GND) +#define PM8350_ADC7_1P25VREF(sid) ((sid) << 8 | ADC7_1P25VREF) +#define PM8350_ADC7_VREF_VADC(sid) ((sid) << 8 | ADC7_VREF_VADC) +#define PM8350_ADC7_DIE_TEMP(sid) ((sid) << 8 | ADC7_DIE_TEMP) + +#define PM8350_ADC7_AMUX_THM1(sid) ((sid) << 8 | ADC7_AMUX_THM1) +#define PM8350_ADC7_AMUX_THM2(sid) ((sid) << 8 | ADC7_AMUX_THM2) +#define PM8350_ADC7_AMUX_THM3(sid) ((sid) << 8 | ADC7_AMUX_THM3) +#define PM8350_ADC7_AMUX_THM4(sid) ((sid) << 8 | ADC7_AMUX_THM4) +#define PM8350_ADC7_AMUX_THM5(sid) ((sid) << 8 | ADC7_AMUX_THM5) +#define PM8350_ADC7_GPIO1(sid) ((sid) << 8 | ADC7_GPIO1) +#define PM8350_ADC7_GPIO2(sid) ((sid) << 8 | ADC7_GPIO2) +#define PM8350_ADC7_GPIO3(sid) ((sid) << 8 | ADC7_GPIO3) +#define PM8350_ADC7_GPIO4(sid) ((sid) << 8 | ADC7_GPIO4) /* 30k pull-up1 */ -#define PM8350_ADC7_AMUX_THM1_30K_PU(sid) ((sid) << 8 | 0x24) -#define PM8350_ADC7_AMUX_THM2_30K_PU(sid) ((sid) << 8 | 0x25) -#define PM8350_ADC7_AMUX_THM3_30K_PU(sid) ((sid) << 8 | 0x26) -#define PM8350_ADC7_AMUX_THM4_30K_PU(sid) ((sid) << 8 | 0x27) -#define PM8350_ADC7_AMUX_THM5_30K_PU(sid) ((sid) << 8 | 0x28) -#define PM8350_ADC7_GPIO1_30K_PU(sid) ((sid) << 8 | 0x2a) -#define PM8350_ADC7_GPIO2_30K_PU(sid) ((sid) << 8 | 0x2b) -#define PM8350_ADC7_GPIO3_30K_PU(sid) ((sid) << 8 | 0x2c) -#define PM8350_ADC7_GPIO4_30K_PU(sid) ((sid) << 8 | 0x2d) +#define PM8350_ADC7_AMUX_THM1_30K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM1_30K_PU) +#define PM8350_ADC7_AMUX_THM2_30K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM2_30K_PU) +#define PM8350_ADC7_AMUX_THM3_30K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM3_30K_PU) +#define PM8350_ADC7_AMUX_THM4_30K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM4_30K_PU) +#define PM8350_ADC7_AMUX_THM5_30K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM5_30K_PU) +#define PM8350_ADC7_GPIO1_30K_PU(sid) ((sid) << 8 | ADC7_GPIO1_30K_PU) +#define PM8350_ADC7_GPIO2_30K_PU(sid) ((sid) << 8 | ADC7_GPIO2_30K_PU) +#define PM8350_ADC7_GPIO3_30K_PU(sid) ((sid) << 8 | ADC7_GPIO3_30K_PU) +#define PM8350_ADC7_GPIO4_30K_PU(sid) ((sid) << 8 | ADC7_GPIO4_30K_PU) /* 100k pull-up2 */ -#define PM8350_ADC7_AMUX_THM1_100K_PU(sid) ((sid) << 8 | 0x44) -#define PM8350_ADC7_AMUX_THM2_100K_PU(sid) ((sid) << 8 | 0x45) -#define PM8350_ADC7_AMUX_THM3_100K_PU(sid) ((sid) << 8 | 0x46) -#define PM8350_ADC7_AMUX_THM4_100K_PU(sid) ((sid) << 8 | 0x47) -#define PM8350_ADC7_AMUX_THM5_100K_PU(sid) ((sid) << 8 | 0x48) -#define PM8350_ADC7_GPIO1_100K_PU(sid) ((sid) << 8 | 0x4a) -#define PM8350_ADC7_GPIO2_100K_PU(sid) ((sid) << 8 | 0x4b) -#define PM8350_ADC7_GPIO3_100K_PU(sid) ((sid) << 8 | 0x4c) -#define PM8350_ADC7_GPIO4_100K_PU(sid) ((sid) << 8 | 0x4d) +#define PM8350_ADC7_AMUX_THM1_100K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM1_100K_PU) +#define PM8350_ADC7_AMUX_THM2_100K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM2_100K_PU) +#define PM8350_ADC7_AMUX_THM3_100K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM3_100K_PU) +#define PM8350_ADC7_AMUX_THM4_100K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM4_100K_PU) +#define PM8350_ADC7_AMUX_THM5_100K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM5_100K_PU) +#define PM8350_ADC7_GPIO1_100K_PU(sid) ((sid) << 8 | ADC7_GPIO1_100K_PU) +#define PM8350_ADC7_GPIO2_100K_PU(sid) ((sid) << 8 | ADC7_GPIO2_100K_PU) +#define PM8350_ADC7_GPIO3_100K_PU(sid) ((sid) << 8 | ADC7_GPIO3_100K_PU) +#define PM8350_ADC7_GPIO4_100K_PU(sid) ((sid) << 8 | ADC7_GPIO4_100K_PU) /* 400k pull-up3 */ -#define PM8350_ADC7_AMUX_THM1_400K_PU(sid) ((sid) << 8 | 0x64) -#define PM8350_ADC7_AMUX_THM2_400K_PU(sid) ((sid) << 8 | 0x65) -#define PM8350_ADC7_AMUX_THM3_400K_PU(sid) ((sid) << 8 | 0x66) -#define PM8350_ADC7_AMUX_THM4_400K_PU(sid) ((sid) << 8 | 0x67) -#define PM8350_ADC7_AMUX_THM5_400K_PU(sid) ((sid) << 8 | 0x68) -#define PM8350_ADC7_GPIO1_400K_PU(sid) ((sid) << 8 | 0x6a) -#define PM8350_ADC7_GPIO2_400K_PU(sid) ((sid) << 8 | 0x6b) -#define PM8350_ADC7_GPIO3_400K_PU(sid) ((sid) << 8 | 0x6c) -#define PM8350_ADC7_GPIO4_400K_PU(sid) ((sid) << 8 | 0x6d) +#define PM8350_ADC7_AMUX_THM1_400K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM1_400K_PU) +#define PM8350_ADC7_AMUX_THM2_400K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM2_400K_PU) +#define PM8350_ADC7_AMUX_THM3_400K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM3_400K_PU) +#define PM8350_ADC7_AMUX_THM4_400K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM4_400K_PU) +#define PM8350_ADC7_AMUX_THM5_400K_PU(sid) ((sid) << 8 | ADC7_AMUX_THM5_400K_PU) +#define PM8350_ADC7_GPIO1_400K_PU(sid) ((sid) << 8 | ADC7_GPIO1_400K_PU) +#define PM8350_ADC7_GPIO2_400K_PU(sid) ((sid) << 8 | ADC7_GPIO2_400K_PU) +#define PM8350_ADC7_GPIO3_400K_PU(sid) ((sid) << 8 | ADC7_GPIO3_400K_PU) +#define PM8350_ADC7_GPIO4_400K_PU(sid) ((sid) << 8 | ADC7_GPIO4_400K_PU) /* 1/3 Divider */ -#define PM8350_ADC7_GPIO4_DIV3(sid) ((sid) << 8 | 0x8d) +#define PM8350_ADC7_GPIO4_DIV3(sid) ((sid) << 8 | ADC7_GPIO4_DIV3) -#define PM8350_ADC7_VPH_PWR(sid) ((sid) << 8 | 0x8e) +#define PM8350_ADC7_VPH_PWR(sid) ((sid) << 8 | ADC7_VPH_PWR) #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h index dc2497c27e16..57c7977666d3 100644 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pm8350b.h @@ -10,79 +10,81 @@ #define PM8350B_SID 3 #endif +#include + /* ADC channels for PM8350B_ADC for PMIC7 */ -#define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | 0x0) -#define PM8350B_ADC7_1P25VREF (PM8350B_SID << 8 | 0x01) -#define PM8350B_ADC7_VREF_VADC (PM8350B_SID << 8 | 0x02) -#define PM8350B_ADC7_DIE_TEMP (PM8350B_SID << 8 | 0x03) +#define PM8350B_ADC7_REF_GND (PM8350B_SID << 8 | ADC7_REF_GND) +#define PM8350B_ADC7_1P25VREF (PM8350B_SID << 8 | ADC7_1P25VREF) +#define PM8350B_ADC7_VREF_VADC (PM8350B_SID << 8 | ADC7_VREF_VADC) +#define PM8350B_ADC7_DIE_TEMP (PM8350B_SID << 8 | ADC7_DIE_TEMP) -#define PM8350B_ADC7_AMUX_THM1 (PM8350B_SID << 8 | 0x04) -#define PM8350B_ADC7_AMUX_THM2 (PM8350B_SID << 8 | 0x05) -#define PM8350B_ADC7_AMUX_THM3 (PM8350B_SID << 8 | 0x06) -#define PM8350B_ADC7_AMUX_THM4 (PM8350B_SID << 8 | 0x07) -#define PM8350B_ADC7_AMUX_THM5 (PM8350B_SID << 8 | 0x08) -#define PM8350B_ADC7_AMUX_THM6 (PM8350B_SID << 8 | 0x09) -#define PM8350B_ADC7_GPIO1 (PM8350B_SID << 8 | 0x0a) -#define PM8350B_ADC7_GPIO2 (PM8350B_SID << 8 | 0x0b) -#define PM8350B_ADC7_GPIO3 (PM8350B_SID << 8 | 0x0c) -#define PM8350B_ADC7_GPIO4 (PM8350B_SID << 8 | 0x0d) +#define PM8350B_ADC7_AMUX_THM1 (PM8350B_SID << 8 | ADC7_AMUX_THM1) +#define PM8350B_ADC7_AMUX_THM2 (PM8350B_SID << 8 | ADC7_AMUX_THM2) +#define PM8350B_ADC7_AMUX_THM3 (PM8350B_SID << 8 | ADC7_AMUX_THM3) +#define PM8350B_ADC7_AMUX_THM4 (PM8350B_SID << 8 | ADC7_AMUX_THM4) +#define PM8350B_ADC7_AMUX_THM5 (PM8350B_SID << 8 | ADC7_AMUX_THM5) +#define PM8350B_ADC7_AMUX_THM6 (PM8350B_SID << 8 | ADC7_AMUX_THM6) +#define PM8350B_ADC7_GPIO1 (PM8350B_SID << 8 | ADC7_GPIO1) +#define PM8350B_ADC7_GPIO2 (PM8350B_SID << 8 | ADC7_GPIO2) +#define PM8350B_ADC7_GPIO3 (PM8350B_SID << 8 | ADC7_GPIO3) +#define PM8350B_ADC7_GPIO4 (PM8350B_SID << 8 | ADC7_GPIO4) -#define PM8350B_ADC7_CHG_TEMP (PM8350B_SID << 8 | 0x10) -#define PM8350B_ADC7_USB_IN_V_16 (PM8350B_SID << 8 | 0x11) -#define PM8350B_ADC7_VDC_16 (PM8350B_SID << 8 | 0x12) -#define PM8350B_ADC7_CC1_ID (PM8350B_SID << 8 | 0x13) -#define PM8350B_ADC7_VREF_BAT_THERM (PM8350B_SID << 8 | 0x15) -#define PM8350B_ADC7_IIN_FB (PM8350B_SID << 8 | 0x17) +#define PM8350B_ADC7_CHG_TEMP (PM8350B_SID << 8 | ADC7_CHG_TEMP) +#define PM8350B_ADC7_USB_IN_V_16 (PM8350B_SID << 8 | ADC7_USB_IN_V_16) +#define PM8350B_ADC7_VDC_16 (PM8350B_SID << 8 | ADC7_VDC_16) +#define PM8350B_ADC7_CC1_ID (PM8350B_SID << 8 | ADC7_CC1_ID) +#define PM8350B_ADC7_VREF_BAT_THERM (PM8350B_SID << 8 | ADC7_VREF_BAT_THERM) +#define PM8350B_ADC7_IIN_FB (PM8350B_SID << 8 | ADC7_IIN_FB) /* 30k pull-up1 */ -#define PM8350B_ADC7_AMUX_THM1_30K_PU (PM8350B_SID << 8 | 0x24) -#define PM8350B_ADC7_AMUX_THM2_30K_PU (PM8350B_SID << 8 | 0x25) -#define PM8350B_ADC7_AMUX_THM3_30K_PU (PM8350B_SID << 8 | 0x26) -#define PM8350B_ADC7_AMUX_THM4_30K_PU (PM8350B_SID << 8 | 0x27) -#define PM8350B_ADC7_AMUX_THM5_30K_PU (PM8350B_SID << 8 | 0x28) -#define PM8350B_ADC7_AMUX_THM6_30K_PU (PM8350B_SID << 8 | 0x29) -#define PM8350B_ADC7_GPIO1_30K_PU (PM8350B_SID << 8 | 0x2a) -#define PM8350B_ADC7_GPIO2_30K_PU (PM8350B_SID << 8 | 0x2b) -#define PM8350B_ADC7_GPIO3_30K_PU (PM8350B_SID << 8 | 0x2c) -#define PM8350B_ADC7_GPIO4_30K_PU (PM8350B_SID << 8 | 0x2d) -#define PM8350B_ADC7_CC1_ID_30K_PU (PM8350B_SID << 8 | 0x33) +#define PM8350B_ADC7_AMUX_THM1_30K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM1_30K_PU) +#define PM8350B_ADC7_AMUX_THM2_30K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM2_30K_PU) +#define PM8350B_ADC7_AMUX_THM3_30K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM3_30K_PU) +#define PM8350B_ADC7_AMUX_THM4_30K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM4_30K_PU) +#define PM8350B_ADC7_AMUX_THM5_30K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM5_30K_PU) +#define PM8350B_ADC7_AMUX_THM6_30K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM6_30K_PU) +#define PM8350B_ADC7_GPIO1_30K_PU (PM8350B_SID << 8 | ADC7_GPIO1_30K_PU) +#define PM8350B_ADC7_GPIO2_30K_PU (PM8350B_SID << 8 | ADC7_GPIO2_30K_PU) +#define PM8350B_ADC7_GPIO3_30K_PU (PM8350B_SID << 8 | ADC7_GPIO3_30K_PU) +#define PM8350B_ADC7_GPIO4_30K_PU (PM8350B_SID << 8 | ADC7_GPIO4_30K_PU) +#define PM8350B_ADC7_CC1_ID_30K_PU (PM8350B_SID << 8 | ADC7_CC1_ID_30K_PU) /* 100k pull-up2 */ -#define PM8350B_ADC7_AMUX_THM1_100K_PU (PM8350B_SID << 8 | 0x44) -#define PM8350B_ADC7_AMUX_THM2_100K_PU (PM8350B_SID << 8 | 0x45) -#define PM8350B_ADC7_AMUX_THM3_100K_PU (PM8350B_SID << 8 | 0x46) -#define PM8350B_ADC7_AMUX_THM4_100K_PU (PM8350B_SID << 8 | 0x47) -#define PM8350B_ADC7_AMUX_THM5_100K_PU (PM8350B_SID << 8 | 0x48) -#define PM8350B_ADC7_AMUX_THM6_100K_PU (PM8350B_SID << 8 | 0x49) -#define PM8350B_ADC7_GPIO1_100K_PU (PM8350B_SID << 8 | 0x4a) -#define PM8350B_ADC7_GPIO2_100K_PU (PM8350B_SID << 8 | 0x4b) -#define PM8350B_ADC7_GPIO3_100K_PU (PM8350B_SID << 8 | 0x4c) -#define PM8350B_ADC7_GPIO4_100K_PU (PM8350B_SID << 8 | 0x4d) -#define PM8350B_ADC7_CC1_ID_100K_PU (PM8350B_SID << 8 | 0x53) +#define PM8350B_ADC7_AMUX_THM1_100K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM1_100K_PU) +#define PM8350B_ADC7_AMUX_THM2_100K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM2_100K_PU) +#define PM8350B_ADC7_AMUX_THM3_100K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM3_100K_PU) +#define PM8350B_ADC7_AMUX_THM4_100K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM4_100K_PU) +#define PM8350B_ADC7_AMUX_THM5_100K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM5_100K_PU) +#define PM8350B_ADC7_AMUX_THM6_100K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM6_100K_PU) +#define PM8350B_ADC7_GPIO1_100K_PU (PM8350B_SID << 8 | ADC7_GPIO1_100K_PU) +#define PM8350B_ADC7_GPIO2_100K_PU (PM8350B_SID << 8 | ADC7_GPIO2_100K_PU) +#define PM8350B_ADC7_GPIO3_100K_PU (PM8350B_SID << 8 | ADC7_GPIO3_100K_PU) +#define PM8350B_ADC7_GPIO4_100K_PU (PM8350B_SID << 8 | ADC7_GPIO4_100K_PU) +#define PM8350B_ADC7_CC1_ID_100K_PU (PM8350B_SID << 8 | ADC7_CC1_ID_100K_PU) /* 400k pull-up3 */ -#define PM8350B_ADC7_AMUX_THM1_400K_PU (PM8350B_SID << 8 | 0x64) -#define PM8350B_ADC7_AMUX_THM2_400K_PU (PM8350B_SID << 8 | 0x65) -#define PM8350B_ADC7_AMUX_THM3_400K_PU (PM8350B_SID << 8 | 0x66) -#define PM8350B_ADC7_AMUX_THM4_400K_PU (PM8350B_SID << 8 | 0x67) -#define PM8350B_ADC7_AMUX_THM5_400K_PU (PM8350B_SID << 8 | 0x68) -#define PM8350B_ADC7_AMUX_THM6_400K_PU (PM8350B_SID << 8 | 0x69) -#define PM8350B_ADC7_GPIO1_400K_PU (PM8350B_SID << 8 | 0x6a) -#define PM8350B_ADC7_GPIO2_400K_PU (PM8350B_SID << 8 | 0x6b) -#define PM8350B_ADC7_GPIO3_400K_PU (PM8350B_SID << 8 | 0x6c) -#define PM8350B_ADC7_GPIO4_400K_PU (PM8350B_SID << 8 | 0x6d) -#define PM8350B_ADC7_CC1_ID_400K_PU (PM8350B_SID << 8 | 0x73) +#define PM8350B_ADC7_AMUX_THM1_400K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM1_400K_PU) +#define PM8350B_ADC7_AMUX_THM2_400K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM2_400K_PU) +#define PM8350B_ADC7_AMUX_THM3_400K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM3_400K_PU) +#define PM8350B_ADC7_AMUX_THM4_400K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM4_400K_PU) +#define PM8350B_ADC7_AMUX_THM5_400K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM5_400K_PU) +#define PM8350B_ADC7_AMUX_THM6_400K_PU (PM8350B_SID << 8 | ADC7_AMUX_THM6_400K_PU) +#define PM8350B_ADC7_GPIO1_400K_PU (PM8350B_SID << 8 | ADC7_GPIO1_400K_PU) +#define PM8350B_ADC7_GPIO2_400K_PU (PM8350B_SID << 8 | ADC7_GPIO2_400K_PU) +#define PM8350B_ADC7_GPIO3_400K_PU (PM8350B_SID << 8 | ADC7_GPIO3_400K_PU) +#define PM8350B_ADC7_GPIO4_400K_PU (PM8350B_SID << 8 | ADC7_GPIO4_400K_PU) +#define PM8350B_ADC7_CC1_ID_400K_PU (PM8350B_SID << 8 | ADC7_CC1_ID_400K_PU) /* 1/3 Divider */ -#define PM8350B_ADC7_GPIO1_DIV3 (PM8350B_SID << 8 | 0x8a) -#define PM8350B_ADC7_GPIO2_DIV3 (PM8350B_SID << 8 | 0x8b) -#define PM8350B_ADC7_GPIO3_DIV3 (PM8350B_SID << 8 | 0x8c) -#define PM8350B_ADC7_GPIO4_DIV3 (PM8350B_SID << 8 | 0x8d) +#define PM8350B_ADC7_GPIO1_DIV3 (PM8350B_SID << 8 | ADC7_GPIO1_DIV3) +#define PM8350B_ADC7_GPIO2_DIV3 (PM8350B_SID << 8 | ADC7_GPIO2_DIV3) +#define PM8350B_ADC7_GPIO3_DIV3 (PM8350B_SID << 8 | ADC7_GPIO3_DIV3) +#define PM8350B_ADC7_GPIO4_DIV3 (PM8350B_SID << 8 | ADC7_GPIO4_DIV3) -#define PM8350B_ADC7_VPH_PWR (PM8350B_SID << 8 | 0x8e) -#define PM8350B_ADC7_VBAT_SNS (PM8350B_SID << 8 | 0x8f) +#define PM8350B_ADC7_VPH_PWR (PM8350B_SID << 8 | ADC7_VPH_PWR) +#define PM8350B_ADC7_VBAT_SNS (PM8350B_SID << 8 | ADC7_VBAT_SNS) -#define PM8350B_ADC7_SBUx (PM8350B_SID << 8 | 0x94) -#define PM8350B_ADC7_VBAT_2S_MID (PM8350B_SID << 8 | 0x96) +#define PM8350B_ADC7_SBUx (PM8350B_SID << 8 | ADC7_SBU) +#define PM8350B_ADC7_VBAT_2S_MID (PM8350B_SID << 8 | ADC7_VBAT_2S_MID) #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350B_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h index 6c296870e95b..3d1a41a22cef 100644 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pmk8350.h @@ -10,37 +10,39 @@ #define PMK8350_SID 0 #endif +#include + /* ADC channels for PMK8350_ADC for PMIC7 */ -#define PMK8350_ADC7_REF_GND (PMK8350_SID << 8 | 0x0) -#define PMK8350_ADC7_1P25VREF (PMK8350_SID << 8 | 0x01) -#define PMK8350_ADC7_VREF_VADC (PMK8350_SID << 8 | 0x02) -#define PMK8350_ADC7_DIE_TEMP (PMK8350_SID << 8 | 0x03) +#define PMK8350_ADC7_REF_GND (PMK8350_SID << 8 | ADC7_REF_GND) +#define PMK8350_ADC7_1P25VREF (PMK8350_SID << 8 | ADC7_1P25VREF) +#define PMK8350_ADC7_VREF_VADC (PMK8350_SID << 8 | ADC7_VREF_VADC) +#define PMK8350_ADC7_DIE_TEMP (PMK8350_SID << 8 | ADC7_DIE_TEMP) -#define PMK8350_ADC7_AMUX_THM1 (PMK8350_SID << 8 | 0x04) -#define PMK8350_ADC7_AMUX_THM2 (PMK8350_SID << 8 | 0x05) -#define PMK8350_ADC7_AMUX_THM3 (PMK8350_SID << 8 | 0x06) -#define PMK8350_ADC7_AMUX_THM4 (PMK8350_SID << 8 | 0x07) -#define PMK8350_ADC7_AMUX_THM5 (PMK8350_SID << 8 | 0x08) +#define PMK8350_ADC7_AMUX_THM1 (PMK8350_SID << 8 | ADC7_AMUX_THM1) +#define PMK8350_ADC7_AMUX_THM2 (PMK8350_SID << 8 | ADC7_AMUX_THM2) +#define PMK8350_ADC7_AMUX_THM3 (PMK8350_SID << 8 | ADC7_AMUX_THM3) +#define PMK8350_ADC7_AMUX_THM4 (PMK8350_SID << 8 | ADC7_AMUX_THM4) +#define PMK8350_ADC7_AMUX_THM5 (PMK8350_SID << 8 | ADC7_AMUX_THM5) /* 30k pull-up1 */ -#define PMK8350_ADC7_AMUX_THM1_30K_PU (PMK8350_SID << 8 | 0x24) -#define PMK8350_ADC7_AMUX_THM2_30K_PU (PMK8350_SID << 8 | 0x25) -#define PMK8350_ADC7_AMUX_THM3_30K_PU (PMK8350_SID << 8 | 0x26) -#define PMK8350_ADC7_AMUX_THM4_30K_PU (PMK8350_SID << 8 | 0x27) -#define PMK8350_ADC7_AMUX_THM5_30K_PU (PMK8350_SID << 8 | 0x28) +#define PMK8350_ADC7_AMUX_THM1_30K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM1_30K_PU) +#define PMK8350_ADC7_AMUX_THM2_30K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM2_30K_PU) +#define PMK8350_ADC7_AMUX_THM3_30K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM3_30K_PU) +#define PMK8350_ADC7_AMUX_THM4_30K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM4_30K_PU) +#define PMK8350_ADC7_AMUX_THM5_30K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM5_30K_PU) /* 100k pull-up2 */ -#define PMK8350_ADC7_AMUX_THM1_100K_PU (PMK8350_SID << 8 | 0x44) -#define PMK8350_ADC7_AMUX_THM2_100K_PU (PMK8350_SID << 8 | 0x45) -#define PMK8350_ADC7_AMUX_THM3_100K_PU (PMK8350_SID << 8 | 0x46) -#define PMK8350_ADC7_AMUX_THM4_100K_PU (PMK8350_SID << 8 | 0x47) -#define PMK8350_ADC7_AMUX_THM5_100K_PU (PMK8350_SID << 8 | 0x48) +#define PMK8350_ADC7_AMUX_THM1_100K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM1_100K_PU) +#define PMK8350_ADC7_AMUX_THM2_100K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM2_100K_PU) +#define PMK8350_ADC7_AMUX_THM3_100K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM3_100K_PU) +#define PMK8350_ADC7_AMUX_THM4_100K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM4_100K_PU) +#define PMK8350_ADC7_AMUX_THM5_100K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM5_100K_PU) /* 400k pull-up3 */ -#define PMK8350_ADC7_AMUX_THM1_400K_PU (PMK8350_SID << 8 | 0x64) -#define PMK8350_ADC7_AMUX_THM2_400K_PU (PMK8350_SID << 8 | 0x65) -#define PMK8350_ADC7_AMUX_THM3_400K_PU (PMK8350_SID << 8 | 0x66) -#define PMK8350_ADC7_AMUX_THM4_400K_PU (PMK8350_SID << 8 | 0x67) -#define PMK8350_ADC7_AMUX_THM5_400K_PU (PMK8350_SID << 8 | 0x68) +#define PMK8350_ADC7_AMUX_THM1_400K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM1_400K_PU) +#define PMK8350_ADC7_AMUX_THM2_400K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM2_400K_PU) +#define PMK8350_ADC7_AMUX_THM3_400K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM3_400K_PU) +#define PMK8350_ADC7_AMUX_THM4_400K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM4_400K_PU) +#define PMK8350_ADC7_AMUX_THM5_400K_PU (PMK8350_SID << 8 | ADC7_AMUX_THM5_400K_PU) #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMK8350_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h index d6df1b19e5ff..c5adfa82b20d 100644 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735a.h @@ -10,19 +10,21 @@ #define PMR735A_SID 4 #endif +#include + /* ADC channels for PMR735A_ADC for PMIC7 */ -#define PMR735A_ADC7_REF_GND (PMR735A_SID << 8 | 0x0) -#define PMR735A_ADC7_1P25VREF (PMR735A_SID << 8 | 0x01) -#define PMR735A_ADC7_VREF_VADC (PMR735A_SID << 8 | 0x02) -#define PMR735A_ADC7_DIE_TEMP (PMR735A_SID << 8 | 0x03) +#define PMR735A_ADC7_REF_GND (PMR735A_SID << 8 | ADC7_REF_GND) +#define PMR735A_ADC7_1P25VREF (PMR735A_SID << 8 | ADC7_1P25VREF) +#define PMR735A_ADC7_VREF_VADC (PMR735A_SID << 8 | ADC7_VREF_VADC) +#define PMR735A_ADC7_DIE_TEMP (PMR735A_SID << 8 | ADC7_DIE_TEMP) -#define PMR735A_ADC7_GPIO1 (PMR735A_SID << 8 | 0x0a) -#define PMR735A_ADC7_GPIO2 (PMR735A_SID << 8 | 0x0b) -#define PMR735A_ADC7_GPIO3 (PMR735A_SID << 8 | 0x0c) +#define PMR735A_ADC7_GPIO1 (PMR735A_SID << 8 | ADC7_GPIO1) +#define PMR735A_ADC7_GPIO2 (PMR735A_SID << 8 | ADC7_GPIO2) +#define PMR735A_ADC7_GPIO3 (PMR735A_SID << 8 | ADC7_GPIO3) /* 100k pull-up2 */ -#define PMR735A_ADC7_GPIO1_100K_PU (PMR735A_SID << 8 | 0x4a) -#define PMR735A_ADC7_GPIO2_100K_PU (PMR735A_SID << 8 | 0x4b) -#define PMR735A_ADC7_GPIO3_100K_PU (PMR735A_SID << 8 | 0x4c) +#define PMR735A_ADC7_GPIO1_100K_PU (PMR735A_SID << 8 | ADC7_GPIO1_100K_PU) +#define PMR735A_ADC7_GPIO2_100K_PU (PMR735A_SID << 8 | ADC7_GPIO2_100K_PU) +#define PMR735A_ADC7_GPIO3_100K_PU (PMR735A_SID << 8 | ADC7_GPIO3_100K_PU) #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735A_H */ diff --git a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h index 8da0e7dab315..fdb8dd9ae541 100644 --- a/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h +++ b/include/dt-bindings/iio/qcom,spmi-adc7-pmr735b.h @@ -10,19 +10,21 @@ #define PMR735B_SID 5 #endif +#include + /* ADC channels for PMR735B_ADC for PMIC7 */ -#define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | 0x0) -#define PMR735B_ADC7_1P25VREF (PMR735B_SID << 8 | 0x01) -#define PMR735B_ADC7_VREF_VADC (PMR735B_SID << 8 | 0x02) -#define PMR735B_ADC7_DIE_TEMP (PMR735B_SID << 8 | 0x03) +#define PMR735B_ADC7_REF_GND (PMR735B_SID << 8 | ADC7_REF_GND) +#define PMR735B_ADC7_1P25VREF (PMR735B_SID << 8 | ADC7_1P25VREF) +#define PMR735B_ADC7_VREF_VADC (PMR735B_SID << 8 | ADC7_VREF_VADC) +#define PMR735B_ADC7_DIE_TEMP (PMR735B_SID << 8 | ADC7_DIE_TEMP) -#define PMR735B_ADC7_GPIO1 (PMR735B_SID << 8 | 0x0a) -#define PMR735B_ADC7_GPIO2 (PMR735B_SID << 8 | 0x0b) -#define PMR735B_ADC7_GPIO3 (PMR735B_SID << 8 | 0x0c) +#define PMR735B_ADC7_GPIO1 (PMR735B_SID << 8 | ADC7_GPIO1) +#define PMR735B_ADC7_GPIO2 (PMR735B_SID << 8 | ADC7_GPIO2) +#define PMR735B_ADC7_GPIO3 (PMR735B_SID << 8 | ADC7_GPIO3) /* 100k pull-up2 */ -#define PMR735B_ADC7_GPIO1_100K_PU (PMR735B_SID << 8 | 0x4a) -#define PMR735B_ADC7_GPIO2_100K_PU (PMR735B_SID << 8 | 0x4b) -#define PMR735B_ADC7_GPIO3_100K_PU (PMR735B_SID << 8 | 0x4c) +#define PMR735B_ADC7_GPIO1_100K_PU (PMR735B_SID << 8 | ADC7_GPIO1_100K_PU) +#define PMR735B_ADC7_GPIO2_100K_PU (PMR735B_SID << 8 | ADC7_GPIO2_100K_PU) +#define PMR735B_ADC7_GPIO3_100K_PU (PMR735B_SID << 8 | ADC7_GPIO3_100K_PU) #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PMR735B_H */ From patchwork Fri Jul 7 12:30:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 700410 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3164DC00528 for ; Fri, 7 Jul 2023 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id l5-20020a2e8685000000b002b6ee99fff2sm756803lji.34.2023.07.07.05.30.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 05:30:29 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jonathan Cameron , Lars-Peter Clausen , linux-iio@vger.kernel.org Subject: [PATCH v2 2/8] arm64: dts: qcom: pm8350: fix thermal zone name Date: Fri, 7 Jul 2023 15:30:21 +0300 Message-Id: <20230707123027.1510723-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> References: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The name of the thermal zone in pm8350.dtsi (pm8350c-thermal) conflicts with the thermal zone in pm8350c.dtsi. Rename the thermal zone according to the chip name. Fixes: 7a79b95f4288 ("arm64: dts: qcom: pm8350: add temp sensor and thermal zone config") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/pm8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8350.dtsi b/arch/arm64/boot/dts/qcom/pm8350.dtsi index 2dfeb99300d7..9ed9ba23e81e 100644 --- a/arch/arm64/boot/dts/qcom/pm8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350.dtsi @@ -8,7 +8,7 @@ / { thermal-zones { - pm8350_thermal: pm8350c-thermal { + pm8350_thermal: pm8350-thermal { polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&pm8350_temp_alarm>; From patchwork Fri Jul 7 12:30:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 700194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A147C04A6A for ; Fri, 7 Jul 2023 12:30:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232634AbjGGMam (ORCPT ); Fri, 7 Jul 2023 08:30:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232577AbjGGMak (ORCPT ); Fri, 7 Jul 2023 08:30:40 -0400 Received: from mail-lj1-x22c.google.com (mail-lj1-x22c.google.com [IPv6:2a00:1450:4864:20::22c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C89A213B for ; Fri, 7 Jul 2023 05:30:32 -0700 (PDT) Received: by mail-lj1-x22c.google.com with SMTP id 38308e7fff4ca-2b70bfc8db5so14155211fa.2 for ; Fri, 07 Jul 2023 05:30:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688733031; x=1691325031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+iOhcYpnzo0XIV0YBU7Aq8iXtwYGavR9eFvXZloUIQ8=; b=wGceMGK7XXBwAwlUtHh99qpcolXpleueiazdnHEdysvWB0uA98ZxytfmjJESZXrbuw 5h6WRAc92f/nIMUuLzjy9oQp5vlQK1JOKCPcT221fnICI6jVM4hwXDwFEhtO7E4m04yP 4vLZ/uqcnTtYYYcd3s3rjBeRmIPnQWVpT6LeE/WqY9fJeZ4csnr3zAGV8WjKQfjEqDMn 2e1JOybYDfs/NwfGoP6wfmmOgtiZrRzHkEtAkEL1SsuxS5ySQUz0tFw+Wy/HNBIAf4Qa erGllcSCxRIZoSoFAIDBH3N9uB/RVIck771EKrCrxavdDoBnnPbYtyw2CDy9aoEIqKLB UKTQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688733031; x=1691325031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+iOhcYpnzo0XIV0YBU7Aq8iXtwYGavR9eFvXZloUIQ8=; b=ReN3r4fUHSIIdZV0RgPedLEO0pZD34bLfi0PX0GMchVyymhAS4z6s4xvebDlJUvmno W/wUlGM7MKhR4vmzRgNFzq6nszxua0lr/QGAgs32qMqDId5C7+W8xVvflj6q2aO1/C3U wunN8gNeFDOUt8h+bwQeGnIpEcjKtktlIOJIoxQBZQ3e5Dhaj3tAsdwtH+YQcV53pjuc QgfxorNEkCtyH2okTaLTLyGuL8npUHO3JWu0up3TEU04Hy7nHsuTWvZ7yGBjXnbAMDB3 vCgJ48vHjfC3pjT+ZwbfIS+CBJrW/viv+nTTUWEN308oGzWOByoc2cvGahPI0LQZWqTc P8SA== X-Gm-Message-State: ABy/qLYhPP89P9LXWrB605JAtZn1KYZl53HaEqXNHRzaDS5DmN1Bqc8j juUrFFhvPTqTZhpmCHoQs5MKqg== X-Google-Smtp-Source: APBJJlFfJhjGwXsY+2oKhsXoUHiy189s6DkLIg75Za/l/C8VYS/r3oD5tr71GYraH1xRa97GjDARLw== X-Received: by 2002:a2e:8447:0:b0:2b5:80c9:9806 with SMTP id u7-20020a2e8447000000b002b580c99806mr3430469ljh.6.1688733030723; Fri, 07 Jul 2023 05:30:30 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id l5-20020a2e8685000000b002b6ee99fff2sm756803lji.34.2023.07.07.05.30.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 05:30:30 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jonathan Cameron , Lars-Peter Clausen , linux-iio@vger.kernel.org Subject: [PATCH v2 3/8] arm64: dts: qcom: pm8350b: fix thermal zone name Date: Fri, 7 Jul 2023 15:30:22 +0300 Message-Id: <20230707123027.1510723-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> References: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The name of the thermal zone in pm8350b.dtsi (pm8350c-thermal) conflicts with the thermal zone in pm8350c.dtsi. Rename the thermal zone according to the chip name. Fixes: 5c1399299d9d ("arm64: dts: qcom: pm8350b: add temp sensor and thermal zone config") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/pm8350b.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pm8350b.dtsi b/arch/arm64/boot/dts/qcom/pm8350b.dtsi index f1c7bd9d079c..05c105898892 100644 --- a/arch/arm64/boot/dts/qcom/pm8350b.dtsi +++ b/arch/arm64/boot/dts/qcom/pm8350b.dtsi @@ -8,7 +8,7 @@ / { thermal-zones { - pm8350b_thermal: pm8350c-thermal { + pm8350b_thermal: pm8350b-thermal { polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&pm8350b_temp_alarm>; From patchwork Fri Jul 7 12:30:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 700409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 398F0C001DF for ; Fri, 7 Jul 2023 12:30:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232307AbjGGMan (ORCPT ); Fri, 7 Jul 2023 08:30:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59378 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232589AbjGGMal (ORCPT ); Fri, 7 Jul 2023 08:30:41 -0400 Received: from mail-lj1-x235.google.com (mail-lj1-x235.google.com [IPv6:2a00:1450:4864:20::235]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 562FE268A for ; Fri, 7 Jul 2023 05:30:33 -0700 (PDT) Received: by mail-lj1-x235.google.com with SMTP id 38308e7fff4ca-2b5c231c23aso29105941fa.0 for ; Fri, 07 Jul 2023 05:30:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688733031; x=1691325031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=89AdRZgQvPlVelxOzYk73hwb0yohQu0q875LmPhcpjU=; b=g9fUlbmUbO51cBm23uFw+HH6Qus0lvYED9r0yPf26KNI17omm0G0fkq4+CFxbanuul nMFhrJEmgbKuIRplh5ZGyKKhBV+TRWsr0xu0F4LiTjuHgU15fE8YiZHxaQiXduXy7yWC /wzY72rzuIXePBS6fqe1l0uW5QEhFKMlI3PLJdguT2gMrIkwLxRagx/+U+FBKE6VxyYG NMhIHrGCgtGPk66ScSkpxRTHrKicdfO27GP6BU0y/QFM556z2Cr6EfWJii31IoSda4SZ Cl5ZB0Ga3ZVRTkQotB9pYBYDBLNPsibXgxA+yilvMktj+FFU7ISFIrH4hUhoVWScPq1C vMPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688733031; x=1691325031; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=89AdRZgQvPlVelxOzYk73hwb0yohQu0q875LmPhcpjU=; b=OcG+Gf+wuNgxwpuoZyB1+3RIHMgeb4F0t89T6N7ZYAr0ZjHB56NjPaheKxld4jc3mJ lTMniTf06EL9q4J1jbDOhQMsij/PlY4JTvhovYc8VXMQs/OjXeclnxHajOy8Fk4aTRmC B/BS2prCoUdsLzTvYb4/3Bg/yMN0/JXOKQxSrmDqoH7uisTkfGv89bv0MdpxWZ5DzIow w0kS4jB1tt2Wd9X7ep3tmv9pw/DmauiJtoEVmJPAVfnktXldfLjOIbzOLxb5HuS4Kud3 1iH/+o/F6p6Pf9kt95EvEBksRqrMVw9r5xSMIPSS5O0pmdjcHwuh8Lf3VRRaJpIqdHlH GAmw== X-Gm-Message-State: ABy/qLZpY1qxTN2Iy1uLsisRCz9ADgFxArF8aD5El4XTQK/VTCKL0Hsx S/nG+0KGvIEw9olDIfgrmleg7Q== X-Google-Smtp-Source: APBJJlGUIaCJCI/A8RmmPjtvVo69gFy6EG+FW88sQ/Zz0XRyctXpv0lNteSBISEYwpo8tIQw51RDWg== X-Received: by 2002:a2e:300a:0:b0:2b6:e361:4b3c with SMTP id w10-20020a2e300a000000b002b6e3614b3cmr3313758ljw.14.1688733031462; Fri, 07 Jul 2023 05:30:31 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id l5-20020a2e8685000000b002b6ee99fff2sm756803lji.34.2023.07.07.05.30.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 05:30:31 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jonathan Cameron , Lars-Peter Clausen , linux-iio@vger.kernel.org Subject: [PATCH v2 4/8] arm64: dts: qcom: pmr735b: fix thermal zone name Date: Fri, 7 Jul 2023 15:30:23 +0300 Message-Id: <20230707123027.1510723-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> References: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The name of the thermal zone in pmr735b.dtsi (pmr735a-thermal) conflicts with the thermal zone in pmr735a.dtsi. Rename the thermal zone according to the chip name. Fixes: 6f3426b3dea4 ("arm64: dts: qcom: pmr735b: add temp sensor and thermal zone config") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/pmr735b.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pmr735b.dtsi b/arch/arm64/boot/dts/qcom/pmr735b.dtsi index ec24c4478005..f7473e247322 100644 --- a/arch/arm64/boot/dts/qcom/pmr735b.dtsi +++ b/arch/arm64/boot/dts/qcom/pmr735b.dtsi @@ -8,7 +8,7 @@ / { thermal-zones { - pmr735a_thermal: pmr735a-thermal { + pmr735b_thermal: pmr735b-thermal { polling-delay-passive = <100>; polling-delay = <0>; thermal-sensors = <&pmr735b_temp_alarm>; From patchwork Fri Jul 7 12:30:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 700193 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE1F9EB64DA for ; Fri, 7 Jul 2023 12:30:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232360AbjGGMap (ORCPT ); Fri, 7 Jul 2023 08:30:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59382 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232617AbjGGMal (ORCPT ); Fri, 7 Jul 2023 08:30:41 -0400 Received: from mail-lj1-x231.google.com (mail-lj1-x231.google.com [IPv6:2a00:1450:4864:20::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3E851212D for ; Fri, 7 Jul 2023 05:30:34 -0700 (PDT) Received: by mail-lj1-x231.google.com with SMTP id 38308e7fff4ca-2b703d7ed3aso29264371fa.1 for ; Fri, 07 Jul 2023 05:30:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688733032; x=1691325032; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3lvtanpZ92WUBFRdOaKgxHw3kXibz5BcF/5lJ267JFA=; b=r6DjFYU7TMrk48/8ywwWcJpg299u+3E78tM569vbym+0k7JJdQDGDumTJEzbbFzJu1 NsFG7ejlFoKomS+19cayMojb4Tf8A7hL64HjCor1MfAY0iSNWx/XD0+GrN3MVcWLnBvy 3j5IOqm+9tbnYZs1LF+zZ4QD8IR+vIYokhsqII43darEdhPhOx6ulZ2JTK1T/siaCKDe GBsX/dj5UW6ccOcO+VaV1O3O/fz3LPMPQEBC2DkPP8pgUN6oZoJqIcb9dPZdA1oMcTys YoS03Hph3i5+9oP6/YQqZKsT/EoQL4tvRN89tAtBx/UyGPj7bM6uKIKhH9WABeGmW0VV 2iyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688733032; x=1691325032; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3lvtanpZ92WUBFRdOaKgxHw3kXibz5BcF/5lJ267JFA=; b=CFRfZn85RnBaRmCUzn0612oIEEBwbdL4irlRO9pGVGMSNEljU0gtrhi+2q8LUEp1PA HtkmfYb626+d62tDRIVt3/MyKHNrD/n0VxxljBxtOxTt8FjIWzRWDZmD8mxVAOrzUjDN ebZzcNrINj5HgC64EoDA2750bvlHDbvkYTHDsHcen6huyHRRgKZjY+Q0yy8/weKGjv7q W+1MoSbOOuIB2bLIMzhvMJmoy/LVwbDb0pwSnH68gZXHcgvnUugEzWoJd9EAnVd+obMv vRp8hgfsNaMaJsafk3pgeyUMrHmX9vvELDP8rPhoNuxHiOW6ZfezVisnOyfWuuAi4qUJ wmdQ== X-Gm-Message-State: ABy/qLZZXN0FFddXNAktHodAatN6x5rDHXKNGg1lPxLIp3v9x51euIiy bmQQ5SX8yM0/T/QRw0gkG5SRNA== X-Google-Smtp-Source: APBJJlGObOywR0a8IYbmlxF4Ssy6sZF9mRZeSMKzVzYcGYrzKhaJwi+ml9/JicMgvXlctFWgPNn9TA== X-Received: by 2002:a2e:3313:0:b0:2b6:fa3e:f2fa with SMTP id d19-20020a2e3313000000b002b6fa3ef2famr3704396ljc.32.1688733032364; Fri, 07 Jul 2023 05:30:32 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id l5-20020a2e8685000000b002b6ee99fff2sm756803lji.34.2023.07.07.05.30.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 05:30:31 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jonathan Cameron , Lars-Peter Clausen , linux-iio@vger.kernel.org Subject: [PATCH v2 5/8] arm64: dts: qcom: pmk8350: fix ADC-TM compatible string Date: Fri, 7 Jul 2023 15:30:24 +0300 Message-Id: <20230707123027.1510723-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> References: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The commit b2de43136058 ("arm64: dts: qcom: pmk8350: Add peripherals for pmk8350") for the ADC TM (thermal monitoring device) have used the compatible string from the vendor kernel ("qcom,adc-tm7"). Use the proper compatible string that is defined in the upstream kernel ("qcom,spmi-adc-tm5-gen2"). Fixes: b2de43136058 ("arm64: dts: qcom: pmk8350: Add peripherals for pmk8350") Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/pmk8350.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/pmk8350.dtsi b/arch/arm64/boot/dts/qcom/pmk8350.dtsi index bc6297e7253e..1eb74017062d 100644 --- a/arch/arm64/boot/dts/qcom/pmk8350.dtsi +++ b/arch/arm64/boot/dts/qcom/pmk8350.dtsi @@ -59,7 +59,7 @@ pmk8350_vadc: adc@3100 { }; pmk8350_adc_tm: adc-tm@3400 { - compatible = "qcom,adc-tm7"; + compatible = "qcom,spmi-adc-tm5-gen2"; reg = <0x3400>; interrupts = ; #address-cells = <1>; From patchwork Fri Jul 7 12:30:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 700408 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1B28DC04FE1 for ; Fri, 7 Jul 2023 12:30:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232671AbjGGMao (ORCPT ); Fri, 7 Jul 2023 08:30:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232391AbjGGMal (ORCPT ); Fri, 7 Jul 2023 08:30:41 -0400 Received: from mail-lj1-x22d.google.com (mail-lj1-x22d.google.com [IPv6:2a00:1450:4864:20::22d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D5845268C for ; Fri, 7 Jul 2023 05:30:34 -0700 (PDT) Received: by mail-lj1-x22d.google.com with SMTP id 38308e7fff4ca-2b6f0508f54so27816291fa.3 for ; Fri, 07 Jul 2023 05:30:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688733033; x=1691325033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EoTvC+FrPkguSl4Zm3LJi2fZKp9GwIiJLIM/2x+q44k=; b=XMQLVDUgOs2zAp/mtYLxOzGQrGh+Aw5UJI2Q3sUibZPDbcZ5xYw3nqyw9GVJb/wOpz MTzitgX8FVLTQb9+BetAsjf4btXJOGj2caP/ID0WDhc2oxsiqLTHeZjOEnhaVYoZCBKM OrERRlbCJPOHEjl2k88eqwvuv3y22+zqrWiYcl2es8tndVFUz0Vj5k0+vBZPUEYWfMy8 4DHFDoRSZO72UN8twAneGiG+y7yLb6McBRIJd6DKF9RA+kvEEcG+ERQARlpT3yaQRa6Q UftP1af1HQnHnulKiJoU0fU8G1XIvTBj4wanSD3Q3KbopKW5MNvMmwW9GF4amNFYYe76 st8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688733033; x=1691325033; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EoTvC+FrPkguSl4Zm3LJi2fZKp9GwIiJLIM/2x+q44k=; b=kFaLMlGr+tn5EC4IJRdkYqRY7244l7uc1PS4rpiSlQSao/g7qbDpsfFP5RLAVUoDc5 X6fBywJNzn2WjDA16IHT6WnWzBNXLSMlEucshUdwT+SYqZax7OXyDNtBzbvbIll/uYHU 63W+x2VFeyycQhdDI9xKG5D5EzsxoEkohVfPWYIBfIKNQnbwu6efM4/4oFmsLkH9VvJk rrrsTbMoHI3mtszCVipttqxevaZFmIsVSIJOepqrJ/26lyGHSpdWFPah/nrHaclDDk5E NqBd31KFjbhWJ/edVOmGTkdGMd4ZSAQm7SMtpuwSVa3DGpNfCoqyRHJofO/XAYmft8Rs ipjA== X-Gm-Message-State: ABy/qLaHSsGY5SX+9zYUB1ojUcksw2i9Iw6UI0/YOo7wXh/Dqc1SLJWT 7yH/BkHVxmwaIwCz0ocfGTbgYA== X-Google-Smtp-Source: APBJJlGVBuGbHNDcfEk7nBuPYPp7akBZvaYr3NoC9XntND/cnztquHhDIBi80w3XbOqF1UgzrQ6k1g== X-Received: by 2002:a2e:8611:0:b0:2b6:9c1d:dea3 with SMTP id a17-20020a2e8611000000b002b69c1ddea3mr3760036lji.2.1688733033256; Fri, 07 Jul 2023 05:30:33 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id l5-20020a2e8685000000b002b6ee99fff2sm756803lji.34.2023.07.07.05.30.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 05:30:32 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jonathan Cameron , Lars-Peter Clausen , linux-iio@vger.kernel.org, Neil Armstrong Subject: [PATCH v2 6/8] arm64: dts: qcom: sm8450-hdk: remove pmr735b PMIC inclusion Date: Fri, 7 Jul 2023 15:30:25 +0300 Message-Id: <20230707123027.1510723-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> References: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The 8450-HDK doesn't use PMR735B PMIC. Drop its inclusion to remove the warning during the HDK bootup. Fixes: 30464456a1ea ("arm64: dts: qcom: sm8450-hdk: add pmic files") Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 1 - 1 file changed, 1 deletion(-) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index bc4c125d1832..dabb7e872f38 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -14,7 +14,6 @@ #include "pm8450.dtsi" #include "pmk8350.dtsi" #include "pmr735a.dtsi" -#include "pmr735b.dtsi" / { model = "Qualcomm Technologies, Inc. SM8450 HDK"; From patchwork Fri Jul 7 12:30:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 700192 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 40886C05053 for ; Fri, 7 Jul 2023 12:30:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232592AbjGGMaq (ORCPT ); Fri, 7 Jul 2023 08:30:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59398 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230007AbjGGMam (ORCPT ); Fri, 7 Jul 2023 08:30:42 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92BD9268E for ; Fri, 7 Jul 2023 05:30:35 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4fba03becc6so3791994e87.0 for ; Fri, 07 Jul 2023 05:30:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688733034; x=1691325034; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0PTCa9Eb+3TnyEnviBdJNY98MQJTj8XpgBrb8rcKVOo=; b=woMXTtK1rBMkAjJbab8TJIgbHj8vq+4z+J84OGBnj9JrOSWWqKgjZzgE0ii4vjqZrr 9Hh8nlo16hJcahweXCGGFi5+tO9a1TJ1Wq6imVF9EqxdobtY9TqAt0o1iDzzas0EGDAz LSQ+G78WvJxFv8JBGdBtGjKTDp/eFmokhnI4Tr30g9eRFDDv9muaJc90aHfZSVdB4z9N S0T6+9DAUVMcI7fkzRXoNXhb0tOOcZMsMjPw3bTYH2HMYplCtHbofkKCpcIxdj2fq4yc I3p3+VyuUu7HJUCG6Z2G/MtKerQaoLtC++L0SrmplmN5IqhmeMx94XAnFHiYI/GuM+5c MjUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688733034; x=1691325034; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0PTCa9Eb+3TnyEnviBdJNY98MQJTj8XpgBrb8rcKVOo=; b=JatgVznt8bhrTRTPzxGx/sFpdpSduU9KU6KA8m/iKI7xBQBPvl4gxlAbajCCv2vkTT 4VVXDHBhe32G581cpYEOPqTUzDlywL0GFrbqLMlp4M2NqKbO7vecm1+y3yIZlqNrWcFM FQiVB4M4V3AZIAk9DyHwOh0AKAEIGtqYR9TfsAvqvUQG3vKTSUSQiS8dmwy1TG2vvATr r9wZKU2FELDxPT/M5vcwjqDbhKDTzBXrUHtgOG2AKJk9KEei1G7zP9QbDseHO/7g9mqc LXdY/iRw06vL0kC5kG1XTcih+qR7wZXjyTGykOvzgMcSgUp2xzbXmWF0O3qsFw3PPL+M OUsg== X-Gm-Message-State: ABy/qLZxs4q7/xSebuesFjV1Tf/eI89FvIMjZ1TkZB1J6ziGM5nlnOPA 7azIOEfiG7zc8TcKDtEV3jAphA== X-Google-Smtp-Source: APBJJlEVWz936J/Qpk9Z39PvdPUeaI0iNevQYNquvaUyh5Nu/7wyfP3QStK7pRROcgVaI9lWpWnNMQ== X-Received: by 2002:a05:6512:3d87:b0:4fb:95b0:1423 with SMTP id k7-20020a0565123d8700b004fb95b01423mr3015421lfv.4.1688733033921; Fri, 07 Jul 2023 05:30:33 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id l5-20020a2e8685000000b002b6ee99fff2sm756803lji.34.2023.07.07.05.30.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 05:30:33 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jonathan Cameron , Lars-Peter Clausen , linux-iio@vger.kernel.org Subject: [PATCH v2 7/8] arm64: dts: qcom: sm8450-hdk: define DIE_TEMP channels Date: Fri, 7 Jul 2023 15:30:26 +0300 Message-Id: <20230707123027.1510723-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> References: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Declare the DIE_TEMP channels provided by PMICs. Use them to provide temperature reading for the spmi-temp-alarm thermal zones. Reviewed-by: Konrad Dybcio Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 43 +++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index dabb7e872f38..d07e402eaba3 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -6,6 +6,10 @@ /dts-v1/; #include +#include +#include +#include +#include #include #include "sm8450.dtsi" #include "pm8350.dtsi" @@ -588,6 +592,45 @@ &pcie1_phy { vdda-pll-supply = <&vreg_l6b_1p2>; }; +&pm8350_temp_alarm { + io-channels = <&pmk8350_vadc PM8350_ADC7_DIE_TEMP(1)>; + io-channel-names = "thermal"; +}; + +&pm8350b_temp_alarm { + io-channels = <&pmk8350_vadc PM8350B_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmr735a_temp_alarm { + io-channels = <&pmk8350_vadc PMR735A_ADC7_DIE_TEMP>; + io-channel-names = "thermal"; +}; + +&pmk8350_vadc { + status = "okay"; + + channel@3 { + reg = ; + label = "pmk8350_die_temp"; + }; + + channel@103 { + reg = ; + label = "pm8350_die_temp"; + }; + + channel@303 { + reg = ; + label = "pm8350b_die_temp"; + }; + + channel@403 { + reg = ; + label = "pmr735a_die_temp"; + }; +}; + &remoteproc_adsp { status = "okay"; firmware-name = "qcom/sm8450/adsp.mbn"; From patchwork Fri Jul 7 12:30:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 700407 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 00D80C04E69 for ; Fri, 7 Jul 2023 12:30:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230098AbjGGMar (ORCPT ); Fri, 7 Jul 2023 08:30:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59388 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230289AbjGGMan (ORCPT ); Fri, 7 Jul 2023 08:30:43 -0400 Received: from mail-lj1-x22b.google.com (mail-lj1-x22b.google.com [IPv6:2a00:1450:4864:20::22b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id A800F172B for ; Fri, 7 Jul 2023 05:30:36 -0700 (PDT) Received: by mail-lj1-x22b.google.com with SMTP id 38308e7fff4ca-2b700e85950so27289841fa.3 for ; Fri, 07 Jul 2023 05:30:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688733035; x=1691325035; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yTSBGkbCdTiuLImTC/+Q/VqyS/BNdIlHaPBfQkN8Fbg=; b=X0mHk2nwAm0xIRsxPWOcmqo74FEyr3W9KrBwXBbmVCUzelHpCfL1boyOKefeLb65Bv ULwuwvhMr1F8s0FkXw6VyYHTbQnWvrFcPcPc6N0/xA5CMZGwpZ9WSS42MFAbfA+yw7m7 CBkqigP2cyugtdnPoB0tEbfPHmef/hhss0L7u51x7bWHO2dHYCP2D7lCIZeTVUQ5IicA LmjG7PzU/hGl/JDHAZy5204VNiJC01PD73apE6gYM06zSvQx6vJnRDPMJzItm12lWVx1 HtSMSzCRWFmN+GWWKv5KFgKTyPWOf3lpPzadPFBxFtws0Ca2UPa/6/ZjeHqIVWNyrYT2 yEFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688733035; x=1691325035; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yTSBGkbCdTiuLImTC/+Q/VqyS/BNdIlHaPBfQkN8Fbg=; b=F2NAcSzPX3QKqhP3RPUGfFIsr5bTD5UT2V/D6cDWkuks7DFDNX1Tfgz+n0yxBvJ2AQ 386brEdwthSBZNJIl4YHniEX4NB5QvIlGQxlNR/jERG1S0gcVlXmlBvYf9oQ7ZCT9dT1 rjkTCBEpFL7ugEY3TcTIkPGTSqoBTOxK7XFV4CGV/l3oG0HVJJkhxEhtWFrNf6esSvul SBldUa+AQgjjzOIilhyI8QJz2KYzlwAzG7k9W9e7SzkER6hpDTtTxflPfvhfAHSaumKN VPH/NhWI4i219L8cC90Z2hG74UtD9poQphKcfoEX/teCoNlZAu72JuWDNo+yGPh/0kRD GNDw== X-Gm-Message-State: ABy/qLYDf1skBRwHs0P0BtBv2inHzTM4mmPvQ79ra0gJT+twWleDvjT9 jxnSKVxZ07bfi1/cpgp3J94FPw== X-Google-Smtp-Source: APBJJlFy3tzD5h45ARrNTXDkqtUYWCDJ2mAZYtRLy7+eWRoCdJFboNx6hUgnpec6EBha2RvS1liMdQ== X-Received: by 2002:a2e:9d04:0:b0:2b6:e8a0:a7f8 with SMTP id t4-20020a2e9d04000000b002b6e8a0a7f8mr3481998lji.31.1688733034716; Fri, 07 Jul 2023 05:30:34 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id l5-20020a2e8685000000b002b6ee99fff2sm756803lji.34.2023.07.07.05.30.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Jul 2023 05:30:34 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Jonathan Cameron , Lars-Peter Clausen , linux-iio@vger.kernel.org Subject: [PATCH v2 8/8] arm64: dts: qcom: sm8450-hdk: add ADC-TM thermal zones Date: Fri, 7 Jul 2023 15:30:27 +0300 Message-Id: <20230707123027.1510723-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> References: <20230707123027.1510723-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add thermal zones controlled through the ADC-TM (ADC thermal monitoring) PMIC interface. This includes several onboard sensors and the XO thermal sensor. Signed-off-by: Dmitry Baryshkov --- arch/arm64/boot/dts/qcom/sm8450-hdk.dts | 244 ++++++++++++++++++++++++ 1 file changed, 244 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts index d07e402eaba3..4dfc964a4bb1 100644 --- a/arch/arm64/boot/dts/qcom/sm8450-hdk.dts +++ b/arch/arm64/boot/dts/qcom/sm8450-hdk.dts @@ -133,6 +133,120 @@ pmic_glink_sbu: endpoint { }; }; + thermal-zones { + camera-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 2>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + rear-tof-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 5>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + skin-msm-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 1>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + therm1-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 3>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + therm2-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 6>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + usb-conn-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 7>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + wide-rfc-thermal { + polling-delay-passive = <250>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 4>; + + trips { + active-config0 { + temperature = <75000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + + xo-thermal { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&pmk8350_adc_tm 0>; + + trips { + active-config0 { + temperature = <50000>; + hysteresis = <4000>; + type = "passive"; + }; + }; + }; + }; + vph_pwr: vph-pwr-regulator { compatible = "regulator-fixed"; regulator-name = "vph_pwr"; @@ -607,6 +721,66 @@ &pmr735a_temp_alarm { io-channel-names = "thermal"; }; +&pmk8350_adc_tm { + status = "okay"; + + xo-therm@0 { + reg = <0>; + io-channels = <&pmk8350_vadc PMK8350_ADC7_AMUX_THM1_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + skin-msm-therm@1 { + reg = <1>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM1_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + camera-therm@2 { + reg = <2>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM2_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + therm1-therm@3 { + reg = <3>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM3_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + wide-rfc-therm@4 { + reg = <4>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM4_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + rear-tof-therm@5 { + reg = <5>; + io-channels = <&pmk8350_vadc PM8350_ADC7_AMUX_THM5_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + therm2-therm@6 { + reg = <6>; + io-channels = <&pmk8350_vadc PM8350_ADC7_GPIO3_100K_PU(1)>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; + + usb-conn-therm@7 { + reg = <7>; + io-channels = <&pmk8350_vadc PM8350B_ADC7_AMUX_THM5_100K_PU>; + qcom,ratiometric; + qcom,hw-settle-time-us = <200>; + }; +}; + &pmk8350_vadc { status = "okay"; @@ -615,20 +789,90 @@ channel@3 { label = "pmk8350_die_temp"; }; + channel@44 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "pmk8350_xo_therm"; + }; + channel@103 { reg = ; label = "pm8350_die_temp"; }; + channel@144 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "skin_msm_temp"; + }; + + channel@145 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "camera_temp"; + }; + + channel@146 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "therm1_temp"; + }; + + channel@147 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "wide_rfc_temp"; + }; + + channel@148 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "rear_tof_temp"; + }; + + channel@14c { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "therm2_temp"; + }; + channel@303 { reg = ; label = "pm8350b_die_temp"; }; + channel@348 { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "usb_conn_temp"; + }; + channel@403 { reg = ; label = "pmr735a_die_temp"; }; + + channel@44a { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "qtm_w_temp"; + }; + + channel@44b { + reg = ; + qcom,hw-settle-time = <200>; + qcom,ratiometric; + label = "qtm_n_temp"; + }; }; &remoteproc_adsp {