From patchwork Thu Jul 6 21:10:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 699663 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BCD12C001DF for ; Thu, 6 Jul 2023 21:11:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229619AbjGFVLf (ORCPT ); Thu, 6 Jul 2023 17:11:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231820AbjGFVLD (ORCPT ); Thu, 6 Jul 2023 17:11:03 -0400 Received: from mail-pl1-x631.google.com (mail-pl1-x631.google.com [IPv6:2607:f8b0:4864:20::631]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C08381BD2 for ; Thu, 6 Jul 2023 14:11:02 -0700 (PDT) Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1b8b2b60731so5478685ad.2 for ; Thu, 06 Jul 2023 14:11:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688677862; x=1691269862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W2Rwgr6QwxnDtS6HyV0L0tAHznvzmmEQLZHqSK1brrI=; b=faQT1Vazrp4jLAmXd5ELV/chB0+/Nb84nj3pqLjbuXOrWAY0obaMTPFRyrpTdgwiHl NG5EXAhOUdGKydr/TwzH8oHPUeCcXC6enYGeuY3QnXbZhM68wwxvKwob0mjRWVGvIHhD Badi14FGo46KQkpJ3RQ06b/CULj+yJVcUQtRcO8WGGBb4N31Uil/z0pVTKEzPOPdPRuV QnhIs2gdn96ekMDPfLyHJtT05F+aYOwvqs0O9vi35siy6lxXFvbMZXl0HmKb6HWnmDM6 Z3ou/8CWr4va06eaz7G1eYXga0xw0jxN2JAcnYAnPF5YiQ/JndYYPOwqkCXkxExR0G9x MqJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688677862; x=1691269862; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W2Rwgr6QwxnDtS6HyV0L0tAHznvzmmEQLZHqSK1brrI=; b=I5OjFrJFFDBnED5YSFuOZDnPebcQFuYPUAKEeNwH3oL0kIMP7PuykV1J68a+KNgmbc qrjsD4WYB8avTcM2JhM8C+bP33VpZElvKQtQSotkBTs5bEKDAqy6hi5B3pK9jN9s4l0l kWTV4uj/r6/KD1qzoU5RtgYrlcBHbmYWZdUAHjlKJPmZ2pPhgn4X2CJrSPCVyCWd41Tw 6224hmjXOrOjUthCiokQfDXg1dtn4ewrCiLUWXBKT5OVpLtUI+OeCFdNs7yBgBMfaQ3T U0ZLnSfTHU52+eRQQoHJGKFzv4fbDmZ1VEjn7hXTGE0CMxr0sO8wAAk5V4i7uyHtqwt+ 54Gw== X-Gm-Message-State: ABy/qLau3fweM/GkxS/LQIqdg6GmHnQvJzqI4iBzMPkkFKKBwhntKGWu iHKtUUEFZDrvOC23MNYU0po= X-Google-Smtp-Source: APBJJlELnYsm5UJKAY2Zeoxp/pXc4lBNDhNskji4oUIWf7DCQQV4bL7xHFzKe3xg49QSCiLyyoeQqA== X-Received: by 2002:a17:902:d902:b0:1b3:cf98:a20b with SMTP id c2-20020a170902d90200b001b3cf98a20bmr2082702plz.54.1688677862008; Thu, 06 Jul 2023 14:11:02 -0700 (PDT) Received: from localhost ([2a00:79e1:abd:4a00:6c80:7c10:75a0:44f4]) by smtp.gmail.com with ESMTPSA id m12-20020a1709026bcc00b001b7fd27144dsm1842964plt.40.2023.07.06.14.11.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 14:11:01 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Rob Clark Subject: [PATCH 01/12] drm/msm/adreno: Remove GPU name Date: Thu, 6 Jul 2023 14:10:34 -0700 Message-ID: <20230706211045.204925-2-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230706211045.204925-1-robdclark@gmail.com> References: <20230706211045.204925-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark No real need to have marketing names in the kernel. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/adreno_device.c | 24 ---------------------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 13 +++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 3 files changed, 5 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index ce8d0b2475bf..5eba0ae5c9a7 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -24,7 +24,6 @@ static const struct adreno_info gpulist[] = { { .rev = ADRENO_REV(2, 0, 0, 0), .revn = 200, - .name = "A200", .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", [ADRENO_FW_PFP] = "yamato_pfp.fw", @@ -35,7 +34,6 @@ static const struct adreno_info gpulist[] = { }, { /* a200 on i.mx51 has only 128kib gmem */ .rev = ADRENO_REV(2, 0, 0, 1), .revn = 201, - .name = "A200", .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", [ADRENO_FW_PFP] = "yamato_pfp.fw", @@ -46,7 +44,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(2, 2, 0, ANY_ID), .revn = 220, - .name = "A220", .fw = { [ADRENO_FW_PM4] = "leia_pm4_470.fw", [ADRENO_FW_PFP] = "leia_pfp_470.fw", @@ -57,7 +54,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 0, 5, ANY_ID), .revn = 305, - .name = "A305", .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", [ADRENO_FW_PFP] = "a300_pfp.fw", @@ -68,7 +64,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 0, 6, 0), .revn = 307, /* because a305c is revn==306 */ - .name = "A306", .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", [ADRENO_FW_PFP] = "a300_pfp.fw", @@ -79,7 +74,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), .revn = 320, - .name = "A320", .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", [ADRENO_FW_PFP] = "a300_pfp.fw", @@ -90,7 +84,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(3, 3, 0, ANY_ID), .revn = 330, - .name = "A330", .fw = { [ADRENO_FW_PM4] = "a330_pm4.fw", [ADRENO_FW_PFP] = "a330_pfp.fw", @@ -101,7 +94,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(4, 0, 5, ANY_ID), .revn = 405, - .name = "A405", .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", [ADRENO_FW_PFP] = "a420_pfp.fw", @@ -112,7 +104,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(4, 2, 0, ANY_ID), .revn = 420, - .name = "A420", .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", [ADRENO_FW_PFP] = "a420_pfp.fw", @@ -123,7 +114,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(4, 3, 0, ANY_ID), .revn = 430, - .name = "A430", .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", [ADRENO_FW_PFP] = "a420_pfp.fw", @@ -134,7 +124,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 0, 6, ANY_ID), .revn = 506, - .name = "A506", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -152,7 +141,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 0, 8, ANY_ID), .revn = 508, - .name = "A508", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -169,7 +157,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 0, 9, ANY_ID), .revn = 509, - .name = "A509", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -187,7 +174,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 1, 0, ANY_ID), .revn = 510, - .name = "A510", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -202,7 +188,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 1, 2, ANY_ID), .revn = 512, - .name = "A512", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -219,7 +204,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 3, 0, 2), .revn = 530, - .name = "A530", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -238,7 +222,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(5, 4, 0, ANY_ID), .revn = 540, - .name = "A540", .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", [ADRENO_FW_PFP] = "a530_pfp.fw", @@ -268,7 +251,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), .revn = 618, - .name = "A618", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a630_gmu.bin", @@ -279,7 +261,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619, - .name = "A619", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a619_gmu.bin", @@ -292,7 +273,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), .revn = 630, - .name = "A630", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a630_gmu.bin", @@ -305,7 +285,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 4, 0, ANY_ID), .revn = 640, - .name = "A640", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a640_gmu.bin", @@ -318,7 +297,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 5, 0, ANY_ID), .revn = 650, - .name = "A650", .fw = { [ADRENO_FW_SQE] = "a650_sqe.fw", [ADRENO_FW_GMU] = "a650_gmu.bin", @@ -332,7 +310,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 6, 0, ANY_ID), .revn = 660, - .name = "A660", .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a660_gmu.bin", @@ -357,7 +334,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 8, 0, ANY_ID), .revn = 680, - .name = "A680", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", [ADRENO_FW_GMU] = "a640_gmu.bin", diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 5c5901d65950..e3cd9ff6ff1d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1105,14 +1105,11 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, speedbin = 0xffff; adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); - gpu_name = adreno_gpu->info->name; - if (!gpu_name) { - gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d", - rev->core, rev->major, rev->minor, - rev->patchid); - if (!gpu_name) - return -ENOMEM; - } + gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d", + rev->core, rev->major, rev->minor, + rev->patchid); + if (!gpu_name) + return -ENOMEM; adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index cf45007400c8..6830c3776c2d 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -61,7 +61,6 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; struct adreno_info { struct adreno_rev rev; uint32_t revn; - const char *name; const char *fw[ADRENO_FW_MAX]; uint32_t gmem; u64 quirks; From patchwork Thu Jul 6 21:10:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 701247 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4E88EB64D9 for ; Thu, 6 Jul 2023 21:11:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229910AbjGFVLg (ORCPT ); Thu, 6 Jul 2023 17:11:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47692 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232480AbjGFVLF (ORCPT ); Thu, 6 Jul 2023 17:11:05 -0400 Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 766EF1BC9 for ; Thu, 6 Jul 2023 14:11:04 -0700 (PDT) Received: by mail-pj1-x102c.google.com with SMTP id 98e67ed59e1d1-262c42d3fafso834510a91.0 for ; Thu, 06 Jul 2023 14:11:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688677864; x=1691269864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YQnN829O1lAOpEHGj2SRxckFk9YAJvOeNQ8or0cs/+c=; b=dLbZB0alBGG9X9K4r4xMGfQjuKH4vzeWUhFfbqMN9hhDU494AN6pH+ziHxSULWBHZB 2nbAkU5jryqWDNBiLHtPmdQ8S9X2DNcPx19gJ75X8AlumlVKZN6CzyuGUgJqNISfQ2p7 34L+T5mED0Dqy4BMd/0RSskL0tIYzHok5Y9QJw8zR1l7auNRCeRVTZUHGzVWqHPC1jRm LMuD90wRQD1wBqDL5bQSk735DuBbDVRWdPusGOFYNYbebFqzkj/6gB6JBsA154SGA8Rp gQN3lakDrpGeAjyIWE4QmDhBfdRSTrpzJTx3hLmlaml88vOSeml5GsNRYMX26jsnREWR 9Ecg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688677864; x=1691269864; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YQnN829O1lAOpEHGj2SRxckFk9YAJvOeNQ8or0cs/+c=; b=L5H/GbPCxVh2rxrgM7ogqHWr+juehEDeIbv2s5i0XymER2BcsiWwKhSP/ZnhwsvCLP MDgdKSnLX2tLHP7HWKli4PeM9H95fCTj0CtTYSmSmMwDOWsNh90AIefsnc3DC3B/6q2q X4x8q5A18rAiUxv0lVlpLt12Q/xi1QchzWeQYUCp75c5cZOEgKSe61QHcAewQk2gUQ8A XvdfVTLplCWSucYl+dGY2Lnrgegbngzo99IztgG/wWRXUKfz5vRONsLJ4wB9zESkVJAw mnkugaG+Mj5FW+ruRn1zyYcy/eEpeNnuyUPl156sScVmzfT1MbI9ppNmXOP5NuzrpVd/ Y/Ng== X-Gm-Message-State: ABy/qLbBUUAMDsrzC/byextFNB7TQ3QBCUKIuiwbRbOYEzXajGMlDgaq QWToqpFuipSBo1LsKrc1zI0= X-Google-Smtp-Source: APBJJlFHAh9+le0qFXEZH+KPlE6cQwRonzAqFixkDlWN+lhqtYm6SXxl2FI3IyK6liholOWKpPTpqg== X-Received: by 2002:a17:90a:fe07:b0:262:ca9c:edcb with SMTP id ck7-20020a17090afe0700b00262ca9cedcbmr4929640pjb.9.1688677863834; Thu, 06 Jul 2023 14:11:03 -0700 (PDT) Received: from localhost ([2a00:79e1:abd:4a00:6c80:7c10:75a0:44f4]) by smtp.gmail.com with ESMTPSA id 16-20020a631750000000b0055386b1415dsm1704942pgx.51.2023.07.06.14.11.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 14:11:03 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Rob Clark Subject: [PATCH 02/12] drm/msm/adreno: Remove redundant gmem size param Date: Thu, 6 Jul 2023 14:10:35 -0700 Message-ID: <20230706211045.204925-3-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230706211045.204925-1-robdclark@gmail.com> References: <20230706211045.204925-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Even in the ocmem case, the allocated ocmem buffer size should match the requested size. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a2xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_device.c | 1 - drivers/gpu/drm/msm/adreno/adreno_gpu.c | 8 ++++---- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 - 6 files changed, 7 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c index c67089a7ebc1..50ee03bc94b4 100644 --- a/drivers/gpu/drm/msm/adreno/a2xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a2xx_gpu.c @@ -205,7 +205,7 @@ static int a2xx_hw_init(struct msm_gpu *gpu) A2XX_MH_INTERRUPT_MASK_MMU_PAGE_FAULT); for (i = 3; i <= 5; i++) - if ((SZ_16K << i) == adreno_gpu->gmem) + if ((SZ_16K << i) == adreno_gpu->info->gmem) break; gpu_write(gpu, REG_A2XX_RB_EDRAM_INFO, i); diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index a99310b68793..f0803e94ebe5 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -749,7 +749,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu) gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_LO, 0x00100000); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MIN_HI, 0x00000000); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_LO, - 0x00100000 + adreno_gpu->gmem - 1); + 0x00100000 + adreno_gpu->info->gmem - 1); gpu_write(gpu, REG_A5XX_UCHE_GMEM_RANGE_MAX_HI, 0x00000000); if (adreno_is_a506(adreno_gpu) || adreno_is_a508(adreno_gpu) || diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index b3ada1e7b598..edbade75020f 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -1270,7 +1270,7 @@ static int hw_init(struct msm_gpu *gpu) gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MIN, 0x00100000); gpu_write64(gpu, REG_A6XX_UCHE_GMEM_RANGE_MAX, - 0x00100000 + adreno_gpu->gmem - 1); + 0x00100000 + adreno_gpu->info->gmem - 1); } gpu_write(gpu, REG_A6XX_UCHE_FILTER_CNTL, 0x804); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 5eba0ae5c9a7..326912284a95 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -239,7 +239,6 @@ static const struct adreno_info gpulist[] = { }, { .rev = ADRENO_REV(6, 1, 0, ANY_ID), .revn = 610, - .name = "A610", .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", }, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index e3cd9ff6ff1d..4f59682f585e 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -320,7 +320,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, *value = adreno_gpu->info->revn; return 0; case MSM_PARAM_GMEM_SIZE: - *value = adreno_gpu->gmem; + *value = adreno_gpu->info->gmem; return 0; case MSM_PARAM_GMEM_BASE: *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0; @@ -1041,14 +1041,15 @@ int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu, return PTR_ERR(ocmem); } - ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->gmem); + ocmem_hdl = ocmem_allocate(ocmem, OCMEM_GRAPHICS, adreno_gpu->info->gmem); if (IS_ERR(ocmem_hdl)) return PTR_ERR(ocmem_hdl); adreno_ocmem->ocmem = ocmem; adreno_ocmem->base = ocmem_hdl->addr; adreno_ocmem->hdl = ocmem_hdl; - adreno_gpu->gmem = ocmem_hdl->len; + + WARN_ON(ocmem_hdl->len != adreno_gpu->info->gmem); return 0; } @@ -1097,7 +1098,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); - adreno_gpu->gmem = adreno_gpu->info->gmem; adreno_gpu->revn = adreno_gpu->info->revn; adreno_gpu->rev = *rev; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 6830c3776c2d..aaf09c642dc6 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -77,7 +77,6 @@ struct adreno_gpu { struct msm_gpu base; struct adreno_rev rev; const struct adreno_info *info; - uint32_t gmem; /* actual gmem size */ uint32_t revn; /* numeric revision name */ uint16_t speedbin; const struct adreno_gpu_funcs *funcs; From patchwork Thu Jul 6 21:10:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 699662 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4729AC001DE for ; Thu, 6 Jul 2023 21:11:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230170AbjGFVLg (ORCPT ); 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Thu, 06 Jul 2023 14:11:05 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Rob Clark Subject: [PATCH 03/12] drm/msm/adreno: Remove redundant revn param Date: Thu, 6 Jul 2023 14:10:36 -0700 Message-ID: <20230706211045.204925-4-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230706211045.204925-1-robdclark@gmail.com> References: <20230706211045.204925-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark This just duplicates what is in adreno_info, and can cause confusion if used before it is set. Signed-off-by: Rob Clark Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 2 -- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 1 - drivers/gpu/drm/msm/adreno/adreno_gpu.h | 22 +++++++++------------- 3 files changed, 9 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index edbade75020f..5ba8b5aca502 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2484,8 +2484,6 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) return ERR_PTR(-EINVAL); /* Assign these early so that we can use the is_aXYZ helpers */ - /* Numeric revision IDs (e.g. 630) */ - adreno_gpu->revn = info->revn; /* New-style ADRENO_REV()-only */ adreno_gpu->rev = info->rev; /* Quirk data */ diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 4f59682f585e..2e62a7ce9f13 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1098,7 +1098,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->funcs = funcs; adreno_gpu->info = adreno_info(config->rev); - adreno_gpu->revn = adreno_gpu->info->revn; adreno_gpu->rev = *rev; if (adreno_read_speedbin(dev, &speedbin) || !speedbin) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index aaf09c642dc6..d31e2d37c61b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -77,7 +77,6 @@ struct adreno_gpu { struct msm_gpu base; struct adreno_rev rev; const struct adreno_info *info; - uint32_t revn; /* numeric revision name */ uint16_t speedbin; const struct adreno_gpu_funcs *funcs; @@ -147,10 +146,9 @@ bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn) { - /* revn can be zero, but if not is set at same time as info */ - WARN_ON_ONCE(!gpu->info); - - return gpu->revn == revn; + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->revn == revn; } static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) @@ -160,18 +158,16 @@ static inline bool adreno_has_gmu_wrapper(const struct adreno_gpu *gpu) static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) { - /* revn can be zero, but if not is set at same time as info */ - WARN_ON_ONCE(!gpu->info); - - return (gpu->revn < 300); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return (gpu->info->revn < 300); } static inline bool adreno_is_a20x(const struct adreno_gpu *gpu) { - /* revn can be zero, but if not is set at same time as info */ - WARN_ON_ONCE(!gpu->info); - - return (gpu->revn < 210); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return (gpu->info->revn < 210); } static inline bool adreno_is_a225(const struct adreno_gpu *gpu) From patchwork Thu Jul 6 21:10:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 701246 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A335EEB64DC for ; Thu, 6 Jul 2023 21:11:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231820AbjGFVLi (ORCPT ); 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Thu, 06 Jul 2023 14:11:06 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Rob Clark Subject: [PATCH 04/12] drm/msm/adreno: Use quirk identify hw_apriv Date: Thu, 6 Jul 2023 14:10:37 -0700 Message-ID: <20230706211045.204925-5-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230706211045.204925-1-robdclark@gmail.com> References: <20230706211045.204925-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Rather than just open coding a list of gpu-id matches. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 3 +-- drivers/gpu/drm/msm/adreno/adreno_device.c | 4 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 3 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 5ba8b5aca502..6f8c4381fa4a 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2489,8 +2489,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) /* Quirk data */ adreno_gpu->info = info; - if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu)) - adreno_gpu->base.hw_apriv = true; + adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); a6xx_llc_slices_init(pdev, a6xx_gpu); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 326912284a95..f469f951a907 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -302,6 +302,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg, @@ -315,6 +316,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", .hwcg = a660_hwcg, @@ -327,6 +329,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .hwcg = a660_hwcg, .address_space_size = SZ_16G, @@ -350,6 +353,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", .hwcg = a690_hwcg, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index d31e2d37c61b..a7c4a2c536e3 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -32,6 +32,7 @@ enum { #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) +#define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) struct adreno_rev { uint8_t core; From patchwork Thu Jul 6 21:10:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 701245 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33B0FEB64DD for ; Thu, 6 Jul 2023 21:11:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232073AbjGFVLi (ORCPT ); Thu, 6 Jul 2023 17:11:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232710AbjGFVLL (ORCPT ); Thu, 6 Jul 2023 17:11:11 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 66C891BEE for ; Thu, 6 Jul 2023 14:11:09 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-666e6ecb52dso771758b3a.2 for ; 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With the move to opaque chip-id's for future devices, we should avoid trying to infer things like generation from the numerical value. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_device.c | 23 +++++++++++++++------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 17 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index f469f951a907..3c531da417b9 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -256,6 +256,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), @@ -266,6 +267,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg, @@ -278,6 +280,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a630_zap.mdt", .hwcg = a630_hwcg, @@ -290,6 +293,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, @@ -302,7 +306,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_128K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg, @@ -316,7 +321,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_1M + SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a660_zap.mdt", .hwcg = a660_hwcg, @@ -329,7 +335,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_512K, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .hwcg = a660_hwcg, .address_space_size = SZ_16G, @@ -342,6 +349,7 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_2M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, @@ -353,7 +361,8 @@ static const struct adreno_info gpulist[] = { }, .gmem = SZ_4M, .inactive_period = DRM_MSM_INACTIVE_PERIOD, - .quirks = ADRENO_QUIRK_HAS_HW_APRIV, + .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT | + ADRENO_QUIRK_HAS_HW_APRIV, .init = a6xx_gpu_init, .zapfw = "a690_zap.mdt", .hwcg = a690_hwcg, @@ -565,9 +574,9 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) if (ret) return ret; - if (config.rev.core >= 6) - if (!adreno_has_gmu_wrapper(to_adreno_gpu(gpu))) - priv->has_cached_coherent = true; + priv->has_cached_coherent = + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) && + !adreno_has_gmu_wrapper(to_adreno_gpu(gpu)); return 0; } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index a7c4a2c536e3..e08d41337169 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -33,6 +33,7 @@ enum { #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) +#define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) struct adreno_rev { uint8_t core; From patchwork Thu Jul 6 21:10:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 699661 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 36795C00528 for ; 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Thu, 06 Jul 2023 14:11:10 -0700 (PDT) Received: from localhost ([2a00:79e1:abd:4a00:6c80:7c10:75a0:44f4]) by smtp.gmail.com with ESMTPSA id y25-20020aa78559000000b0063f1a1e3003sm1658094pfn.166.2023.07.06.14.11.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 14:11:09 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Rob Clark Subject: [PATCH 06/12] drm/msm/adreno: Allow SoC specific gpu device table entries Date: Thu, 6 Jul 2023 14:10:39 -0700 Message-ID: <20230706211045.204925-7-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230706211045.204925-1-robdclark@gmail.com> References: <20230706211045.204925-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark There are cases where there are differences due to SoC integration. Such as cache-coherency support, and (in the next patch) e-fuse to speedbin mappings. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_device.c | 34 +++++++++++++++++++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 1 + 2 files changed, 31 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index 3c531da417b9..e62bc895a31f 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -258,6 +258,32 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, + }, { + .machine = "qcom,sm4350", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, + }, { + .machine = "qcom,sm6375", + .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .revn = 619, + .fw = { + [ADRENO_FW_SQE] = "a630_sqe.fw", + [ADRENO_FW_GMU] = "a619_gmu.bin", + }, + .gmem = SZ_512K, + .inactive_period = DRM_MSM_INACTIVE_PERIOD, + .init = a6xx_gpu_init, + .zapfw = "a615_zap.mdt", + .hwcg = a615_hwcg, }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619, @@ -409,6 +435,8 @@ const struct adreno_info *adreno_info(struct adreno_rev rev) /* identify gpu: */ for (i = 0; i < ARRAY_SIZE(gpulist); i++) { const struct adreno_info *info = &gpulist[i]; + if (info->machine && !of_machine_is_compatible(info->machine)) + continue; if (adreno_cmp_rev(info->rev, rev)) return info; } @@ -563,6 +591,8 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) config.rev.minor, config.rev.patchid); priv->is_a2xx = config.rev.core == 2; + priv->has_cached_coherent = + !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); gpu = info->init(drm); if (IS_ERR(gpu)) { @@ -574,10 +604,6 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) if (ret) return ret; - priv->has_cached_coherent = - !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT) && - !adreno_has_gmu_wrapper(to_adreno_gpu(gpu)); - return 0; } diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index e08d41337169..d5335b99c64c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -61,6 +61,7 @@ extern const struct adreno_reglist a612_hwcg[], a615_hwcg[], a630_hwcg[], a640_h extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; struct adreno_info { + const char *machine; struct adreno_rev rev; uint32_t revn; const char *fw[ADRENO_FW_MAX]; From patchwork Thu Jul 6 21:10:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 699660 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42C81C001DF for ; Thu, 6 Jul 2023 21:11:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232370AbjGFVLj (ORCPT ); Thu, 6 Jul 2023 17:11:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232745AbjGFVLP (ORCPT ); Thu, 6 Jul 2023 17:11:15 -0400 Received: from mail-oo1-xc2a.google.com (mail-oo1-xc2a.google.com [IPv6:2607:f8b0:4864:20::c2a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 98A031BFF for ; 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Thu, 06 Jul 2023 14:11:11 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Rob Clark Subject: [PATCH 07/12] drm/msm/adreno: Move speedbin mapping to device table Date: Thu, 6 Jul 2023 14:10:40 -0700 Message-ID: <20230706211045.204925-8-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230706211045.204925-1-robdclark@gmail.com> References: <20230706211045.204925-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark This simplifies the code. Signed-off-by: Rob Clark Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 171 ++------------------- drivers/gpu/drm/msm/adreno/adreno_device.c | 51 ++++++ drivers/gpu/drm/msm/adreno/adreno_gpu.h | 25 +++ 3 files changed, 92 insertions(+), 155 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 6f8c4381fa4a..77b23c004b94 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2204,159 +2204,19 @@ static bool a6xx_progress(struct msm_gpu *gpu, struct msm_ringbuffer *ring) return progress; } -static u32 a610_get_speed_bin(u32 fuse) +static u32 fuse_to_supp_hw(const struct adreno_info *info, u32 fuse) { - /* - * There are (at least) three SoCs implementing A610: SM6125 (trinket), - * SM6115 (bengal) and SM6225 (khaje). Trinket does not have speedbinning, - * as only a single SKU exists and we don't support khaje upstream yet. - * Hence, this matching table is only valid for bengal and can be easily - * expanded if need be. - */ - - if (fuse == 0) - return 0; - else if (fuse == 206) - return 1; - else if (fuse == 200) - return 2; - else if (fuse == 157) - return 3; - else if (fuse == 127) - return 4; - - return UINT_MAX; -} - -static u32 a618_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 169) - return 1; - else if (fuse == 174) - return 2; - - return UINT_MAX; -} - -static u32 a619_holi_get_speed_bin(u32 fuse) -{ - /* - * There are (at least) two SoCs implementing A619_holi: SM4350 (holi) - * and SM6375 (blair). Limit the fuse matching to the corresponding - * SoC to prevent bogus frequency setting (as improbable as it may be, - * given unexpected fuse values are.. unexpected! But still possible.) - */ - - if (fuse == 0) - return 0; - - if (of_machine_is_compatible("qcom,sm4350")) { - if (fuse == 138) - return 1; - else if (fuse == 92) - return 2; - } else if (of_machine_is_compatible("qcom,sm6375")) { - if (fuse == 190) - return 1; - else if (fuse == 177) - return 2; - } else - pr_warn("Unknown SoC implementing A619_holi!\n"); - - return UINT_MAX; -} - -static u32 a619_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 120) - return 4; - else if (fuse == 138) - return 3; - else if (fuse == 169) - return 2; - else if (fuse == 180) - return 1; - - return UINT_MAX; -} - -static u32 a640_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 1) - return 1; - - return UINT_MAX; -} - -static u32 a650_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 1) - return 1; - /* Yep, 2 and 3 are swapped! :/ */ - else if (fuse == 2) - return 3; - else if (fuse == 3) - return 2; - - return UINT_MAX; -} + if (!info->speedbins) + return UINT_MAX; -static u32 adreno_7c3_get_speed_bin(u32 fuse) -{ - if (fuse == 0) - return 0; - else if (fuse == 117) - return 0; - else if (fuse == 190) - return 1; + for (int i = 0; info->speedbins[i] != UINT_MAX; i += 2) + if (info->speedbins[i] == fuse) + return (1 << info->speedbins[i + 1]); return UINT_MAX; } -static u32 fuse_to_supp_hw(struct device *dev, struct adreno_gpu *adreno_gpu, u32 fuse) -{ - u32 val = UINT_MAX; - - if (adreno_is_a610(adreno_gpu)) - val = a610_get_speed_bin(fuse); - - if (adreno_is_a618(adreno_gpu)) - val = a618_get_speed_bin(fuse); - - else if (adreno_is_a619_holi(adreno_gpu)) - val = a619_holi_get_speed_bin(fuse); - - else if (adreno_is_a619(adreno_gpu)) - val = a619_get_speed_bin(fuse); - - else if (adreno_is_7c3(adreno_gpu)) - val = adreno_7c3_get_speed_bin(fuse); - - else if (adreno_is_a640(adreno_gpu)) - val = a640_get_speed_bin(fuse); - - else if (adreno_is_a650(adreno_gpu)) - val = a650_get_speed_bin(fuse); - - if (val == UINT_MAX) { - DRM_DEV_ERROR(dev, - "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", - fuse); - return UINT_MAX; - } - - return (1 << val); -} - -static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_gpu) +static int a6xx_set_supported_hw(struct device *dev, const struct adreno_info *info) { u32 supp_hw; u32 speedbin; @@ -2375,7 +2235,14 @@ static int a6xx_set_supported_hw(struct device *dev, struct adreno_gpu *adreno_g return ret; } - supp_hw = fuse_to_supp_hw(dev, adreno_gpu, speedbin); + supp_hw = fuse_to_supp_hw(info, speedbin); + + if (supp_hw == UINT_MAX) { + DRM_DEV_ERROR(dev, + "missing support for speed-bin: %u. Some OPPs may not be supported by hardware\n", + speedbin); + return UINT_MAX; + } ret = devm_pm_opp_set_supported_hw(dev, &supp_hw, 1); if (ret) @@ -2483,17 +2350,11 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) if (!info) return ERR_PTR(-EINVAL); - /* Assign these early so that we can use the is_aXYZ helpers */ - /* New-style ADRENO_REV()-only */ - adreno_gpu->rev = info->rev; - /* Quirk data */ - adreno_gpu->info = info; - adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); a6xx_llc_slices_init(pdev, a6xx_gpu); - ret = a6xx_set_supported_hw(&pdev->dev, adreno_gpu); + ret = a6xx_set_supported_hw(&pdev->dev, info); if (ret) { a6xx_destroy(&(a6xx_gpu->base.base)); return ERR_PTR(ret); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index e62bc895a31f..b7f70cfe6081 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -247,6 +247,20 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a610_zap.mdt", .hwcg = a612_hwcg, + /* + * There are (at least) three SoCs implementing A610: SM6125 + * (trinket), SM6115 (bengal) and SM6225 (khaje). Trinket does + * not have speedbinning, as only a single SKU exists and we + * don't support khaje upstream yet. Hence, this matching + * table is only valid for bengal. + */ + .speedbins = ADRENO_SPEEDBINS( + 0, 0, + 206, 1, + 200, 2, + 157, 3, + 127, 4 + ), }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), .revn = 618, @@ -258,6 +272,11 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .quirks = ADRENO_QUIRK_HAS_CACHED_COHERENT, .init = a6xx_gpu_init, + .speedbins = ADRENO_SPEEDBINS( + 0, 0, + 169, 1, + 174, 2 + ), }, { .machine = "qcom,sm4350", .rev = ADRENO_REV(6, 1, 9, ANY_ID), @@ -271,6 +290,11 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + 0, 0, + 138, 1, + 92, 2 + ), }, { .machine = "qcom,sm6375", .rev = ADRENO_REV(6, 1, 9, ANY_ID), @@ -284,6 +308,11 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + 0, 0, + 190, 1, + 177, 2 + ), }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), .revn = 619, @@ -297,6 +326,13 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a615_zap.mdt", .hwcg = a615_hwcg, + .speedbins = ADRENO_SPEEDBINS( + 0, 0, + 120, 4, + 138, 3, + 169, 2, + 180, 1 + ), }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), .revn = 630, @@ -323,6 +359,10 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, + .speedbins = ADRENO_SPEEDBINS( + 0, 0, + 1, 1 + ), }, { .rev = ADRENO_REV(6, 5, 0, ANY_ID), .revn = 650, @@ -338,6 +378,12 @@ static const struct adreno_info gpulist[] = { .zapfw = "a650_zap.mdt", .hwcg = a650_hwcg, .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + 0, 0, + 1, 1, + 2, 3, /* Yep, 2 and 3 are swapped! :/ */ + 3, 2 + ), }, { .rev = ADRENO_REV(6, 6, 0, ANY_ID), .revn = 660, @@ -366,6 +412,11 @@ static const struct adreno_info gpulist[] = { .init = a6xx_gpu_init, .hwcg = a660_hwcg, .address_space_size = SZ_16G, + .speedbins = ADRENO_SPEEDBINS( + 0, 0, + 117, 0, + 190, 1 + ), }, { .rev = ADRENO_REV(6, 8, 0, ANY_ID), .revn = 680, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index d5335b99c64c..994ac26ce731 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -72,8 +72,33 @@ struct adreno_info { u32 inactive_period; const struct adreno_reglist *hwcg; u64 address_space_size; + /** + * @speedbins: Optional table of fuse to speedbin mappings + * + * Consists of pairs of fuse, index mappings, terminated with + * UINT_MAX sentinal. + */ + uint32_t *speedbins; }; +/* + * Helper to build a speedbin table, ie. the table: + * fuse | speedbin + * -----+--------- + * 0 | 0 + * 169 | 1 + * 174 | 2 + * + * would be declared as: + * + * .speedbins = ADRENO_SPEEDBINS( + * 0, 0, + * 169, 1, + * 174, 2 + * ), + */ +#define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX } + const struct adreno_info *adreno_info(struct adreno_rev rev); struct adreno_gpu { From patchwork Thu Jul 6 21:10:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 701244 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1134C001B0 for ; Thu, 6 Jul 2023 21:11:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231482AbjGFVLj (ORCPT ); Thu, 6 Jul 2023 17:11:39 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47936 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232759AbjGFVLQ (ORCPT ); Thu, 6 Jul 2023 17:11:16 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01F5D1FC4 for ; Thu, 6 Jul 2023 14:11:13 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1b8bbcfd89aso6289585ad.1 for ; Thu, 06 Jul 2023 14:11:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20221208; t=1688677873; x=1691269873; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=KE/HRYJUOwz46737Zy2ObEKXxP27JaI6CDUPzYPq7g0=; b=eyiCDb6DseoefFt0ZKXZL5H68R3nBUdg8Vrz7cvGEZfTIfi7dmy5XcwkzluURuafAw VqQCHIMAAuHQsr3II8jknIIoYvlltl1p+QKLVieyZ4u3W5TXG068mnc/a1XMaG6dkoo9 /ryB/Z7nJFgVbhQ+SSy+MfP0u2NX1K+UUxJRJO9cyh6XElm7g1sQVLuyLDwwbX7O2AqL X8iCaV4P5K3EuR0PUur20BzPih0Rxm8upfAMr+TUky7ufxFkRwh2BQ/VaAVaSC8LBrrm 5XVshLfePtcU68umqBGk49ChTNLKPyTh1Z0zua/KCNy5grZQUPsyW6bGK2XJgfGUFICE uvSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688677873; x=1691269873; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KE/HRYJUOwz46737Zy2ObEKXxP27JaI6CDUPzYPq7g0=; b=hjJC+2tT2N8VwYSDRorXCIB2oSqZTZQ0yTeMNnparpG0VmRP7lSOulT8lZgWUUL/6z GV4hqteCnweej4nU5NGKgbaCknhJ7zHVE065Uedeq87PeD8zrLaqqTL+e9bN8z35g5vU 40A9dRN2QE9kOv310XqthBbGX8Wwi+Wkvb9TMv+ePA9g4ytFglbOdybU2YsysAsBdnXQ rVW8PAOcUGHuwebm5EZgg8tBSHW5FU8sxSLMKwYUcbVaZCxr9jeozUA/Y/AB+KHO0gxD z2azUDh/eqMPDA5iZKRS9xqbUDQrwPeYdkhQASf6/xqzOyzEO0VBL3SzPKJQ3hadBmuH qtfQ== X-Gm-Message-State: ABy/qLaL12WyASRN6QZ7jjod4hI6C9+gg7XVOb75aXy1UaNTBl3ZEyXX U0Q+NWpu8YZPzKkooRjGIXo= X-Google-Smtp-Source: APBJJlEJFBA3x0Ya3PZPHVy7BtH2LbjmFHSPj+Fu//78cBPxZ7VhDZjTPZ7sf86h3jgHkNmFziM8bA== X-Received: by 2002:a17:90a:c292:b0:263:f5fa:cf1b with SMTP id f18-20020a17090ac29200b00263f5facf1bmr2299944pjt.30.1688677873373; Thu, 06 Jul 2023 14:11:13 -0700 (PDT) Received: from localhost ([2a00:79e1:abd:4a00:6c80:7c10:75a0:44f4]) by smtp.gmail.com with ESMTPSA id l4-20020a17090aaa8400b00262fc3d911esm209033pjq.28.2023.07.06.14.11.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 14:11:12 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Rob Clark Subject: [PATCH 08/12] drm/msm/adreno: Bring the a630 family together Date: Thu, 6 Jul 2023 14:10:41 -0700 Message-ID: <20230706211045.204925-9-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230706211045.204925-1-robdclark@gmail.com> References: <20230706211045.204925-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark All of these are derivatives of a630. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 2 +- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 7 ++++--- 2 files changed, 5 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index 5deb79924897..f1bb20574018 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -1617,7 +1617,7 @@ int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node) SZ_256K - SZ_16K, 0x44000, "dcache"); if (ret) goto err_memory; - } else if (adreno_is_a630(adreno_gpu) || adreno_is_a615_family(adreno_gpu)) { + } else if (adreno_is_a630_family(adreno_gpu)) { /* HFI v1, has sptprac */ gmu->legacy = true; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 994ac26ce731..6066cfaaea52 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -335,10 +335,11 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu) /* The order of args is important here to handle ANY_ID correctly */ return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev); }; -/* check for a615, a616, a618, a619 or any derivatives */ -static inline int adreno_is_a615_family(const struct adreno_gpu *gpu) +/* check for a615, a616, a618, a619 or any a630 derivatives */ +static inline int adreno_is_a630_family(const struct adreno_gpu *gpu) { - return adreno_is_revn(gpu, 615) || + return adreno_is_revn(gpu, 630) || + adreno_is_revn(gpu, 615) || adreno_is_revn(gpu, 616) || adreno_is_revn(gpu, 618) || adreno_is_revn(gpu, 619); From patchwork Thu Jul 6 21:10:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 699659 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8EF17EB64D9 for ; Thu, 6 Jul 2023 21:11:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232394AbjGFVLk (ORCPT ); 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Thu, 06 Jul 2023 14:11:14 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Rob Clark Subject: [PATCH 09/12] drm/msm/adreno: Add adreno family Date: Thu, 6 Jul 2023 14:10:42 -0700 Message-ID: <20230706211045.204925-10-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230706211045.204925-1-robdclark@gmail.com> References: <20230706211045.204925-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Sometimes it is useful to know the sub-generation (or "family"). And in any case, this helps us get away from infering the generation from the numerical chip-id. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_device.c | 31 ++++++++++++++- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 11 +++--- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 46 ++++++++++++++++------ 3 files changed, 70 insertions(+), 18 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index b7f70cfe6081..dcd6363ac7b0 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -23,6 +23,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); static const struct adreno_info gpulist[] = { { .rev = ADRENO_REV(2, 0, 0, 0), + .family = ADRENO_2XX_GEN1, .revn = 200, .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", @@ -33,6 +34,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { /* a200 on i.mx51 has only 128kib gmem */ .rev = ADRENO_REV(2, 0, 0, 1), + .family = ADRENO_2XX_GEN1, .revn = 201, .fw = { [ADRENO_FW_PM4] = "yamato_pm4.fw", @@ -43,6 +45,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { .rev = ADRENO_REV(2, 2, 0, ANY_ID), + .family = ADRENO_2XX_GEN2, .revn = 220, .fw = { [ADRENO_FW_PM4] = "leia_pm4_470.fw", @@ -53,6 +56,7 @@ static const struct adreno_info gpulist[] = { .init = a2xx_gpu_init, }, { .rev = ADRENO_REV(3, 0, 5, ANY_ID), + .family = ADRENO_3XX, .revn = 305, .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", @@ -63,6 +67,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 0, 6, 0), + .family = ADRENO_3XX, .revn = 307, /* because a305c is revn==306 */ .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", @@ -73,6 +78,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), + .family = ADRENO_3XX, .revn = 320, .fw = { [ADRENO_FW_PM4] = "a300_pm4.fw", @@ -83,6 +89,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(3, 3, 0, ANY_ID), + .family = ADRENO_3XX, .revn = 330, .fw = { [ADRENO_FW_PM4] = "a330_pm4.fw", @@ -93,6 +100,7 @@ static const struct adreno_info gpulist[] = { .init = a3xx_gpu_init, }, { .rev = ADRENO_REV(4, 0, 5, ANY_ID), + .family = ADRENO_4XX, .revn = 405, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", @@ -103,6 +111,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(4, 2, 0, ANY_ID), + .family = ADRENO_4XX, .revn = 420, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", @@ -113,6 +122,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(4, 3, 0, ANY_ID), + .family = ADRENO_4XX, .revn = 430, .fw = { [ADRENO_FW_PM4] = "a420_pm4.fw", @@ -123,6 +133,7 @@ static const struct adreno_info gpulist[] = { .init = a4xx_gpu_init, }, { .rev = ADRENO_REV(5, 0, 6, ANY_ID), + .family = ADRENO_5XX, .revn = 506, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -140,6 +151,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a506_zap.mdt", }, { .rev = ADRENO_REV(5, 0, 8, ANY_ID), + .family = ADRENO_5XX, .revn = 508, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -156,6 +168,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a508_zap.mdt", }, { .rev = ADRENO_REV(5, 0, 9, ANY_ID), + .family = ADRENO_5XX, .revn = 509, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -173,6 +186,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a512_zap.mdt", }, { .rev = ADRENO_REV(5, 1, 0, ANY_ID), + .family = ADRENO_5XX, .revn = 510, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -187,6 +201,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, }, { .rev = ADRENO_REV(5, 1, 2, ANY_ID), + .family = ADRENO_5XX, .revn = 512, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -203,6 +218,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a512_zap.mdt", }, { .rev = ADRENO_REV(5, 3, 0, 2), + .family = ADRENO_5XX, .revn = 530, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -221,6 +237,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a530_zap.mdt", }, { .rev = ADRENO_REV(5, 4, 0, ANY_ID), + .family = ADRENO_5XX, .revn = 540, .fw = { [ADRENO_FW_PM4] = "a530_pm4.fw", @@ -238,6 +255,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a540_zap.mdt", }, { .rev = ADRENO_REV(6, 1, 0, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 610, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -263,6 +281,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 1, 8, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 618, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -280,6 +299,7 @@ static const struct adreno_info gpulist[] = { }, { .machine = "qcom,sm4350", .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -298,6 +318,7 @@ static const struct adreno_info gpulist[] = { }, { .machine = "qcom,sm6375", .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -315,6 +336,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -335,6 +357,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 3, 0, ANY_ID), + .family = ADRENO_6XX_GEN1, .revn = 630, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -348,6 +371,7 @@ static const struct adreno_info gpulist[] = { .hwcg = a630_hwcg, }, { .rev = ADRENO_REV(6, 4, 0, ANY_ID), + .family = ADRENO_6XX_GEN2, .revn = 640, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -365,6 +389,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 5, 0, ANY_ID), + .family = ADRENO_6XX_GEN3, .revn = 650, .fw = { [ADRENO_FW_SQE] = "a650_sqe.fw", @@ -386,6 +411,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 6, 0, ANY_ID), + .family = ADRENO_6XX_GEN4, .revn = 660, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", @@ -401,6 +427,7 @@ static const struct adreno_info gpulist[] = { .address_space_size = SZ_16G, }, { .rev = ADRENO_REV(6, 3, 5, ANY_ID), + .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a660_gmu.bin", @@ -419,6 +446,7 @@ static const struct adreno_info gpulist[] = { ), }, { .rev = ADRENO_REV(6, 8, 0, ANY_ID), + .family = ADRENO_6XX_GEN2, .revn = 680, .fw = { [ADRENO_FW_SQE] = "a630_sqe.fw", @@ -432,6 +460,7 @@ static const struct adreno_info gpulist[] = { .hwcg = a640_hwcg, }, { .rev = ADRENO_REV(6, 9, 0, ANY_ID), + .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", [ADRENO_FW_GMU] = "a690_gmu.bin", @@ -641,7 +670,7 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, config.rev.minor, config.rev.patchid); - priv->is_a2xx = config.rev.core == 2; + priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = !!(info->quirks & ADRENO_QUIRK_HAS_CACHED_COHERENT); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 2e62a7ce9f13..75ff7fb46099 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -1079,8 +1079,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, u32 speedbin; int ret; + adreno_gpu->funcs = funcs; + adreno_gpu->info = adreno_info(config->rev); + adreno_gpu->rev = *rev; + /* Only handle the core clock when GMU is not in use (or is absent). */ - if (adreno_has_gmu_wrapper(adreno_gpu) || config->rev.core < 6) { + if (adreno_has_gmu_wrapper(adreno_gpu) || + adreno_gpu->info->family < ADRENO_6XX_GEN1) { /* * This can only be done before devm_pm_opp_of_add_table(), or * dev_pm_opp_set_config() will WARN_ON() @@ -1096,10 +1101,6 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, devm_pm_opp_set_clkname(dev, "core"); } - adreno_gpu->funcs = funcs; - adreno_gpu->info = adreno_info(config->rev); - adreno_gpu->rev = *rev; - if (adreno_read_speedbin(dev, &speedbin) || !speedbin) speedbin = 0xffff; adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 6066cfaaea52..2fa14dcd4e40 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -29,6 +29,25 @@ enum { ADRENO_FW_MAX, }; +/** + * @enum adreno_family: identify generation and possibly sub-generation + * + * In some cases there are distinct sub-generations within a major revision + * so it helps to be able to group the GPU devices by generation and if + * necessary sub-generation. + */ +enum adreno_family { + ADRENO_2XX_GEN1, /* a20x */ + ADRENO_2XX_GEN2, /* a22x */ + ADRENO_3XX, + ADRENO_4XX, + ADRENO_5XX, + ADRENO_6XX_GEN1, /* a630 family */ + ADRENO_6XX_GEN2, /* a640 family */ + ADRENO_6XX_GEN3, /* a650 family */ + ADRENO_6XX_GEN4, /* a660 family */ +}; + #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0) #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1) #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2) @@ -63,6 +82,7 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; struct adreno_info { const char *machine; struct adreno_rev rev; + enum adreno_family family; uint32_t revn; const char *fw[ADRENO_FW_MAX]; uint32_t gmem; @@ -188,14 +208,14 @@ static inline bool adreno_is_a2xx(const struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return (gpu->info->revn < 300); + return gpu->info->family < ADRENO_2XX_GEN2; } static inline bool adreno_is_a20x(const struct adreno_gpu *gpu) { if (WARN_ON_ONCE(!gpu->info)) return false; - return (gpu->info->revn < 210); + return gpu->info->family == ADRENO_2XX_GEN1; } static inline bool adreno_is_a225(const struct adreno_gpu *gpu) @@ -338,29 +358,31 @@ static inline int adreno_is_a690(const struct adreno_gpu *gpu) /* check for a615, a616, a618, a619 or any a630 derivatives */ static inline int adreno_is_a630_family(const struct adreno_gpu *gpu) { - return adreno_is_revn(gpu, 630) || - adreno_is_revn(gpu, 615) || - adreno_is_revn(gpu, 616) || - adreno_is_revn(gpu, 618) || - adreno_is_revn(gpu, 619); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family == ADRENO_6XX_GEN1; } static inline int adreno_is_a660_family(const struct adreno_gpu *gpu) { - return adreno_is_a660(gpu) || adreno_is_a690(gpu) || adreno_is_7c3(gpu); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family == ADRENO_6XX_GEN4; } /* check for a650, a660, or any derivatives */ static inline int adreno_is_a650_family(const struct adreno_gpu *gpu) { - return adreno_is_revn(gpu, 650) || - adreno_is_revn(gpu, 620) || - adreno_is_a660_family(gpu); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family >= ADRENO_6XX_GEN3; } static inline int adreno_is_a640_family(const struct adreno_gpu *gpu) { - return adreno_is_a640(gpu) || adreno_is_a680(gpu); + if (WARN_ON_ONCE(!gpu->info)) + return false; + return gpu->info->family == ADRENO_6XX_GEN2; } u64 adreno_private_address_space_size(struct msm_gpu *gpu); From patchwork Thu Jul 6 21:10:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Rob Clark X-Patchwork-Id: 701243 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 06663EB64DC for ; Thu, 6 Jul 2023 21:11:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232453AbjGFVLl (ORCPT ); Thu, 6 Jul 2023 17:11:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48026 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232783AbjGFVLU (ORCPT ); Thu, 6 Jul 2023 17:11:20 -0400 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p12-20020a056a000b4c00b00644d77560bbmr2747265pfo.20.1688677876416; Thu, 06 Jul 2023 14:11:16 -0700 (PDT) Received: from localhost ([2a00:79e1:abd:4a00:6c80:7c10:75a0:44f4]) by smtp.gmail.com with ESMTPSA id g15-20020a62e30f000000b00682a16f0b00sm1653068pfh.210.2023.07.06.14.11.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Jul 2023 14:11:16 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Rob Clark Subject: [PATCH 10/12] drm/msm/adreno: Add helper for formating chip-id Date: Thu, 6 Jul 2023 14:10:43 -0700 Message-ID: <20230706211045.204925-11-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230706211045.204925-1-robdclark@gmail.com> References: <20230706211045.204925-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark This is used in a few places, including one that is parsed by userspace tools. So let's standardize it a bit better. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/adreno_device.c | 8 +++----- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 19 ++++++++----------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 6 ++++++ 3 files changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index dcd6363ac7b0..fd2e183bce60 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -661,14 +661,12 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) info = adreno_info(config.rev); if (!info) { - dev_warn(drm->dev, "Unknown GPU revision: %u.%u.%u.%u\n", - config.rev.core, config.rev.major, - config.rev.minor, config.rev.patchid); + dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n", + ADRENO_CHIPID_ARGS(config.rev)); return -ENXIO; } - DBG("Found GPU: %u.%u.%u.%u", config.rev.core, config.rev.major, - config.rev.minor, config.rev.patchid); + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev)); priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 75ff7fb46099..1a982a926f21 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -847,10 +847,9 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, if (IS_ERR_OR_NULL(state)) return; - drm_printf(p, "revision: %d (%d.%d.%d.%d)\n", - adreno_gpu->info->revn, adreno_gpu->rev.core, - adreno_gpu->rev.major, adreno_gpu->rev.minor, - adreno_gpu->rev.patchid); + drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n", + adreno_gpu->info->revn, + ADRENO_CHIPID_ARGS(adreno_gpu->rev)); /* * If this is state collected due to iova fault, so fault related info * @@ -921,10 +920,9 @@ void adreno_dump_info(struct msm_gpu *gpu) struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); int i; - printk("revision: %d (%d.%d.%d.%d)\n", - adreno_gpu->info->revn, adreno_gpu->rev.core, - adreno_gpu->rev.major, adreno_gpu->rev.minor, - adreno_gpu->rev.patchid); + printk("revision: %u (%"ADRENO_CHIPID_FMT")\n", + adreno_gpu->info->revn, + ADRENO_CHIPID_ARGS(adreno_gpu->rev)); for (i = 0; i < gpu->nr_rings; i++) { struct msm_ringbuffer *ring = gpu->rb[i]; @@ -1105,9 +1103,8 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, speedbin = 0xffff; adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); - gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%d.%d.%d.%d", - rev->core, rev->major, rev->minor, - rev->patchid); + gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, + ADRENO_CHIPID_ARGS(config->rev)); if (!gpu_name) return -ENOMEM; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 2fa14dcd4e40..73e7155f164c 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -66,6 +66,12 @@ struct adreno_rev { #define ADRENO_REV(core, major, minor, patchid) \ ((struct adreno_rev){ core, major, minor, patchid }) +/* Helper for formating the chip_id in the way that userspace tools like + * crashdec expect. + */ +#define ADRENO_CHIPID_FMT "u.%u.%u.%u" +#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid + struct adreno_gpu_funcs { struct msm_gpu_funcs base; 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Thu, 06 Jul 2023 14:11:17 -0700 (PDT) From: Rob Clark To: dri-devel@lists.freedesktop.org Cc: linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org, Konrad Dybcio , Rob Clark Subject: [PATCH 11/12] dt-bindings: drm/msm/gpu: Extend bindings for chip-id Date: Thu, 6 Jul 2023 14:10:44 -0700 Message-ID: <20230706211045.204925-12-robdclark@gmail.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230706211045.204925-1-robdclark@gmail.com> References: <20230706211045.204925-1-robdclark@gmail.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Rob Clark Upcoming GPUs use an opaque chip-id for identifying the GPU. Signed-off-by: Rob Clark --- Documentation/devicetree/bindings/display/msm/gpu.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 58ca8912a8c3..56b9b247e8c2 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -13,6 +13,12 @@ maintainers: properties: compatible: oneOf: + - description: | + The driver is parsing the compat string for Adreno to + figure out the chip-id. + items: + - pattern: '^qcom,adreno-[0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f][0-9a-f]$' + - const: qcom,adreno - description: | The driver is parsing the compat string for Adreno to figure out the gpu-id and patch level. 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This means that we need to explicitly list different patch revisions in the device table. Signed-off-by: Rob Clark --- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 2 +- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 11 +- drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +- drivers/gpu/drm/msm/adreno/a6xx_gmu.c | 13 ++- drivers/gpu/drm/msm/adreno/a6xx_gpu.c | 9 +- drivers/gpu/drm/msm/adreno/adreno_device.c | 128 ++++++++++----------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 16 +-- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 51 ++++---- 8 files changed, 122 insertions(+), 110 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 715436cb3996..8b4cdf95f445 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -145,7 +145,7 @@ static void a4xx_enable_hwcg(struct msm_gpu *gpu) gpu_write(gpu, REG_A4XX_RBBM_CLOCK_DELAY_HLSQ, 0x00220000); /* Early A430's have a timing issue with SP/TP power collapse; disabling HW clock gating prevents it. */ - if (adreno_is_a430(adreno_gpu) && adreno_gpu->rev.patchid < 2) + if (adreno_is_a430(adreno_gpu) && adreno_patchid(adreno_gpu) < 2) gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0); else gpu_write(gpu, REG_A4XX_RBBM_CLOCK_CTL, 0xAAAAAAAA); diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index f0803e94ebe5..70d2b5342cd9 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -1744,6 +1744,7 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) struct msm_drm_private *priv = dev->dev_private; struct platform_device *pdev = priv->gpu_pdev; struct adreno_platform_config *config = pdev->dev.platform_data; + const struct adreno_info *info; struct a5xx_gpu *a5xx_gpu = NULL; struct adreno_gpu *adreno_gpu; struct msm_gpu *gpu; @@ -1770,7 +1771,15 @@ struct msm_gpu *a5xx_gpu_init(struct drm_device *dev) nr_rings = 4; - if (adreno_cmp_rev(ADRENO_REV(5, 1, 0, ANY_ID), config->rev)) + /* + * Note that we wouldn't have been able to get this far if there is not + * a device table entry for this chip_id + */ + info = adreno_find_info(config->chip_id); + if (WARN_ON(!info)) + return ERR_PTR(-EINVAL); + + if (info->revn == 510) nr_rings = 1; ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, nr_rings); diff --git a/drivers/gpu/drm/msm/adreno/a5xx_power.c b/drivers/gpu/drm/msm/adreno/a5xx_power.c index 0e63a1429189..7705f8010484 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_power.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_power.c @@ -179,7 +179,7 @@ static void a540_lm_setup(struct msm_gpu *gpu) /* The battery current limiter isn't enabled for A540 */ config = AGC_LM_CONFIG_BCL_DISABLED; - config |= adreno_gpu->rev.patchid << AGC_LM_CONFIG_GPU_VERSION_SHIFT; + config |= adreno_patchid(adreno_gpu) << AGC_LM_CONFIG_GPU_VERSION_SHIFT; /* For now disable GPMU side throttling */ config |= AGC_LM_CONFIG_THROTTLE_DISABLE; diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c index f1bb20574018..a9ba547a120c 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gmu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gmu.c @@ -790,10 +790,15 @@ static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state) gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0, (1 << 31) | (0xa << 18) | (0xa0)); - chipid = adreno_gpu->rev.core << 24; - chipid |= adreno_gpu->rev.major << 16; - chipid |= adreno_gpu->rev.minor << 12; - chipid |= adreno_gpu->rev.patchid << 8; + /* Note that the GMU has a slightly different layout for + * chip_id, for whatever reason, so a bit of massaging + * is needed. The upper 16b are the same, but minor and + * patchid are packed in four bits each with the lower + * 8b unused: + */ + chipid = adreno_gpu->chip_id & 0xffff0000; + chipid |= (adreno_gpu->chip_id << 4) & 0xf000; /* minor */ + chipid |= (adreno_gpu->chip_id << 8) & 0x0f00; /* patchid */ gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid); diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c index 77b23c004b94..ed075729ca09 100644 --- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c @@ -2344,10 +2344,13 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev) /* * We need to know the platform type before calling into adreno_gpu_init * so that the hw_apriv flag can be correctly set. Snoop into the info - * and grab the revision number + * and grab the revision number. + * + * Note that we wouldn't have been able to get this far if there is not + * a device table entry for this chip_id */ - info = adreno_info(config->rev); - if (!info) + info = adreno_find_info(config->chip_id); + if (WARN_ON(!info)) return ERR_PTR(-EINVAL); adreno_gpu->base.hw_apriv = !!(info->quirks & ADRENO_QUIRK_HAS_HW_APRIV); diff --git a/drivers/gpu/drm/msm/adreno/adreno_device.c b/drivers/gpu/drm/msm/adreno/adreno_device.c index fd2e183bce60..4a718ff33635 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_device.c +++ b/drivers/gpu/drm/msm/adreno/adreno_device.c @@ -22,7 +22,7 @@ module_param_named(allow_vram_carveout, allow_vram_carveout, bool, 0600); static const struct adreno_info gpulist[] = { { - .rev = ADRENO_REV(2, 0, 0, 0), + .chip_ids = ADRENO_CHIP_IDS(0x02000000), .family = ADRENO_2XX_GEN1, .revn = 200, .fw = { @@ -33,7 +33,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a2xx_gpu_init, }, { /* a200 on i.mx51 has only 128kib gmem */ - .rev = ADRENO_REV(2, 0, 0, 1), + .chip_ids = ADRENO_CHIP_IDS(0x02000001), .family = ADRENO_2XX_GEN1, .revn = 201, .fw = { @@ -44,7 +44,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a2xx_gpu_init, }, { - .rev = ADRENO_REV(2, 2, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x02020000), .family = ADRENO_2XX_GEN2, .revn = 220, .fw = { @@ -55,7 +55,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a2xx_gpu_init, }, { - .rev = ADRENO_REV(3, 0, 5, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x03000500), .family = ADRENO_3XX, .revn = 305, .fw = { @@ -66,7 +66,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, }, { - .rev = ADRENO_REV(3, 0, 6, 0), + .chip_ids = ADRENO_CHIP_IDS(0x03000600), .family = ADRENO_3XX, .revn = 307, /* because a305c is revn==306 */ .fw = { @@ -77,7 +77,11 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, }, { - .rev = ADRENO_REV(3, 2, ANY_ID, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS( + 0x03020000, + 0x03020001, + 0x03020002 + ), .family = ADRENO_3XX, .revn = 320, .fw = { @@ -88,7 +92,11 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, }, { - .rev = ADRENO_REV(3, 3, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS( + 0x03030000, + 0x03030001, + 0x03030002 + ), .family = ADRENO_3XX, .revn = 330, .fw = { @@ -99,7 +107,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a3xx_gpu_init, }, { - .rev = ADRENO_REV(4, 0, 5, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x04000500), .family = ADRENO_4XX, .revn = 405, .fw = { @@ -110,7 +118,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a4xx_gpu_init, }, { - .rev = ADRENO_REV(4, 2, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x04020000), .family = ADRENO_4XX, .revn = 420, .fw = { @@ -121,7 +129,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a4xx_gpu_init, }, { - .rev = ADRENO_REV(4, 3, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x04030000), .family = ADRENO_4XX, .revn = 430, .fw = { @@ -132,7 +140,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = DRM_MSM_INACTIVE_PERIOD, .init = a4xx_gpu_init, }, { - .rev = ADRENO_REV(5, 0, 6, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05000600), .family = ADRENO_5XX, .revn = 506, .fw = { @@ -150,7 +158,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a506_zap.mdt", }, { - .rev = ADRENO_REV(5, 0, 8, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05000800), .family = ADRENO_5XX, .revn = 508, .fw = { @@ -167,7 +175,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a508_zap.mdt", }, { - .rev = ADRENO_REV(5, 0, 9, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05000900), .family = ADRENO_5XX, .revn = 509, .fw = { @@ -185,7 +193,7 @@ static const struct adreno_info gpulist[] = { /* Adreno 509 uses the same ZAP as 512 */ .zapfw = "a512_zap.mdt", }, { - .rev = ADRENO_REV(5, 1, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05010000), .family = ADRENO_5XX, .revn = 510, .fw = { @@ -200,7 +208,7 @@ static const struct adreno_info gpulist[] = { .inactive_period = 250, .init = a5xx_gpu_init, }, { - .rev = ADRENO_REV(5, 1, 2, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05010200), .family = ADRENO_5XX, .revn = 512, .fw = { @@ -217,7 +225,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a512_zap.mdt", }, { - .rev = ADRENO_REV(5, 3, 0, 2), + .chip_ids = ADRENO_CHIP_IDS(0x05030002), .family = ADRENO_5XX, .revn = 530, .fw = { @@ -236,7 +244,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a530_zap.mdt", }, { - .rev = ADRENO_REV(5, 4, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x05040001), .family = ADRENO_5XX, .revn = 540, .fw = { @@ -254,7 +262,7 @@ static const struct adreno_info gpulist[] = { .init = a5xx_gpu_init, .zapfw = "a540_zap.mdt", }, { - .rev = ADRENO_REV(6, 1, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010000), .family = ADRENO_6XX_GEN1, .revn = 610, .fw = { @@ -280,7 +288,7 @@ static const struct adreno_info gpulist[] = { 127, 4 ), }, { - .rev = ADRENO_REV(6, 1, 8, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010800), .family = ADRENO_6XX_GEN1, .revn = 618, .fw = { @@ -298,7 +306,7 @@ static const struct adreno_info gpulist[] = { ), }, { .machine = "qcom,sm4350", - .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010900), .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { @@ -317,7 +325,7 @@ static const struct adreno_info gpulist[] = { ), }, { .machine = "qcom,sm6375", - .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010900), .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { @@ -335,7 +343,7 @@ static const struct adreno_info gpulist[] = { 177, 2 ), }, { - .rev = ADRENO_REV(6, 1, 9, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06010900), .family = ADRENO_6XX_GEN1, .revn = 619, .fw = { @@ -356,7 +364,7 @@ static const struct adreno_info gpulist[] = { 180, 1 ), }, { - .rev = ADRENO_REV(6, 3, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06030002), .family = ADRENO_6XX_GEN1, .revn = 630, .fw = { @@ -370,7 +378,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a630_zap.mdt", .hwcg = a630_hwcg, }, { - .rev = ADRENO_REV(6, 4, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06040001), .family = ADRENO_6XX_GEN2, .revn = 640, .fw = { @@ -388,7 +396,7 @@ static const struct adreno_info gpulist[] = { 1, 1 ), }, { - .rev = ADRENO_REV(6, 5, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06050002), .family = ADRENO_6XX_GEN3, .revn = 650, .fw = { @@ -410,7 +418,7 @@ static const struct adreno_info gpulist[] = { 3, 2 ), }, { - .rev = ADRENO_REV(6, 6, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06060001), .family = ADRENO_6XX_GEN4, .revn = 660, .fw = { @@ -426,7 +434,7 @@ static const struct adreno_info gpulist[] = { .hwcg = a660_hwcg, .address_space_size = SZ_16G, }, { - .rev = ADRENO_REV(6, 3, 5, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06030500), .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", @@ -445,7 +453,7 @@ static const struct adreno_info gpulist[] = { 190, 1 ), }, { - .rev = ADRENO_REV(6, 8, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06080000), .family = ADRENO_6XX_GEN2, .revn = 680, .fw = { @@ -459,7 +467,7 @@ static const struct adreno_info gpulist[] = { .zapfw = "a640_zap.mdt", .hwcg = a640_hwcg, }, { - .rev = ADRENO_REV(6, 9, 0, ANY_ID), + .chip_ids = ADRENO_CHIP_IDS(0x06090000), .family = ADRENO_6XX_GEN4, .fw = { [ADRENO_FW_SQE] = "a660_sqe.fw", @@ -494,31 +502,16 @@ MODULE_FIRMWARE("qcom/a630_sqe.fw"); MODULE_FIRMWARE("qcom/a630_gmu.bin"); MODULE_FIRMWARE("qcom/a630_zap.mbn"); -static inline bool _rev_match(uint8_t entry, uint8_t id) -{ - return (entry == ANY_ID) || (entry == id); -} - -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2) -{ - - return _rev_match(rev1.core, rev2.core) && - _rev_match(rev1.major, rev2.major) && - _rev_match(rev1.minor, rev2.minor) && - _rev_match(rev1.patchid, rev2.patchid); -} - -const struct adreno_info *adreno_info(struct adreno_rev rev) +const struct adreno_info *adreno_find_info(uint32_t chip_id) { - int i; - /* identify gpu: */ - for (i = 0; i < ARRAY_SIZE(gpulist); i++) { + for (int i = 0; i < ARRAY_SIZE(gpulist); i++) { const struct adreno_info *info = &gpulist[i]; if (info->machine && !of_machine_is_compatible(info->machine)) continue; - if (adreno_cmp_rev(info->rev, rev)) - return info; + for (int j = 0; info->chip_ids[j]; j++) + if (info->chip_ids[j] == chip_id) + return info; } return NULL; @@ -598,12 +591,11 @@ struct msm_gpu *adreno_load_gpu(struct drm_device *dev) return NULL; } -static int find_chipid(struct device *dev, struct adreno_rev *rev) +static int find_chipid(struct device *dev, uint32_t *chipid) { struct device_node *node = dev->of_node; const char *compat; int ret; - u32 chipid; /* first search the compat strings for qcom,adreno-XYZ.W: */ ret = of_property_read_string_index(node, "compatible", 0, &compat); @@ -612,32 +604,34 @@ static int find_chipid(struct device *dev, struct adreno_rev *rev) if (sscanf(compat, "qcom,adreno-%u.%u", &r, &patch) == 2 || sscanf(compat, "amd,imageon-%u.%u", &r, &patch) == 2) { - rev->core = r / 100; + uint32_t core, major, minor; + + core = r / 100; r %= 100; - rev->major = r / 10; + major = r / 10; r %= 10; - rev->minor = r; - rev->patchid = patch; + minor = r; + + *chipid = (core << 24) | + (major << 16) | + (minor << 8) | + patch; return 0; } + + if (sscanf(compat, "qcom,adreno-%08x", chipid) == 1) + return 0; } /* and if that fails, fall back to legacy "qcom,chipid" property: */ - ret = of_property_read_u32(node, "qcom,chipid", &chipid); + ret = of_property_read_u32(node, "qcom,chipid", chipid); if (ret) { DRM_DEV_ERROR(dev, "could not parse qcom,chipid: %d\n", ret); return ret; } - rev->core = (chipid >> 24) & 0xff; - rev->major = (chipid >> 16) & 0xff; - rev->minor = (chipid >> 8) & 0xff; - rev->patchid = (chipid & 0xff); - dev_warn(dev, "Using legacy qcom,chipid binding!\n"); - dev_warn(dev, "Use compatible qcom,adreno-%u%u%u.%u instead.\n", - rev->core, rev->major, rev->minor, rev->patchid); return 0; } @@ -651,22 +645,22 @@ static int adreno_bind(struct device *dev, struct device *master, void *data) struct msm_gpu *gpu; int ret; - ret = find_chipid(dev, &config.rev); + ret = find_chipid(dev, &config.chip_id); if (ret) return ret; dev->platform_data = &config; priv->gpu_pdev = to_platform_device(dev); - info = adreno_info(config.rev); + info = adreno_find_info(config.chip_id); if (!info) { dev_warn(drm->dev, "Unknown GPU revision: %"ADRENO_CHIPID_FMT"\n", - ADRENO_CHIPID_ARGS(config.rev)); + ADRENO_CHIPID_ARGS(config.chip_id)); return -ENXIO; } - DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.rev)); + DBG("Found GPU: %"ADRENO_CHIPID_FMT, ADRENO_CHIPID_ARGS(config.chip_id)); priv->is_a2xx = info->family < ADRENO_3XX; priv->has_cached_coherent = diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 1a982a926f21..1274609a74b1 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -326,10 +326,7 @@ int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx, *value = !adreno_is_a650_family(adreno_gpu) ? 0x100000 : 0; return 0; case MSM_PARAM_CHIP_ID: - *value = (uint64_t)adreno_gpu->rev.patchid | - ((uint64_t)adreno_gpu->rev.minor << 8) | - ((uint64_t)adreno_gpu->rev.major << 16) | - ((uint64_t)adreno_gpu->rev.core << 24); + *value = adreno_gpu->chip_id; if (!adreno_gpu->info->revn) *value |= ((uint64_t) adreno_gpu->speedbin) << 32; return 0; @@ -849,7 +846,7 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, drm_printf(p, "revision: %u (%"ADRENO_CHIPID_FMT")\n", adreno_gpu->info->revn, - ADRENO_CHIPID_ARGS(adreno_gpu->rev)); + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id)); /* * If this is state collected due to iova fault, so fault related info * @@ -922,7 +919,7 @@ void adreno_dump_info(struct msm_gpu *gpu) printk("revision: %u (%"ADRENO_CHIPID_FMT")\n", adreno_gpu->info->revn, - ADRENO_CHIPID_ARGS(adreno_gpu->rev)); + ADRENO_CHIPID_ARGS(adreno_gpu->chip_id)); for (i = 0; i < gpu->nr_rings; i++) { struct msm_ringbuffer *ring = gpu->rb[i]; @@ -1072,14 +1069,13 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, struct adreno_platform_config *config = dev->platform_data; struct msm_gpu_config adreno_gpu_config = { 0 }; struct msm_gpu *gpu = &adreno_gpu->base; - struct adreno_rev *rev = &config->rev; const char *gpu_name; u32 speedbin; int ret; adreno_gpu->funcs = funcs; - adreno_gpu->info = adreno_info(config->rev); - adreno_gpu->rev = *rev; + adreno_gpu->info = adreno_find_info(config->chip_id); + adreno_gpu->chip_id = config->chip_id; /* Only handle the core clock when GMU is not in use (or is absent). */ if (adreno_has_gmu_wrapper(adreno_gpu) || @@ -1104,7 +1100,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu->speedbin = (uint16_t) (0xffff & speedbin); gpu_name = devm_kasprintf(dev, GFP_KERNEL, "%"ADRENO_CHIPID_FMT, - ADRENO_CHIPID_ARGS(config->rev)); + ADRENO_CHIPID_ARGS(config->chip_id)); if (!gpu_name) return -ENOMEM; diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index 73e7155f164c..18f53c7ab589 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -54,23 +54,15 @@ enum adreno_family { #define ADRENO_QUIRK_HAS_HW_APRIV BIT(3) #define ADRENO_QUIRK_HAS_CACHED_COHERENT BIT(4) -struct adreno_rev { - uint8_t core; - uint8_t major; - uint8_t minor; - uint8_t patchid; -}; - -#define ANY_ID 0xff - -#define ADRENO_REV(core, major, minor, patchid) \ - ((struct adreno_rev){ core, major, minor, patchid }) - /* Helper for formating the chip_id in the way that userspace tools like * crashdec expect. */ #define ADRENO_CHIPID_FMT "u.%u.%u.%u" -#define ADRENO_CHIPID_ARGS(_r) (_r).core, (_r).major, (_r).minor, (_r).patchid +#define ADRENO_CHIPID_ARGS(_c) \ + (((_c) >> 24) & 0xff), \ + (((_c) >> 16) & 0xff), \ + (((_c) >> 8) & 0xff), \ + ((_c) & 0xff) struct adreno_gpu_funcs { struct msm_gpu_funcs base; @@ -87,7 +79,12 @@ extern const struct adreno_reglist a660_hwcg[], a690_hwcg[]; struct adreno_info { const char *machine; - struct adreno_rev rev; + /** + * @chipids: Table of matching chip-ids + * + * Terminated with 0 sentinal + */ + uint32_t *chip_ids; enum adreno_family family; uint32_t revn; const char *fw[ADRENO_FW_MAX]; @@ -107,6 +104,8 @@ struct adreno_info { uint32_t *speedbins; }; +#define ADRENO_CHIP_IDS(tbl...) (uint32_t[]) { tbl, 0 } + /* * Helper to build a speedbin table, ie. the table: * fuse | speedbin @@ -125,12 +124,12 @@ struct adreno_info { */ #define ADRENO_SPEEDBINS(tbl...) (uint32_t[]) { tbl, UINT_MAX } -const struct adreno_info *adreno_info(struct adreno_rev rev); +const struct adreno_info *adreno_find_info(uint32_t chip_id); struct adreno_gpu { struct msm_gpu base; - struct adreno_rev rev; const struct adreno_info *info; + uint32_t chip_id; uint16_t speedbin; const struct adreno_gpu_funcs *funcs; @@ -179,7 +178,7 @@ struct adreno_ocmem { /* platform config data (ie. from DT, or pdata) */ struct adreno_platform_config { - struct adreno_rev rev; + uint32_t chip_id; }; #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000) @@ -196,7 +195,15 @@ struct adreno_platform_config { __ret; \ }) -bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2); +static inline uint8_t adreno_patchid(const struct adreno_gpu *gpu) +{ + /* It is probably ok to assume legacy "adreno_rev" format + * for all a6xx devices, but probably best to limit this + * to older things. + */ + WARN_ON_ONCE(gpu->info->family >= ADRENO_6XX_GEN1); + return gpu->chip_id & 0xff; +} static inline bool adreno_is_revn(const struct adreno_gpu *gpu, uint32_t revn) { @@ -252,7 +259,7 @@ static inline bool adreno_is_a330(const struct adreno_gpu *gpu) static inline bool adreno_is_a330v2(const struct adreno_gpu *gpu) { - return adreno_is_a330(gpu) && (gpu->rev.patchid > 0); + return adreno_is_a330(gpu) && (adreno_patchid(gpu) > 0); } static inline int adreno_is_a405(const struct adreno_gpu *gpu) @@ -342,8 +349,7 @@ static inline int adreno_is_a650(const struct adreno_gpu *gpu) static inline int adreno_is_7c3(const struct adreno_gpu *gpu) { - /* The order of args is important here to handle ANY_ID correctly */ - return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev); + return gpu->info->chip_ids[0] == 0x06030500; } static inline int adreno_is_a660(const struct adreno_gpu *gpu) @@ -358,8 +364,7 @@ static inline int adreno_is_a680(const struct adreno_gpu *gpu) static inline int adreno_is_a690(const struct adreno_gpu *gpu) { - /* The order of args is important here to handle ANY_ID correctly */ - return adreno_cmp_rev(ADRENO_REV(6, 9, 0, ANY_ID), gpu->rev); + return gpu->info->chip_ids[0] == 0x06090000; }; /* check for a615, a616, a618, a619 or any a630 derivatives */ static inline int adreno_is_a630_family(const struct adreno_gpu *gpu)