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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.35 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/11] target/arm: Add raw_writes ops for register whose write induce TLB maintenance Date: Tue, 4 Jul 2023 17:36:24 +0100 Message-Id: <20230704163634.3188465-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Eric Auger Some registers whose 'cooked' writefns induce TLB maintenance do not have raw_writefn ops defined. If only the writefn ops is set (ie. no raw_writefn is provided), it is assumed the cooked also work as the raw one. For those registers it is not obvious the tlb_flush works on KVM mode so better/safer setting the raw write. Signed-off-by: Eric Auger Suggested-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.c | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d08c058e424..a0b84efab52 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4189,14 +4189,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = { .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 0, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_TTBR0_EL1, - .writefn = vmsa_ttbr_write, .resetvalue = 0, + .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 0, .crn = 2, .crm = 0, .opc2 = 1, .access = PL1_RW, .accessfn = access_tvm_trvm, .fgt = FGT_TTBR1_EL1, - .writefn = vmsa_ttbr_write, .resetvalue = 0, + .writefn = vmsa_ttbr_write, .resetvalue = 0, .raw_writefn = raw_write, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64, @@ -4456,13 +4456,13 @@ static const ARMCPRegInfo lpae_cp_reginfo[] = { .type = ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) }, - .writefn = vmsa_ttbr_write, }, + .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1, .access = PL1_RW, .accessfn = access_tvm_trvm, .type = ARM_CP_64BIT | ARM_CP_ALIAS, .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, - .writefn = vmsa_ttbr_write, }, + .writefn = vmsa_ttbr_write, .raw_writefn = raw_write }, }; static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -5911,7 +5911,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .type = ARM_CP_IO, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, .access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.hcr_el2), - .writefn = hcr_write }, + .writefn = hcr_write, .raw_writefn = raw_write }, { .name = "HCR", .state = ARM_CP_STATE_AA32, .type = ARM_CP_ALIAS | ARM_CP_IO, .cp = 15, .opc1 = 4, .crn = 1, .crm = 1, .opc2 = 0, @@ -5983,6 +5983,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { { .name = "TCR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 2, .access = PL2_RW, .writefn = vmsa_tcr_el12_write, + .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.tcr_el[2]) }, { .name = "VTCR", .state = ARM_CP_STATE_AA32, .cp = 15, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 2, @@ -5999,10 +6000,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .type = ARM_CP_64BIT | ARM_CP_ALIAS, .access = PL2_RW, .accessfn = access_el3_aa32ns, .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2), - .writefn = vttbr_write }, + .writefn = vttbr_write, .raw_writefn = raw_write }, { .name = "VTTBR_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 1, .opc2 = 0, - .access = PL2_RW, .writefn = vttbr_write, + .access = PL2_RW, .writefn = vttbr_write, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.vttbr_el2) }, { .name = "SCTLR_EL2", .state = ARM_CP_STATE_BOTH, .opc0 = 3, .opc1 = 4, .crn = 1, .crm = 0, .opc2 = 0, @@ -6014,7 +6015,8 @@ static const ARMCPRegInfo el2_cp_reginfo[] = { .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el[2]) }, { .name = "TTBR0_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 0, - .access = PL2_RW, .resetvalue = 0, .writefn = vmsa_tcr_ttbr_el2_write, + .access = PL2_RW, .resetvalue = 0, + .writefn = vmsa_tcr_ttbr_el2_write, .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el[2]) }, { .name = "HTTBR", .cp = 15, .opc1 = 4, .crm = 2, .access = PL2_RW, .type = ARM_CP_64BIT | ARM_CP_ALIAS, @@ -6201,12 +6203,12 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { { .name = "SCR_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 0, .access = PL3_RW, .fieldoffset = offsetof(CPUARMState, cp15.scr_el3), - .resetfn = scr_reset, .writefn = scr_write }, + .resetfn = scr_reset, .writefn = scr_write, .raw_writefn = raw_write }, { .name = "SCR", .type = ARM_CP_ALIAS | ARM_CP_NEWEL, .cp = 15, .opc1 = 0, .crn = 1, .crm = 1, .opc2 = 0, .access = PL1_RW, .accessfn = access_trap_aa32s_el1, .fieldoffset = offsetoflow32(CPUARMState, cp15.scr_el3), - .writefn = scr_write }, + .writefn = scr_write, .raw_writefn = raw_write }, { .name = "SDER32_EL3", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 6, .crn = 1, .crm = 1, .opc2 = 1, .access = PL3_RW, .resetvalue = 0, @@ -7927,6 +7929,7 @@ static const ARMCPRegInfo vhe_reginfo[] = { { .name = "TTBR1_EL2", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 4, .crn = 2, .crm = 0, .opc2 = 1, .access = PL2_RW, .writefn = vmsa_tcr_ttbr_el2_write, + .raw_writefn = raw_write, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el[2]) }, #ifndef CONFIG_USER_ONLY { .name = "CNTHV_CVAL_EL2", .state = ARM_CP_STATE_AA64, From patchwork Tue Jul 4 16:36:25 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/11] hw/arm/sbsa-ref: use XHCI to replace EHCI Date: Tue, 4 Jul 2023 17:36:25 +0100 Message-Id: <20230704163634.3188465-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Yuquan Wang The current sbsa-ref cannot use EHCI controller which is only able to do 32-bit DMA, since sbsa-ref doesn't have RAM below 4GB. Hence, this uses XHCI to provide a usb controller with 64-bit DMA capablity instead of EHCI. We bump the platform version to 0.3 with this change. Although the hardware at the USB controller address changes, the firmware and Linux can both cope with this -- on an older non-XHCI-aware firmware/kernel setup the probe routine simply fails and the guest proceeds without any USB. (This isn't a loss of functionality, because the old USB controller never worked in the first place.) So we can call this a backwards-compatible change and only bump the minor version. Signed-off-by: Yuquan Wang Message-id: 20230621103847.447508-2-wangyuquan1236@phytium.com.cn [PMM: tweaked commit message; add line to docs about what changes in platform version 0.3] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/sbsa.rst | 5 ++++- hw/arm/sbsa-ref.c | 23 +++++++++++++---------- hw/arm/Kconfig | 2 +- 3 files changed, 18 insertions(+), 12 deletions(-) diff --git a/docs/system/arm/sbsa.rst b/docs/system/arm/sbsa.rst index a8e0b530a24..bca61608ff8 100644 --- a/docs/system/arm/sbsa.rst +++ b/docs/system/arm/sbsa.rst @@ -19,7 +19,7 @@ The ``sbsa-ref`` board supports: - A configurable number of AArch64 CPUs - GIC version 3 - System bus AHCI controller - - System bus EHCI controller + - System bus XHCI controller - CDROM and hard disc on AHCI bus - E1000E ethernet card on PCIe bus - Bochs display adapter on PCIe bus @@ -68,3 +68,6 @@ Platform version changes: 0.2 GIC ITS information is present in devicetree. + +0.3 + The USB controller is an XHCI device, not EHCI diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 82a28b2e0be..1a8519b868f 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -42,6 +42,7 @@ #include "hw/pci-host/gpex.h" #include "hw/qdev-properties.h" #include "hw/usb.h" +#include "hw/usb/xhci.h" #include "hw/char/pl011.h" #include "hw/watchdog/sbsa_gwdt.h" #include "net/net.h" @@ -85,7 +86,7 @@ enum { SBSA_SECURE_UART_MM, SBSA_SECURE_MEM, SBSA_AHCI, - SBSA_EHCI, + SBSA_XHCI, }; struct SBSAMachineState { @@ -123,7 +124,7 @@ static const MemMapEntry sbsa_ref_memmap[] = { [SBSA_SMMU] = { 0x60050000, 0x00020000 }, /* Space here reserved for more SMMUs */ [SBSA_AHCI] = { 0x60100000, 0x00010000 }, - [SBSA_EHCI] = { 0x60110000, 0x00010000 }, + [SBSA_XHCI] = { 0x60110000, 0x00010000 }, /* Space here reserved for other devices */ [SBSA_PCIE_PIO] = { 0x7fff0000, 0x00010000 }, /* 32-bit address PCIE MMIO space */ @@ -143,7 +144,7 @@ static const int sbsa_ref_irqmap[] = { [SBSA_SECURE_UART] = 8, [SBSA_SECURE_UART_MM] = 9, [SBSA_AHCI] = 10, - [SBSA_EHCI] = 11, + [SBSA_XHCI] = 11, [SBSA_SMMU] = 12, /* ... to 15 */ [SBSA_GWDT_WS0] = 16, }; @@ -230,7 +231,7 @@ static void create_fdt(SBSAMachineState *sms) * fw compatibility. */ qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); - qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 2); + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 3); if (ms->numa_state->have_numa_distance) { int size = nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); @@ -604,13 +605,15 @@ static void create_ahci(const SBSAMachineState *sms) } } -static void create_ehci(const SBSAMachineState *sms) +static void create_xhci(const SBSAMachineState *sms) { - hwaddr base = sbsa_ref_memmap[SBSA_EHCI].base; - int irq = sbsa_ref_irqmap[SBSA_EHCI]; + hwaddr base = sbsa_ref_memmap[SBSA_XHCI].base; + int irq = sbsa_ref_irqmap[SBSA_XHCI]; + DeviceState *dev = qdev_new(TYPE_XHCI_SYSBUS); - sysbus_create_simple("platform-ehci-usb", base, - qdev_get_gpio_in(sms->gic, irq)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, base); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(sms->gic, irq)); } static void create_smmu(const SBSAMachineState *sms, PCIBus *bus) @@ -832,7 +835,7 @@ static void sbsa_ref_init(MachineState *machine) create_ahci(sms); - create_ehci(sms); + create_xhci(sms); create_pcie(sms); diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7de17d1e8c3..7e683484405 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -266,7 +266,7 @@ config SBSA_REF select PL011 # UART select PL031 # RTC select PL061 # GPIO - select USB_EHCI_SYSBUS + select USB_XHCI_SYSBUS select WDT_SBSA select BOCHS_DISPLAY From patchwork Tue Jul 4 16:36:26 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:36 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/11] target/arm: Avoid splitting Zregs across lines in dump Date: Tue, 4 Jul 2023 17:36:26 +0100 Message-Id: <20230704163634.3188465-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Allow the line length to extend to 548 columns. While annoyingly wide, it's still less confusing than the continuations we print. Also, the default VL used by Linux (and max for A64FX) uses only 140 columns. Signed-off-by: Richard Henderson Message-id: 20230622151201.1578522-2-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 36 ++++++++++++++---------------------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a1e77698ba2..f12c714bc43 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -955,7 +955,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) ARMCPU *cpu = ARM_CPU(cs); CPUARMState *env = &cpu->env; uint32_t psr = pstate_read(env); - int i; + int i, j; int el = arm_current_el(env); const char *ns_status; bool sve; @@ -1014,7 +1014,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) } if (sve) { - int j, zcr_len = sve_vqm1_for_el(env, el); + int zcr_len = sve_vqm1_for_el(env, el); for (i = 0; i <= FFR_PRED_NUM; i++) { bool eol; @@ -1054,32 +1054,24 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) } } - for (i = 0; i < 32; i++) { - if (zcr_len == 0) { + if (zcr_len == 0) { + /* + * With vl=16, there are only 37 columns per register, + * so output two registers per line. + */ + for (i = 0; i < 32; i++) { qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 "%s", i, env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0], i & 1 ? "\n" : " "); - } else if (zcr_len == 1) { - qemu_fprintf(f, "Z%02d=%016" PRIx64 ":%016" PRIx64 - ":%016" PRIx64 ":%016" PRIx64 "\n", - i, env->vfp.zregs[i].d[3], env->vfp.zregs[i].d[2], - env->vfp.zregs[i].d[1], env->vfp.zregs[i].d[0]); - } else { + } + } else { + for (i = 0; i < 32; i++) { + qemu_fprintf(f, "Z%02d=", i); for (j = zcr_len; j >= 0; j--) { - bool odd = (zcr_len - j) % 2 != 0; - if (j == zcr_len) { - qemu_fprintf(f, "Z%02d[%x-%x]=", i, j, j - 1); - } else if (!odd) { - if (j > 0) { - qemu_fprintf(f, " [%x-%x]=", j, j - 1); - } else { - qemu_fprintf(f, " [%x]=", j); - } - } qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%s", env->vfp.zregs[i].d[j * 2 + 1], - env->vfp.zregs[i].d[j * 2], - odd || j == 0 ? "\n" : ":"); + env->vfp.zregs[i].d[j * 2 + 0], + j ? ":" : "\n"); } } } From patchwork Tue Jul 4 16:36:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 698967 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2364704wrs; Tue, 4 Jul 2023 09:38:11 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7g1b8aFCTAVbEnBxmdW6bxu2yBaRc4RHqmKetEpmIFFzxY0EeVzUJyp+r+WrocMdSokX0s X-Received: by 2002:ac8:5890:0:b0:403:3885:b80f with SMTP id t16-20020ac85890000000b004033885b80fmr19524751qta.57.1688488691480; Tue, 04 Jul 2023 09:38:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688488691; cv=none; d=google.com; s=arc-20160816; b=oUF2+hTdgcSBT5IouU6Hl3UdXDgW+vyiB4y0HP7RoqJdGg4zQYeqhnwPHx5MiodXPn TXBad4ir6fvDlsxxrEBYfVSr6KZ5tTaaQJtD9sqW2yYHZCkN/DDhK+f4WcppxFvPesCe ASPPcfau7ndROH2fo1vnDZgAnpdfcqA9zCDgGqKQj8TXhdkZfUSQafA4qHQna3wcTOyq UOPwpv8fY7iNAWQAWrGbO4BnV7Sz3HkkbFn0u5kZV5cZMnQ765PLfqct/TT3IwuHZCHk X5bgrLK/Ir6NmPWEIGu2Dp74nfyBt7yQpyH1Wo320S7dI7e6EQwQsZ5k3DH28ms+4Dmv h2pA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=kTYABhSkRPbMfHK4MqNnIuIncwaUJ0xXtOeHrnGp338=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=aaR3we/i0tnHi7qwkfjL8Pc93mR00ntg5noNofffvrfHKzEwZR/E4o9VPiIolsZYlW boRK1W2WL6O5mvUwyNPenj7CQjcCC0ICGe2a9y8K1Og/HHouFs0ygLSC+VQYM9rZIcyh tq1iYp+8Eoz8y+K6zCqu4UpMQIvvKz/KHY38h3oPqb1pVbxUhCCtbvjHBh2zvLdKc8rt XRrfNT+hgSgFHLKd9hiQM8yU+aWG8k6NcZ+EsMMtK64KVXLagVtwGnsWabTNqDyAPA2c sZMOFSs99yaGd/+7E02NY1pbmI6fazZa68G/xXdrrB5f9WxqnYhtIpB1ZmFEBQZTXQoA Cspw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=h5wSPoS2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/11] target/arm: Dump ZA[] when active Date: Tue, 4 Jul 2023 17:36:27 +0100 Message-Id: <20230704163634.3188465-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson Always print each matrix row whole, one per line, so that we get the entire matrix in the proper shape. Signed-off-by: Richard Henderson Message-id: 20230622151201.1578522-3-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/cpu.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f12c714bc43..adf84f96860 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1082,6 +1082,24 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) i, q[1], q[0], (i & 1 ? "\n" : " ")); } } + + if (cpu_isar_feature(aa64_sme, cpu) && + FIELD_EX64(env->svcr, SVCR, ZA) && + sme_exception_el(env, el) == 0) { + int zcr_len = sve_vqm1_for_el_sm(env, el, true); + int svl = (zcr_len + 1) * 16; + int svl_lg10 = svl < 100 ? 2 : 3; + + for (i = 0; i < svl; i++) { + qemu_fprintf(f, "ZA[%0*d]=", svl_lg10, i); + for (j = zcr_len; j >= 0; --j) { + qemu_fprintf(f, "%016" PRIx64 ":%016" PRIx64 "%c", + env->zarray[i].d[2 * j + 1], + env->zarray[i].d[2 * j], + j ? ':' : '\n'); + } + } + } } #else From patchwork Tue Jul 4 16:36:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 698963 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2364522wrs; Tue, 4 Jul 2023 09:37:54 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7IKgzKfXt5M152LA08NqiyKTGjojQUnwD05zd7aCd3470drALZo5QUMLYECuA0avYYyZZz X-Received: by 2002:a05:620a:f10:b0:75f:9c6d:d99b with SMTP id v16-20020a05620a0f1000b0075f9c6dd99bmr15741829qkl.8.1688488674068; Tue, 04 Jul 2023 09:37:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688488674; cv=none; d=google.com; s=arc-20160816; b=k9jbiiVZDkI7bp8iQVbMc/mq2f2O7kwf//aiDH6ADQlUb5nmkQBypOxRmb+VUWmeUl OR4EYVeLTaKvR2/Pbq3Fyl8bP3UhhvFAsiNhCAEqfYNlQhgNiQ08BY8MjppLgdqwJy0b 3mqE8c4w9fv6l90X6c2Dt4K9aBZJEwJpJm5RETKqSPknlLO8wA9r9gaME4RL2U2uqOLz oiduhCqfkK18fi9im29IleKxNU+WkXqyWooWeCNgZSAbXcdDgxBOZDG180FPmXdTI3fr TEO/EQiu9oiMXZZmMZBBkhZ7XvlUN4V+Uo/YAUBlCQYAFP3wWOa3/Vgmjq3sb/gm8FAH lgsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=6iQY7+PhbnjlrKHmBY15bJBqwm1HUFH2IaULsHG+tok=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=yuIRz4kcvAQbCE5TKG75a9CT5AybxJnMGVH0f/ld0i+aJ4tiyNylhkN24bwJ51lI12 oFgKrbpP6Y4EXgN4aowqkhuk0Yva2J6py3P1wg1YJ1Jf/6YJIgreqKFs/ULxHcU+33pI GXvVO4MaqvrxuuOQCLeVZoJWb++/19KZykzrm19mrEA8LdyEwyxhprconziJvP0w/Nqg BGVTyq0q/r8MQzDmTlSE7/IMsac6C0YSqGMI1I8b7eeEM6Vo16YmCShcSmKKcJ4XE4nN BrD72nrnpRWCT0jKxcDEEb4EfL4jsE+H1z90wn6a5TWONFwFxOlKS6fxOM6a7+HluZUE D7Pw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gFpqnzVl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/11] target/arm: Fix SME full tile indexing Date: Tue, 4 Jul 2023 17:36:28 +0100 Message-Id: <20230704163634.3188465-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Richard Henderson For the outer product set of insns, which take an entire matrix tile as output, the argument is not a combined tile+column. Therefore using get_tile_rowcol was incorrect, as we extracted the tile number from itself. The test case relies only on assembler support for SME, since no release of GCC recognizes -march=armv9-a+sme yet. Cc: qemu-stable@nongnu.org Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1620 Signed-off-by: Richard Henderson Message-id: 20230622151201.1578522-5-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/tcg/translate-sme.c | 24 ++++++--- tests/tcg/aarch64/sme-outprod1.c | 83 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 10 ++-- 3 files changed, 108 insertions(+), 9 deletions(-) create mode 100644 tests/tcg/aarch64/sme-outprod1.c diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index d0054e3f775..6038b0a06f1 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -95,6 +95,21 @@ static TCGv_ptr get_tile_rowcol(DisasContext *s, int esz, int rs, return addr; } +/* + * Resolve tile.size[0] to a host pointer. + * Used by e.g. outer product insns where we require the entire tile. + */ +static TCGv_ptr get_tile(DisasContext *s, int esz, int tile) +{ + TCGv_ptr addr = tcg_temp_new_ptr(); + int offset; + + offset = tile * sizeof(ARMVectorReg) + offsetof(CPUARMState, zarray); + + tcg_gen_addi_ptr(addr, cpu_env, offset); + return addr; +} + static bool trans_ZERO(DisasContext *s, arg_ZERO *a) { if (!dc_isar_feature(aa64_sme, s)) { @@ -260,8 +275,7 @@ static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz, return true; } - /* Sum XZR+zad to find ZAd. */ - za = get_tile_rowcol(s, esz, 31, a->zad, false); + za = get_tile(s, esz, a->zad); zn = vec_full_reg_ptr(s, a->zn); pn = pred_full_reg_ptr(s, a->pn); pm = pred_full_reg_ptr(s, a->pm); @@ -286,8 +300,7 @@ static bool do_outprod(DisasContext *s, arg_op *a, MemOp esz, return true; } - /* Sum XZR+zad to find ZAd. */ - za = get_tile_rowcol(s, esz, 31, a->zad, false); + za = get_tile(s, esz, a->zad); zn = vec_full_reg_ptr(s, a->zn); zm = vec_full_reg_ptr(s, a->zm); pn = pred_full_reg_ptr(s, a->pn); @@ -308,8 +321,7 @@ static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, return true; } - /* Sum XZR+zad to find ZAd. */ - za = get_tile_rowcol(s, esz, 31, a->zad, false); + za = get_tile(s, esz, a->zad); zn = vec_full_reg_ptr(s, a->zn); zm = vec_full_reg_ptr(s, a->zm); pn = pred_full_reg_ptr(s, a->pn); diff --git a/tests/tcg/aarch64/sme-outprod1.c b/tests/tcg/aarch64/sme-outprod1.c new file mode 100644 index 00000000000..6e5972d75e3 --- /dev/null +++ b/tests/tcg/aarch64/sme-outprod1.c @@ -0,0 +1,83 @@ +/* + * SME outer product, 1 x 1. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include + +extern void foo(float *dst); + +asm( +" .arch_extension sme\n" +" .type foo, @function\n" +"foo:\n" +" stp x29, x30, [sp, -80]!\n" +" mov x29, sp\n" +" stp d8, d9, [sp, 16]\n" +" stp d10, d11, [sp, 32]\n" +" stp d12, d13, [sp, 48]\n" +" stp d14, d15, [sp, 64]\n" +" smstart\n" +" ptrue p0.s, vl4\n" +" fmov z0.s, #1.0\n" +/* + * An outer product of a vector of 1.0 by itself should be a matrix of 1.0. + * Note that we are using tile 1 here (za1.s) rather than tile 0. + */ +" zero {za}\n" +" fmopa za1.s, p0/m, p0/m, z0.s, z0.s\n" +/* + * Read the first 4x4 sub-matrix of elements from tile 1: + * Note that za1h should be interchangable here. + */ +" mov w12, #0\n" +" mova z0.s, p0/m, za1v.s[w12, #0]\n" +" mova z1.s, p0/m, za1v.s[w12, #1]\n" +" mova z2.s, p0/m, za1v.s[w12, #2]\n" +" mova z3.s, p0/m, za1v.s[w12, #3]\n" +/* + * And store them to the input pointer (dst in the C code): + */ +" st1w {z0.s}, p0, [x0]\n" +" add x0, x0, #16\n" +" st1w {z1.s}, p0, [x0]\n" +" add x0, x0, #16\n" +" st1w {z2.s}, p0, [x0]\n" +" add x0, x0, #16\n" +" st1w {z3.s}, p0, [x0]\n" +" smstop\n" +" ldp d8, d9, [sp, 16]\n" +" ldp d10, d11, [sp, 32]\n" +" ldp d12, d13, [sp, 48]\n" +" ldp d14, d15, [sp, 64]\n" +" ldp x29, x30, [sp], 80\n" +" ret\n" +" .size foo, . - foo" +); + +int main() +{ + float dst[16]; + int i, j; + + foo(dst); + + for (i = 0; i < 16; i++) { + if (dst[i] != 1.0f) { + break; + } + } + + if (i == 16) { + return 0; /* success */ + } + + /* failure */ + for (i = 0; i < 4; ++i) { + for (j = 0; j < 4; ++j) { + printf("%f ", (double)dst[i * 4 + j]); + } + printf("\n"); + } + return 1; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index cec1d4b2875..97cfc43600a 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -26,7 +26,7 @@ config-cc.mak: Makefile $(call cc-option,-march=armv8.5-a, CROSS_CC_HAS_ARMV8_5); \ $(call cc-option,-mbranch-protection=standard, CROSS_CC_HAS_ARMV8_BTI); \ $(call cc-option,-march=armv8.5-a+memtag, CROSS_CC_HAS_ARMV8_MTE); \ - $(call cc-option,-march=armv9-a+sme, CROSS_CC_HAS_ARMV9_SME)) 3> config-cc.mak + $(call cc-option,-Wa$(COMMA)-march=armv9-a+sme, CROSS_AS_HAS_ARMV9_SME)) 3> config-cc.mak -include config-cc.mak ifneq ($(CROSS_CC_HAS_ARMV8_2),) @@ -61,11 +61,15 @@ AARCH64_TESTS += mte-1 mte-2 mte-3 mte-4 mte-5 mte-6 mte-7 mte-%: CFLAGS += -march=armv8.5-a+memtag endif +ifneq ($(CROSS_AS_HAS_ARMV9_SME),) +AARCH64_TESTS += sme-outprod1 +endif + ifneq ($(CROSS_CC_HAS_SVE),) # System Registers Tests AARCH64_TESTS += sysregs -ifneq ($(CROSS_CC_HAS_ARMV9_SME),) -sysregs: CFLAGS+=-march=armv9-a+sme -DHAS_ARMV9_SME +ifneq ($(CROSS_AS_HAS_ARMV9_SME),) +sysregs: CFLAGS+=-Wa,-march=armv9-a+sme -DHAS_ARMV9_SME else sysregs: CFLAGS+=-march=armv8.1-a+sve endif From patchwork Tue Jul 4 16:36:29 2023 Content-Type: text/plain; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/11] target/arm: Handle IC IVAU to improve compatibility with JITs Date: Tue, 4 Jul 2023 17:36:29 +0100 Message-Id: <20230704163634.3188465-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: John Högberg Unlike architectures with precise self-modifying code semantics (e.g. x86) ARM processors do not maintain coherency for instruction execution and memory, requiring an instruction synchronization barrier on every core that will execute the new code, and on many models also the explicit use of cache management instructions. While this is required to make JITs work on actual hardware, QEMU has gotten away with not handling this since it does not emulate caches, and unconditionally invalidates code whenever the softmmu or the user-mode page protection logic detects that code has been modified. Unfortunately the latter does not work in the face of dual-mapped code (a common W^X workaround), where one page is executable and the other is writable: user-mode has no way to connect one with the other as that is only known to the kernel and the emulated application. This commit works around the issue by telling software that instruction cache invalidation is required by clearing the CPR_EL0.DIC flag (regardless of whether the emulated processor needs it), and then invalidating code in IC IVAU instructions. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1034 Co-authored-by: Richard Henderson Signed-off-by: John Högberg Reviewed-by: Richard Henderson Message-id: 168778890374.24232.3402138851538068785-1@git.sr.ht [PMM: removed unnecessary AArch64 feature check; moved "clear CTR_EL1.DIC" code up a bit so it's not in the middle of the vfp/neon related tests] Signed-off-by: Peter Maydell --- target/arm/cpu.c | 11 +++++++++++ target/arm/helper.c | 47 ++++++++++++++++++++++++++++++++++++++++++--- 2 files changed, 55 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index adf84f96860..822efa5b2c1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1694,6 +1694,17 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) return; } +#ifdef CONFIG_USER_ONLY + /* + * User mode relies on IC IVAU instructions to catch modification of + * dual-mapped code. + * + * Clear CTR_EL0.DIC to ensure that software that honors these flags uses + * IC IVAU even if the emulated processor does not normally require it. + */ + cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); +#endif + if (arm_feature(env, ARM_FEATURE_AARCH64) && cpu->has_vfp != cpu->has_neon) { /* diff --git a/target/arm/helper.c b/target/arm/helper.c index a0b84efab52..8e836aaee13 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5234,6 +5234,36 @@ static void mdcr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, } } +#ifdef CONFIG_USER_ONLY +/* + * `IC IVAU` is handled to improve compatibility with JITs that dual-map their + * code to get around W^X restrictions, where one region is writable and the + * other is executable. + * + * Since the executable region is never written to we cannot detect code + * changes when running in user mode, and rely on the emulated JIT telling us + * that the code has changed by executing this instruction. + */ +static void ic_ivau_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t icache_line_mask, start_address, end_address; + const ARMCPU *cpu; + + cpu = env_archcpu(env); + + icache_line_mask = (4 << extract32(cpu->ctr, 0, 4)) - 1; + start_address = value & ~icache_line_mask; + end_address = value | icache_line_mask; + + mmap_lock(); + + tb_invalidate_phys_range(start_address, end_address); + + mmap_unlock(); +} +#endif + static const ARMCPRegInfo v8_cp_reginfo[] = { /* * Minimal set of EL0-visible registers. This will need to be expanded @@ -5273,7 +5303,10 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64, .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2, .access = PL1_R, .type = ARM_CP_CURRENTEL }, - /* Cache ops: all NOPs since we don't emulate caches */ + /* + * Instruction cache ops. All of these except `IC IVAU` NOP because we + * don't emulate caches. + */ { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0, .access = PL1_W, .type = ARM_CP_NOP, @@ -5286,9 +5319,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] = { .accessfn = access_tocu }, { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1, - .access = PL0_W, .type = ARM_CP_NOP, + .access = PL0_W, .fgt = FGT_ICIVAU, - .accessfn = access_tocu }, + .accessfn = access_tocu, +#ifdef CONFIG_USER_ONLY + .type = ARM_CP_NO_RAW, + .writefn = ic_ivau_write +#else + .type = ARM_CP_NOP +#endif + }, + /* Cache ops: all NOPs since we don't emulate caches */ { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64, .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1, .access = PL1_W, .accessfn = aa64_cacheop_poc_access, From patchwork Tue Jul 4 16:36:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 698969 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2364925wrs; Tue, 4 Jul 2023 09:38:38 -0700 (PDT) X-Google-Smtp-Source: APBJJlHiX/vvtrQfrCNxa3ew+lvwHBaDP0PdnUTXKsYguw9E68igptMN6dK42BVi+1kPmbCc0Xdd X-Received: by 2002:a05:6214:e84:b0:635:e197:7781 with SMTP id hf4-20020a0562140e8400b00635e1977781mr18409795qvb.48.1688488718514; Tue, 04 Jul 2023 09:38:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688488718; cv=none; d=google.com; s=arc-20160816; b=Ht1HdiOVp5MUO1W/shEwub8exdn2PSU9JEd7e3SfDTd92F+hLlPDsEsembMpVZuafi LaNQ61QdQ1nfdto2MLJJyKbs68zDNKcxpGvu1EYjIIQ/XdXE4ioOjQtCfqheWTEBvSRA kKiIiG2qjtB4PInuBJzyuzCOeT+k9PCilPJbtgvG6o+e3Fsy8zDftOF6JPtttHDvR1oj eC+aIiwdzug/KM6gqYNvofTAun/caMYzN1NxySJEqc2ebWrOQ1lbf4u+sal0M5edPTWR lx1U35CjU7XLDI7F+EUdTVxp5KoMECcjLXjtnXOVaaRwE4w8tCfJHbcsXCSitn4aHE7E v6kg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=1+5gA5Gx3OWByEd+ONnCyhPvuTERrBtfW0lccmJX71g=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Cj7KjsPw2K1XE7gF8iwWJuTzIil1H/4/fJIuO39etMlDbods1Ah4mfspESW4bLdpEn o0djjeSxwMcvze+EWrt5K8QPXBeCrTYxHV20jdYojb43Mgegrj6nW31Ww/ylyg2PMHZH HoAPfk64Jx8N+BYIIIu5SLHdAcnA1UmyRnQQnDLcSGXT4GR/sLP2uyEbH22zssoalepu XZ9nexlZusqdH5RMmucAJ6RaDs20wzaPsQKcJHZ0yJmNVhkIh6I0Bbp0rlLoShpEO6RV X3SI7O3L9Dph6TJY+pZpNUnnvwWF3WsHGp/GgBtT82AP9OdLBTVuU6kGK9qWdWO57Xcd ZCuA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dSmoL2fs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/11] tests/tcg/aarch64: Add testcases for IC IVAU and dual-mapped code Date: Tue, 4 Jul 2023 17:36:30 +0100 Message-Id: <20230704163634.3188465-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: John Högberg https://gitlab.com/qemu-project/qemu/-/issues/1034 Signed-off-by: John Högberg Message-id: 168778890374.24232.3402138851538068785-2@git.sr.ht Reviewed-by: Peter Maydell [PMM: fixed typo in comment] Signed-off-by: Peter Maydell --- tests/tcg/aarch64/icivau.c | 189 ++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 3 +- 2 files changed, 191 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/icivau.c diff --git a/tests/tcg/aarch64/icivau.c b/tests/tcg/aarch64/icivau.c new file mode 100644 index 00000000000..77b9e98d5e5 --- /dev/null +++ b/tests/tcg/aarch64/icivau.c @@ -0,0 +1,189 @@ +/* + * Tests the IC IVAU-driven workaround for catching changes made to dual-mapped + * code that would otherwise go unnoticed in user mode. + * + * Copyright (c) 2023 Ericsson AB + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include +#include + +#define MAX_CODE_SIZE 128 + +typedef int (SelfModTest)(uint32_t, uint32_t*); +typedef int (BasicTest)(int); + +static void mark_code_modified(const uint32_t *exec_data, size_t length) +{ + int dc_required, ic_required; + unsigned long ctr_el0; + + /* + * Clear the data/instruction cache, as indicated by the CTR_ELO.{DIC,IDC} + * flags. + * + * For completeness we might be tempted to assert that we should fail when + * the whole code update sequence is omitted, but that would make the test + * flaky as it can succeed by coincidence on actual hardware. + */ + asm ("mrs %0, ctr_el0\n" : "=r"(ctr_el0)); + + /* CTR_EL0.IDC */ + dc_required = !((ctr_el0 >> 28) & 1); + + /* CTR_EL0.DIC */ + ic_required = !((ctr_el0 >> 29) & 1); + + if (dc_required) { + size_t dcache_stride, i; + + /* + * Step according to the minimum cache size, as the cache maintenance + * instructions operate on the cache line of the given address. + * + * We assume that exec_data is properly aligned. + */ + dcache_stride = (4 << ((ctr_el0 >> 16) & 0xF)); + + for (i = 0; i < length; i += dcache_stride) { + const char *dc_addr = &((const char *)exec_data)[i]; + asm volatile ("dc cvau, %x[dc_addr]\n" + : /* no outputs */ + : [dc_addr] "r"(dc_addr) + : "memory"); + } + + asm volatile ("dmb ish\n"); + } + + if (ic_required) { + size_t icache_stride, i; + + icache_stride = (4 << (ctr_el0 & 0xF)); + + for (i = 0; i < length; i += icache_stride) { + const char *ic_addr = &((const char *)exec_data)[i]; + asm volatile ("ic ivau, %x[ic_addr]\n" + : /* no outputs */ + : [ic_addr] "r"(ic_addr) + : "memory"); + } + + asm volatile ("dmb ish\n"); + } + + asm volatile ("isb sy\n"); +} + +static int basic_test(uint32_t *rw_data, const uint32_t *exec_data) +{ + /* + * As user mode only misbehaved for dual-mapped code when previously + * translated code had been changed, we'll start off with this basic test + * function to ensure that there's already some translated code at + * exec_data before the next test. This should cause the next test to fail + * if `mark_code_modified` fails to invalidate the code. + * + * Note that the payload is in binary form instead of inline assembler + * because we cannot use __attribute__((naked)) on this platform and the + * workarounds are at least as ugly as this is. + */ + static const uint32_t basic_payload[] = { + 0xD65F03C0 /* 0x00: RET */ + }; + + BasicTest *copied_ptr = (BasicTest *)exec_data; + + memcpy(rw_data, basic_payload, sizeof(basic_payload)); + mark_code_modified(exec_data, sizeof(basic_payload)); + + return copied_ptr(1234) == 1234; +} + +static int self_modification_test(uint32_t *rw_data, const uint32_t *exec_data) +{ + /* + * This test is self-modifying in an attempt to cover an edge case where + * the IC IVAU instruction invalidates itself. + * + * Note that the IC IVAU instruction is 16 bytes into the function, in what + * will be the same cache line as the modified instruction on machines with + * a cache line size >= 16 bytes. + */ + static const uint32_t self_mod_payload[] = { + /* Overwrite the placeholder instruction with the new one. */ + 0xB9001C20, /* 0x00: STR w0, [x1, 0x1C] */ + + /* Get the executable address of the modified instruction. */ + 0x100000A8, /* 0x04: ADR x8, <0x1C> */ + + /* Mark the modified instruction as updated. */ + 0xD50B7B28, /* 0x08: DC CVAU x8 */ + 0xD5033BBF, /* 0x0C: DMB ISH */ + 0xD50B7528, /* 0x10: IC IVAU x8 */ + 0xD5033BBF, /* 0x14: DMB ISH */ + 0xD5033FDF, /* 0x18: ISB */ + + /* Placeholder instruction, overwritten above. */ + 0x52800000, /* 0x1C: MOV w0, 0 */ + + 0xD65F03C0 /* 0x20: RET */ + }; + + SelfModTest *copied_ptr = (SelfModTest *)exec_data; + int i; + + memcpy(rw_data, self_mod_payload, sizeof(self_mod_payload)); + mark_code_modified(exec_data, sizeof(self_mod_payload)); + + for (i = 1; i < 10; i++) { + /* Replace the placeholder instruction with `MOV w0, i` */ + uint32_t new_instr = 0x52800000 | (i << 5); + + if (copied_ptr(new_instr, rw_data) != i) { + return 0; + } + } + + return 1; +} + +int main(int argc, char **argv) +{ + const char *shm_name = "qemu-test-tcg-aarch64-icivau"; + int fd; + + fd = shm_open(shm_name, O_CREAT | O_RDWR, S_IRUSR | S_IWUSR); + + if (fd < 0) { + return EXIT_FAILURE; + } + + /* Unlink early to avoid leaving garbage in case the test crashes. */ + shm_unlink(shm_name); + + if (ftruncate(fd, MAX_CODE_SIZE) == 0) { + const uint32_t *exec_data; + uint32_t *rw_data; + + rw_data = mmap(0, MAX_CODE_SIZE, PROT_READ | PROT_WRITE, + MAP_SHARED, fd, 0); + exec_data = mmap(0, MAX_CODE_SIZE, PROT_READ | PROT_EXEC, + MAP_SHARED, fd, 0); + + if (rw_data && exec_data) { + if (basic_test(rw_data, exec_data) && + self_modification_test(rw_data, exec_data)) { + return EXIT_SUCCESS; + } + } + } + + return EXIT_FAILURE; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 97cfc43600a..bf9d21d72fb 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -9,9 +9,10 @@ AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 VPATH += $(AARCH64_SRC) # Base architecture tests -AARCH64_TESTS=fcvt pcalign-a64 +AARCH64_TESTS=fcvt pcalign-a64 icivau fcvt: LDFLAGS+=-lm +icivau: LDFLAGS+=-lrt run-fcvt: fcvt $(call run-test,$<,$(QEMU) $<, "$< on $(TARGET_NAME)") From patchwork Tue Jul 4 16:36:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 698959 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2364239wrs; Tue, 4 Jul 2023 09:37:19 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7H33G2MlCxgtymRl125/K9hHocO3TKXs1Lv1evktPseawTZ4YESf6eAsbEkGuRNhaygJJ8 X-Received: by 2002:a05:620a:4113:b0:765:59d8:d421 with SMTP id j19-20020a05620a411300b0076559d8d421mr17833697qko.1.1688488639041; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.38 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/11] tests/qtest: xlnx-canfd-test: Fix code coverity issues Date: Tue, 4 Jul 2023 17:36:31 +0100 Message-Id: <20230704163634.3188465-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Vikram Garhwal Following are done to fix the coverity issues: 1. Change read_data to fix the CID 1512899: Out-of-bounds access (OVERRUN) 2. Fix match_rx_tx_data to fix CID 1512900: Logically dead code (DEADCODE) 3. Replace rand() in generate_random_data() with g_rand_int() Signed-off-by: Vikram Garhwal Message-id: 20230628202758.16398-1-vikram.garhwal@amd.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- tests/qtest/xlnx-canfd-test.c | 33 +++++++++++---------------------- 1 file changed, 11 insertions(+), 22 deletions(-) diff --git a/tests/qtest/xlnx-canfd-test.c b/tests/qtest/xlnx-canfd-test.c index 76ee106d4f4..78ec9ef2a76 100644 --- a/tests/qtest/xlnx-canfd-test.c +++ b/tests/qtest/xlnx-canfd-test.c @@ -170,23 +170,23 @@ static void generate_random_data(uint32_t *buf_tx, bool is_canfd_frame) /* Generate random TX data for CANFD frame. */ if (is_canfd_frame) { for (int i = 0; i < CANFD_FRAME_SIZE - 2; i++) { - buf_tx[2 + i] = rand(); + buf_tx[2 + i] = g_random_int(); } } else { /* Generate random TX data for CAN frame. */ for (int i = 0; i < CAN_FRAME_SIZE - 2; i++) { - buf_tx[2 + i] = rand(); + buf_tx[2 + i] = g_random_int(); } } } -static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx) +static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx, + uint32_t frame_size) { uint32_t int_status; uint32_t fifo_status_reg_value; /* At which RX FIFO the received data is stored. */ uint8_t store_ind = 0; - bool is_canfd_frame = false; /* Read the interrupt on CANFD rx. */ int_status = qtest_readl(qts, can_base_addr + R_ISR_OFFSET) & ISR_RXOK; @@ -207,16 +207,9 @@ static void read_data(QTestState *qts, uint64_t can_base_addr, uint32_t *buf_rx) buf_rx[0] = qtest_readl(qts, can_base_addr + R_RX0_ID_OFFSET); buf_rx[1] = qtest_readl(qts, can_base_addr + R_RX0_DLC_OFFSET); - is_canfd_frame = (buf_rx[1] >> DLC_FD_BIT_SHIFT) & 1; - - if (is_canfd_frame) { - for (int i = 0; i < CANFD_FRAME_SIZE - 2; i++) { - buf_rx[i + 2] = qtest_readl(qts, - can_base_addr + R_RX0_DATA1_OFFSET + 4 * i); - } - } else { - buf_rx[2] = qtest_readl(qts, can_base_addr + R_RX0_DATA1_OFFSET); - buf_rx[3] = qtest_readl(qts, can_base_addr + R_RX0_DATA2_OFFSET); + for (int i = 0; i < frame_size - 2; i++) { + buf_rx[i + 2] = qtest_readl(qts, + can_base_addr + R_RX0_DATA1_OFFSET + 4 * i); } /* Clear the RX interrupt. */ @@ -272,10 +265,6 @@ static void match_rx_tx_data(const uint32_t *buf_tx, const uint32_t *buf_rx, g_assert_cmpint((buf_rx[size] & DLC_FD_BIT_MASK), ==, (buf_tx[size] & DLC_FD_BIT_MASK)); } else { - if (!is_canfd_frame && size == 4) { - break; - } - g_assert_cmpint(buf_rx[size], ==, buf_tx[size]); } @@ -318,7 +307,7 @@ static void test_can_data_transfer(void) write_data(qts, CANFD0_BASE_ADDR, buf_tx, false); send_data(qts, CANFD0_BASE_ADDR); - read_data(qts, CANFD1_BASE_ADDR, buf_rx); + read_data(qts, CANFD1_BASE_ADDR, buf_rx, CAN_FRAME_SIZE); match_rx_tx_data(buf_tx, buf_rx, false); qtest_quit(qts); @@ -358,7 +347,7 @@ static void test_canfd_data_transfer(void) write_data(qts, CANFD0_BASE_ADDR, buf_tx, true); send_data(qts, CANFD0_BASE_ADDR); - read_data(qts, CANFD1_BASE_ADDR, buf_rx); + read_data(qts, CANFD1_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE); match_rx_tx_data(buf_tx, buf_rx, true); qtest_quit(qts); @@ -397,7 +386,7 @@ static void test_can_loopback(void) write_data(qts, CANFD0_BASE_ADDR, buf_tx, true); send_data(qts, CANFD0_BASE_ADDR); - read_data(qts, CANFD0_BASE_ADDR, buf_rx); + read_data(qts, CANFD0_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE); match_rx_tx_data(buf_tx, buf_rx, true); generate_random_data(buf_tx, true); @@ -405,7 +394,7 @@ static void test_can_loopback(void) write_data(qts, CANFD1_BASE_ADDR, buf_tx, true); send_data(qts, CANFD1_BASE_ADDR); - read_data(qts, CANFD1_BASE_ADDR, buf_rx); + read_data(qts, CANFD1_BASE_ADDR, buf_rx, CANFD_FRAME_SIZE); match_rx_tx_data(buf_tx, buf_rx, true); qtest_quit(qts); From patchwork Tue Jul 4 16:36:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 698966 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2364699wrs; Tue, 4 Jul 2023 09:38:11 -0700 (PDT) X-Google-Smtp-Source: APBJJlEzib/2XAV4YsWx5s58rrEUZQohq1IivM3krhHWyvRtz39znZNgk4JlLQSAYaNHTWZEWnko X-Received: by 2002:a05:620a:404d:b0:767:55ed:8d22 with SMTP id i13-20020a05620a404d00b0076755ed8d22mr12516423qko.25.1688488690992; Tue, 04 Jul 2023 09:38:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688488690; cv=none; d=google.com; s=arc-20160816; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/11] target/arm: gdbstub: Guard M-profile code with CONFIG_TCG Date: Tue, 4 Jul 2023 17:36:32 +0100 Message-Id: <20230704163634.3188465-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Fabiano Rosas This code is only relevant when TCG is present in the build. Building with --disable-tcg --enable-xen on an x86 host we get: $ ../configure --target-list=x86_64-softmmu,aarch64-softmmu --disable-tcg --enable-xen $ make -j$(nproc) ... libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `m_sysreg_ptr': ../target/arm/gdbstub.c:358: undefined reference to `arm_v7m_get_sp_ptr' ../target/arm/gdbstub.c:361: undefined reference to `arm_v7m_get_sp_ptr' libqemu-aarch64-softmmu.fa.p/target_arm_gdbstub.c.o: in function `arm_gdb_get_m_systemreg': ../target/arm/gdbstub.c:405: undefined reference to `arm_v7m_mrs_control' Signed-off-by: Fabiano Rosas Message-id: 20230628164821.16771-1-farosas@suse.de Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/gdbstub.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index 03b17c814f6..f421c5d041c 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -324,6 +324,7 @@ static int arm_gen_dynamic_sysreg_xml(CPUState *cs, int base_reg) return cpu->dyn_sysreg_xml.num; } +#ifdef CONFIG_TCG typedef enum { M_SYSREG_MSP, M_SYSREG_PSP, @@ -481,6 +482,7 @@ static int arm_gen_dynamic_m_secextreg_xml(CPUState *cs, int orig_base_reg) return cpu->dyn_m_secextreg_xml.num; } #endif +#endif /* CONFIG_TCG */ const char *arm_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) { @@ -561,6 +563,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) arm_gen_dynamic_sysreg_xml(cs, cs->gdb_num_regs), "system-registers.xml", 0); +#ifdef CONFIG_TCG if (arm_feature(env, ARM_FEATURE_M) && tcg_enabled()) { gdb_register_coprocessor(cs, arm_gdb_get_m_systemreg, arm_gdb_set_m_systemreg, @@ -575,4 +578,5 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) } #endif } +#endif /* CONFIG_TCG */ } From patchwork Tue Jul 4 16:36:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 698965 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2364683wrs; Tue, 4 Jul 2023 09:38:10 -0700 (PDT) X-Google-Smtp-Source: APBJJlFFq95bMMjQ2DbV9qHzRkL4YKniIW6C+NN4y/QCENjm/J4jDLR9Vv0wuRljhiqJAmUB56R1 X-Received: by 2002:a05:6214:e8e:b0:635:e209:178a with SMTP id hf14-20020a0562140e8e00b00635e209178amr18857186qvb.10.1688488690224; Tue, 04 Jul 2023 09:38:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688488690; cv=none; d=google.com; s=arc-20160816; b=pxvmhLCZ/VPpvR+KyvqzHS8VbLFtbnDELF1sKxA8RWwHAwUua8lM8cEN/hFWXJxVCD 3X9q+e0hTGebs+Rxn7domacGtwhWGYZvO8vRXYGaP2cjJhX14UDqZaTqGc2fiQQuiVeB cc7Wa4IOvlpfhYmp5/lFtklts2sJjtgs1jb8oKkFEar5mQ11LShirRc4Lvh+ve5QtyY3 FoBoFt8j7Ss0HDzSpen6wrDIv6Bxei0E5Nf4vedgs4OH7/hpWTHbjP5LuCSt1DKzKSob W0Suxe/hXnLXtvvCVQGPOnJuRPva3RrKVF0LncmjxAmbJCfvipExrpM34k/PCclROnUC xakA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=ljXuz5WdOwWpxwvCuXAlprlm5SQ6d0e/c1sdlk1yWik=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=m3oCZK0PPyvjImAv4h/0zuZgQTxgy5VhCocMB0/5dYnvIz134GZ6+2cqjHmRfXTpfc enGELMHI4YH6+ajizesZFphweAQk9cJx04KacenwacBSxoMvZSBeBRn0eVbXJ/UktaBG VlzmfmwZvMkA7SQ+oM9lfDLbvUE8RO9iK4eEsgQvNcV0s23eofzzegABtQjoAmBP4oto eS1vi3FxMyVQh1wnQFU373SXHJiU3mYWVk3cBr63xK2bIAEeqp/c0eevw7zpmPXjYrG7 U9QCXGqj4lsjhA4uUDYFfdWN5LhmnRwyj0gciUrpHZo2J5XUNmB7Ld9rY4+F5MYP1Dir dExQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iXQM3l4h; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.39 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:39 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/11] hw: arm: allwinner-sramc: Set class_size Date: Tue, 4 Jul 2023 17:36:33 +0100 Message-Id: <20230704163634.3188465-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Akihiko Odaki AwSRAMCClass is larger than SysBusDeviceClass so the class size must be advertised accordingly. Fixes: 05def917e1 ("hw: arm: allwinner-sramc: Add SRAM Controller support for R40") Signed-off-by: Akihiko Odaki Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Message-id: 20230628110905.38125-1-akihiko.odaki@daynix.com Signed-off-by: Peter Maydell --- hw/misc/allwinner-sramc.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/misc/allwinner-sramc.c b/hw/misc/allwinner-sramc.c index a8b731f8f28..d76c24d081f 100644 --- a/hw/misc/allwinner-sramc.c +++ b/hw/misc/allwinner-sramc.c @@ -159,6 +159,7 @@ static const TypeInfo allwinner_sramc_info = { .parent = TYPE_SYS_BUS_DEVICE, .instance_init = allwinner_sramc_init, .instance_size = sizeof(AwSRAMCState), + .class_size = sizeof(AwSRAMCClass), .class_init = allwinner_sramc_class_init, }; From patchwork Tue Jul 4 16:36:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter Maydell X-Patchwork-Id: 698964 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2364675wrs; Tue, 4 Jul 2023 09:38:09 -0700 (PDT) X-Google-Smtp-Source: APBJJlGsM6GCI9x9bgbCuZXsBR/fntbMlcHxShZnaYQACV9Kc7Bib8DxehLAZabYJaOMw+b9DGnT X-Received: by 2002:ad4:5947:0:b0:635:fa7b:6c1f with SMTP id eo7-20020ad45947000000b00635fa7b6c1fmr16123002qvb.62.1688488689383; Tue, 04 Jul 2023 09:38:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688488689; cv=none; d=google.com; s=arc-20160816; b=GO+YfpB0kMlF4EJ9uXvnTyxakgyPhmvHKtLZ9oiCAEDnri7condp9uKFHnJqY79w9X ICYATrleXj4Y6r3jqGnxgiAJ2fUFpzAJgm9GWzhskhs3Y9woe/5FRzr3cgNxxazlBjfD l6aPkaXeev+sHuIBPPA0yrY5bIq0+60cEz2jtHXMUEoyBfcNQWJ3crH/kTee5upk4Ls+ azAi/UMWZw+IWVsz5iPdOjy31kInLQUBmyp1bL+UxAtGks7cIrHMiz6iST6RkVksbeDj /VLeBsf8BcHtxyD0WWPT7x3iNH8WdYZBzJ7sK98xtW0VMTaAncPZ5QEEHhz6j/xHXWXV YgNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:to:from :dkim-signature; bh=REQxdvHqMD5dtevjQjK3Wnx/HFYuQ118HppndU5qJ5M=; fh=PnYt+qEB9tAfMKoqBm2xjKOFpYyFFGPudh5cVIoieJM=; b=Bh+m/Wl314YSG0U8BfyrXEUE9x1B0qhx0tmLwppj0PFGkCv/c0m7rl3OGmKymhInUK l/ELEZsjCwbNVa208VkzhWL20PIzPxfZICZvlqfhVCYWIZiPWcAJNtoiFeR8PAlgulli qLOhI1Kf18mY79GncFunPtc3K3/E8cPQx7VL2Gp9eOtS5o/+IF7pYTF/OBwGkULY/kBc Qka5GZ/AQQYFYepHKlHGQlyIBvITGmLEGAAL/iod5gdXhBTW1zSFpSzO8f2smD8rP7Uh 1xZFzF6aGL3etJLLCKsQUwds1FgPRX2DuxH3zUGa23/dL3uDg+aPLKkONZmuUfAyhuZQ 9ecw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=CRa2WQ7k; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id r8-20020a056000014800b003143b032b7asm4354258wrx.116.2023.07.04.09.36.40 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Jul 2023 09:36:40 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/11] target/xtensa: Assert that interrupt level is within bounds Date: Tue, 4 Jul 2023 17:36:34 +0100 Message-Id: <20230704163634.3188465-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230704163634.3188465-1-peter.maydell@linaro.org> References: <20230704163634.3188465-1-peter.maydell@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In handle_interrupt() we use level as an index into the interrupt_vector[] array. This is safe because we have checked it against env->config->nlevel, but Coverity can't see that (and it is only true because each CPU config sets its XCHAL_NUM_INTLEVELS to something less than MAX_NLEVELS), so it complains about a possible array overrun (CID 1507131) Add an assert() which will make Coverity happy and catch the unlikely case of a mis-set XCHAL_NUM_INTLEVELS in future. Signed-off-by: Peter Maydell Acked-by: Max Filippov Message-id: 20230623154135.1930261-1-peter.maydell@linaro.org --- target/xtensa/exc_helper.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index d4823a65cda..43f6a862de2 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -169,6 +169,9 @@ static void handle_interrupt(CPUXtensaState *env) CPUState *cs = env_cpu(env); if (level > 1) { + /* env->config->nlevel check should have ensured this */ + assert(level < sizeof(env->config->interrupt_vector)); + env->sregs[EPC1 + level - 1] = env->pc; env->sregs[EPS2 + level - 2] = env->sregs[PS]; env->sregs[PS] =