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[209.51.188.17]) by mx.google.com with ESMTPS id y9-20020a05622a120900b004034fff09cdsi4845219qtx.747.2023.07.04.07.50.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jul 2023 07:50:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Bj/E2EPD"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGhMJ-0003V3-FN; Tue, 04 Jul 2023 10:50:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGhMF-0003UR-HO for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:50:26 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGhMD-0002pL-VH for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:50:23 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3fbc587febfso49972555e9.2 for ; Tue, 04 Jul 2023 07:50:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688482220; x=1691074220; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pk+gpOgsGH8h9nBVWWWI6hEwEfEczbV1bP+WYEKdNPQ=; b=Bj/E2EPDp15WN8r6eDFi/vxSVU7gTqJOmBi3HUoQANyUVl/EO5GP/9tonq7FrvUNNz 5+dfNGXjFzTKYIqrMc3JU9GkF0YbtTQvjKYz6qZrqSpAY1snuc0nDau/eh5NKFp9XuCT CcTF423qll1CdckH5lLSpYZJtlFaMezdddwuzsFJhgO6KENFN7KtDe9veOUAKnzOZ00w uqNAXBwb/LEwbz0R6XLoeLlsXb14lmWdOG9kkKHaB16IaKlR3M/3mJ6eO3ykiSIwIfeN 7SsDDuJjXlP+Rdq2bL/s18s3AU1zfzFlH5XY3KDIC1Ngj5NDAEa9RRevjnHfvGuIMeY0 kR6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688482220; x=1691074220; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pk+gpOgsGH8h9nBVWWWI6hEwEfEczbV1bP+WYEKdNPQ=; b=l8y1UaRnvxA+BiCHdxM14Z+N3v6J/MPhaHxF6hlDrCHYlx/FSboi8ZLeYX0kCrPWFr LrNz6gL5EPahT6hbfVrJcYiznnbvWccdqelyeuINXM3Fp0ouzSge98AOS8im5QtrfDoe pS/JLyH6ppcjkg5pgZDZQcKNBMOBCjzxPIEUXnJ9P3F/lBEsDEqKAN5WVSrsVuTV+sU+ EYgklVn2UTcNxZIZGBX0w+Ht7B+DmDISqYPp3cW+xM6+3daJ1YQxcXWU9cZIwZHaLE1z TvNJHyYuR85SMeb2HnsvL+v/OOIcavva2rWCV2Fg6loB2/763Dv/S9YSH888tX6u7qjm b/eA== X-Gm-Message-State: AC+VfDxx2p+c5McO4h6uZlUvj657VKGcMkXpTzBUt9JbREaYSt+zHKtA WMwWqPHglMTOgNjQ2a0r33646tLTW452XzjUEAA= X-Received: by 2002:a1c:4c10:0:b0:3fa:991c:2af9 with SMTP id z16-20020a1c4c10000000b003fa991c2af9mr10396745wmf.16.1688482220429; Tue, 04 Jul 2023 07:50:20 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id e10-20020a056000194a00b0031134bcdacdsm28630753wry.42.2023.07.04.07.50.19 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:50:20 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 01/19] hw/timer/arm_timer: Declare QOM types using DEFINE_TYPES() macro Date: Tue, 4 Jul 2023 16:49:54 +0200 Message-Id: <20230704145012.49870-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. Replace the type_init() / type_register_static() combination. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 35 +++++++++++++++-------------------- 1 file changed, 15 insertions(+), 20 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 69c8863472..e410b37a23 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -380,13 +380,6 @@ static void icp_pit_init(Object *obj) save themselves. */ } -static const TypeInfo icp_pit_info = { - .name = TYPE_INTEGRATOR_PIT, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(icp_pit_state), - .instance_init = icp_pit_init, -}; - static Property sp804_properties[] = { DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), @@ -402,18 +395,20 @@ static void sp804_class_init(ObjectClass *klass, void *data) k->vmsd = &vmstate_sp804; } -static const TypeInfo sp804_info = { - .name = TYPE_SP804, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(SP804State), - .instance_init = sp804_init, - .class_init = sp804_class_init, +static const TypeInfo arm_timer_types[] = { + { + .name = TYPE_INTEGRATOR_PIT, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(icp_pit_state), + .instance_init = icp_pit_init, + + }, { + .name = TYPE_SP804, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SP804State), + .instance_init = sp804_init, + .class_init = sp804_class_init, + } }; -static void arm_timer_register_types(void) -{ - type_register_static(&icp_pit_info); - type_register_static(&sp804_info); -} - -type_init(arm_timer_register_types) +DEFINE_TYPES(arm_timer_types) From patchwork Tue Jul 4 14:49:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698947 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2314981wrs; Tue, 4 Jul 2023 07:52:28 -0700 (PDT) X-Google-Smtp-Source: APBJJlERXyfZONEYXK9mRa4TqKvMdbt2pjcLGcNMzAFnX3OImjIL4Vump9ADCM8GGV1qw6vYj9lU X-Received: by 2002:a05:620a:2b10:b0:765:6517:1366 with SMTP id do16-20020a05620a2b1000b0076565171366mr12789074qkb.30.1688482347697; Tue, 04 Jul 2023 07:52:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482347; cv=none; d=google.com; s=arc-20160816; b=BfKCSgqcIdAowdFC9/hQZ2tLWdGM71MsI3hlUmo57J0KJmSw6UVsLjWzWq4l2U/Dl6 OSoYjhUTNyWPftd1+y8KW5j+YK5fwcIHrrA8OvScG7W8S7hDI7JKcK/O1SgutI0pO9OI kVdJsJBQWcEid5KmfyoGMxweqkgJNXYK5d0NKOf592ZD7P0lbtTOeiJfe4vYFC3RmAhK SOzwgBm96NnURAT58+t3WaWGQJhoOBjtBZUzohqgnqYOa4fxU2LhhNhNIzRKMN0ap19l e2tlSNAaBgWMjCZeQ0bGY96tm2ogSd4Vu3N5XxlXyO2HN2XsexSYUFfS9vhgLUwjvwP2 mv8Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=rgvgFhMQ/riqnKFVtebpDqRyF4pQ1AQW92hIbSGCdrk=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=tf+wwme8IugMJDxHg8OnO/5LanLVqAbIPDLGzQDDm+nrRpM14Vz7zIFYptC7LQP0RZ WovUr6puE1Rah//Z1uPsgiJ4RPZiczLHFWzehGZdwQJpVjnRJUgUTbDuUYagojHIbBeV E6QvInFnKrLLLpIGReVcTfiIjk1qHXc7q7WbUD9l8qbGmLbe3i1FM83aAXoz4mJJJXz4 pRoQmdo5wYmnuq8qbKxc8PlXl6iJOj6/qacx5KmmaD9orPc2sk64uB3exjh7D3BJadbI lo6Yb/aOmzXWBsRHYEBhOdIr0RKLv4dBO1BgOlgX+bTFkmL1zWmdXLmalxhym2EA/yaN xmNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cmdzf5TX; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Tue, 04 Jul 2023 07:50:25 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 02/19] hw/timer/arm_timer: Remove pointless cast from void * Date: Tue, 4 Jul 2023 16:49:55 +0200 Message-Id: <20230704145012.49870-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index e410b37a23..30a34a9a92 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -52,7 +52,7 @@ static void arm_timer_update(arm_timer_state *s) static uint32_t arm_timer_read(void *opaque, hwaddr offset) { - arm_timer_state *s = (arm_timer_state *)opaque; + arm_timer_state *s = opaque; switch (offset >> 2) { case 0: /* TimerLoad */ @@ -99,7 +99,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload) static void arm_timer_write(void *opaque, hwaddr offset, uint32_t value) { - arm_timer_state *s = (arm_timer_state *)opaque; + arm_timer_state *s = opaque; int freq; switch (offset >> 2) { @@ -154,7 +154,7 @@ static void arm_timer_write(void *opaque, hwaddr offset, static void arm_timer_tick(void *opaque) { - arm_timer_state *s = (arm_timer_state *)opaque; + arm_timer_state *s = opaque; s->int_level = 1; arm_timer_update(s); } @@ -214,7 +214,7 @@ static const uint8_t sp804_ids[] = { /* Merge the IRQs from the two component devices. */ static void sp804_set_irq(void *opaque, int irq, int level) { - SP804State *s = (SP804State *)opaque; + SP804State *s = opaque; s->level[irq] = level; qemu_set_irq(s->irq, s->level[0] || s->level[1]); @@ -223,7 +223,7 @@ static void sp804_set_irq(void *opaque, int irq, int level) static uint64_t sp804_read(void *opaque, hwaddr offset, unsigned size) { - SP804State *s = (SP804State *)opaque; + SP804State *s = opaque; if (offset < 0x20) { return arm_timer_read(s->timer[0], offset); @@ -255,7 +255,7 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, static void sp804_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - SP804State *s = (SP804State *)opaque; + SP804State *s = opaque; if (offset < 0x20) { arm_timer_write(s->timer[0], offset, value); @@ -324,7 +324,7 @@ struct icp_pit_state { static uint64_t icp_pit_read(void *opaque, hwaddr offset, unsigned size) { - icp_pit_state *s = (icp_pit_state *)opaque; + icp_pit_state *s = opaque; int n; /* ??? Don't know the PrimeCell ID for this device. */ @@ -340,7 +340,7 @@ static uint64_t icp_pit_read(void *opaque, hwaddr offset, static void icp_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - icp_pit_state *s = (icp_pit_state *)opaque; + icp_pit_state *s = opaque; int n; n = offset >> 8; From patchwork Tue Jul 4 14:49:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698939 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2314599wrs; Tue, 4 Jul 2023 07:51:21 -0700 (PDT) X-Google-Smtp-Source: APBJJlHBE6NMKnka0LSrK2oSj0MasTLXes5aFHkAW4/9eQ2ZWhYIaaw0JWuaqB2lwnrK1nSuQu6r X-Received: by 2002:a05:6214:2624:b0:634:3994:13e0 with SMTP id gv4-20020a056214262400b00634399413e0mr18147801qvb.18.1688482280827; Tue, 04 Jul 2023 07:51:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482280; cv=none; d=google.com; s=arc-20160816; b=iTvQWa6Ily5O3K53m7QvLrFkO3F5Glk0zldwUX6RYdJFz70meSH3bzDidxTxw4ElYw 63C30FT5i3tvSVPIbmU0jXtxQN7MaeY7Gog3BY7qlQFgTWhdT+kOcq+aZCRO+oin9jms ToW3bX0/wnKvEz2DJpo0/owN95fwX8zKGrZtKtkLEY7IiVoPKeqRwPi8q8SNh3BMvOwE sUefthrEX5CIVpwspYzPgw+hN9kmX19xRy8605YtFc0+WOWMFgOKLFQ89NnQXIZgArtc qfpdNTgxq9KvMyUtSXOg9hS3YuZu08cgaq2/ej5sUuAhWgMBxdHJ/CfjZ9DOBCPVT785 Tx8A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=UhMO8Q1jA2bR32jdxudf4HkyOq0yWx3SI4nwIyth1l8=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=mw3Y1BYlUGruLnVruaI5LeV0hOFd0KYqDUgnn5qxHtoHj9tAehijJdbFgM1JNbvw4w 79+VhX97pnOMvUAPgF/D9SMD4zP0DTHV55NiOQXn9xU7XIpAwMWreHgGCE8KzQjlQLun lf+wnl2SS6+v1F9s84ctD2ZNnkBEDo4rEoARqh/AuubV2IoloDBuhLW/Uo/yFfCp562J gT4BIJNHCNSJKRnzbDH945/QSPrAI5uO6lLuu7QpGYo2Vbudjfy636Fzte1GWHkewueu R0OMuJvUDjGCENbUPjj5c3ZMSS9KpYLmDO0qVcx/lHXFv8jEsBwEzQuujn5DOGn1BEMq /IWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IBTtopKG; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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What follows the "Integrator/CP timer module." is strictly ICP related. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 30a34a9a92..0e5d5d0f6d 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -309,6 +309,21 @@ static void sp804_realize(DeviceState *dev, Error **errp) s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); } +static Property sp804_properties[] = { + DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), + DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sp804_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *k = DEVICE_CLASS(klass); + + k->realize = sp804_realize; + device_class_set_props(k, sp804_properties); + k->vmsd = &vmstate_sp804; +} + /* Integrator/CP timer module. */ #define TYPE_INTEGRATOR_PIT "integrator_pit" @@ -380,21 +395,6 @@ static void icp_pit_init(Object *obj) save themselves. */ } -static Property sp804_properties[] = { - DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), - DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), - DEFINE_PROP_END_OF_LIST(), -}; - -static void sp804_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *k = DEVICE_CLASS(klass); - - k->realize = sp804_realize; - device_class_set_props(k, sp804_properties); - k->vmsd = &vmstate_sp804; -} - static const TypeInfo arm_timer_types[] = { { .name = TYPE_INTEGRATOR_PIT, From patchwork Tue Jul 4 14:49:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698941 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2314677wrs; Tue, 4 Jul 2023 07:51:32 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5nQUk28vzwnwI9/axU5FGyE5QaDLXoX2URiwIxxoZkpxX9tUzqnh1yrctAy+QqIPqIgdJB X-Received: by 2002:a05:622a:1910:b0:403:35b7:c030 with SMTP id w16-20020a05622a191000b0040335b7c030mr16216361qtc.59.1688482291907; Tue, 04 Jul 2023 07:51:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482291; cv=none; d=google.com; s=arc-20160816; b=Wsf8wGnW2e97IeI0ptXdyiAYVvSBphCw02TQRojmhMzNkhFtLjayJjEtUM42k2gXIP qv2zzbtMT+icGobupnWtj6E8tCjdILiNp3Ek6mdMiBgwSRn4LNAeKqtvLbPvx8r7VtwI hcxvZeAka3q6Be91riOkyYR+s5fRfb7A+Zj/Lsr6ZT0XpefAeAFpZRS24AQAfOIlsett if16qD8G8GhJDa5n5qXx2Lrgjf7QNAkdekm0QzotkdlZ/Yv9zFzEb9tF4PeU/GM7t3Il AYIZC9OlJoUCHJ+pEhzRMSQve8xzch5L6kHEZPFgZgluGZYzsApLdrTTJg2lLrQn90Er QHBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gOIzLPOnHecDCNWW1WAVm9BTrVEQSroQYADUt2FEwKw=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=cTq+ltBniSEm2gvRJtxS71rFHvhGEP10jme/D2egHAFZK9Sdi1k/OUf4nl83ygWtol 0shaDh4iHZej5v7qo/cxYqTSp1OzvjCw/5UpGJESLmcYSWc2rAZeymQ2WkRymNPLsY4m //lWBm73qVdaA1RWlNyGtW8qqnIuHiGBFgB2JXNvbyvJNkBcs+0x190IaxMufen4MWeZ AteW7eNbyiSh//kjPecOMzzDyCTtooZRCptoljj0tDkJoLLWmbz3avXgVy2FCi5oM+Qs l1G4Y7WnQ/cODDp1O3Z6OvCi9sKpQdKSqZ2p45XiFukcmXu1AEN0lxw4rKVhJNUAnkR+ iAVw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tLJM0vQs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w12-20020ac857cc000000b003f69abc8e60si13352758qta.339.2023.07.04.07.51.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jul 2023 07:51:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tLJM0vQs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGhN6-00049z-80; Tue, 04 Jul 2023 10:51:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGhMe-0003nP-Gt for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:50:49 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGhMU-0002zJ-3h for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:50:43 -0400 Received: by mail-wr1-x42b.google.com with SMTP id ffacd0b85a97d-307d20548adso6297784f8f.0 for ; Tue, 04 Jul 2023 07:50:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688482235; x=1691074235; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gOIzLPOnHecDCNWW1WAVm9BTrVEQSroQYADUt2FEwKw=; b=tLJM0vQsru0+TU+0rZ7SyswPc2vgJ3H4a72Qg9FG0tQi+6YnROEc3BpPB3APRt4pJn TfA/XghcUuNHaoGwW1bdvaUn4SxUo5+3/gU17iSqNyDk5xTJjE5j3bJvZqdacQtlfjZY ZN7nbzcEqOlKtTol12hja8+VEOYuPwj94YGDqaWm4uI9cKIA5q6KAtPFQrcm/cEqFY45 v9GGllsTQrF8BAIeGnKpC++/Frx+JsRtxf1EAlnuN8uNY8WURZRdy+eOMFMzIHi7b+hF hwSghL2JaF14NUYjYOWRVAoCGsMkahe+CKaOuDKufjO66MO7rdk+T28p34aMM/c0nqi0 cgBg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688482235; x=1691074235; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gOIzLPOnHecDCNWW1WAVm9BTrVEQSroQYADUt2FEwKw=; b=V0TrID2xYqi1HicR+jA+fzU9HDd4n2WQIGJx6R/+m8FsszAGDnmxk2jJuGZ+rjWQ7b f3tMy88SAoiCT8sy1lM21OdJkg52u5NeJ42HXP6xtiCcBqk8sVM0aXk2tVqB6BLazRwH lcCYRrrPQaEd5aNG14zeD61B5G38aOuvJilMBnDkPbVROf7vu7PJ0n/r758CV0nWMdB5 dc/7L/fbMuE9khhofhTZmMokKugL2dKHC9b16K3PHYqIYlVawgZCWZViYfwobmBew3qu 8wpCXuQgMSoV6lJee8PlXMHC49Kiz9l4+pvSu/K2gjgmKO6Am+p+E1rCRYJxSrNeFn3r u9GQ== X-Gm-Message-State: ABy/qLYfvNT2AAPy3zwIZ5SAuRGwoCRqKg4ejwRK2KDSKCish4sla8mv 0KKKhaZ0zM3n8PNr5fMCxKCkDHYqit9+Hk72U+4= X-Received: by 2002:adf:fe02:0:b0:307:8c47:a266 with SMTP id n2-20020adffe02000000b003078c47a266mr9066354wrr.61.1688482235763; Tue, 04 Jul 2023 07:50:35 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id h9-20020adff189000000b003143c532431sm3293979wro.27.2023.07.04.07.50.34 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:50:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 04/19] hw/timer/arm_timer: CamelCase rename icp_pit_state -> IntegratorPIT Date: Tue, 4 Jul 2023 16:49:57 +0200 Message-Id: <20230704145012.49870-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=philmd@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Following docs/devel/style.rst guidelines, rename icp_pit_state using CamelCase as IntegratorPIT (PIT is an acronym). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 0e5d5d0f6d..c741e89cb4 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -327,9 +327,9 @@ static void sp804_class_init(ObjectClass *klass, void *data) /* Integrator/CP timer module. */ #define TYPE_INTEGRATOR_PIT "integrator_pit" -OBJECT_DECLARE_SIMPLE_TYPE(icp_pit_state, INTEGRATOR_PIT) +OBJECT_DECLARE_SIMPLE_TYPE(IntegratorPIT, INTEGRATOR_PIT) -struct icp_pit_state { +struct IntegratorPIT { SysBusDevice parent_obj; MemoryRegion iomem; @@ -339,7 +339,7 @@ struct icp_pit_state { static uint64_t icp_pit_read(void *opaque, hwaddr offset, unsigned size) { - icp_pit_state *s = opaque; + IntegratorPIT *s = opaque; int n; /* ??? Don't know the PrimeCell ID for this device. */ @@ -355,7 +355,7 @@ static uint64_t icp_pit_read(void *opaque, hwaddr offset, static void icp_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - icp_pit_state *s = opaque; + IntegratorPIT *s = opaque; int n; n = offset >> 8; @@ -375,7 +375,7 @@ static const MemoryRegionOps icp_pit_ops = { static void icp_pit_init(Object *obj) { - icp_pit_state *s = INTEGRATOR_PIT(obj); + IntegratorPIT *s = INTEGRATOR_PIT(obj); SysBusDevice *dev = SYS_BUS_DEVICE(obj); /* Timer 0 runs at the system clock speed (40MHz). */ @@ -399,7 +399,7 @@ static const TypeInfo arm_timer_types[] = { { .name = TYPE_INTEGRATOR_PIT, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(icp_pit_state), + .instance_size = sizeof(IntegratorPIT), .instance_init = icp_pit_init, }, { From patchwork Tue Jul 4 14:49:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698942 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2314714wrs; Tue, 4 Jul 2023 07:51:39 -0700 (PDT) X-Google-Smtp-Source: APBJJlFX1KbIDu7aeVZSseU1aYVvQ3XusYwb3S+rwUOC7odnYDIjkIjzgCeAFgElJa56cCQoIIdH X-Received: by 2002:ac8:5cc6:0:b0:400:829e:c395 with SMTP id s6-20020ac85cc6000000b00400829ec395mr15960661qta.6.1688482298911; Tue, 04 Jul 2023 07:51:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482298; cv=none; d=google.com; s=arc-20160816; b=e8CQf23AaqLpwtkp5AEnmexBPA1x0j/qRVuyjt82kJp313BNhDQ/Xq2eOncchvvVg1 MVWUN4OsXwECLDZl0n3nieB8g+EoQqf1nU/QytuX9Takm3rTnnlgqj0KtpsaP2mMQ4Ik nru8yqIKxHn2lNtVgcbrg7zp27CmQKRFHkNWmu6UW6LKoAxT/Jz5gr4fXMIGxVKflPGs vJkkiobfhaFAfPurECkL8CTfkks8ev5qDbpCrrk5C1LfMq/Lc1O2lxhZJfYZUqXKT5CS 7BSf0XzHVFwyqnxP4PwKdgRWXW8AWJyqRLN4xGoqaFEDSQ2biaANVYLjOguR5Jz0pw/v pU4A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8Y5uqlDug0UobussbvEXXtJ8MTJBYQAz+WAikQsGjjQ=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=oj3Lwcn3tNWnNvyKXR4sJ9+KaO5fYrjr1wjK9sje4Rx5IUVHMMCHryHZfmUcyR8nqa 425K7iGrmi/YP2W2q/hcUUupsAMPO7zD0NlZhKsUCgGjB6DoaTbG8aFxINKW6b2uXTig JWzhxt/VHZdAkQeh+XPboeW8BFWmmWDWhqPI40LRjIWZNy5R+1+BhET01lOcbK98okTi JLT9tg691kwqjuiiCKruYohQg5YIbzGdxz713abizHJWSc5W+USQ2fXbtOOrgHufb/DV V1myT05kXHc52bb2RQL/6HBrykCTl4OGRo2bGWSVqYhp7LmP+K3uSHb9eIGoTurhJwQZ fQyw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=o6pc1i4a; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index c741e89cb4..8a2939483f 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -36,11 +36,11 @@ typedef struct { int freq; int int_level; qemu_irq irq; -} arm_timer_state; +} ArmTimer; /* Check all active timers, and schedule the next timer interrupt. */ -static void arm_timer_update(arm_timer_state *s) +static void arm_timer_update(ArmTimer *s) { /* Update interrupts. */ if (s->int_level && (s->control & TIMER_CTRL_IE)) { @@ -52,7 +52,7 @@ static void arm_timer_update(arm_timer_state *s) static uint32_t arm_timer_read(void *opaque, hwaddr offset) { - arm_timer_state *s = opaque; + ArmTimer *s = opaque; switch (offset >> 2) { case 0: /* TimerLoad */ @@ -79,7 +79,7 @@ static uint32_t arm_timer_read(void *opaque, hwaddr offset) * Reset the timer limit after settings have changed. * May only be called from inside a ptimer transaction block. */ -static void arm_timer_recalibrate(arm_timer_state *s, int reload) +static void arm_timer_recalibrate(ArmTimer *s, int reload) { uint32_t limit; @@ -99,7 +99,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload) static void arm_timer_write(void *opaque, hwaddr offset, uint32_t value) { - arm_timer_state *s = opaque; + ArmTimer *s = opaque; int freq; switch (offset >> 2) { @@ -154,7 +154,7 @@ static void arm_timer_write(void *opaque, hwaddr offset, static void arm_timer_tick(void *opaque) { - arm_timer_state *s = opaque; + ArmTimer *s = opaque; s->int_level = 1; arm_timer_update(s); } @@ -164,19 +164,19 @@ static const VMStateDescription vmstate_arm_timer = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_UINT32(control, arm_timer_state), - VMSTATE_UINT32(limit, arm_timer_state), - VMSTATE_INT32(int_level, arm_timer_state), - VMSTATE_PTIMER(timer, arm_timer_state), + VMSTATE_UINT32(control, ArmTimer), + VMSTATE_UINT32(limit, ArmTimer), + VMSTATE_INT32(int_level, ArmTimer), + VMSTATE_PTIMER(timer, ArmTimer), VMSTATE_END_OF_LIST() } }; -static arm_timer_state *arm_timer_init(uint32_t freq) +static ArmTimer *arm_timer_init(uint32_t freq) { - arm_timer_state *s; + ArmTimer *s; - s = g_new0(arm_timer_state, 1); + s = g_new0(ArmTimer, 1); s->freq = freq; s->control = TIMER_CTRL_IE; @@ -198,7 +198,7 @@ struct SP804State { SysBusDevice parent_obj; MemoryRegion iomem; - arm_timer_state *timer[2]; + ArmTimer *timer[2]; uint32_t freq0, freq1; int level[2]; qemu_irq irq; @@ -333,7 +333,7 @@ struct IntegratorPIT { SysBusDevice parent_obj; MemoryRegion iomem; - arm_timer_state *timer[3]; + ArmTimer *timer[3]; }; static uint64_t icp_pit_read(void *opaque, hwaddr offset, From patchwork Tue Jul 4 14:49:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698948 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2315005wrs; Tue, 4 Jul 2023 07:52:31 -0700 (PDT) X-Google-Smtp-Source: APBJJlHSul8Pf8byzki9FQrj1xt4TmqUDyXuYHS2dQvK/aRtULOMFS6PTjq8/qDWhsOmnP55BG50 X-Received: by 2002:ad4:438a:0:b0:628:74d6:ba89 with SMTP id s10-20020ad4438a000000b0062874d6ba89mr12648670qvr.60.1688482351144; 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Suggested-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 8a2939483f..41045de8ed 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -192,9 +192,9 @@ static ArmTimer *arm_timer_init(uint32_t freq) */ #define TYPE_SP804 "sp804" -OBJECT_DECLARE_SIMPLE_TYPE(SP804State, SP804) +OBJECT_DECLARE_SIMPLE_TYPE(SP804Timer, SP804) -struct SP804State { +struct SP804Timer { SysBusDevice parent_obj; MemoryRegion iomem; @@ -214,7 +214,7 @@ static const uint8_t sp804_ids[] = { /* Merge the IRQs from the two component devices. */ static void sp804_set_irq(void *opaque, int irq, int level) { - SP804State *s = opaque; + SP804Timer *s = opaque; s->level[irq] = level; qemu_set_irq(s->irq, s->level[0] || s->level[1]); @@ -223,7 +223,7 @@ static void sp804_set_irq(void *opaque, int irq, int level) static uint64_t sp804_read(void *opaque, hwaddr offset, unsigned size) { - SP804State *s = opaque; + SP804Timer *s = opaque; if (offset < 0x20) { return arm_timer_read(s->timer[0], offset); @@ -255,7 +255,7 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, static void sp804_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - SP804State *s = opaque; + SP804Timer *s = opaque; if (offset < 0x20) { arm_timer_write(s->timer[0], offset, value); @@ -283,14 +283,14 @@ static const VMStateDescription vmstate_sp804 = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_INT32_ARRAY(level, SP804State, 2), + VMSTATE_INT32_ARRAY(level, SP804Timer, 2), VMSTATE_END_OF_LIST() } }; static void sp804_init(Object *obj) { - SP804State *s = SP804(obj); + SP804Timer *s = SP804(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); sysbus_init_irq(sbd, &s->irq); @@ -301,7 +301,7 @@ static void sp804_init(Object *obj) static void sp804_realize(DeviceState *dev, Error **errp) { - SP804State *s = SP804(dev); + SP804Timer *s = SP804(dev); s->timer[0] = arm_timer_init(s->freq0); s->timer[1] = arm_timer_init(s->freq1); @@ -310,8 +310,8 @@ static void sp804_realize(DeviceState *dev, Error **errp) } static Property sp804_properties[] = { - DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), - DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), + DEFINE_PROP_UINT32("freq0", SP804Timer, freq0, 1000000), + DEFINE_PROP_UINT32("freq1", SP804Timer, freq1, 1000000), DEFINE_PROP_END_OF_LIST(), }; @@ -405,7 +405,7 @@ static const TypeInfo arm_timer_types[] = { }, { .name = TYPE_SP804, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(SP804State), + .instance_size = sizeof(SP804Timer), .instance_init = sp804_init, .class_init = sp804_class_init, } From patchwork Tue Jul 4 14:50:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698943 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2314734wrs; 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 41045de8ed..8dae845998 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -191,8 +191,8 @@ static ArmTimer *arm_timer_init(uint32_t freq) * https://developer.arm.com/documentation/ddi0271/latest/ */ -#define TYPE_SP804 "sp804" -OBJECT_DECLARE_SIMPLE_TYPE(SP804Timer, SP804) +#define TYPE_SP804_TIMER "sp804" +OBJECT_DECLARE_SIMPLE_TYPE(SP804Timer, SP804_TIMER) struct SP804Timer { SysBusDevice parent_obj; @@ -290,7 +290,7 @@ static const VMStateDescription vmstate_sp804 = { static void sp804_init(Object *obj) { - SP804Timer *s = SP804(obj); + SP804Timer *s = SP804_TIMER(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); sysbus_init_irq(sbd, &s->irq); @@ -301,7 +301,7 @@ static void sp804_init(Object *obj) static void sp804_realize(DeviceState *dev, Error **errp) { - SP804Timer *s = SP804(dev); + SP804Timer *s = SP804_TIMER(dev); s->timer[0] = arm_timer_init(s->freq0); s->timer[1] = arm_timer_init(s->freq1); @@ -403,7 +403,7 @@ static const TypeInfo arm_timer_types[] = { .instance_init = icp_pit_init, }, { - .name = TYPE_SP804, + .name = TYPE_SP804_TIMER, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(SP804Timer), .instance_init = sp804_init, From patchwork Tue Jul 4 14:50:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698945 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2314938wrs; Tue, 4 Jul 2023 07:52:20 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7lBANfDj9b6fHXjLuTlBgQE0qlshR7taNSfxNP9z3MAVR8zLco7uBT09P+KS3BGJ5Nx4si X-Received: by 2002:ac8:5c56:0:b0:3f4:dec2:76cc with SMTP id j22-20020ac85c56000000b003f4dec276ccmr18231785qtj.49.1688482340577; Tue, 04 Jul 2023 07:52:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482340; cv=none; d=google.com; s=arc-20160816; b=nnnoaQ5vQLYXfHxalmgcUh7Jc/f3HZS3BUoxtDHgP1kRdlHlfSHJ9bfK89hba13RQv lNLf6+SMQ8TYyUiLFcnZ6p/84eGqNRUpIMnNwyPEorD2GLwze4BLLKspuzlVB66QgfKm mpetYMDlN/JuaA3X7SFMKZWqica18x+9dA2JlQWOf/SzHMf1MXp/+utIEAtQFBMzSgSc 3FGKnhlsQJd8CxLLakV3bmUXZtq4I+IanLJKpvEecSP+VApCt+XriJxNfU//RaNnEIfm S7SOASCN+uh/MFIKK+ON3Hhaa4UaR7Tq9DjYN49X60EX1swYea5MetP3ljuaKqW6pULH XsgQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dgWYaksSJaOtaePi8Z6uVzlBPseEZMVW7Vioeltdwwg=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=Vj56YYwTDIScC/K6dtxMhZ2fw8R6gmpAt/ZeyxFJ3/Gco9KrPXgh1+Lt3dXvzjvY60 WxNIM9rY8I1/yNVxsCkSosMVRfk7foFi6csQ3He/++hKw1wQORrt/QZd4RTTljK4IXEm 6tIZJqSElVeAglpBk85Q+d81Qn6iC4IfK6yGlV9dkTTR/LvcE+h1E/E8LUfVWtIgBXvk TIRgW2fAbpMCqD5HcrZmlmy7zuiTvpbpSGHprZLl5xGNHOO3tS+XEFyp+DZRwrQP66WF KXks9pXSyWM6QB/od+StwJabR8hf0AWOClYb9c25wCJoNxmkzRJuCrwrGid+uNzgBg6c Odww== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lkAdqkx6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q11-20020a05622a030b00b0040366e73423si54491qtw.530.2023.07.04.07.52.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jul 2023 07:52:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lkAdqkx6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGhNH-0004df-Tg; Tue, 04 Jul 2023 10:51:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGhMs-0004AL-8v for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:11 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGhMo-00035j-8z for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:01 -0400 Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3143b70d6easo1844610f8f.2 for ; Tue, 04 Jul 2023 07:50:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688482256; x=1691074256; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dgWYaksSJaOtaePi8Z6uVzlBPseEZMVW7Vioeltdwwg=; b=lkAdqkx653X4o9NMfbfuxXpqzYhzCsDeI2xC9GFs59Ec1kHZggnAe4xQW0aUPyma01 OrFHMnGFq7Qzm7HjHPmUGU3MhRpc3IssBFA4GyI14PUdKodRoLtLPRTq4sL234fGdxe6 8NOESHFt8DT9pYTiQFuVpLami0HE+PfHWdbQVQOihe8z5cl60mLG4xKVH5oNWz4b6am9 ckfKJ/aNlrx7baamol6TweP86vjBw9x9h/3oZ07GZAIYFQT8XjA57qQxJ5WuHFeyBIJN AC6BWIKmmIC7BVH+IWO1bVs2GXtrORlJFAes0EyUBMcdcbt0ot7x3Wa9h0w8zyQzjG+q F8iQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688482256; x=1691074256; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dgWYaksSJaOtaePi8Z6uVzlBPseEZMVW7Vioeltdwwg=; b=e6gHQCjApemIqW6H09pNEnf4KcVvGhiV8T7scndBEec3E3Vp1qsYBMGW0MIKAqzPmj +xKlR++QvplCdvAWItVqEesoEAVfqWrJvmUmwq8C4IdbTQlmk4riqeBNC0q1/Q0CXMTc hvdOYwLf6Nmog/vWFE3lg4FWrifyMzC2RM8qdQlhhw4PCdKUa9XPmvH614twTiYejIG0 I7dH6qr+v2oUCrbifOL72kF4t8IcY77yrBE3B/T8k0mqSEKTd79YaNVdGOHNyI1slbkm WJAB5Qm89aQUojpPDg+K7b2tXvXb7p6Gitv1sTbgvsmM7/q2PrmXqEUEDDeZ7H/MwAll 1TGg== X-Gm-Message-State: ABy/qLaJ0EaYHOQclqbKTBxYgkyAMmceqdffToNNkvj0gzl3TJVMHZ8M 8MKwMPJOnY/JXElR0XH/2gKCJC1of0bIMvnY74M= X-Received: by 2002:adf:eb8c:0:b0:314:2ba3:15dd with SMTP id t12-20020adfeb8c000000b003142ba315ddmr8043553wrn.16.1688482256402; Tue, 04 Jul 2023 07:50:56 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id x8-20020a5d4908000000b0031432c2fb95sm7226101wrq.88.2023.07.04.07.50.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:50:56 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 08/19] hw/timer/arm_timer: Extract arm_timer_reset_hold() Date: Tue, 4 Jul 2023 16:50:01 +0200 Message-Id: <20230704145012.49870-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Extract arm_timer_reset_hold() before converting this model to QOM/QDev in few commits. This will become our ResettableHoldPhase handler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 8dae845998..0d7fac4d78 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -172,13 +172,20 @@ static const VMStateDescription vmstate_arm_timer = { } }; +static void arm_timer_reset_hold(ArmTimer *s) +{ + s->limit = 0; + s->int_level = 0; + s->control = TIMER_CTRL_IE; +} + static ArmTimer *arm_timer_init(uint32_t freq) { ArmTimer *s; s = g_new0(ArmTimer, 1); s->freq = freq; - s->control = TIMER_CTRL_IE; + arm_timer_reset_hold(s); s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_LEGACY); vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_arm_timer, s); From patchwork Tue Jul 4 14:50:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698953 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2315169wrs; Tue, 4 Jul 2023 07:52:55 -0700 (PDT) X-Google-Smtp-Source: APBJJlEBmVnFmUUjSgho8SsdMVsZQBtvhXYzqpKkpp1w2EQO/l5h8zFGvXP+7ZuqGXH2a57KWFyM X-Received: by 2002:a05:620a:3905:b0:75b:23a0:deb7 with SMTP id qr5-20020a05620a390500b0075b23a0deb7mr16057577qkn.53.1688482375292; Tue, 04 Jul 2023 07:52:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482375; cv=none; d=google.com; s=arc-20160816; b=D0xNx9GwqDG6cggZh9Z7EKbehmjeh1KrQk+6YLpRqxUkVtY6h07KSDhtt5kmyPayN2 JdAj0W3Ia4R/8yHf/OK5dTR+vb4jT/N92ri45bRCV4LYHhIVZV9W+apdO4VVmgreZ5Fg RQ9Bkv+NOk9tl0pAhxb1aR+/kvakcK1NuoVJsmYz7iUacCAYVRH7Cz8IN1I3FPTxElOv TOOpzkCLu8Fb7qske0pwS1gCt0rBjPmN9dPNet3t/ef5QHP0WhLY865/tPBRPQojwwgj tTWuAvJtRABLeXxDIXL5ytnxvrkGCd9OV+iYhGb65FJa7jtlKWIdw3apY9AL/+v0eB63 G2DQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vDbZi+FugjgWhilKkMiEZjysEFMTjfONCoSIxxTN6sY=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=rEdq18NXS+3TdjpX2fTwxWxA4t2SgwJoGyL/aF/aa31rrqnEAEptw17R8AyE9LZEhk ypF33L3kTVUNOK/AEiiOobcKS143sx6JednRD5pfDnqGzOlvgVPnpuYN5fkgigZT7Np4 seLL62dhDiLCL4M4FaIvImBvsEH5dQ1D1vC1I1Zdv7BQzGjKE8jiQ8CnnGOsIBsSOf6r uLdpB2tLCmk8f+7XXWBOmc7xmb0gBJMVwW7grzClG0kOCLkidC2QPdn64GOwW9QUUvjv JUjjf0BwA4v6osWUEK2h1THEOK0NwISqZmmhUl/YCkne6xcq8oCaHl+vLjwDlnCxD+Vt SdCg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cf31yA0r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id qz6-20020a05620a8c0600b0075ceb12a254si10613255qkn.16.2023.07.04.07.52.55 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jul 2023 07:52:55 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Cf31yA0r; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGhNH-0004cn-Nl; Tue, 04 Jul 2023 10:51:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGhMw-0004CQ-6V for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:12 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGhMt-00036p-75 for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:05 -0400 Received: by mail-wr1-x42f.google.com with SMTP id ffacd0b85a97d-313f1085ac2so6334781f8f.1 for ; Tue, 04 Jul 2023 07:51:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688482261; x=1691074261; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vDbZi+FugjgWhilKkMiEZjysEFMTjfONCoSIxxTN6sY=; b=Cf31yA0rPCjRrlKVGtc1E7y9DsccYWcUESQjyLath1r2cZniaPx3hntbzaqVcsGwna 8vPKoruKH5ImwitIN/gfVxOQfTttNiSeOcGAD5d2V6GffczXEOg8VcXzR/CLHXBcj4Ew EOj4m7vRMfiOfM+o57OEqfllLZNrOedU6bzV0r7ohxoNVydF+J4DfwIaNntJaowFCRqE e9tYLqi2ipjgqoZCbZ/PLXHSDLvWbC59Yb8TgGaECtFDPBPYUQEhIxmLWPpdK13Lg4bJ zyEOjqMXBba8k5seb8Yw0/pHnal7nBGyb2BuAMuyUxNoWx4E/U47wqNSfmb7h7xmmmz6 tAyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688482261; x=1691074261; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vDbZi+FugjgWhilKkMiEZjysEFMTjfONCoSIxxTN6sY=; b=TISdcERJFJvq20UHzv22rCDz3X1WHNrYK998z3sxkLfbl+BbDE1jNepXD6MNQrbDpq MuRyRiS/m4aNylxdYo7YQe4AE0KwzTxHNeI6oId11gSYoE+fl4/0klJ0FW4tgyYbrkgJ NfqjVp0N9FWxRsFpHlqYfbpZoUYF4FHMB/bf0q3rhJZrrSzMnW6UX2jaLEjdTzq8CRk8 LQOUkMDkmKfrLE8xVhc61sp+y+c4eKX/KepiEYHemGbg4YdmBLZ63xChKxsZxZq4lfdG 7kNgUXE6UsM+/8UNmpMn1WdS+Czsyd6MFXGW48TM7U8eCuKua0Y72SRPoAfKH+DQlM+3 IPWA== X-Gm-Message-State: ABy/qLZ4xka6+Uy2QbdTfG2LoljZCDbo1XLqw0Dv/5Xa2NKtBRJgn5RY LD8gi4Lf/3cDlFsLUAhaSYHW3GGVb8MQdbyER3k= X-Received: by 2002:adf:ef4e:0:b0:314:25c6:7f6d with SMTP id c14-20020adfef4e000000b0031425c67f6dmr10401009wrp.14.1688482261685; Tue, 04 Jul 2023 07:51:01 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id e17-20020a5d5951000000b00313f61889ecsm22420188wri.66.2023.07.04.07.51.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:51:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 09/19] hw/timer/arm_timer: Convert read/write handlers to MemoryRegionOps ones Date: Tue, 4 Jul 2023 16:50:02 +0200 Message-Id: <20230704145012.49870-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=philmd@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In order to simplify the QOM convertion of ARM_TIMER in a few commits, start converting the read/write() handlers to follow the MemoryRegionOps::read/write() prototypes. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 0d7fac4d78..cbd82e8365 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -50,7 +50,7 @@ static void arm_timer_update(ArmTimer *s) } } -static uint32_t arm_timer_read(void *opaque, hwaddr offset) +static uint64_t arm_timer_read(void *opaque, hwaddr offset, unsigned size) { ArmTimer *s = opaque; @@ -97,7 +97,7 @@ static void arm_timer_recalibrate(ArmTimer *s, int reload) } static void arm_timer_write(void *opaque, hwaddr offset, - uint32_t value) + uint64_t value, unsigned size) { ArmTimer *s = opaque; int freq; @@ -233,10 +233,10 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, SP804Timer *s = opaque; if (offset < 0x20) { - return arm_timer_read(s->timer[0], offset); + return arm_timer_read(&s->timer[0], offset, size); } if (offset < 0x40) { - return arm_timer_read(s->timer[1], offset - 0x20); + return arm_timer_read(&s->timer[1], offset - 0x20, size); } /* TimerPeriphID */ @@ -265,12 +265,12 @@ static void sp804_write(void *opaque, hwaddr offset, SP804Timer *s = opaque; if (offset < 0x20) { - arm_timer_write(s->timer[0], offset, value); + arm_timer_write(&s->timer[0], offset, value, size); return; } if (offset < 0x40) { - arm_timer_write(s->timer[1], offset - 0x20, value); + arm_timer_write(&s->timer[1], offset - 0x20, value, size); return; } @@ -356,7 +356,7 @@ static uint64_t icp_pit_read(void *opaque, hwaddr offset, return 0; } - return arm_timer_read(s->timer[n], offset & 0xff); + return arm_timer_read(&s->timer[n], offset & 0xff, size); } static void icp_pit_write(void *opaque, hwaddr offset, @@ -371,7 +371,7 @@ static void icp_pit_write(void *opaque, hwaddr offset, return; } - arm_timer_write(s->timer[n], offset & 0xff, value); + arm_timer_write(&s->timer[n], offset & 0xff, value, size); } static const MemoryRegionOps icp_pit_ops = { From patchwork Tue Jul 4 14:50:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698946 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2314947wrs; Tue, 4 Jul 2023 07:52:22 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7ngl96AAjLCPTFZ1WBxN1y3f/ccGfTg8GJk3MRucTyrQ6dfwyrqi9S1ep27L3ccSKam4xV X-Received: by 2002:a05:620a:424d:b0:765:8204:dd64 with SMTP id w13-20020a05620a424d00b007658204dd64mr15914497qko.7.1688482341886; Tue, 04 Jul 2023 07:52:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482341; cv=none; d=google.com; s=arc-20160816; b=uYYhdMPfpum/IYdVqbJIzyv85VTz3df9RCB+uJnP8+cZqu6+q0v75A4MdFtAaLL3d4 zugrLj1d0DANm++FPkhSsoQWzRJ//3Hz1V1unhLyeVQ6qwt9tVrMhgvlCt2xo9YKRsbN rOlRZKRY+g356h3ZsUuR1bvmwIE+YIKaPja/2Q3ADhiLYBOesPd70fHP68sqmNg87YIK alRDhMbnWhRi8yrHI0F+RBdL8cX8RcJDV55L3K2Q1Q7O5/XdxlOzVr+pm/8FcK7eR3lH lu9X3Q/af7ICf/CRMx4aTcOxWoUPJ1bxsWh3cnsONb7NUegBOpXPoP0N7YaHtmJua6IO yg9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=qqlw3Rk5PWDcCN3qJsPC9utAFftgQ+lEqjZf5us/n9A=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=EoN0AWoB211hP7diT2c9nDD9hijofDC5DRLf6T7h5VbMW6+Y84rwFBlIp4EIFugk1w 58mhGjFQztPlqZxMgq7/KRcvWDf51WaK3ld88wbOpFB00cPSdKOcs1vCEiif9uaJCHXE roysGMcpIcwRj4hPRrm3nKI0fpGnioY79qNLm4xb0NiJumZiYmvLKrRzzRs5XbvAKDs1 ohcTxSzpZiaj3kqKWlaEDsafZZgX08qfDiEKDUe80F4V4XhMIt2p2HFdiwuZfizlvtKN ZkoVkIATZlBuf/pax0cuuDumZR8vrEY6ZDqOJtOHQWtMMzOleYC/o/sqQjPE60PrYeCx UsLw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="LcFT8p/c"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Here arm_timer_init() is a such combination, so rename it as arm_timer_new() to emphasis the returned device is already realized. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index cbd82e8365..4ef34b0f60 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -179,7 +179,7 @@ static void arm_timer_reset_hold(ArmTimer *s) s->control = TIMER_CTRL_IE; } -static ArmTimer *arm_timer_init(uint32_t freq) +static ArmTimer *arm_timer_new(uint32_t freq) { ArmTimer *s; @@ -310,8 +310,8 @@ static void sp804_realize(DeviceState *dev, Error **errp) { SP804Timer *s = SP804_TIMER(dev); - s->timer[0] = arm_timer_init(s->freq0); - s->timer[1] = arm_timer_init(s->freq1); + s->timer[0] = arm_timer_new(s->freq0); + s->timer[1] = arm_timer_new(s->freq1); s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0); s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); } @@ -386,10 +386,10 @@ static void icp_pit_init(Object *obj) SysBusDevice *dev = SYS_BUS_DEVICE(obj); /* Timer 0 runs at the system clock speed (40MHz). */ - s->timer[0] = arm_timer_init(40000000); + s->timer[0] = arm_timer_new(40000000); /* The other two timers run at 1MHz. */ - s->timer[1] = arm_timer_init(1000000); - s->timer[2] = arm_timer_init(1000000); + s->timer[1] = arm_timer_new(1000000); + s->timer[2] = arm_timer_new(1000000); sysbus_init_irq(dev, &s->timer[0]->irq); sysbus_init_irq(dev, &s->timer[1]->irq); From patchwork Tue Jul 4 14:50:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698949 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2315108wrs; Tue, 4 Jul 2023 07:52:46 -0700 (PDT) X-Google-Smtp-Source: APBJJlF5oEVFQrT0Tebtfa8vvVOJpvquMi7W2Bt97x3V9EEc6J4r21FUsN7vBF1Z7kwxmiicMmpe X-Received: by 2002:a05:6214:174:b0:632:23c7:d043 with SMTP id y20-20020a056214017400b0063223c7d043mr12052929qvs.52.1688482366760; Tue, 04 Jul 2023 07:52:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482366; cv=none; d=google.com; s=arc-20160816; b=Ftv6RpEMMmTaBgVAm1JDqVy1SSfCv+Ws1cc+ipIlNhK6rnv33KPbKWHLMGD7ZnwvXA uc0fjLtt/hDnRmXyv7dOV7zwSxs81Yuj5s67Y0NYKfBDHPDAqv2+K58iX1Nbu32FVxJS xl4uV8wm0Gob7gYuuxzYIwx9GxEmZuifX0hlufh+GJqDl4/LFeDabf+R9wzoI6aveW5E f7Mk2CThLfwiFWO9Xtj01TXlm9ye8PfoQ4ezZs8hqWhvKaKdLVIdnvkLuiD+jIxCqP1H s0+1P9yF7EJH8pW+WgxtjrnLn67m+v2VpO/o3uI3nNDa0I/gnveJh38CA+dUuqOIAE5O HFJg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=XqL6wbsoBKcWRQEkNfzmSMwKA1cCT5j0UC3IEqUISV4=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=j0CM3lAsNE5olf2q5hbWIZHWvhbtSDEk8uPxJIBgpWYWUx5/bHTQgdHXRTsEr8a1IV fqdbLU5AQESL1efcBIYJ4DQ8KH076/uf9tbwAS39mrbSC5epSV6yA8y8y79CFywbH+u3 W8lI3WrOS4MVPskG37Y77xvrniOwqShaEUTNP2L2vmwgfCxlLefKZeQxGZ5JgIiDXoXV xrS60M/TUiH2Y4ieUXPnGjtTN6WoZdD9jvLM1oO98oeJa1myffhEwJv8ZJ6NyoxBwt6m 4NoYTCbDkSbMSa8Iev8AkeqPX2P3NMYcaLaCqVCieiHaZEALSvhuqffirIIxidVPeUc7 uVqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FQZ+59a8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gf15-20020a056214250f00b0062388040b4csi13724446qvb.203.2023.07.04.07.52.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jul 2023 07:52:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FQZ+59a8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGhNI-0004qQ-TH; Tue, 04 Jul 2023 10:51:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGhN7-0004Ga-0s for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:20 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGhN4-00039M-Sh for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:16 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-3141fa31c2bso5550938f8f.2 for ; Tue, 04 Jul 2023 07:51:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688482272; x=1691074272; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=XqL6wbsoBKcWRQEkNfzmSMwKA1cCT5j0UC3IEqUISV4=; b=FQZ+59a8s3fLXBux9rcwdzHsa/HQWeASBJLIRjGIQB21cjKiVuleUhShtM+yRaVodA i20u2SqR6j1ZHtFeR+1JzzXt07b1gAUQLl1v1Gfc2Z1Q/pkDn3uIq7+Z0CFNPpafUY57 j5rrjg+WZdneduS62OoeiLHplR1c7y8tK/LfJzmtd1HQlEKfHrzHhxB7AzJf5aPzzf7A MhylTQ6ig1e4Iw6RBRCWgp8aO5ZhwWN1xfN3lWsaXGru2dq+ocTrZnMl+2EsphPMsSO/ WE/vaFiZ97ZY8qC90vmHI5TY5P3l9EMwhwwmCI/9H1xlPaAoM1Al6tqaIbsoN6cXCh4o nfYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688482272; x=1691074272; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=XqL6wbsoBKcWRQEkNfzmSMwKA1cCT5j0UC3IEqUISV4=; b=hxitxY5v7zoIzPW1P3ZpPZKgWFg7HVTrqWZ4KtwpDcWlIoJ2/bwzZAfUBCnweCPA2P 9/XkM0woSG7D4tGpdFraknyQHqNynX0lK6IIh+5p9OlOybUuO8aSh8/CPQi885eGEE39 PofjXvv3CEG9UzNPVc6mq1gHUne0F9UW6u4BrcjzFXp6MGzMXIsiq8pF5jhkN06J2Hmf nuruoBxKiyTfnwdxR0eW+FdYcuo4EGwZPKJRbSNwRdPpdJsTyjUjfRavEme6etaggV9m 7AOPTNtDe2c8zwPSxLziOPhU8548RSMlKa4//YA+9qbbhjVngeuTSR9jLtzJ9HLVcmwh prfg== X-Gm-Message-State: ABy/qLb53euOO2FYLXSY1pcNyGx6Y3ajJM9f9sOINtL3slXngVmBtYOk bOLefEzw3UJr9toj0pn3NHHNr0bg9845lIGr8QI= X-Received: by 2002:adf:f049:0:b0:313:f708:5d4 with SMTP id t9-20020adff049000000b00313f70805d4mr12107156wro.24.1688482271995; Tue, 04 Jul 2023 07:51:11 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id p5-20020a5d68c5000000b00314283a525bsm10137803wrw.93.2023.07.04.07.51.11 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:51:11 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 11/19] hw/timer/arm_timer: Convert ArmTimer::freq to uint32_t type Date: Tue, 4 Jul 2023 16:50:04 +0200 Message-Id: <20230704145012.49870-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation of accessing ArmTimer::freq as a QOM property, convert it to uint32_t (so we'll be able to use DEFINE_PROP_UINT32). Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 4ef34b0f60..2b5fb75577 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -33,7 +33,7 @@ typedef struct { ptimer_state *timer; uint32_t control; uint32_t limit; - int freq; + uint32_t freq; int int_level; qemu_irq irq; } ArmTimer; From patchwork Tue Jul 4 14:50:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698954 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2315247wrs; Tue, 4 Jul 2023 07:53:07 -0700 (PDT) X-Google-Smtp-Source: APBJJlH89ZkQ0QHM7XQNhUGxjeW5dsqi4tD7wUvNg1rIvaKAI/FS4e6NmhiY0t3kpvKNraFSl+VK X-Received: by 2002:a05:620a:4407:b0:767:2021:4997 with SMTP id v7-20020a05620a440700b0076720214997mr17903812qkp.7.1688482386830; Tue, 04 Jul 2023 07:53:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482386; cv=none; d=google.com; s=arc-20160816; b=OEqi+6JgiBpCHG/C8YhAXn7NtvvqvMD20kZmctvtwmgt85JU7PC8OTgieMAda4OENp nzBFPPGHh7dEnlAKEV89KYypQTC2YxYtk35Y0ILen0Hf+jYQjAI6aGVLe25uQL8u0qS5 T8jl6nFZCBLWoydEFzBpg8NlQxq/8xvOcAN9NcY0tMJZ6EAmLogTvont5s61xSmu+kKF 0Tq2dbMAF+heQ/Qhvln1rESa6fPFIU67Z+QeCbX8Fdz7QKTAePQ9/V1yz+IIKph7Eerm cpcBxsZCDrbLfrPhpZrCMJEl7uHENVutXZVpY+qkYi1aqKcLUctVkkhRxu8mAhEW2hAc hJDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=KxfHnKj3l6GtT3pvrUKnD3RECUZu48JxXvoYVsgVb2Y=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=caystpNTVpI8OCUCdaWoWbEKRbg0voxuHQbCReqvjasW2WCdHrfajOFjiCMEuP9wru V4l15miwWAxI46wYDCfJEWLo4j89WjdliTqrV2YAZdC0bj1U33tvAsYlvKjZhxJprLr0 TooZK78kK1I2kWwqO7+plzztAMYvb/Pwu6oj9os92mi3OOTdxXcC9iXoWxpYlxr+laO5 MFVBc8VMA11r8yrIhl2ju61xLFoa0OlycBHT0aniuFH8KtcHCMSapWLx9/qUBGlippbZ OXW9wxqCVojmFS6j8J6OnA4T8tt+rSduhmddGEZ/KLuL21pqBtv0WdJOu7UUj/6MN5zm ErQQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=FavhkjPS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Be consistent and use another one for the frequencies. This will allow to simplify using for() loop statement in the next commit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 2b5fb75577..0ad0e55df8 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -206,7 +206,7 @@ struct SP804Timer { MemoryRegion iomem; ArmTimer *timer[2]; - uint32_t freq0, freq1; + uint32_t freq[2]; int level[2]; qemu_irq irq; }; @@ -310,15 +310,15 @@ static void sp804_realize(DeviceState *dev, Error **errp) { SP804Timer *s = SP804_TIMER(dev); - s->timer[0] = arm_timer_new(s->freq0); - s->timer[1] = arm_timer_new(s->freq1); + s->timer[0] = arm_timer_new(s->freq[0]); + s->timer[1] = arm_timer_new(s->freq[1]); s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0); s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); } static Property sp804_properties[] = { - DEFINE_PROP_UINT32("freq0", SP804Timer, freq0, 1000000), - DEFINE_PROP_UINT32("freq1", SP804Timer, freq1, 1000000), + DEFINE_PROP_UINT32("freq0", SP804Timer, freq[0], 1000000), + DEFINE_PROP_UINT32("freq1", SP804Timer, freq[1], 1000000), DEFINE_PROP_END_OF_LIST(), }; From patchwork Tue Jul 4 14:50:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698955 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2315278wrs; Tue, 4 Jul 2023 07:53:11 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ66+hE2LK9ZS1hl/orrilKsHCgYpaCYN6DTmYaaiTXZs1+/yYeKb6fmzsjGO6RZnlWjTTSN X-Received: by 2002:ac8:4e85:0:b0:400:9126:3f16 with SMTP id 5-20020ac84e85000000b0040091263f16mr18192015qtp.1.1688482391326; Tue, 04 Jul 2023 07:53:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482391; cv=none; d=google.com; s=arc-20160816; b=s64tfKty1jJ0wSS7BngIS+oTMsA/5JUBmO2NZ99TVnvJFW9ArmuatAxcA9D2kLu4Dd GHZfzHw5RDJbHCT1hANcBXdOBGK6slr59nCyjVZKRVQ1LKwz1Btwh0RdKCtyBWSFGF9U xvsHqo+yN1PiItV9dPIL+2wXa9ADEt1Y7cwcpA03HvBRYM2lBrEq7xYGG1RX8SyV8ANf wBri4EWien0vLfv8pbl+XMkjSLe04JTRAvd/SJbCoGSofpBWMapvbAGQhnC3MScgLG9K XgldEUuBEbPqopVchFGikG3zXoClY9Dq8CoEuQlTzg+s5guNvoaGYeSNQdKx6YP43e0o EwWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=SzuTpH2SlaRUugw0Q+vEokTxq/EmNFEx2lClbuErT5w=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=NcV+33A81Uq8IA1BX43l4eV/REHyDZyBVPJfBIeLV+5Isss4oqcbzl6DLTMfh696gn Z4g8YXF6sdkzWycpu9vCggkLpZh8A371Nw4/E20ehvys9C2X8eTDEwrl/F80BbYMvAAO NeYn1JLAypWsRCsHghHyIpwfrz9EUUwMArRASgXwHeU6j+XKJTCxlza6mYfIBnrWodoH fzFsA3yQIGSDqdFnERH148zO2ASqPc51xSfka67RKzZHMoV8uwjBjCdjn2PknRVsAuq+ VsQz14Y3Z0gPV8u2JmR7p6lBnqIb0fpcYtVYg4e5d/iUsaYDXBn6Pgh5kGGmNDC5QBKH fLcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L6bJC9PZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id v4-20020ac85784000000b004035311cccasi4418749qta.432.2023.07.04.07.53.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jul 2023 07:53:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=L6bJC9PZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGhNV-0005wp-Kr; Tue, 04 Jul 2023 10:51:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGhNG-0004Qm-93 for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:26 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGhNE-0003Bh-F4 for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:25 -0400 Received: by mail-wr1-x42a.google.com with SMTP id ffacd0b85a97d-31438512cafso2265952f8f.2 for ; Tue, 04 Jul 2023 07:51:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688482282; x=1691074282; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=SzuTpH2SlaRUugw0Q+vEokTxq/EmNFEx2lClbuErT5w=; b=L6bJC9PZWfO98ArDSxA87MfqXDAV1km1gyimivtbcW6qe7QO5mhX54b5JnyCDjP8X2 35aADaIydszdNk3dOMps6sjKAjRZHfZ+cA1mdos0Xn4hS45Bwvp2UwgFvRlRQc6yjQ6q AVpE8JDFRdmJX0+zxrusSmJf7Xe79Kjy1bDSC3tP/W7FCS5z9CHNImrhAoVyPxQNlKDR SBlhozuiJC+dgOACsw66GOaM29ijB/SdFft8pgxui0wiprP83mPPKtH9mb91CrVCrywF mIp6jOBvxS+y+YQCq0h0AYuqpWZo9cE4JCY2OHluNct6+Nl8Idrit1zl0pjVUoHej81L HPjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688482282; x=1691074282; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=SzuTpH2SlaRUugw0Q+vEokTxq/EmNFEx2lClbuErT5w=; b=Zjrl1hRZChh9fiUEPKTzC3VxQgNyISSlHxy18HjPKgGT8NVPTDc+gcyB54X3Tk2/Ad Dg/K70lh6IJ1sJ1Wx10QpU6fPpFa8hWO/Bqwx//G7agpKT0nWjMvHo1M0tdzf8loBgPK S5vhO/So/PbLsNlmPGCbXXmBCIi+oJ7opPq5W8SAnj87SbuBBbviw8x1LSt6CSOZsd8x CRKq1SIXrTaXrrXqn/3rDS1YFQxKYNbaWeSxwJytuVs/x9z0KCXeXJmMJz5jVvRhTINC QnbtAtbL68Vf6z85cNtlGRWPw7rkSK6QL8nlwcf+aKrPWJILQq8HTWHX6O4q9C+xQIin +xkw== X-Gm-Message-State: ABy/qLaX4c//q8hG9GQRbNNU4tIW4spYlxEl7sjUcnJDIWLAwDIS7uZ9 qy7vjUyBjfkTwbhAF32MwD1ykbuKgBPRVBDXb2M= X-Received: by 2002:a05:6000:52:b0:313:ec93:c1c1 with SMTP id k18-20020a056000005200b00313ec93c1c1mr11251095wrx.32.1688482282139; Tue, 04 Jul 2023 07:51:22 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id q18-20020adfcd92000000b003140f47224csm16103787wrj.15.2023.07.04.07.51.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:51:21 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 13/19] hw/timer/arm_timer: Iterate on timers using for() loop statement Date: Tue, 4 Jul 2023 16:50:06 +0200 Message-Id: <20230704145012.49870-14-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The same pattern is used for each timer, 2 or 3 times. To avoid too much code churn in the next commits, iterate on the number of timers using a for() loop statement. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 0ad0e55df8..68cd50314f 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -310,10 +310,10 @@ static void sp804_realize(DeviceState *dev, Error **errp) { SP804Timer *s = SP804_TIMER(dev); - s->timer[0] = arm_timer_new(s->freq[0]); - s->timer[1] = arm_timer_new(s->freq[1]); - s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0); - s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); + for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { + s->timer[i] = arm_timer_new(s->freq[i]); + s->timer[i]->irq = qemu_allocate_irq(sp804_set_irq, s, i); + } } static Property sp804_properties[] = { @@ -382,18 +382,19 @@ static const MemoryRegionOps icp_pit_ops = { static void icp_pit_init(Object *obj) { + static const uint32_t tmr_freq[] = { + /* Timer 0 runs at the system clock speed (40MHz). */ + 40000000, + /* The other two timers run at 1MHz. */ + 1000000, 1000000 + }; IntegratorPIT *s = INTEGRATOR_PIT(obj); SysBusDevice *dev = SYS_BUS_DEVICE(obj); - /* Timer 0 runs at the system clock speed (40MHz). */ - s->timer[0] = arm_timer_new(40000000); - /* The other two timers run at 1MHz. */ - s->timer[1] = arm_timer_new(1000000); - s->timer[2] = arm_timer_new(1000000); - - sysbus_init_irq(dev, &s->timer[0]->irq); - sysbus_init_irq(dev, &s->timer[1]->irq); - sysbus_init_irq(dev, &s->timer[2]->irq); + for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { + s->timer[i] = arm_timer_new(tmr_freq[i]); + sysbus_init_irq(dev, &s->timer[i]->irq); + } memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, "icp_pit", 0x1000); From patchwork Tue Jul 4 14:50:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698952 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2315160wrs; Tue, 4 Jul 2023 07:52:53 -0700 (PDT) X-Google-Smtp-Source: APBJJlH5QqiF/tbhO4V3Pewp+jZyLq+/v0vWgJHKuzwiehgyWdtGDHAjE8dwMum60BypjuHyM8UT X-Received: by 2002:ac8:5710:0:b0:402:d96c:c840 with SMTP id 16-20020ac85710000000b00402d96cc840mr14808034qtw.18.1688482372835; Tue, 04 Jul 2023 07:52:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482372; cv=none; d=google.com; s=arc-20160816; b=QQVkIgSHizbVHl0L9X7ryLVLFdK4RVFfOTb18dmCG6q99OdYstB/sP+DSgqjuh0wYX HsThX0++rKjsAIyJ+92T5oWfAoQWGH52aRFnfkUDO2jSvpcMO0xglWKIa0ZdCk7LMMlU iZIUTN1tl1tpfkycPbsdspkiLV3ecmi2Jmw6fpAQQJ1IUo/FwMlPhMWFvBEFev+DOScL Peyks5JcsFCxZxRu0/vzxcsI0UbLgLxVbkOFNMnqJu4HB70LN1sNH+o5GpQBvWiUdVuX DFOo69kfZb94Zy/jnnqRRFfI03OoeyA0omhp1yiruYoVolZWmkXuYL2oupD4rcCjcuJa wTBw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=b+zARDWiYMa2zugIyhbA2CbxSW+PpQ6qM0E0b9gZz88=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=nQ+A/fm6uACLgSJErE4jVdZHSwc8KhFHLbloNTNP1twunNCZ5RSlysapIggup6c2LC lWheQhz4mIWWW2va4csmK9B2SfKy+o1Af1P969VZ0XWWtaobRdaLfZfPN4LHKsOOHpf0 Xn/KPLgMCDGAYlB5AYHAxYWNR44IvK4ld1BeaLA8BLy8aYlHVTvIQcoRrYedW59XugoO zVDy6QEooqkiSMIGds1yJ6x1PitfPd6SbJ/f7WBWqh9TTUGAHPwzESrEd81buHcAUJcC XUimTeMa0NaIrOhIUzaFXZQiZ4/Z65VkTGb49LEL/JxboMEzHgwL8YNYcBEiCKEjgkvJ eVGQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kU67izzl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e8-20020ac85988000000b00403484a3db7si5950114qte.10.2023.07.04.07.52.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jul 2023 07:52:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kU67izzl; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGhNV-0005yx-VV; Tue, 04 Jul 2023 10:51:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGhNK-00057C-Ne for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:34 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGhNI-0003EM-TX for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:30 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3fbc59de009so58797565e9.3 for ; Tue, 04 Jul 2023 07:51:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688482287; x=1691074287; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=b+zARDWiYMa2zugIyhbA2CbxSW+PpQ6qM0E0b9gZz88=; b=kU67izzlgoXrC7euI1YdCWpidyIYfhKlX2LloXcpixbhbnfZ5TaN6EFZjVhkKxOK91 dkhKIl/s6QyWgidUU4C0e7K3RwUCpYrMjHXv5xoAGzqqEx7mAOo/Qn1H4uLovCQ9RMfx Vlo82LLn38SU7tzuEPteIssjt/6dySXu9oGjM9iVu+GWTnzIKYRlDQrd0GrBSHAz8EWk Q3c7qp9qI4m9miHPd3MWeSyHS1vMifZrpj9VzuYJfZb2lAEIwtKE9Uyeb5n8DIMkcUnm AOOCLsazU9Am1qxdYv9iDHWizznTllD1hjUO3roJzeZq4ZQrTY5aqHLE6KEmEbbta2jx S5eQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688482287; x=1691074287; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=b+zARDWiYMa2zugIyhbA2CbxSW+PpQ6qM0E0b9gZz88=; b=kHgY4GQeM6F+1HfCmWiiG0xanvS1GeoDrHV3JunxJPFIYUCA6TzqdLed31DEQ2S+dd YivZJncTGR90rJB8+TmYSWkv8cQtYN7O85o6L6py1mb0Tddq0jbbX/+Xp4G0Q2x6kLeB HGG0MsN0iFG3g80Q3hCB5lJcTXCEeeqdEbmd24srT7r+ZdCLoka/6bU6+5BvH4/rYPhU WZ/Vv1Rzo/OLvfL/KqwBNAaGjzhHB8KcKmQwSWQLfG3FrAjiYNeAZYl85tgy0iBwDOKW tfImhrVKSQ+kdXui1HYFOROvOhVQRIx1UyoeGe9BQ6Sju41jh88OjjG2fVDQVhkxUXyw TH7A== X-Gm-Message-State: AC+VfDzkJUb4mvt0qeWXsOOtoo3i8EmThr0syMZukocYVmfnn16zJK8y RMkH2p5U4q8VRnF5d+tG2tFHz8eIBFV8QJNUnZE= X-Received: by 2002:a1c:cc16:0:b0:3fb:404c:15e2 with SMTP id h22-20020a1ccc16000000b003fb404c15e2mr11246156wmb.41.1688482287277; Tue, 04 Jul 2023 07:51:27 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id m13-20020a7bcb8d000000b003fba97b1252sm20393533wmi.1.2023.07.04.07.51.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:51:26 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 14/19] hw/timer/arm_timer: Pass timer output IRQ as parameter to arm_timer_new Date: Tue, 4 Jul 2023 16:50:07 +0200 Message-Id: <20230704145012.49870-15-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Both SP804Timer/IntegratorPIT peek at ArmTimer internal state. This is fine so far but we want to convert ArmTimer to QOM where peeking at QOM state internal should be avoided. ArmTimer's IRQ is just a pointer, so we can pass/set it via argument, avoiding accessing ArmTimer internal state except from the arm_timer_*() methods. Once ArmTimer get QOM'ified (in a few commits), it will inherit the SysBus API. This IRQ will then become a SysBus IRQ within this ArmTimer object. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Richard Henderson --- hw/timer/arm_timer.c | 13 ++++++++----- 1 file changed, 8 insertions(+), 5 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 68cd50314f..f6bec28884 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -179,7 +179,7 @@ static void arm_timer_reset_hold(ArmTimer *s) s->control = TIMER_CTRL_IE; } -static ArmTimer *arm_timer_new(uint32_t freq) +static ArmTimer *arm_timer_new(uint32_t freq, qemu_irq irq_out) { ArmTimer *s; @@ -187,6 +187,7 @@ static ArmTimer *arm_timer_new(uint32_t freq) s->freq = freq; arm_timer_reset_hold(s); + s->irq = irq_out; s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_LEGACY); vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_arm_timer, s); return s; @@ -209,6 +210,7 @@ struct SP804Timer { uint32_t freq[2]; int level[2]; qemu_irq irq; + qemu_irq irq_in[2]; }; static const uint8_t sp804_ids[] = { @@ -311,8 +313,8 @@ static void sp804_realize(DeviceState *dev, Error **errp) SP804Timer *s = SP804_TIMER(dev); for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { - s->timer[i] = arm_timer_new(s->freq[i]); - s->timer[i]->irq = qemu_allocate_irq(sp804_set_irq, s, i); + s->irq_in[i] = qemu_allocate_irq(sp804_set_irq, s, i); + s->timer[i] = arm_timer_new(s->freq[i], s->irq_in[i]); } } @@ -341,6 +343,7 @@ struct IntegratorPIT { MemoryRegion iomem; ArmTimer *timer[3]; + qemu_irq irq_in[3]; }; static uint64_t icp_pit_read(void *opaque, hwaddr offset, @@ -392,8 +395,8 @@ static void icp_pit_init(Object *obj) SysBusDevice *dev = SYS_BUS_DEVICE(obj); for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { - s->timer[i] = arm_timer_new(tmr_freq[i]); - sysbus_init_irq(dev, &s->timer[i]->irq); + s->timer[i] = arm_timer_new(tmr_freq[i], s->irq_in[i]); + sysbus_init_irq(dev, &s->irq_in[i]); } memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, From patchwork Tue Jul 4 14:50:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698957 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2315297wrs; Tue, 4 Jul 2023 07:53:13 -0700 (PDT) X-Google-Smtp-Source: APBJJlFLL6yDQgJA39l//xeMwBqGQoRkXpJ4FQ3S6JrckH2HofToFJdBSlJd066xNknX0rQFHcqL X-Received: by 2002:a05:6214:1d23:b0:636:14d4:4450 with SMTP id f3-20020a0562141d2300b0063614d44450mr18127878qvd.3.1688482392985; Tue, 04 Jul 2023 07:53:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482392; cv=none; d=google.com; s=arc-20160816; b=Ruhg+Go2P7fRkqp361mATRUPUp1lI6v8WGqBMVfuClMOarpFTuWXLlc2qwkuNMA0Vo x5o1lTdN9IjjMafLwMkrlQNBT4FjRuG6qni+KqxbVyNUnOkxcmBpF5/w5chhKBoMSYIY q2/bs6jClxuGvd/nBeP9b5Wf+aBV9QDvCg0hhbFQrQ9EeyApmYCt86aXdeSveAY+UgrR Dw9fPBLVvct4lhL+idfeYD79gg9WONo/MLSxQCemeg2ceLY0B/uUWKNgdRwxxiSlm1j5 6PMfd/i20IvEPwNT3s7C2w19pXbmys0JLFv56Ju0A4fiaV9F2VNinGt3MFdShRgUjCpd AYEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=TCPWCNW3sULrKOxLX0GNQbm2gqBGrznr8P5ALvlpdo0=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=uzkzU/fEq/HrHlBnheo7hFWEvYxmRg7UDcaqxhcovwKbthvn+jwxONp/nB9fIWdI3R Su6IwBqSpCl+cKervO6KEhJzK1LbFsCJMIeY9LxTGAGXTI12VUROnySHN/yIdqw1vYRZ T2fMsu6lg1PzdcvmIm1OK5foH37bCBXmM7izrZr1MDLFR7io4xK+HSvkffmm/a9FFQd7 frttFc1II321zQGLfRriPhSQCL7tJ/0iTvFhhV9mwPHnLRWMs6e8lKemlbm7td8NV541 BkXOVVhjjFJvjz2HA37Oq+MejSFKDW9Qnwyil7m7YcWmvzxV8a9p7oi6kSuz6Ocs2guc xLdQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gx+eoLAz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gw6-20020a0562140f0600b00635e113a0easi12777928qvb.41.2023.07.04.07.53.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jul 2023 07:53:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gx+eoLAz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGhNW-000675-Mc; Tue, 04 Jul 2023 10:51:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGhNQ-0005SN-Mj for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:36 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGhNO-0003Fk-3v for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:36 -0400 Received: by mail-wr1-x42c.google.com with SMTP id ffacd0b85a97d-31297125334so4911112f8f.0 for ; Tue, 04 Jul 2023 07:51:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688482292; x=1691074292; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=TCPWCNW3sULrKOxLX0GNQbm2gqBGrznr8P5ALvlpdo0=; b=gx+eoLAzdCaf2mFU71JLWi4Vszd+vOyUX62jA1rtmJsj1QOhsMhmegoflCkqq+ARel 049ZkE412nzx5Erpi3pt+A7nnS7ILZxJnrHQ2qJcSVQy1LU9Ex7qWhJM29oDM4FiOiWy 1+HVMbV9rptsCAm/oZ217opeW5Owt431wVOEy0NhLNvOoKt66Njg3LX9Ig2Dd4mEagr3 01BBpbzyLFSfnJj5Ohn79QcuMdZXGCHfHMrwNtNwRgsANR/GVpD7wzgyr1KuIXp2bYkE 4YDANPQxjPCEat75RUdNf8ZDxBzN0Ud8ZK4zeOezTYtU+lGVcuGT7lnnvBqNnGoNq6T4 UQXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688482292; x=1691074292; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TCPWCNW3sULrKOxLX0GNQbm2gqBGrznr8P5ALvlpdo0=; b=d1Y51ubCrekB6MkirVTHjks0Wpk5mD+CCshdFU95ULbbQfkIwlTofY2jf64+la4S7P 9bgaciDAVL8Mrqu8RYXVR6+4bP8lEpUm902mP3wxTynunu4V9w9OrPsctosbPLdtWhDC aj38q4eUd57y6M8Lra54jx1CKaEA5K85L6EQUstQqhVtVVTvlxjT+UkP2rsNt71FlhVD nRmiO8LdX17wsjDkwzH2EHWDOlVBVZy9Fj0U4mblvKz1L/9ZWpo9JLRIopnOvg6wooV7 93O8gr/4sQIYdcnONrRVow41VWUPanlEsA3u5K88vvg0lMSG3a2+GIKDEoCDXxg+nzOP dXLA== X-Gm-Message-State: AC+VfDxPChhmvj4S1CzFSuoQoxnfZpMgVgeYldiQevOC7yPRjTumozfv eVVNw5e1neBXBcMFgqH2JIxH/bc+KWTovtRToWg= X-Received: by 2002:adf:e3c9:0:b0:313:ef28:d3d6 with SMTP id k9-20020adfe3c9000000b00313ef28d3d6mr16845550wrm.6.1688482292605; Tue, 04 Jul 2023 07:51:32 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id g5-20020adff405000000b003143cb109d5sm2883604wro.14.2023.07.04.07.51.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:51:32 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 15/19] hw/timer/arm_timer: Fix misuse of SysBus IRQ in IntegratorPIT Date: Tue, 4 Jul 2023 16:50:08 +0200 Message-Id: <20230704145012.49870-16-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org SysBus IRQ are *output* IRQs. As some sort of simplification to avoid to forward it, IntegratorPIT misuses it as ARM timer input IRQ. Fix that by using a simple IRQ forwarder handler. Note: sysbus_pass_irq() forwards GPIOs and IRQs from a container to an inner device but only work with an entire set of IRQs, so we can not use it here where we forward a single IRQ from each timer. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell Acked-by: Richard Henderson --- hw/timer/arm_timer.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index f6bec28884..aae7f3cf9d 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -344,6 +344,7 @@ struct IntegratorPIT { MemoryRegion iomem; ArmTimer *timer[3]; qemu_irq irq_in[3]; + qemu_irq irq[3]; }; static uint64_t icp_pit_read(void *opaque, hwaddr offset, @@ -383,6 +384,13 @@ static const MemoryRegionOps icp_pit_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; +static void icp_pit_fwd_irq(void *opaque, int n, int level) +{ + IntegratorPIT *s = opaque; + + qemu_set_irq(s->irq[n], level); +} + static void icp_pit_init(Object *obj) { static const uint32_t tmr_freq[] = { @@ -394,9 +402,14 @@ static void icp_pit_init(Object *obj) IntegratorPIT *s = INTEGRATOR_PIT(obj); SysBusDevice *dev = SYS_BUS_DEVICE(obj); + qdev_init_gpio_in_named(DEVICE(obj), icp_pit_fwd_irq, + "timer-in", ARRAY_SIZE(s->timer)); + for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { s->timer[i] = arm_timer_new(tmr_freq[i], s->irq_in[i]); - sysbus_init_irq(dev, &s->irq_in[i]); + sysbus_init_irq(dev, &s->irq[i]); + sysbus_connect_irq(dev, i, + qdev_get_gpio_in_named(DEVICE(obj), "timer-in", i)); } memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, From patchwork Tue Jul 4 14:50:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698951 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2315154wrs; Tue, 4 Jul 2023 07:52:52 -0700 (PDT) X-Google-Smtp-Source: APBJJlF5iJSGeXW5i1I5v8xLddfNSwDey/wmBD0jLzWYP+NTZ6aaXy52tXt6BYJ8LIGJFVU2xvdt X-Received: by 2002:a05:620a:394c:b0:767:6cd5:ec5e with SMTP id qs12-20020a05620a394c00b007676cd5ec5emr7772542qkn.55.1688482372175; Tue, 04 Jul 2023 07:52:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482372; cv=none; d=google.com; s=arc-20160816; b=JC2MJsqEorKmpTDxfewLbvrs3ed8r2lG5LGGRn0tSCWdljqBfisiA/z5Kwr53LIZNy mOh7N2onOtt+Bccg++C9esmzpaIK9Mzg4CEG+uCo/LxLjJWpH4JuknpP5JAw/L2StYrW P6F8S1aLODVbXNzrOyguairmu8BXNlvioPAzTTz30wCqQHzn2m+RnSuvKgdE8CBfObE6 8GdSTJwqD+wKDybGczbhq6UjeTiA/jaYE6y0qdHUzKB0nDy2xk0vjAAkDaTqTosNUmSt 2E0la9Gyc7q8Ru9ROk/puWrc6pvD/9xhKD71UjCb1+voZMP3U7ZXVAyKAj/a6+kyF7tQ j1Ww== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wgqnt2VX3X1H7hrQYVz6F1zcu6hxE23p/SOYvZ7/smg=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=ykQ7EUh/wymiJ8EyBQKPtzg0gWMN7gPbyzX7O1ueJ8+HLNe/vJjd5Q6NAuH9ayQs9K SpU3i15Z+hZTjnDEhGk6yZXIG1oGiVO2bRq+/6U7aYnrDw+gEqxUcl8MNZymfZWXPq2h r/wen73V70igSFxoMgSdK5TfMpFHtM6KRK1cFGuptOnQifosFJaMPd4M84qSCbGh636X Afh/Rqfbj9eua/MKhLj/JAKCp+TvXp1MBwMsFt95EKg4mHyY+/8r6nXtlLOc9ZbBS67j VByG9ZiyYPtoOpoXHtyLqowvy3ly4fAsGcXGhbdhPkjTz43/GLycYLMJZVMt6WH/CNYL Sl+g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IbEpMfAQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id uc24-20020a05620a6a1800b0076255d1bc16si11430730qkn.730.2023.07.04.07.52.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jul 2023 07:52:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IbEpMfAQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGhNZ-0006U9-1M; Tue, 04 Jul 2023 10:51:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGhNW-00063g-Cx for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:42 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGhNT-0003HS-JE for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:42 -0400 Received: by mail-wm1-x32a.google.com with SMTP id 5b1f17b1804b1-3fbd33a573cso29731965e9.2 for ; Tue, 04 Jul 2023 07:51:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688482298; x=1691074298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=wgqnt2VX3X1H7hrQYVz6F1zcu6hxE23p/SOYvZ7/smg=; b=IbEpMfAQNaks5OtQCxWJ65MC1we/3JI3XmlZcyjC97imIfLZcYPtR3XCH02u3u6XpC BkfjiOmqKTSMe3SFdMXp1M/0cZWXoGCd91YS6jvmhiQP3E5qsoMF3TZt6Xba3PM6qXyu iIPRM6rRqovJk4TUo1ruuE4qb9KdSB+Hk/cF/azlAVnxDKSGsmcVTnOvEephnCGcMNOj PYNTiTaK6StHtKMIOc7eV9YjtTjeZVuEH/fiwpJyEd5GvceDbrlUu1TslyTxOP/FQ0kC HEVd+pDa8quxpbEDgwGDsiZ7Ql+Jl3TDeEB3Y96BAH/57wFhT/4VuSu2sZkBUURdWTMz a1PA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688482298; x=1691074298; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=wgqnt2VX3X1H7hrQYVz6F1zcu6hxE23p/SOYvZ7/smg=; b=jr2qljB/6xhRxYP7qqt+818NVwCoqHcy8Ox88N02SKTwQLRxuo1pqmT4lVeHDJwfVx Ret7uJTmdj0PFAKrHaJFdbwz3xunh/MvTPOHM3RMM1j1m3qlr2Mvv+bO4gdxr/1os8Pu YLt7LTF+gBH5s6to2FsmL/Zrq2bnjHOi4gBebPTPNm2SVH0ebM62FrAzosWKS3GYQ+a+ pnv3j2Z2etXDExxKjgPLml9vbmXCNr16tYOZhssWTDN0Cf8ctHG0lvPEXI89VwbD1bnE HHlE2Iy+rYAPp8nHOqiPoubt+UFJFa8B4TkG1CWJhNur7+VoztQVieUQ3hzeg+WkaIOZ /peA== X-Gm-Message-State: AC+VfDyr+jkqxT9O041Hxosr3L743qoKTiLE+05LdlebRhSEwNwMLUS4 56DLt2+Q88b4cyaRcE76ICbulP3kCOcIwehZGmA= X-Received: by 2002:a05:600c:2049:b0:3f9:b31d:5689 with SMTP id p9-20020a05600c204900b003f9b31d5689mr10696015wmg.36.1688482297790; Tue, 04 Jul 2023 07:51:37 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id z7-20020a05600c220700b003fa999cefc0sm24555314wml.36.2023.07.04.07.51.36 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:51:37 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 16/19] hw/timer/arm_timer: Extract icp_pit_realize() from icp_pit_init() Date: Tue, 4 Jul 2023 16:50:09 +0200 Message-Id: <20230704145012.49870-17-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org To make the next commit easier to digest, extract icp_pit_realize() from icp_pit_init() as a preliminary step. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index aae7f3cf9d..30e29cc166 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -408,8 +408,6 @@ static void icp_pit_init(Object *obj) for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { s->timer[i] = arm_timer_new(tmr_freq[i], s->irq_in[i]); sysbus_init_irq(dev, &s->irq[i]); - sysbus_connect_irq(dev, i, - qdev_get_gpio_in_named(DEVICE(obj), "timer-in", i)); } memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, @@ -419,12 +417,31 @@ static void icp_pit_init(Object *obj) save themselves. */ } +static void icp_pit_realize(DeviceState *dev, Error **errp) +{ + IntegratorPIT *s = INTEGRATOR_PIT(dev); + + for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { + SysBusDevice *tmr = SYS_BUS_DEVICE(&s->timer[i]); + + sysbus_connect_irq(tmr, i, qdev_get_gpio_in_named(dev, "timer-in", i)); + } +} + +static void icp_pit_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *k = DEVICE_CLASS(klass); + + k->realize = icp_pit_realize; +} + static const TypeInfo arm_timer_types[] = { { .name = TYPE_INTEGRATOR_PIT, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(IntegratorPIT), .instance_init = icp_pit_init, + .class_init = icp_pit_class_init, }, { .name = TYPE_SP804_TIMER, From patchwork Tue Jul 4 14:50:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698956 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2315283wrs; Tue, 4 Jul 2023 07:53:12 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4v/yoDeiCQd13qW2RSLYRRV7mxGMIQ9Zh8gq7jMQgwzOyke/VORfxeeTIOah5OlRhDoq/e X-Received: by 2002:a05:620a:4727:b0:767:3771:f770 with SMTP id bs39-20020a05620a472700b007673771f770mr14602462qkb.40.1688482391808; Tue, 04 Jul 2023 07:53:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482391; cv=none; d=google.com; s=arc-20160816; b=QIeHaq+lOw1DTxHy2BIvwc837XR9aMOdVZr3iRCm3k+STkfo80XLH7X5Y//eOlrWDp ueAONlUcd2LFyrU4yTU4EYXHXAiw6zQBuS7xOgtvk/XFZhuKX4bUmCK1NWlTgVLhDNN6 cEDwiR5iJf4aozionE6Jv9OV564yQ2EKRExM0Kr3iqY5e7gcm2W7a4+P/QyY3yVsuZQl OHjJgFgRTNI0+d47a5pBN+o13ZFKm8dnpSGnP7ihmZhVyMmOVkATBeGTWBbu2fhBKr33 pn8r0TE7Gkrt+JdwtFmOe0tVDQzwN+5lw40orb0lW/BE7URla3q4pMarwrzoAxmK2W1n 5cjw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=FoiopN5m4eo81u2lGvLxlfXk+Lie1Jj0bV1bknAcSnc=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=NCBRe4T42s1i6h6kwajKHt33o4OmsyfyFWMRyIiZ0tCeqHxSXFVg3fCaVrJOAd5nv0 SNBv5zLqjRPNrU9vyOYKL92VjQgXUU2Z326HCT1LCBagbCpmFYTiGsoBn6TbpZYmiD6c H2+E3SnSLQNy6Zq73a0w3ccT/K+HkT13+Z98SaivRbZtx0M1A2RUUZblOx1H8W3ijYjC aCAcjHH3Ollp6PSyy3ZX1RwVszK0C1A7vik2jJwTE4yG+1tQXf3HbwD+nNNTpioahVaa +zfatk+psSgRbV2cR0P4VySUxp1fDPbJaeoVQa2ElTIvC397AbgPETLSCv13U9tsvYG5 9F0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NLlf2MXb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f13-20020a37ad0d000000b0076718c32823si10551467qkm.459.2023.07.04.07.53.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 04 Jul 2023 07:53:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NLlf2MXb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qGhNc-0006vv-4R; Tue, 04 Jul 2023 10:51:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qGhNa-0006gK-Lc for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:46 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qGhNY-0003Il-Ji for qemu-devel@nongnu.org; Tue, 04 Jul 2023 10:51:46 -0400 Received: by mail-wr1-x433.google.com with SMTP id ffacd0b85a97d-3143798f542so2366808f8f.2 for ; Tue, 04 Jul 2023 07:51:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1688482303; x=1691074303; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FoiopN5m4eo81u2lGvLxlfXk+Lie1Jj0bV1bknAcSnc=; b=NLlf2MXbxKxVRsfadigRs4LvNadXGP0v8RuNq6kz02Q9WjFHArpZ9pl73sChV6e4uI OIw2/hyLCBAvrmTJVR8Du4fp0khwf06IjRahypseTwQgxkvtQ68PYlqyc59weq0o2Jj8 e/5d3eUWtRU854AKzoOsV4TveqsiIcOVYGsNttbKqVsDrT/sktvA7BwegqqfazCiLSlD bj25lbdZJP7pSNxzbWG4iILncHH9OOnI03z7GFS6QFQqRM/E9Pk+aiCmlLOJwr1Z/JkR MHgl4T/UAYBLgp/8PnuUQfSO/aspqQlkUTR0GMSSZLlgAHdWtrc2Gu4h2FMiGyYmA3CB sIfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1688482303; x=1691074303; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FoiopN5m4eo81u2lGvLxlfXk+Lie1Jj0bV1bknAcSnc=; b=jm/RYGmnfNfFxLLinihfS5+25VVMC4SMTMBOCS3wzQimaui4xEoH5FvCHDZ3RCBG16 90psyfvefO82rBeF82Kgf7BuMeZB8igWDZ7NijaeGABGs3FjusEjYP532DWE91odN6vw ef8g1QRn7I2i0Ox2VOzas1dc5ViEaz7kLjQPNKeYtUxw1J0+A6Kxic9+f9OuLWpgbVFV H0nMOXcO7DNzzTby3YKOwK/r1jw6K2lkJZFdtVSkyzoyBdjaLZ+RocXI+KvrejRDCed9 gc1QqTdXxjDK4yca1vF8I1tZefmJI9rv3EvLD5u10fgPUgqh3Nx34meSnfzaAskOma1U zU+g== X-Gm-Message-State: ABy/qLbrpY94Jcca+ncr+FFM7rlQQ+ntIwcsCCQcoMVOP8X20ihDRvU4 81bnil1AtfWOjLwvtZ6amHkRwkYpYoENwwcTUbA= X-Received: by 2002:adf:f210:0:b0:314:1aed:8f5f with SMTP id p16-20020adff210000000b003141aed8f5fmr11837753wro.34.1688482303020; Tue, 04 Jul 2023 07:51:43 -0700 (PDT) Received: from localhost.localdomain ([176.176.157.122]) by smtp.gmail.com with ESMTPSA id f13-20020a5d50cd000000b003143b7449ffsm3865602wrt.25.2023.07.04.07.51.41 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Tue, 04 Jul 2023 07:51:42 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Paolo Bonzini , Mark Cave-Ayland , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH v2 17/19] hw/timer/arm_timer: QDev'ify ARM_TIMER Date: Tue, 4 Jul 2023 16:50:10 +0200 Message-Id: <20230704145012.49870-18-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230704145012.49870-1-philmd@linaro.org> References: <20230704145012.49870-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Introduce the ARM_TIMER sysbus device, exposing one output IRQ and a single MMIO region. arm_timer_new() is converted as QOM instance init()/finalize() handlers. Note in arm_timer_finalize() we release a ptimer handle which was previously leaked. ArmTimer is directly embedded into SP804Timer/IntegratorPIT, and is initialized as a QOM child. Since the timer frequency belongs to ARM_TIMER, have it hold the QOM property. SP804Timer/IntegratorPIT directly access it. For IntegratorPIT, each ARM_TIMER sysbus output IRQ is wired as input IRQ. For the SP804Timer, we add a TYPE_OR_IRQ to OR the ARM_TIMER sysbus output IRQs together, exposing a single output IRQ. The Kconfig entry have to select the OR_IRQ dependency. Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/arm_timer.c | 139 ++++++++++++++++++++++++++++++++----------- hw/timer/Kconfig | 1 + 2 files changed, 105 insertions(+), 35 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 30e29cc166..8207723ab5 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -12,11 +12,13 @@ #include "migration/vmstate.h" #include "qemu/timer.h" #include "hw/irq.h" +#include "hw/or-irq.h" #include "hw/ptimer.h" #include "hw/qdev-properties.h" #include "qemu/module.h" #include "qemu/log.h" #include "qom/object.h" +#include "qapi/error.h" /* Common timer implementation. */ @@ -29,14 +31,20 @@ #define TIMER_CTRL_PERIODIC (1 << 6) #define TIMER_CTRL_ENABLE (1 << 7) -typedef struct { +#define TYPE_ARM_TIMER "arm-timer" +OBJECT_DECLARE_SIMPLE_TYPE(ArmTimer, ARM_TIMER) + +struct ArmTimer { + SysBusDevice parent_obj; + + MemoryRegion iomem; ptimer_state *timer; uint32_t control; uint32_t limit; uint32_t freq; int int_level; qemu_irq irq; -} ArmTimer; +}; /* Check all active timers, and schedule the next timer interrupt. */ @@ -152,6 +160,14 @@ static void arm_timer_write(void *opaque, hwaddr offset, arm_timer_update(s); } +static const MemoryRegionOps arm_timer_ops = { + .read = arm_timer_read, + .write = arm_timer_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, +}; + static void arm_timer_tick(void *opaque) { ArmTimer *s = opaque; @@ -172,25 +188,49 @@ static const VMStateDescription vmstate_arm_timer = { } }; -static void arm_timer_reset_hold(ArmTimer *s) +static void arm_timer_reset_hold(Object *obj) { + ArmTimer *s = ARM_TIMER(obj); + s->limit = 0; s->int_level = 0; s->control = TIMER_CTRL_IE; } -static ArmTimer *arm_timer_new(uint32_t freq, qemu_irq irq_out) +static void arm_timer_init(Object *obj) { - ArmTimer *s; + ArmTimer *s = ARM_TIMER(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - s = g_new0(ArmTimer, 1); - s->freq = freq; - arm_timer_reset_hold(s); - - s->irq = irq_out; s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_LEGACY); - vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_arm_timer, s); - return s; + + sysbus_init_irq(sbd, &s->irq); + + memory_region_init_io(&s->iomem, obj, &arm_timer_ops, s, + "arm_timer", 0x20); + sysbus_init_mmio(sbd, &s->iomem); +} + +static void arm_timer_finalize(Object *obj) +{ + ArmTimer *s = ARM_TIMER(obj); + + ptimer_free(s->timer); +} + +static Property arm_timer_properties[] = { + DEFINE_PROP_UINT32("freq", ArmTimer, freq, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void arm_timer_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + ResettableClass *rc = RESETTABLE_CLASS(oc); + + dc->vmsd = &vmstate_arm_timer; + device_class_set_props(dc, arm_timer_properties); + rc->phases.hold = arm_timer_reset_hold; } /* @@ -206,11 +246,10 @@ struct SP804Timer { SysBusDevice parent_obj; MemoryRegion iomem; - ArmTimer *timer[2]; - uint32_t freq[2]; - int level[2]; + ArmTimer timer[2]; + int mig_v1_level[2]; + OrIRQState irq_orgate; qemu_irq irq; - qemu_irq irq_in[2]; }; static const uint8_t sp804_ids[] = { @@ -220,15 +259,6 @@ static const uint8_t sp804_ids[] = { 0xd, 0xf0, 0x05, 0xb1 }; -/* Merge the IRQs from the two component devices. */ -static void sp804_set_irq(void *opaque, int irq, int level) -{ - SP804Timer *s = opaque; - - s->level[irq] = level; - qemu_set_irq(s->irq, s->level[0] || s->level[1]); -} - static uint64_t sp804_read(void *opaque, hwaddr offset, unsigned size) { @@ -287,12 +317,26 @@ static const MemoryRegionOps sp804_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; +static int sp804_post_load(void *opaque, int version_id) +{ + SP804Timer *s = opaque; + + if (version_id < 2) { + for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { + qemu_set_irq(qdev_get_gpio_in(DEVICE(&s->irq_orgate), i), + s->mig_v1_level[i]); + } + } + return 0; +} + static const VMStateDescription vmstate_sp804 = { .name = "sp804", - .version_id = 1, + .version_id = 2, .minimum_version_id = 1, + .post_load = sp804_post_load, .fields = (VMStateField[]) { - VMSTATE_INT32_ARRAY(level, SP804Timer, 2), + VMSTATE_INT32_ARRAY(mig_v1_level, SP804Timer, 2), VMSTATE_END_OF_LIST() } }; @@ -306,21 +350,36 @@ static void sp804_init(Object *obj) memory_region_init_io(&s->iomem, obj, &sp804_ops, s, "sp804", 0x1000); sysbus_init_mmio(sbd, &s->iomem); + + object_initialize_child(obj, "timer-irq-orgate", + &s->irq_orgate, TYPE_OR_IRQ); + + for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { + object_initialize_child(obj, "timer[*]", &s->timer[i], TYPE_ARM_TIMER); + } } static void sp804_realize(DeviceState *dev, Error **errp) { SP804Timer *s = SP804_TIMER(dev); + object_property_set_int(OBJECT(&s->irq_orgate), + "num-lines", 2, &error_fatal); + qdev_realize(DEVICE(&s->irq_orgate), NULL, &error_fatal); + for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { - s->irq_in[i] = qemu_allocate_irq(sp804_set_irq, s, i); - s->timer[i] = arm_timer_new(s->freq[i], s->irq_in[i]); + SysBusDevice *tmr = SYS_BUS_DEVICE(&s->timer[i]); + + if (!sysbus_realize(tmr, errp)) { + return; + } + sysbus_connect_irq(tmr, 0, qdev_get_gpio_in(DEVICE(&s->irq_orgate), i)); } } static Property sp804_properties[] = { - DEFINE_PROP_UINT32("freq0", SP804Timer, freq[0], 1000000), - DEFINE_PROP_UINT32("freq1", SP804Timer, freq[1], 1000000), + DEFINE_PROP_UINT32("freq0", SP804Timer, timer[0].freq, 1000000), + DEFINE_PROP_UINT32("freq1", SP804Timer, timer[1].freq, 1000000), DEFINE_PROP_END_OF_LIST(), }; @@ -342,8 +401,7 @@ struct IntegratorPIT { SysBusDevice parent_obj; MemoryRegion iomem; - ArmTimer *timer[3]; - qemu_irq irq_in[3]; + ArmTimer timer[3]; qemu_irq irq[3]; }; @@ -406,7 +464,8 @@ static void icp_pit_init(Object *obj) "timer-in", ARRAY_SIZE(s->timer)); for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { - s->timer[i] = arm_timer_new(tmr_freq[i], s->irq_in[i]); + object_initialize_child(obj, "timer[*]", &s->timer[i], TYPE_ARM_TIMER); + qdev_prop_set_uint32(DEVICE(&s->timer[i]), "freq", tmr_freq[i]); sysbus_init_irq(dev, &s->irq[i]); } @@ -424,7 +483,10 @@ static void icp_pit_realize(DeviceState *dev, Error **errp) for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { SysBusDevice *tmr = SYS_BUS_DEVICE(&s->timer[i]); - sysbus_connect_irq(tmr, i, qdev_get_gpio_in_named(dev, "timer-in", i)); + if (!sysbus_realize(tmr, errp)) { + return; + } + sysbus_connect_irq(tmr, 0, qdev_get_gpio_in_named(dev, "timer-in", i)); } } @@ -437,6 +499,13 @@ static void icp_pit_class_init(ObjectClass *klass, void *data) static const TypeInfo arm_timer_types[] = { { + .name = TYPE_ARM_TIMER, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(ArmTimer), + .instance_init = arm_timer_init, + .instance_finalize = arm_timer_finalize, + .class_init = arm_timer_class_init, + }, { .name = TYPE_INTEGRATOR_PIT, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(IntegratorPIT), diff --git a/hw/timer/Kconfig b/hw/timer/Kconfig index 010be7ed1f..61b048f49c 100644 --- a/hw/timer/Kconfig +++ b/hw/timer/Kconfig @@ -1,6 +1,7 @@ config ARM_TIMER bool select PTIMER + select OR_IRQ config ARM_MPTIMER bool From patchwork Tue Jul 4 14:50:11 2023 Content-Type: text/plain; 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 43 ++++--------------------------------------- 1 file changed, 4 insertions(+), 39 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 8207723ab5..7b455aff4d 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -393,6 +393,7 @@ static void sp804_class_init(ObjectClass *klass, void *data) } /* Integrator/CP timer module. */ +/* ??? Don't know the PrimeCell ID for this device. */ #define TYPE_INTEGRATOR_PIT "integrator_pit" OBJECT_DECLARE_SIMPLE_TYPE(IntegratorPIT, INTEGRATOR_PIT) @@ -405,43 +406,6 @@ struct IntegratorPIT { qemu_irq irq[3]; }; -static uint64_t icp_pit_read(void *opaque, hwaddr offset, - unsigned size) -{ - IntegratorPIT *s = opaque; - int n; - - /* ??? Don't know the PrimeCell ID for this device. */ - n = offset >> 8; - if (n > 2) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); - return 0; - } - - return arm_timer_read(&s->timer[n], offset & 0xff, size); -} - -static void icp_pit_write(void *opaque, hwaddr offset, - uint64_t value, unsigned size) -{ - IntegratorPIT *s = opaque; - int n; - - n = offset >> 8; - if (n > 2) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad timer %d\n", __func__, n); - return; - } - - arm_timer_write(&s->timer[n], offset & 0xff, value, size); -} - -static const MemoryRegionOps icp_pit_ops = { - .read = icp_pit_read, - .write = icp_pit_write, - .endianness = DEVICE_NATIVE_ENDIAN, -}; - static void icp_pit_fwd_irq(void *opaque, int n, int level) { IntegratorPIT *s = opaque; @@ -469,8 +433,7 @@ static void icp_pit_init(Object *obj) sysbus_init_irq(dev, &s->irq[i]); } - memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, - "icp_pit", 0x1000); + memory_region_init(&s->iomem, obj, "icp_pit", 0x1000); sysbus_init_mmio(dev, &s->iomem); /* This device has no state to save/restore. The component timers will save themselves. */ @@ -487,6 +450,8 @@ static void icp_pit_realize(DeviceState *dev, Error **errp) return; } sysbus_connect_irq(tmr, 0, qdev_get_gpio_in_named(dev, "timer-in", i)); + memory_region_add_subregion(&s->iomem, 0x100 * i, + sysbus_mmio_get_region(tmr, 0)); } } From patchwork Tue Jul 4 14:50:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 698950 Delivered-To: patch@linaro.org Received: by 2002:adf:fcc5:0:0:0:0:0 with SMTP id f5csp2315123wrs; Tue, 4 Jul 2023 07:52:48 -0700 (PDT) X-Google-Smtp-Source: APBJJlFh8U/Nt7sFzr83Nlv4T4QERBpbyktRtpMT0GqqMolTnPfuYOC7+qoWlFkOyNzQWbTulUIQ X-Received: by 2002:a05:622a:13d1:b0:403:63b5:3be4 with SMTP id p17-20020a05622a13d100b0040363b53be4mr5919220qtk.27.1688482368363; Tue, 04 Jul 2023 07:52:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1688482368; cv=none; d=google.com; s=arc-20160816; b=R8kMrQ7u08fWmmhhunaedzwOY/7qVaJR5sErODxllkKEgXwEprI5QdayRLTeNZXQFa +yJKaLBs8aoopsjNLLlzYyeZl7ouyjrzvcRlelLHuMXEV9qi49mcpjSDjWYVBirG9Vik Wswbu883+LCwKA1vPDosmQHuhoMK/MJZaswd8Q65wVmZS/lLgyVV3kVR7pyXH+TZ0I+D 45hsBSPhVQ0ibydLGCR6djpuQjcNpv71fFuYJuEHOo9sV5kE9shS4Un5scOi4xnvkpIf B7SlnmeNO9sd5R6fVAj6QS5ayhZXt8ynw78sL/RlMImRb/ksJJ2Of8cKU7kVCOv/MDdh K/Uw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=V69v+7bs2xlDWB5vTHTpi2FU6s9o0pa03HFic+S4ft4=; fh=Lngrjms14biHE1uwg3hJItOsHUc/fKOP3kWz84zgU0I=; b=B7fVa5YOtej1aHeLQn3Yj1OjZqvdQHVBXAKcDREt93uqEqyKT/Ph9cHTuU1j8R9/dW ObZ0sxo52YOaLdrIoAU79fujpVVoXDVm8CZL0hCmiAopg2g5MV5XOIp7g9kAucn7W+VO 6pvLh5x9nJfjYeHBwP5VyLct0QyziHtsgroHlLCmGdeBliRDt7JER8y9zEILtS7CPppB X0ANEsewP9VRqMlGNnNcfOt7ujJqYrFKhw3aAV0sIcvIy5iNeh+CxzMvYnB3jHll0qyo g669WaKoDU1QnxkZMGTYdkKEEB5FTEJrbpFbDTEZUGRiPl3AmvxHG6/dWPZrq6zX2BOB s7BA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=yQ0nI1Hb; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/timer/arm_timer.c | 23 ++--------------------- 1 file changed, 2 insertions(+), 21 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 7b455aff4d..f8d65732dc 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -262,15 +262,6 @@ static const uint8_t sp804_ids[] = { static uint64_t sp804_read(void *opaque, hwaddr offset, unsigned size) { - SP804Timer *s = opaque; - - if (offset < 0x20) { - return arm_timer_read(&s->timer[0], offset, size); - } - if (offset < 0x40) { - return arm_timer_read(&s->timer[1], offset - 0x20, size); - } - /* TimerPeriphID */ if (offset >= 0xfe0 && offset <= 0xffc) { return sp804_ids[(offset - 0xfe0) >> 2]; @@ -294,18 +285,6 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, static void sp804_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - SP804Timer *s = opaque; - - if (offset < 0x20) { - arm_timer_write(&s->timer[0], offset, value, size); - return; - } - - if (offset < 0x40) { - arm_timer_write(&s->timer[1], offset - 0x20, value, size); - return; - } - /* Technically we could be writing to the Test Registers, but not likely */ qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %x\n", __func__, (int)offset); @@ -374,6 +353,8 @@ static void sp804_realize(DeviceState *dev, Error **errp) return; } sysbus_connect_irq(tmr, 0, qdev_get_gpio_in(DEVICE(&s->irq_orgate), i)); + memory_region_add_subregion_overlap(&s->iomem, 0x20 * i, + sysbus_mmio_get_region(tmr, 0), 1); } }