From patchwork Fri Jun 30 15:14:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 698234 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C22BDC001B3 for ; Fri, 30 Jun 2023 15:15:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232246AbjF3PPB (ORCPT ); Fri, 30 Jun 2023 11:15:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34610 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232539AbjF3POx (ORCPT ); Fri, 30 Jun 2023 11:14:53 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8CD9273B; Fri, 30 Jun 2023 08:14:51 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id F1B9F6606E97; Fri, 30 Jun 2023 16:14:46 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1688138090; bh=Ud2ruCQMrs0y4/oeVi64N6XaZrL6MD3Lu7ndY/b2YiA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=oV4l9VwNnlA+6P7wTMtXqsaQI6E6s2cCRXZXQO2tf10jEFXNyMUcdWWQjIqnvusRC Psi77XExouK9jQoH9LCginjP/8rdO8CSiF0e6wxltsNXXbrMEjckKO8wxQQujZ069w v23BibgGDwPQm2AMpieYhupSFyT3Iy322lfvI1dDJXag2NjcjU4Vdklzi+FQo+BjzY tOiT236bdjmzoW2OwxSz1N59WO2M5mHlqjwDWwXDHGBw8r1BfOz4uOsCT3CRHpl7bi Wff51jS2bRnkHbBuYLY6Yfd8utEGF6iXHFRjNjAjYx/bLAOLthWr70K6AIv1yOsXVw XaHbiDForOolA== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Andrew-CT Chen , Conor Dooley , Krzysztof Kozlowski , Mauro Carvalho Chehab , Rob Herring , Tiffany Lin , Yunfei Dong , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v5 1/7] media: dt-bindings: mediatek,vcodec: Allow single clock for mt8183 Date: Fri, 30 Jun 2023 11:14:07 -0400 Message-ID: <20230630151436.155586-2-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230630151436.155586-1-nfraprado@collabora.com> References: <20230630151436.155586-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org MT8173 and MT8183 have different clocks, and consequently clock-names. Relax the number of clocks and set clock-names based on compatible. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Reviewed-by: Krzysztof Kozlowski Signed-off-by: Nícolas F. R. A. Prado --- (no changes since v3) Changes in v3: - Reintroduced this commit from v1 since the active clock is no longer used. - Further constrained clocks as suggested in v1. .../media/mediatek,vcodec-decoder.yaml | 37 ++++++++++++++----- 1 file changed, 28 insertions(+), 9 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml index fad59b486d5d..1506d2693f7d 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml @@ -27,18 +27,12 @@ properties: maxItems: 1 clocks: + minItems: 1 maxItems: 8 clock-names: - items: - - const: vcodecpll - - const: univpll_d2 - - const: clk_cci400_sel - - const: vdec_sel - - const: vdecpll - - const: vencpll - - const: venc_lt_sel - - const: vdec_bus_clk_src + minItems: 1 + maxItems: 8 assigned-clocks: true @@ -88,6 +82,15 @@ allOf: required: - mediatek,scp + properties: + clocks: + minItems: 1 + maxItems: 1 + + clock-names: + items: + - const: vdec + - if: properties: compatible: @@ -99,6 +102,22 @@ allOf: required: - mediatek,vpu + properties: + clocks: + minItems: 8 + maxItems: 8 + + clock-names: + items: + - const: vcodecpll + - const: univpll_d2 + - const: clk_cci400_sel + - const: vdec_sel + - const: vdecpll + - const: vencpll + - const: venc_lt_sel + - const: vdec_bus_clk_src + additionalProperties: false examples: From patchwork Fri Jun 30 15:14:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 698384 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8600AEB64DD for ; Fri, 30 Jun 2023 15:15:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232267AbjF3PPA (ORCPT ); Fri, 30 Jun 2023 11:15:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34632 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232790AbjF3PO4 (ORCPT ); Fri, 30 Jun 2023 11:14:56 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFAE01FCB; Fri, 30 Jun 2023 08:14:55 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 14A546606E9D; Fri, 30 Jun 2023 16:14:50 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1688138094; bh=9a46aNnESj501/E03oYlm9sAjEXaazXllJOV13stIS8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=mN2fz2HIBrCFzuVGExEGiFCckflxkFPgk47NSQBsW/fp5IjkFDaC8+RoE2UmxFMDR 9kRn6U1onXpfrh0uOQJMQt9HmGj6fApXvbOxc5IjHZFFp9Ia4CTL4Yr2QAxAHbCDKB 1ERtxVQ0TPEiodTdayckWUUyU5kiL+ZaA8QSkZB1R4zHTKyaV96dLHvS+Cx6v85kMM AkVxQlUA5vtU0KYYxrIne41Iku2OGDLIp0Y5XUqx0ahDeA2hUzvGKXfzWYa7H09SxN W5i47XkK/F/e8aqZ7F6l1mTcHMZb/Awpf+/U8KwGsgzJN4D+FcsLXdpXmgPbz7SBhO i7xyXoCQgKZbw== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Andrew-CT Chen , Conor Dooley , Krzysztof Kozlowski , Mauro Carvalho Chehab , Rob Herring , Tiffany Lin , Yunfei Dong , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v5 2/7] media: dt-bindings: mediatek,vcodec: Don't require assigned-clocks Date: Fri, 30 Jun 2023 11:14:08 -0400 Message-ID: <20230630151436.155586-3-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230630151436.155586-1-nfraprado@collabora.com> References: <20230630151436.155586-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org On MT8183 it's not necessary to configure the parent for the clocks. Remove the assigned-clocks and assigned-clock-parents from the required list. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- (no changes since v1) .../devicetree/bindings/media/mediatek,vcodec-decoder.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml index 1506d2693f7d..1e56ece44aee 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml @@ -67,8 +67,6 @@ required: - clocks - clock-names - iommus - - assigned-clocks - - assigned-clock-parents allOf: - if: From patchwork Fri Jun 30 15:14:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 698233 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42D1BEB64D7 for ; Fri, 30 Jun 2023 15:15:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232927AbjF3PPF (ORCPT ); Fri, 30 Jun 2023 11:15:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34652 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232287AbjF3PPA (ORCPT ); Fri, 30 Jun 2023 11:15:00 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E2FCF273B; Fri, 30 Jun 2023 08:14:58 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id BB8CA6606E8F; Fri, 30 Jun 2023 16:14:54 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1688138097; bh=oehAssFz6HAeQ18vLi/DNl45rJUtL7SfPUb+CugYsgA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LjenjVT8x02X5Wo0J0gQVKMdrn7KPbNZe5TdqpzE8N9uSXVuzSAo7RdtVWKEdodv5 AxBF3Y/aaaOyE3H98BxTwiDOlsgXv87xs11HUGNfF2KQnoz0fiOAJZcbR4IU0uVLal MYdfmjNfl1QjllztRWsS1GMwuQhR81paUtgQoaE+s+w8GL+OntScy2ejXhLx8ZziT0 q7uhxdBOFsF8g0DHAhfX42r4LSFIHU28AlG+vGMMAHJEi1Nbhu3Md21HGK1/fPSwQz /WOQKJpalRNTHdOeO1dMbONIwLy6o2cRyNN8I7owOYtSLb9CzQ0mzZ0canXGp59VmS ofdrcY4X7CnAg== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Andrew-CT Chen , Conor Dooley , Krzysztof Kozlowski , Mauro Carvalho Chehab , Rob Herring , Tiffany Lin , Yunfei Dong , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v5 3/7] media: dt-bindings: mediatek,vcodec: Remove VDEC_SYS register space Date: Fri, 30 Jun 2023 11:14:09 -0400 Message-ID: <20230630151436.155586-4-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230630151436.155586-1-nfraprado@collabora.com> References: <20230630151436.155586-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The binding expects the first register space to be VDEC_SYS. However this register space is already assigned to a different node on both MT8173 and MT8183: a clock-controller node called 'vdecsys' which is also a syscon. In order to resolve the overlapping address ranges, remove the VDEC_SYS register space from the video decoder, and add a new property to hold the phandle to the syscon, so that iospace can still be handled. Also add reg-names to be able to tell that this new register schema is used, so the driver can keep backward compatibility. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: Krzysztof Kozlowski --- (no changes since v4) Changes in v4: - Removed VDEC_SYS reg from mt8173 as well - Reworded commit Changes in v3: - Removed the active clock - Added a mediatek,vdecsys syscon property Changes in v2: - Merged with patch 1 (media: dt-bindings: mediatek,vcodec: Allow single clock for mt8183) to avoid changing number of clocks twice - Added maxItems to reg-names - Constrained clocks for each compatible - Reordered properties for each compatible .../media/mediatek,vcodec-decoder.yaml | 28 ++++++++++++++++--- 1 file changed, 24 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml index 1e56ece44aee..b401c67e3ba0 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml @@ -21,7 +21,22 @@ properties: - mediatek,mt8183-vcodec-dec reg: - maxItems: 12 + minItems: 11 + maxItems: 11 + + reg-names: + items: + - const: misc + - const: ld + - const: top + - const: cm + - const: ad + - const: av + - const: pp + - const: hwd + - const: hwq + - const: hwb + - const: hwg interrupts: maxItems: 1 @@ -60,6 +75,10 @@ properties: description: Describes point to scp. + mediatek,vdecsys: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the vdecsys syscon node. + required: - compatible - reg @@ -67,6 +86,7 @@ required: - clocks - clock-names - iommus + - mediatek,vdecsys allOf: - if: @@ -126,10 +146,9 @@ examples: #include #include - vcodec_dec: vcodec@16000000 { + vcodec_dec: vcodec@16020000 { compatible = "mediatek,mt8173-vcodec-dec"; - reg = <0x16000000 0x100>, /*VDEC_SYS*/ - <0x16020000 0x1000>, /*VDEC_MISC*/ + reg = <0x16020000 0x1000>, /*VDEC_MISC*/ <0x16021000 0x800>, /*VDEC_LD*/ <0x16021800 0x800>, /*VDEC_TOP*/ <0x16022000 0x1000>, /*VDEC_CM*/ @@ -150,6 +169,7 @@ examples: <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, <&iommu M4U_PORT_HW_VDEC_VLD2_EXT>; mediatek,vpu = <&vpu>; + mediatek,vdecsys = <&vdecsys>; power-domains = <&scpsys MT8173_POWER_DOMAIN_VDEC>; clocks = <&apmixedsys CLK_APMIXED_VCODECPLL>, <&topckgen CLK_TOP_UNIVPLL_D2>, From patchwork Fri Jun 30 15:14:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 698382 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5EA04EB64DA for ; Fri, 30 Jun 2023 15:15:11 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232210AbjF3PPJ (ORCPT ); Fri, 30 Jun 2023 11:15:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34696 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232762AbjF3PPE (ORCPT ); Fri, 30 Jun 2023 11:15:04 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C9D5D35A6; Fri, 30 Jun 2023 08:15:02 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 3DF3E6606E97; Fri, 30 Jun 2023 16:14:58 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1688138101; bh=tcKN7V8jMwtJgXP8lIYDvUvaVxlTOIgSGTz9xCOpjsE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=d/aAyYSmIBa5KAv+QEzgrw1/k4ttW/5EKTk8U3srrHGpLEBI0R3HuOhFpa9sE0skj j6vJ2sKO9t9B2gXTTn1w0U58UMIdTPR76ATQgVaGFiHD2aMeL7vQ8Eu4tKdFugmJNE AxKr7tSCDMQSGh3zE61Eh3gw9ow+K6skcdPLSmwvd2HI/+0xOKJzs4FUW9EM6AdEcf hdYWe3tvOnLAnlJfO3wMfl7KkqiEcRnZG3VHn6aN+2DHC8zW/tghjLa6CLSec/FxEn akRfYWRNZKJTZSklrd+Bs4wdfKIcwx/q8rfH1mSy2Pup+D4TiCgmYOPUi56sDPbaeI 1M5gNEtdQ4L5g== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Andrew-CT Chen , Mauro Carvalho Chehab , Tiffany Lin , Yunfei Dong , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v5 4/7] media: mediatek: vcodec: Define address for VDEC_HW_ACTIVE Date: Fri, 30 Jun 2023 11:14:10 -0400 Message-ID: <20230630151436.155586-5-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230630151436.155586-1-nfraprado@collabora.com> References: <20230630151436.155586-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The VDEC_HW_ACTIVE bit is located at offset 0, bit 4 of the VDECSYS iospace. Only the mask was previously defined, with the address being implicit. Explicitly define the address, and append a '_MASK' suffix to the mask, to make accesses to this bit clearer. This commit brings no functional change. Signed-off-by: Nícolas F. R. A. Prado --- (no changes since v4) Changes in v4: - Made use of BIT() macro for mask Changes in v3: - Added this commit drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c | 4 ++-- drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c | 4 ++-- drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.h | 3 ++- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c index d41f2121b94f..83780d29a9cf 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c @@ -50,8 +50,8 @@ static irqreturn_t mtk_vcodec_dec_irq_handler(int irq, void *priv) ctx = mtk_vcodec_get_curr_ctx(dev, MTK_VDEC_CORE); /* check if HW active or not */ - cg_status = readl(dev->reg_base[0]); - if ((cg_status & VDEC_HW_ACTIVE) != 0) { + cg_status = readl(dev->reg_base[0] + VDEC_HW_ACTIVE_ADDR); + if ((cg_status & VDEC_HW_ACTIVE_MASK) != 0) { mtk_v4l2_err("DEC ISR, VDEC active is not 0x0 (0x%08x)", cg_status); return IRQ_HANDLED; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c index e1cb2f8dca33..41aa66c7295b 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.c @@ -75,8 +75,8 @@ static irqreturn_t mtk_vdec_hw_irq_handler(int irq, void *priv) ctx = mtk_vcodec_get_curr_ctx(dev->main_dev, dev->hw_idx); /* check if HW active or not */ - cg_status = readl(dev->reg_base[VDEC_HW_SYS]); - if (cg_status & VDEC_HW_ACTIVE) { + cg_status = readl(dev->reg_base[VDEC_HW_SYS] + VDEC_HW_ACTIVE_ADDR); + if (cg_status & VDEC_HW_ACTIVE_MASK) { mtk_v4l2_err("vdec active is not 0x0 (0x%08x)", cg_status); return IRQ_HANDLED; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.h b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.h index 36faa8d9d681..ff250e3be78e 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_hw.h @@ -12,7 +12,8 @@ #include "mtk_vcodec_drv.h" -#define VDEC_HW_ACTIVE 0x10 +#define VDEC_HW_ACTIVE_ADDR 0x0 +#define VDEC_HW_ACTIVE_MASK BIT(4) #define VDEC_IRQ_CFG 0x11 #define VDEC_IRQ_CLR 0x10 #define VDEC_IRQ_CFG_REG 0xa4 From patchwork Fri Jun 30 15:14:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 698232 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9632EB64DC for ; Fri, 30 Jun 2023 15:15:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232598AbjF3PPc (ORCPT ); Fri, 30 Jun 2023 11:15:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34708 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232539AbjF3PPX (ORCPT ); Fri, 30 Jun 2023 11:15:23 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D75F93C06; Fri, 30 Jun 2023 08:15:05 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id CB52E6606E8F; Fri, 30 Jun 2023 16:15:01 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1688138104; bh=rJJtwW4PzmZJfVp32PC1meEKziFvUtXx6MtiCW+GUKc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=EPISfpTuPEaBvjiuNdoFViybU+KZKWfhbedynHOpuEAB3+waGY8V3zqNwYy5u4rlg vG7Z2ZZwFE3iLhxXdndY62S/lKw7m+QvcSKyZjNrNYmP37kYSHl6I96fwO4XRU4w+D wXia77mWAarXdYhKTFArXPkQc+Lx0EWTp5IiAQYBcMlqDrlBKobtORrKM26l9z+J31 PGV4d23oV61flg/xTh9pkWZU6GC5hWsSt03lJgpR/IVOsm0vvscc5Q5lw/JTESxWWd aQOtGWQp52VOII/bkfyAgTPaM8u39daLraMrIGhIULxMwl3k5jY1po46OSAtJJmdBf uBEw/P32PLCtw== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Andrew-CT Chen , Mauro Carvalho Chehab , Tiffany Lin , Yunfei Dong , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v5 5/7] media: mediatek: vcodec: Read HW active status from syscon Date: Fri, 30 Jun 2023 11:14:11 -0400 Message-ID: <20230630151436.155586-6-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230630151436.155586-1-nfraprado@collabora.com> References: <20230630151436.155586-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Remove the requirement of a VDEC_SYS reg iospace for both MT8173 and MT8183. To achieve that, rely on a vdecsys syscon to be passed through the DT, and use it to directly read the VDEC_HW_ACTIVE bit during IRQ handling to check whether the HW is active. Also update the VP8 stateful decoder to use the syscon, if present, for writes to VDEC_SYS. The old behavior is still present when reg-names aren't supplied, as to keep backward compatibility. Signed-off-by: Nícolas F. R. A. Prado --- Changes in v5: - Added explicit linux/bitfield.h include for FIELD_GET(), following 0day report Changes in v4: - Added new helper and updated VP8 stateful decoder to use it, so the syscon can also be used by mt8173 - Made handling cleaner - Reworded commit Changes in v3: - Switched handling of VDEC_HW_ACTIVE to use a syscon instead of the 'active' clock - Reworded commit - Removed changes to subdev part of driver, since they aren't used by MT8183 .../mediatek/vcodec/mtk_vcodec_dec_drv.c | 77 ++++++++++++++++--- .../platform/mediatek/vcodec/mtk_vcodec_drv.h | 1 + .../mediatek/vcodec/mtk_vcodec_util.c | 15 ++++ .../mediatek/vcodec/mtk_vcodec_util.h | 2 + .../mediatek/vcodec/vdec/vdec_vp8_if.c | 10 +-- 5 files changed, 87 insertions(+), 18 deletions(-) diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c index 83780d29a9cf..742b6903d030 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_dec_drv.c @@ -5,13 +5,16 @@ * Tiffany Lin */ +#include #include #include #include +#include #include #include #include #include +#include #include #include #include @@ -38,22 +41,30 @@ static int mtk_vcodec_get_hw_count(struct mtk_vcodec_dev *dev) } } +static bool mtk_vcodec_is_hw_active(struct mtk_vcodec_dev *dev) +{ + u32 cg_status; + + if (dev->vdecsys_regmap) + return !regmap_test_bits(dev->vdecsys_regmap, VDEC_HW_ACTIVE_ADDR, + VDEC_HW_ACTIVE_MASK); + + cg_status = readl(dev->reg_base[VDEC_SYS] + VDEC_HW_ACTIVE_ADDR); + return !FIELD_GET(VDEC_HW_ACTIVE_MASK, cg_status); +} + static irqreturn_t mtk_vcodec_dec_irq_handler(int irq, void *priv) { struct mtk_vcodec_dev *dev = priv; struct mtk_vcodec_ctx *ctx; - u32 cg_status = 0; unsigned int dec_done_status = 0; void __iomem *vdec_misc_addr = dev->reg_base[VDEC_MISC] + VDEC_IRQ_CFG_REG; ctx = mtk_vcodec_get_curr_ctx(dev, MTK_VDEC_CORE); - /* check if HW active or not */ - cg_status = readl(dev->reg_base[0] + VDEC_HW_ACTIVE_ADDR); - if ((cg_status & VDEC_HW_ACTIVE_MASK) != 0) { - mtk_v4l2_err("DEC ISR, VDEC active is not 0x0 (0x%08x)", - cg_status); + if (!mtk_vcodec_is_hw_active(dev)) { + mtk_v4l2_err("DEC ISR, VDEC active is not 0x0"); return IRQ_HANDLED; } @@ -82,6 +93,33 @@ static int mtk_vcodec_get_reg_bases(struct mtk_vcodec_dev *dev) { struct platform_device *pdev = dev->plat_dev; int reg_num, i; + struct resource *res; + bool has_vdecsys_reg; + static const char * const mtk_dec_reg_names[] = { + "misc", + "ld", + "top", + "cm", + "ad", + "av", + "pp", + "hwd", + "hwq", + "hwb", + "hwg" + }; + + /* + * If we have reg-names in devicetree, this means that we're on a new + * register organization, which implies that the VDEC_SYS iospace gets + * R/W through a syscon (regmap). + * Here we try to get the "misc" iostart only to check if we have reg-names + */ + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "misc"); + if (res) + has_vdecsys_reg = false; + else + has_vdecsys_reg = true; /* Sizeof(u32) * 4 bytes for each register base. */ reg_num = of_property_count_elems_of_size(pdev->dev.of_node, "reg", @@ -91,12 +129,29 @@ static int mtk_vcodec_get_reg_bases(struct mtk_vcodec_dev *dev) return -EINVAL; } - for (i = 0; i < reg_num; i++) { - dev->reg_base[i] = devm_platform_ioremap_resource(pdev, i); - if (IS_ERR(dev->reg_base[i])) - return PTR_ERR(dev->reg_base[i]); + if (has_vdecsys_reg) { + for (i = 0; i < reg_num; i++) { + dev->reg_base[i] = devm_platform_ioremap_resource(pdev, i); + if (IS_ERR(dev->reg_base[i])) + return PTR_ERR(dev->reg_base[i]); + + mtk_v4l2_debug(2, "reg[%d] base=%p", i, dev->reg_base[i]); + } + } else { + for (i = 0; i < reg_num; i++) { + dev->reg_base[i+1] = devm_platform_ioremap_resource_byname(pdev, mtk_dec_reg_names[i]); + if (IS_ERR(dev->reg_base[i+1])) + return PTR_ERR(dev->reg_base[i+1]); - mtk_v4l2_debug(2, "reg[%d] base=%p", i, dev->reg_base[i]); + mtk_v4l2_debug(2, "reg[%d] base=%p", i+1, dev->reg_base[i+1]); + } + + dev->vdecsys_regmap = syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "mediatek,vdecsys"); + if (IS_ERR(dev->vdecsys_regmap)) { + dev_err(&pdev->dev, "Missing mediatek,vdecsys property"); + return PTR_ERR(dev->vdecsys_regmap); + } } return 0; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h index f17d67e781c9..0b430936f67d 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_drv.h @@ -489,6 +489,7 @@ struct mtk_vcodec_dev { void __iomem *reg_base[NUM_MAX_VCODEC_REG_BASE]; const struct mtk_vcodec_dec_pdata *vdec_pdata; const struct mtk_vcodec_enc_pdata *venc_pdata; + struct regmap *vdecsys_regmap; struct mtk_vcodec_fw *fw_handler; diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c index f214e6f67005..8aaa5eb45444 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.c @@ -8,6 +8,7 @@ #include #include #include +#include #include "mtk_vcodec_dec_hw.h" #include "mtk_vcodec_drv.h" @@ -34,6 +35,20 @@ void __iomem *mtk_vcodec_get_reg_addr(struct mtk_vcodec_ctx *data, } EXPORT_SYMBOL(mtk_vcodec_get_reg_addr); +int mtk_vcodec_write_vdecsys(struct mtk_vcodec_ctx *ctx, unsigned int reg, + unsigned int val) +{ + struct mtk_vcodec_dev *dev = ctx->dev; + + if (dev->vdecsys_regmap) + return regmap_write(dev->vdecsys_regmap, reg, val); + + writel(val, dev->reg_base[VDEC_SYS] + reg); + + return 0; +} +EXPORT_SYMBOL(mtk_vcodec_write_vdecsys); + int mtk_vcodec_mem_alloc(struct mtk_vcodec_ctx *data, struct mtk_vcodec_mem *mem) { diff --git a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h index 88d389b65f13..c8bb4fc5153f 100644 --- a/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h +++ b/drivers/media/platform/mediatek/vcodec/mtk_vcodec_util.h @@ -70,6 +70,8 @@ extern int mtk_vcodec_dbg; void __iomem *mtk_vcodec_get_reg_addr(struct mtk_vcodec_ctx *data, unsigned int reg_idx); +int mtk_vcodec_write_vdecsys(struct mtk_vcodec_ctx *ctx, unsigned int reg, + unsigned int val); int mtk_vcodec_mem_alloc(struct mtk_vcodec_ctx *data, struct mtk_vcodec_mem *mem); void mtk_vcodec_mem_free(struct mtk_vcodec_ctx *data, diff --git a/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_if.c b/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_if.c index 88c046731754..2592fa37b4c8 100644 --- a/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_if.c +++ b/drivers/media/platform/mediatek/vcodec/vdec/vdec_vp8_if.c @@ -91,7 +91,6 @@ struct vdec_vp8_vsi { /** * struct vdec_vp8_hw_reg_base - HW register base - * @sys : base address for sys * @misc : base address for misc * @ld : base address for ld * @top : base address for top @@ -100,7 +99,6 @@ struct vdec_vp8_vsi { * @hwb : base address for hwb */ struct vdec_vp8_hw_reg_base { - void __iomem *sys; void __iomem *misc; void __iomem *ld; void __iomem *top; @@ -170,7 +168,6 @@ static void get_hw_reg_base(struct vdec_vp8_inst *inst) inst->reg_base.top = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_TOP); inst->reg_base.cm = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_CM); inst->reg_base.hwd = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_HWD); - inst->reg_base.sys = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_SYS); inst->reg_base.misc = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_MISC); inst->reg_base.ld = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_LD); inst->reg_base.hwb = mtk_vcodec_get_reg_addr(inst->ctx, VDEC_HWB); @@ -222,17 +219,16 @@ static void read_hw_segmentation_data(struct vdec_vp8_inst *inst) static void enable_hw_rw_function(struct vdec_vp8_inst *inst) { u32 val = 0; - void __iomem *sys = inst->reg_base.sys; void __iomem *misc = inst->reg_base.misc; void __iomem *ld = inst->reg_base.ld; void __iomem *hwb = inst->reg_base.hwb; void __iomem *hwd = inst->reg_base.hwd; - writel(0x1, sys + VP8_RW_CKEN_SET); + mtk_vcodec_write_vdecsys(inst->ctx, VP8_RW_CKEN_SET, 0x1); writel(0x101, ld + VP8_WO_VLD_SRST); writel(0x101, hwb + VP8_WO_VLD_SRST); - writel(1, sys); + mtk_vcodec_write_vdecsys(inst->ctx, 0, 0x1); val = readl(misc + VP8_RW_MISC_SRST); writel((val & 0xFFFFFFFE), misc + VP8_RW_MISC_SRST); @@ -241,7 +237,7 @@ static void enable_hw_rw_function(struct vdec_vp8_inst *inst) writel(0x71201100, misc + VP8_RW_MISC_FUNC_CON); writel(0x0, ld + VP8_WO_VLD_SRST); writel(0x0, hwb + VP8_WO_VLD_SRST); - writel(0x1, sys + VP8_RW_DCM_CON); + mtk_vcodec_write_vdecsys(inst->ctx, VP8_RW_DCM_CON, 0x1); writel(0x1, misc + VP8_RW_MISC_DCM_CON); writel(0x1, hwd + VP8_RW_VP8_CTRL); }