From patchwork Fri Jun 30 12:10:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: zelong dong X-Patchwork-Id: 698145 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A6F83EB64D7 for ; Fri, 30 Jun 2023 12:12:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232599AbjF3MM1 (ORCPT ); Fri, 30 Jun 2023 08:12:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233060AbjF3MMK (ORCPT ); Fri, 30 Jun 2023 08:12:10 -0400 Received: from mail-sh.amlogic.com (mail-sh.amlogic.com [58.32.228.43]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5DBFF3C07; Fri, 30 Jun 2023 05:11:14 -0700 (PDT) Received: from droid10-sz.amlogic.com (10.28.11.69) by mail-sh.amlogic.com (10.18.11.5) with Microsoft SMTP Server id 15.1.2507.13; Fri, 30 Jun 2023 20:11:11 +0800 From: zelong dong To: , , , Rob Herring , CC: , , , , , , Zelong Dong Subject: [PATCH 3/3] arm64: dts: meson: add reset controller for Meson-C3 SoC Date: Fri, 30 Jun 2023 20:10:59 +0800 Message-ID: <20230630121059.28748-4-zelong.dong@amlogic.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20230630121059.28748-1-zelong.dong@amlogic.com> References: <20230630121059.28748-1-zelong.dong@amlogic.com> MIME-Version: 1.0 X-Originating-IP: [10.28.11.69] Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Zelong Dong Add the reset controller device of Meson-C3 SoC family Signed-off-by: Zelong Dong --- arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi index 60ad4f3eef9d..62684b7a684c 100644 --- a/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi +++ b/arch/arm64/boot/dts/amlogic/amlogic-c3.dtsi @@ -6,6 +6,7 @@ #include #include #include +#include / { cpus { @@ -82,6 +83,12 @@ uart_b: serial@7a000 { clock-names = "xtal", "pclk", "baud"; }; + reset: reset-controller@0x2000 { + compatible = "amlogic,meson-c3-reset"; + reg = <0x0 0x2000 0x0 0x98>; + #reset-cells = <1>; + }; + }; }; };