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Wed, 21 Jun 2023 10:37:49 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000EE32.mail.protection.outlook.com (10.167.242.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6521.17 via Frontend Transport; Wed, 21 Jun 2023 10:37:49 +0000 Received: from sanjuamdntb2.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.23; Wed, 21 Jun 2023 05:37:46 -0500 From: Sanjay R Mehta To: , , , CC: , Sanath S , Sanjay R Mehta Subject: [PATCH Internal] thunderbolt: Remove enabling/disabling TMU based on CLx Date: Wed, 21 Jun 2023 05:37:22 -0500 Message-ID: <1687343842-17881-1-git-send-email-Sanju.Mehta@amd.com> X-Mailer: git-send-email 2.7.4 MIME-Version: 1.0 X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EE32:EE_|DM4PR12MB6230:EE_ X-MS-Office365-Filtering-Correlation-Id: 00dfbdd1-ccdf-4942-b14d-08db72438f3e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Jun 2023 10:37:49.3589 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 00dfbdd1-ccdf-4942-b14d-08db72438f3e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EE32.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6230 Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Sanath S Since TMU is enabled by default on Intel SOCs for USB4 before Alpine Ridge, explicit enabling or disabling of TMU is not required. However, the current implementation of enabling or disabling TMU based on CLx state is inadequate as not all SOCs with CLx disabled have TMU enabled by default, such as AMD Yellow Carp and Pink Sardine. To address this, a quirk named "QUIRK_TMU_DEFAULT_ENABLED" is implemented to skip the enabling or disabling of TMU for SOCs where it is already enabled by default, such as Intel SOCs prior to Alpine Ridge. Fixes: 7af9da8ce8f9 ("thunderbolt: Add quirk to disable CLx") Signed-off-by: Sanjay R Mehta Signed-off-by: Sanath S --- drivers/thunderbolt/tb.c | 4 ++++ drivers/thunderbolt/tb.h | 2 ++ drivers/thunderbolt/tmu.c | 6 ++++++ 3 files changed, 12 insertions(+) diff --git a/drivers/thunderbolt/tb.c b/drivers/thunderbolt/tb.c index aa6e11589c28..5fa9fbf095d2 100644 --- a/drivers/thunderbolt/tb.c +++ b/drivers/thunderbolt/tb.c @@ -923,6 +923,10 @@ static void tb_scan_port(struct tb_port *port) tb_switch_lane_bonding_enable(sw); /* Set the link configured */ tb_switch_configure_link(sw); + /* On Alpine Ridge and earlier Platforms, the TMU mode is enabled by default */ + if (sw->generation < 4 || tb_switch_is_tiger_lake(sw)) + sw->quirks |= QUIRK_TMU_DEFAULT_ENABLED; + /* * CL0s and CL1 are enabled and supported together. * Silently ignore CLx enabling in case CLx is not supported. diff --git a/drivers/thunderbolt/tb.h b/drivers/thunderbolt/tb.h index 58df106aaa5e..9252d3875c08 100644 --- a/drivers/thunderbolt/tb.h +++ b/drivers/thunderbolt/tb.h @@ -27,6 +27,8 @@ #define QUIRK_FORCE_POWER_LINK_CONTROLLER BIT(0) /* Disable CLx if not supported */ #define QUIRK_NO_CLX BIT(1) +/* TMU enabled by default */ +#define QUIRK_TMU_DEFAULT_ENABLED BIT(2) /** * struct tb_nvm - Structure holding NVM information diff --git a/drivers/thunderbolt/tmu.c b/drivers/thunderbolt/tmu.c index c926fb71c43d..8e38ab5aae15 100644 --- a/drivers/thunderbolt/tmu.c +++ b/drivers/thunderbolt/tmu.c @@ -387,6 +387,9 @@ int tb_switch_tmu_disable(struct tb_switch *sw) if (sw->tmu.rate == TB_SWITCH_TMU_RATE_OFF) return 0; + if (sw->quirks & QUIRK_TMU_DEFAULT_ENABLED) + return 0; + if (tb_route(sw)) { bool unidirectional = sw->tmu.unidirectional; struct tb_port *down, *up; @@ -643,6 +646,9 @@ int tb_switch_tmu_enable(struct tb_switch *sw) if (tb_switch_tmu_is_enabled(sw)) return 0; + if (sw->quirks & QUIRK_TMU_DEFAULT_ENABLED) + return 0; + if (tb_switch_is_titan_ridge(sw) && unidirectional) { ret = tb_switch_tmu_disable_objections(sw); if (ret)