From patchwork Thu Jun 22 23:48:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan McCann X-Patchwork-Id: 695807 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE574EB64DD for ; Thu, 22 Jun 2023 23:50:40 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230217AbjFVXuk (ORCPT ); Thu, 22 Jun 2023 19:50:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231791AbjFVXui (ORCPT ); Thu, 22 Jun 2023 19:50:38 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B7BBD2134; Thu, 22 Jun 2023 16:50:33 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35MNkVIK020414; Thu, 22 Jun 2023 23:50:27 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=lIhoZGAhJ7XsQZAtBGo4LFt5rsbPEq2Ckf9pnUGIVn0=; b=hmGSo1Q76srNJEnSNy8eQLigLfv8NeD5gPW371yihMNWbbwTw3GndtnpU3g8oLnDjqUo KkK2icLnCFz0+oi9w7Uf938Hex3lUgUvvF6LaThhXRJrtVPT+6ImmmQbcPO8jzI0cqbh QCo7YsnqlbYJ5Fvsw26JHzmAngTH4EHiyqE2H/qbuMjM87qE1g0uRR5xW1HGM6ltGtFp KyBHGt9gLbXin6lcfXsDby4wqrPgL77Bf02rMmWimLtwVsSOlMGpwUHQ1MhwsJM8UfKe 5XJ5lgv1HYGMtcia+UrW9UA3uLOXtmsMdGHn0tpfwNMkxYxHSs/jC0MEwMMUhFqZQ4DI qQ== Received: from nalasppmta02.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3rbvr1n213-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 22 Jun 2023 23:50:26 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35MNoPIS024820 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 22 Jun 2023 23:50:25 GMT Received: from hu-rmccann-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 22 Jun 2023 16:50:25 -0700 From: Ryan McCann Date: Thu, 22 Jun 2023 16:48:53 -0700 Subject: [PATCH 1/6] drm/msm: Update dev core dump to not print backwards MIME-Version: 1.0 Message-ID: <20230622-devcoredump_patch-v1-1-3b2cdcc6a576@quicinc.com> References: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> In-Reply-To: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter CC: Rob Clark , , , , , , Ryan McCann X-Mailer: b4 0.13-dev-8a804 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687477824; l=1114; i=quic_rmccann@quicinc.com; s=20230622; h=from:subject:message-id; bh=tjR+HLDFmB85BQB6KVcriTx2yw4Rbgv0sxiN8pqj+Ig=; b=rFrMJIcJWApV7dquRySW1oVwlR+R+25u+XFOxmgbwkpil9sgq9tfzaICbeoNJUGAJ5HB+hFfM rtjI3irH2x5DMFmDqnD3X19jEtAo1vRGAfsxdMEK/bW//c4DzD59zwJ X-Developer-Key: i=quic_rmccann@quicinc.com; a=ed25519; pk=d/uP3OwPGpj/bTtiHvV1RBZ2S6q4AL6j1+A5y+dmbTI= X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: qDoNvMzwhSG9Q0TIo_nuawxdfphYTvVE X-Proofpoint-ORIG-GUID: qDoNvMzwhSG9Q0TIo_nuawxdfphYTvVE X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-22_17,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 spamscore=0 mlxlogscore=851 lowpriorityscore=0 priorityscore=1501 suspectscore=0 impostorscore=0 phishscore=0 mlxscore=0 bulkscore=0 malwarescore=0 clxscore=1015 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306220205 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Device core dump add block method adds hardware blocks to dumping queue with stack behavior which causes the hardware blocks to be printed in reverse order. Change the addition to dumping queue data structure from "list_add" to "list_add_tail" for FIFO queue behavior. Fixes: 98659487b845 ("drm/msm: add support to take dpu snapshot") Signed-off-by: Ryan McCann --- drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c b/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c index acfe1b31e079..add72bbc28b1 100644 --- a/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c +++ b/drivers/gpu/drm/msm/disp/msm_disp_snapshot_util.c @@ -192,5 +192,5 @@ void msm_disp_snapshot_add_block(struct msm_disp_state *disp_state, u32 len, new_blk->base_addr = base_addr; msm_disp_state_dump_regs(&new_blk->state, new_blk->size, base_addr); - list_add(&new_blk->node, &disp_state->blocks); + list_add_tail(&new_blk->node, &disp_state->blocks); } From patchwork Thu Jun 22 23:48:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan McCann X-Patchwork-Id: 695805 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E0EFDC001B3 for ; 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Thu, 22 Jun 2023 16:50:25 -0700 From: Ryan McCann Date: Thu, 22 Jun 2023 16:48:54 -0700 Subject: [PATCH 2/6] drm/msm/dpu: Drop unused num argument from relevant macros MIME-Version: 1.0 Message-ID: <20230622-devcoredump_patch-v1-2-3b2cdcc6a576@quicinc.com> References: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> In-Reply-To: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter CC: Rob Clark , , , , , , Ryan McCann X-Mailer: b4 0.13-dev-8a804 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687477824; l=3156; i=quic_rmccann@quicinc.com; s=20230622; h=from:subject:message-id; bh=xnnvBmJsnPioeYV/gxXjc7nSiJ8GbxL3usFhUJXby4k=; b=F6ib4glqR7E+3GyOHjJDplcwZhzQ+q02iPSAwTQJeu12eLCTBcmXlvz3xfM1/udEqlQ/EMrGJ p2ECI6mw8iTD5gS9LmQWWM0dnWw5zRAKjAmGx5pFE/w5E33V5Lt0zbJ X-Developer-Key: i=quic_rmccann@quicinc.com; a=ed25519; pk=d/uP3OwPGpj/bTtiHvV1RBZ2S6q4AL6j1+A5y+dmbTI= X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: mF8JxMUBUzwgyk7jTQ2g8JUy6BCbjC7k X-Proofpoint-ORIG-GUID: mF8JxMUBUzwgyk7jTQ2g8JUy6BCbjC7k X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-22_17,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 suspectscore=0 bulkscore=0 mlxscore=0 malwarescore=0 mlxlogscore=806 spamscore=0 impostorscore=0 clxscore=1015 phishscore=0 lowpriorityscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306220205 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop unused parameter "num" from VIG_SBLK_NOSCALE and DMA sub block macros. Update calls to relevant macros to reflect change. Signed-off-by: Ryan McCann --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 0de507d4d7b7..69200b4cf210 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -288,7 +288,7 @@ static const uint32_t wb2_formats[] = { .rotation_cfg = rot_cfg, \ } -#define _DMA_SBLK(num, sdma_pri) \ +#define _DMA_SBLK(sdma_pri) \ { \ .maxdwnscale = SSPP_UNITY_SCALE, \ .maxupscale = SSPP_UNITY_SCALE, \ @@ -323,10 +323,10 @@ static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1); +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2); +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK(3); +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4); #define SSPP_BLK(_name, _id, _base, _len, _features, \ _sblk, _xinid, _type, _clkctrl) \ @@ -365,11 +365,11 @@ static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 = static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 = _VIG_SBLK("2", 9, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 = - _VIG_SBLK("3", 10, DPU_SSPP_SCALER_QSEED4); -static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK("12", 5); -static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK("13", 6); + _VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4); +static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5); +static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK(6); -#define _VIG_SBLK_NOSCALE(num, sdma_pri) \ +#define _VIG_SBLK_NOSCALE(sdma_pri) \ { \ .maxdwnscale = SSPP_UNITY_SCALE, \ .maxupscale = SSPP_UNITY_SCALE, \ @@ -380,8 +380,8 @@ static const struct dpu_sspp_sub_blks sm8550_dma_sblk_5 = _DMA_SBLK("13", 6); .virt_num_formats = ARRAY_SIZE(plane_formats), \ } -static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE("0", 2); -static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK("8", 1); +static const struct dpu_sspp_sub_blks qcm2290_vig_sblk_0 = _VIG_SBLK_NOSCALE(2); +static const struct dpu_sspp_sub_blks qcm2290_dma_sblk_0 = _DMA_SBLK(1); /************************************************************* * MIXER sub blocks config From patchwork Thu Jun 22 23:48:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan McCann X-Patchwork-Id: 694939 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id ABBB4EB64DD for ; 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Thu, 22 Jun 2023 16:50:26 -0700 From: Ryan McCann Date: Thu, 22 Jun 2023 16:48:55 -0700 Subject: [PATCH 3/6] drm/msm/dpu: Define names for unnamed sblks MIME-Version: 1.0 Message-ID: <20230622-devcoredump_patch-v1-3-3b2cdcc6a576@quicinc.com> References: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> In-Reply-To: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter CC: Rob Clark , , , , , , Ryan McCann X-Mailer: b4 0.13-dev-8a804 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687477824; l=3066; i=quic_rmccann@quicinc.com; s=20230622; h=from:subject:message-id; bh=lNOMoAT8r4NJwr47/9QKubUDQvUqJC9SfNtvattQY1w=; b=q60r/Cug5vJB9V27Z1tJ4rZLRzWnoDRW5ByBaZpaG9mnSVvJgjbdwBn7CUClo2lbgS4Mly9Tg HRdFq7mNcBqAuzt7IIluFy/cjNcQSfwt3mr95OyaJbhWxXdlw+KYyyu X-Developer-Key: i=quic_rmccann@quicinc.com; a=ed25519; pk=d/uP3OwPGpj/bTtiHvV1RBZ2S6q4AL6j1+A5y+dmbTI= X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: hJXBELlhKtNKMhOcO4M_5QAnFGRgGVmP X-Proofpoint-GUID: hJXBELlhKtNKMhOcO4M_5QAnFGRgGVmP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-22_17,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 malwarescore=0 spamscore=0 phishscore=0 suspectscore=0 priorityscore=1501 mlxlogscore=919 lowpriorityscore=0 impostorscore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306220205 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Some sub blocks in the hw catalog have not been given a name, so when the registers from that block are dumped, there is no name to reference. Define names for relevant sub blocks to fix this. Signed-off-by: Ryan McCann --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 69200b4cf210..8349ecda1f3c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -444,12 +444,12 @@ static const struct dpu_lm_sub_blks qcm2290_lm_sblk = { * DSPP sub blocks config *************************************************************/ static const struct dpu_dspp_sub_blks msm8998_dspp_sblk = { - .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, + .pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700, .len = 0x90, .version = 0x10007}, }; static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { - .pcc = {.id = DPU_DSPP_PCC, .base = 0x1700, + .pcc = {.name = "pcc", .id = DPU_DSPP_PCC, .base = 0x1700, .len = 0x90, .version = 0x40000}, }; @@ -465,19 +465,19 @@ static const struct dpu_dspp_sub_blks sm8150_dspp_sblk = { * PINGPONG sub blocks config *************************************************************/ static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te = { - .te2 = {.id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, + .te2 = {.name = "te2", .id = DPU_PINGPONG_TE2, .base = 0x2000, .len = 0x0, .version = 0x1}, - .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, + .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0, .len = 0x20, .version = 0x10000}, }; static const struct dpu_pingpong_sub_blks sdm845_pp_sblk = { - .dither = {.id = DPU_PINGPONG_DITHER, .base = 0x30e0, + .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0x30e0, .len = 0x20, .version = 0x10000}, }; static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { - .dither = {.id = DPU_PINGPONG_DITHER, .base = 0xe0, + .dither = {.name = "dither", .id = DPU_PINGPONG_DITHER, .base = 0xe0, .len = 0x20, .version = 0x20000}, }; @@ -517,13 +517,13 @@ static const struct dpu_pingpong_sub_blks sc7280_pp_sblk = { * DSC sub blocks config *************************************************************/ static const struct dpu_dsc_sub_blks dsc_sblk_0 = { - .enc = {.base = 0x100, .len = 0x100}, - .ctl = {.base = 0xF00, .len = 0x10}, + .enc = {.name = "enc", .base = 0x100, .len = 0x100}, + .ctl = {.name = "ctl", .base = 0xF00, .len = 0x10}, }; static const struct dpu_dsc_sub_blks dsc_sblk_1 = { - .enc = {.base = 0x200, .len = 0x100}, - .ctl = {.base = 0xF80, .len = 0x10}, + .enc = {.name = "enc", .base = 0x200, .len = 0x100}, + .ctl = {.name = "ctl", .base = 0xF80, .len = 0x10}, }; #define DSC_BLK(_name, _id, _base, _features) \ From patchwork Thu Jun 22 23:48:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan McCann X-Patchwork-Id: 694940 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7F3DFEB64DA for ; Thu, 22 Jun 2023 23:50:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231828AbjFVXum (ORCPT ); Thu, 22 Jun 2023 19:50:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58538 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231779AbjFVXui (ORCPT ); Thu, 22 Jun 2023 19:50:38 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 848B12123; 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Thu, 22 Jun 2023 23:50:27 +0000 Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35MNoRa2024838 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 22 Jun 2023 23:50:27 GMT Received: from hu-rmccann-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 22 Jun 2023 16:50:26 -0700 From: Ryan McCann Date: Thu, 22 Jun 2023 16:48:56 -0700 Subject: [PATCH 4/6] drm/msm/dpu: Remove redundant suffix in name of sub blocks MIME-Version: 1.0 Message-ID: <20230622-devcoredump_patch-v1-4-3b2cdcc6a576@quicinc.com> References: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> In-Reply-To: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter CC: Rob Clark , , , , , , Ryan McCann X-Mailer: b4 0.13-dev-8a804 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687477824; l=5914; i=quic_rmccann@quicinc.com; s=20230622; h=from:subject:message-id; bh=5E9VdlaJi58Bb3G0Xl0D/kH4yyuyInwCfkAesiWcHl4=; b=Vo2K1e8QwKiRLpYoBnB4WmQ7B+JFpa5cG0l8Mhcw3oE3uzN1zIY1IepGC+b7WyXX/N+dU6yek 1mkOev0uKbNBXRapTzKD9ch30Z/ctaUsL8yL+YGLswFJbIghWOC/Py3 X-Developer-Key: i=quic_rmccann@quicinc.com; a=ed25519; pk=d/uP3OwPGpj/bTtiHvV1RBZ2S6q4AL6j1+A5y+dmbTI= X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: kIbmruUcs4vUc209Y3Oif6S0GXUYop9N X-Proofpoint-GUID: kIbmruUcs4vUc209Y3Oif6S0GXUYop9N X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-22_17,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 suspectscore=0 spamscore=0 mlxscore=0 priorityscore=1501 bulkscore=0 mlxlogscore=999 impostorscore=0 malwarescore=0 clxscore=1015 adultscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306220205 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org For a device core dump, the registers of sub blocks are printed under the title . For example, the csc sub block for an SSPP block "sspp_0" would be printed "sspp_0_csc0". There is a redundant 0 in the title due to a concatention done in the definition of the VIG_SBLK macro, the macro used to define the sub blocks of "sspp_0". Remove this concatenation to eliminate redundancy and remove the num parameter of relevant macros as a consequence of it no longer being used. Signed-off-by: Ryan McCann --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 48 +++++++++++++------------- 1 file changed, 24 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 8349ecda1f3c..c624b2cf0b35 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -252,15 +252,15 @@ static const uint32_t wb2_formats[] = { *************************************************************/ /* SSPP common configuration */ -#define _VIG_SBLK(num, sdma_pri, qseed_ver) \ +#define _VIG_SBLK(sdma_pri, qseed_ver) \ { \ .maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \ .smart_dma_priority = sdma_pri, \ - .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ + .scaler_blk = {.name = "sspp_scaler", \ .id = qseed_ver, \ .base = 0xa00, .len = 0xa0,}, \ - .csc_blk = {.name = STRCAT("sspp_csc", num), \ + .csc_blk = {.name = "sspp_csc", \ .id = DPU_SSPP_CSC_10BIT, \ .base = 0x1a00, .len = 0x100,}, \ .format_list = plane_formats_yuv, \ @@ -270,15 +270,15 @@ static const uint32_t wb2_formats[] = { .rotation_cfg = NULL, \ } -#define _VIG_SBLK_ROT(num, sdma_pri, qseed_ver, rot_cfg) \ +#define _VIG_SBLK_ROT(sdma_pri, qseed_ver, rot_cfg) \ { \ .maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \ .smart_dma_priority = sdma_pri, \ - .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ + .scaler_blk = {.name = "sspp_scaler", \ .id = qseed_ver, \ .base = 0xa00, .len = 0xa0,}, \ - .csc_blk = {.name = STRCAT("sspp_csc", num), \ + .csc_blk = {.name = "sspp_csc", \ .id = DPU_SSPP_CSC_10BIT, \ .base = 0x1a00, .len = 0x100,}, \ .format_list = plane_formats_yuv, \ @@ -300,13 +300,13 @@ static const uint32_t wb2_formats[] = { } static const struct dpu_sspp_sub_blks msm8998_vig_sblk_0 = - _VIG_SBLK("0", 0, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks msm8998_vig_sblk_1 = - _VIG_SBLK("1", 0, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks msm8998_vig_sblk_2 = - _VIG_SBLK("2", 0, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks msm8998_vig_sblk_3 = - _VIG_SBLK("3", 0, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(0, DPU_SSPP_SCALER_QSEED3); static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { .rot_maxheight = 1088, @@ -315,13 +315,13 @@ static const struct dpu_rotation_cfg dpu_rot_sc7280_cfg_v2 = { }; static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = - _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = - _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = - _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = - _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED3); + _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED3); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK(1); static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK(2); @@ -341,29 +341,29 @@ static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK(4); } static const struct dpu_sspp_sub_blks sc7180_vig_sblk_0 = - _VIG_SBLK("0", 4, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(4, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sc7280_vig_sblk_0 = - _VIG_SBLK_ROT("0", 4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); + _VIG_SBLK_ROT(4, DPU_SSPP_SCALER_QSEED4, &dpu_rot_sc7280_cfg_v2); static const struct dpu_sspp_sub_blks sm6115_vig_sblk_0 = - _VIG_SBLK("0", 2, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(2, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_0 = - _VIG_SBLK("0", 5, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(5, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_1 = - _VIG_SBLK("1", 6, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(6, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_2 = - _VIG_SBLK("2", 7, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8250_vig_sblk_3 = - _VIG_SBLK("3", 8, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_0 = - _VIG_SBLK("0", 7, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(7, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_1 = - _VIG_SBLK("1", 8, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(8, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_2 = - _VIG_SBLK("2", 9, DPU_SSPP_SCALER_QSEED4); + _VIG_SBLK(9, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_vig_sblk_3 = _VIG_SBLK(10, DPU_SSPP_SCALER_QSEED4); static const struct dpu_sspp_sub_blks sm8550_dma_sblk_4 = _DMA_SBLK(5); From patchwork Thu Jun 22 23:48:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan McCann X-Patchwork-Id: 694941 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82A30C001B0 for ; Thu, 22 Jun 2023 23:50:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231810AbjFVXul (ORCPT ); Thu, 22 Jun 2023 19:50:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231795AbjFVXui (ORCPT ); Thu, 22 Jun 2023 19:50:38 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C9012135; Thu, 22 Jun 2023 16:50:34 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35MNhnHK030796; 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Thu, 22 Jun 2023 23:50:27 GMT Received: from hu-rmccann-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 22 Jun 2023 16:50:27 -0700 From: Ryan McCann Date: Thu, 22 Jun 2023 16:48:57 -0700 Subject: [PATCH 5/6] drm/msm/disp: Remove redundant prefix in name of sub blocks MIME-Version: 1.0 Message-ID: <20230622-devcoredump_patch-v1-5-3b2cdcc6a576@quicinc.com> References: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> In-Reply-To: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter CC: Rob Clark , , , , , , Ryan McCann X-Mailer: b4 0.13-dev-8a804 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687477824; l=1872; i=quic_rmccann@quicinc.com; s=20230622; h=from:subject:message-id; bh=QupKcsLYZlg8w5T7AlTIsgtyOApCsJxMZ67hvD7d4tg=; b=/rHFv219unClQh8ddg5Ug5Z/Z34tNu9IqJQSd/GABLj9KEm4XkRGnRG05OX2Pyo1UiPhqwjPi gqR66rfgInGAq7mJnUFo7osd20eM25S8fhrXEjniN8F3jeTyTT5VpJ7 X-Developer-Key: i=quic_rmccann@quicinc.com; a=ed25519; pk=d/uP3OwPGpj/bTtiHvV1RBZ2S6q4AL6j1+A5y+dmbTI= X-Originating-IP: [10.49.16.6] X-ClientProxiedBy: nalasex01a.na.qualcomm.com (10.47.209.196) To nalasex01c.na.qualcomm.com (10.47.97.35) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: EPewRx1FQnNj9ZMzhE3ateiULIMk20Br X-Proofpoint-ORIG-GUID: EPewRx1FQnNj9ZMzhE3ateiULIMk20Br X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.591,FMLib:17.11.176.26 definitions=2023-06-22_17,2023-06-22_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 bulkscore=0 mlxscore=0 phishscore=0 impostorscore=0 mlxlogscore=999 priorityscore=1501 malwarescore=0 adultscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306220205 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org When the registers of the csc and scaler sub blocks are printed during a device core dump, the sub block title is printed: . Currently this appears as "sspp_0_sspp_csc" for a csc sub block to an SSPP main block named "sspp_0". Because the name of the sub block defined in the VIG_SBLK macro is "sspp_csc", the result is a redundant name. To avoid this redundancy, remove the duplicate prefix "sspp". Signed-off-by: Ryan McCann --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index c624b2cf0b35..836efa074a35 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -257,10 +257,10 @@ static const uint32_t wb2_formats[] = { .maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \ .smart_dma_priority = sdma_pri, \ - .scaler_blk = {.name = "sspp_scaler", \ + .scaler_blk = {.name = "scaler", \ .id = qseed_ver, \ .base = 0xa00, .len = 0xa0,}, \ - .csc_blk = {.name = "sspp_csc", \ + .csc_blk = {.name = "csc", \ .id = DPU_SSPP_CSC_10BIT, \ .base = 0x1a00, .len = 0x100,}, \ .format_list = plane_formats_yuv, \ @@ -275,10 +275,10 @@ static const uint32_t wb2_formats[] = { .maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \ .smart_dma_priority = sdma_pri, \ - .scaler_blk = {.name = "sspp_scaler", \ + .scaler_blk = {.name = "scaler", \ .id = qseed_ver, \ .base = 0xa00, .len = 0xa0,}, \ - .csc_blk = {.name = "sspp_csc", \ + .csc_blk = {.name = "csc", \ .id = DPU_SSPP_CSC_10BIT, \ .base = 0x1a00, .len = 0x100,}, \ .format_list = plane_formats_yuv, \ From patchwork Thu Jun 22 23:48:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ryan McCann X-Patchwork-Id: 695804 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1E914C001DE for ; Thu, 22 Jun 2023 23:50:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231834AbjFVXun (ORCPT ); Thu, 22 Jun 2023 19:50:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58552 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231790AbjFVXui (ORCPT ); Thu, 22 Jun 2023 19:50:38 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09DE4212B; Thu, 22 Jun 2023 16:50:37 -0700 (PDT) Received: from pps.filterd (m0279866.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35MN47xP005500; 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Thu, 22 Jun 2023 23:50:27 GMT Received: from hu-rmccann-lv.qualcomm.com (10.49.16.6) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Thu, 22 Jun 2023 16:50:27 -0700 From: Ryan McCann Date: Thu, 22 Jun 2023 16:48:58 -0700 Subject: [PATCH 6/6] drm/msm/dpu: Update dev core dump to dump registers of sub blocks MIME-Version: 1.0 Message-ID: <20230622-devcoredump_patch-v1-6-3b2cdcc6a576@quicinc.com> References: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> In-Reply-To: <20230622-devcoredump_patch-v1-0-3b2cdcc6a576@quicinc.com> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Daniel Vetter CC: Rob Clark , , , , , , Ryan McCann X-Mailer: b4 0.13-dev-8a804 X-Developer-Signature: v=1; a=ed25519-sha256; t=1687477824; l=9099; i=quic_rmccann@quicinc.com; s=20230622; h=from:subject:message-id; bh=GPxUKbhVRNfWIyXk3T5WLt4/ZaogBUP0uckeyfQQy4s=; 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Add wrapper function to dump hardware blocks that contain sub blocks. Signed-off-by: Ryan McCann --- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 194 +++++++++++++++++++++++++++----- 1 file changed, 168 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index aa8499de1b9f..9b1b1c382269 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -885,6 +885,154 @@ static int dpu_irq_postinstall(struct msm_kms *kms) return 0; } +static void dpu_kms_mdp_snapshot_add_block(struct msm_disp_state *disp_state, + void __iomem *mmio, void *blk, + enum dpu_hw_blk_type blk_type) +{ + u32 base; + + switch (blk_type) { + case DPU_HW_BLK_TOP: + { + struct dpu_mdp_cfg *top = (struct dpu_mdp_cfg *)blk; + + if (top->features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { + msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0, + mmio + top->base, "top"); + msm_disp_snapshot_add_block(disp_state, top->len - MDP_PERIPH_TOP0_END, + mmio + top->base + MDP_PERIPH_TOP0_END, + "top_2"); + } else { + msm_disp_snapshot_add_block(disp_state, top->len, mmio + top->base, "top"); + } + break; + } + case DPU_HW_BLK_LM: + { + struct dpu_lm_cfg *mixer = (struct dpu_lm_cfg *)blk; + + msm_disp_snapshot_add_block(disp_state, mixer->len, mmio + mixer->base, "%s", + mixer->name); + break; + } + case DPU_HW_BLK_CTL: + { + struct dpu_ctl_cfg *ctl = (struct dpu_ctl_cfg *)blk; + + msm_disp_snapshot_add_block(disp_state, ctl->len, mmio + ctl->base, "%s", + ctl->name); + break; + } + case DPU_HW_BLK_INTF: + { + struct dpu_intf_cfg *intf = (struct dpu_intf_cfg *)blk; + + msm_disp_snapshot_add_block(disp_state, intf->len, mmio + intf->base, "%s", + intf->name); + break; + } + case DPU_HW_BLK_WB: + { + struct dpu_wb_cfg *wb = (struct dpu_wb_cfg *)blk; + + msm_disp_snapshot_add_block(disp_state, wb->len, mmio + wb->base, "%s", + wb->name); + break; + } + case DPU_HW_BLK_SSPP: + { + struct dpu_sspp_cfg *sspp_block = (struct dpu_sspp_cfg *)blk; + const struct dpu_sspp_sub_blks *sblk = sspp_block->sblk; + + base = sspp_block->base; + + msm_disp_snapshot_add_block(disp_state, sspp_block->len, mmio + base, "%s", + sspp_block->name); + + if (sspp_block->features & BIT(DPU_SSPP_SCALER_QSEED3) || + sspp_block->features & BIT(DPU_SSPP_SCALER_QSEED3LITE) || + sspp_block->features & BIT(DPU_SSPP_SCALER_QSEED4)) + msm_disp_snapshot_add_block(disp_state, sblk->scaler_blk.len, + mmio + base + sblk->scaler_blk.base, "%s_%s", + sspp_block->name, sblk->scaler_blk.name); + + if (sspp_block->features & BIT(DPU_SSPP_CSC) || sspp_block->features + & BIT(DPU_SSPP_CSC_10BIT)) + msm_disp_snapshot_add_block(disp_state, sblk->csc_blk.len, + mmio + base + sblk->csc_blk.base, "%s_%s", + sspp_block->name, sblk->csc_blk.name); + break; + } + case DPU_HW_BLK_DSPP: + { + struct dpu_dspp_cfg *dspp_block = (struct dpu_dspp_cfg *)blk; + + base = dspp_block->base; + + msm_disp_snapshot_add_block(disp_state, dspp_block->len, mmio + base, "%s", + dspp_block->name); + + if (dspp_block->features & BIT(DPU_DSPP_PCC)) + msm_disp_snapshot_add_block(disp_state, dspp_block->sblk->pcc.len, + mmio + base + dspp_block->sblk->pcc.base, + "%s_%s", dspp_block->name, + dspp_block->sblk->pcc.name); + break; + } + case DPU_HW_BLK_PINGPONG: + { + struct dpu_pingpong_cfg *pingpong_block = (struct dpu_pingpong_cfg *)blk; + const struct dpu_pingpong_sub_blks *sblk = pingpong_block->sblk; + + base = pingpong_block->base; + + msm_disp_snapshot_add_block(disp_state, pingpong_block->len, mmio + base, "%s", + pingpong_block->name); + + if (pingpong_block->features & BIT(DPU_PINGPONG_TE2)) + msm_disp_snapshot_add_block(disp_state, sblk->te2.len, + mmio + base + sblk->te2.base, "%s_%s", + pingpong_block->name, sblk->te2.name); + + if (pingpong_block->features & BIT(DPU_PINGPONG_DITHER)) + msm_disp_snapshot_add_block(disp_state, sblk->dither.len, + mmio + base + sblk->dither.base, "%s_%s", + pingpong_block->name, sblk->dither.name); + break; + } + case DPU_HW_BLK_DSC: + { + struct dpu_dsc_cfg *dsc_block = (struct dpu_dsc_cfg *)blk; + + base = dsc_block->base; + + if (dsc_block->features & BIT(DPU_DSC_HW_REV_1_2)) { + struct dpu_dsc_blk enc = dsc_block->sblk->enc; + struct dpu_dsc_blk ctl = dsc_block->sblk->ctl; + + /* For now, pass in a length of 0 because the DSC_BLK register space + * overlaps with the sblks' register space. + * + * TODO: Pass in a length of 0 t0 DSC_BLK_1_2 in the HW catalog where + * applicable. + */ + msm_disp_snapshot_add_block(disp_state, 0, mmio + base, "%s", + dsc_block->name); + msm_disp_snapshot_add_block(disp_state, enc.len, mmio + base + enc.base, + "%s_%s", dsc_block->name, enc.name); + msm_disp_snapshot_add_block(disp_state, ctl.len, mmio + base + ctl.base, + "%s_%s", dsc_block->name, ctl.name); + } else { + msm_disp_snapshot_add_block(disp_state, dsc_block->len, mmio + base, "%s", + dsc_block->name); + } + break; + } + default: + DPU_ERROR("Block type not supported."); + } +} + static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms) { int i; @@ -899,53 +1047,47 @@ static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_k /* dump CTL sub-blocks HW regs info */ for (i = 0; i < cat->ctl_count; i++) - msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len, - dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i); + dpu_kms_mdp_snapshot_add_block(disp_state, dpu_kms->mmio, (void *)&cat->ctl[i], + DPU_HW_BLK_CTL); /* dump DSPP sub-blocks HW regs info */ for (i = 0; i < cat->dspp_count; i++) - msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len, - dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i); + dpu_kms_mdp_snapshot_add_block(disp_state, dpu_kms->mmio, (void *)&cat->dspp[i], + DPU_HW_BLK_DSPP); /* dump INTF sub-blocks HW regs info */ for (i = 0; i < cat->intf_count; i++) - msm_disp_snapshot_add_block(disp_state, cat->intf[i].len, - dpu_kms->mmio + cat->intf[i].base, "intf_%d", i); + dpu_kms_mdp_snapshot_add_block(disp_state, dpu_kms->mmio, (void *)&cat->intf[i], + DPU_HW_BLK_INTF); /* dump PP sub-blocks HW regs info */ for (i = 0; i < cat->pingpong_count; i++) - msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len, - dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i); + dpu_kms_mdp_snapshot_add_block(disp_state, dpu_kms->mmio, (void *)&cat->pingpong[i], + DPU_HW_BLK_PINGPONG); /* dump SSPP sub-blocks HW regs info */ for (i = 0; i < cat->sspp_count; i++) - msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len, - dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i); + dpu_kms_mdp_snapshot_add_block(disp_state, dpu_kms->mmio, (void *)&cat->sspp[i], + DPU_HW_BLK_SSPP); /* dump LM sub-blocks HW regs info */ for (i = 0; i < cat->mixer_count; i++) - msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len, - dpu_kms->mmio + cat->mixer[i].base, "lm_%d", i); + dpu_kms_mdp_snapshot_add_block(disp_state, dpu_kms->mmio, (void *)&cat->mixer[i], + DPU_HW_BLK_LM); /* dump WB sub-blocks HW regs info */ for (i = 0; i < cat->wb_count; i++) - msm_disp_snapshot_add_block(disp_state, cat->wb[i].len, - dpu_kms->mmio + cat->wb[i].base, "wb_%d", i); - - if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) { - msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0, - dpu_kms->mmio + cat->mdp[0].base, "top"); - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END, - dpu_kms->mmio + cat->mdp[0].base + MDP_PERIPH_TOP0_END, "top_2"); - } else { - msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len, - dpu_kms->mmio + cat->mdp[0].base, "top"); - } + dpu_kms_mdp_snapshot_add_block(disp_state, dpu_kms->mmio, (void *)&cat->wb[i], + DPU_HW_BLK_WB); + + /* dump top block */ + dpu_kms_mdp_snapshot_add_block(disp_state, dpu_kms->mmio, (void *)&cat->mdp[0], + DPU_HW_BLK_TOP); /* dump DSC sub-blocks HW regs info */ for (i = 0; i < cat->dsc_count; i++) - msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len, - dpu_kms->mmio + cat->dsc[i].base, "dsc_%d", i); + dpu_kms_mdp_snapshot_add_block(disp_state, dpu_kms->mmio, (void *)&cat->dsc[i], + DPU_HW_BLK_DSC); pm_runtime_put_sync(&dpu_kms->pdev->dev); }