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[209.51.188.17]) by mx.google.com with ESMTPS id k15-20020a05620a138f00b0075f02f4a6e3si1644271qki.517.2023.06.21.05.19.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 21 Jun 2023 05:19:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EMClaJq9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBwo4-0006eE-Mr; Wed, 21 Jun 2023 08:19:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBwnm-0006aZ-Gq for qemu-devel@nongnu.org; Wed, 21 Jun 2023 08:19:10 -0400 Received: from mail-lj1-x229.google.com ([2a00:1450:4864:20::229]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBwnj-0000GC-Ih for qemu-devel@nongnu.org; Wed, 21 Jun 2023 08:19:10 -0400 Received: by mail-lj1-x229.google.com with SMTP id 38308e7fff4ca-2b466744368so66018021fa.0 for ; Wed, 21 Jun 2023 05:19:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687349946; x=1689941946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jgqAbaPN1d4W9rZooKKid+wiSp+1N29sW2yxha1lmeQ=; b=EMClaJq9Bv02tiOB76o4+o3foPo+UXj3ZCIUWYYqoB2F0v3Z5owuks/qGTJoZf1+/y zqLf3dYoVTtcUC75C4JeehVqF6gUEwy0PlI9O8B0CIzlN/bzB4/u0zdFBixcpnJL9b7n /pyKisKhod6kJxLinE8LWcuuOPI34v8SD46r3DKQkXeMTxxbJw6U75pYYTIGTYMNVPVe v8DcAJkW53MaIU+wM0OywGtQlD8ivWGoatus3ljlqB80XViwz2IM03EBmziy/Ih1/rld RNf95Ed3MfpdRVcRV7foXC7LekT9LtJrR155rVeEU28BRqZCna0TuH/RYwwJIRUUO0dJ DM3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687349946; x=1689941946; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jgqAbaPN1d4W9rZooKKid+wiSp+1N29sW2yxha1lmeQ=; b=Tj77ahyw+B+8YaKehc0gUxp2UV+Iy4bX/Kj5FK+uU6fwxSA9mVrnVqlZg9Gy/Nobau 50xqLRb5KelOI/cacfoZlp0Rqkkb8nxQGce9pMRCZYwp+vFc4D1pfDIBVAMnaeUMVjFu /9w0iEP+v5YlLvzO6neZHV6GdJbMZDKmX3vHRGoSRCfmbN/kVzYXUmjfLI7DbpUvLTtf xYXkaNDjWquXY7L7NxS3D9UPVDgz/lyKF9/0/cI4RJoUHeb0EwmuqOK2IYv/K9sddQ+W 8/lg5BpnsLmEkuVUBRRosgtyfQSN/XAOzJXUlGKISrorjgcUMHbvDjRUYGx9b5i2EsS7 JNrQ== X-Gm-Message-State: AC+VfDxDE6qTxJqMQY9PzJC29kLuAYmUIw1uPzFE9wOKm1OKJZh9eFTu m0M4zpLhJIoozGGSTdGz6o4OSwhOP6rqUsT5k39Rf39v X-Received: by 2002:a2e:9c82:0:b0:2b4:6678:da57 with SMTP id x2-20020a2e9c82000000b002b46678da57mr7374896lji.6.1687349945564; Wed, 21 Jun 2023 05:19:05 -0700 (PDT) Received: from stoup.lan ([176.176.128.70]) by smtp.gmail.com with ESMTPSA id s6-20020a056402014600b0051bdf152295sm543176edu.76.2023.06.21.05.19.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jun 2023 05:19:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 1/9] accel/tcg: Store some tlb flags in CPUTLBEntryFull Date: Wed, 21 Jun 2023 14:18:54 +0200 Message-Id: <20230621121902.1392277-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621121902.1392277-1-richard.henderson@linaro.org> References: <20230621121902.1392277-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=richard.henderson@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We have run out of bits we can use within the CPUTLBEntry comparators, as TLB_FLAGS_MASK cannot overlap alignment. Store slow_flags[] in CPUTLBEntryFull, and merge with the flags from the comparator. A new TLB_FORCE_SLOW bit is set within the comparator as an indication that the slow path must be used. Move TLB_BSWAP to TLB_SLOW_FLAGS_MASK. Since we are out of bits, we cannot create a new bit without moving an old one. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/exec/cpu-all.h | 21 +++++++-- include/exec/cpu-defs.h | 6 +++ accel/tcg/cputlb.c | 96 ++++++++++++++++++++++++----------------- 3 files changed, 80 insertions(+), 43 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 09bf4c0cc6..4422f4bb07 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -327,17 +327,30 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) /* Set if TLB entry contains a watchpoint. */ #define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) -/* Set if TLB entry requires byte swap. */ -#define TLB_BSWAP (1 << (TARGET_PAGE_BITS_MIN - 5)) +/* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ +#define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) /* Set if TLB entry writes ignored. */ #define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) -/* Use this mask to check interception with an alignment mask +/* + * Use this mask to check interception with an alignment mask * in a TCG backend. */ #define TLB_FLAGS_MASK \ (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_WATCHPOINT | TLB_BSWAP | TLB_DISCARD_WRITE) + | TLB_WATCHPOINT | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) + +/* + * Flags stored in CPUTLBEntryFull.slow_flags[x]. + * TLB_FORCE_SLOW must be set in CPUTLBEntry.addr_idx[x]. + */ +/* Set if TLB entry requires byte swap. */ +#define TLB_BSWAP (1 << 0) + +#define TLB_SLOW_FLAGS_MASK TLB_BSWAP + +/* The two sets of flags must not overlap. */ +QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); /** * tlb_hit_page: return true if page aligned @addr is a hit against the diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index 4cb77c8dec..c174d5371a 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -124,6 +124,12 @@ typedef struct CPUTLBEntryFull { /* @lg_page_size contains the log2 of the page size. */ uint8_t lg_page_size; + /* + * Additional tlb flags for use by the slow path. If non-zero, + * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. + */ + uint8_t slow_flags[3]; + /* * Allow target-specific additions to this structure. * This may be used to cache items from the guest cpu diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 14ce97c33b..b40ce5ea0f 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1110,6 +1110,24 @@ static void tlb_add_large_page(CPUArchState *env, int mmu_idx, env_tlb(env)->d[mmu_idx].large_page_mask = lp_mask; } +static inline void tlb_set_compare(CPUTLBEntryFull *full, CPUTLBEntry *ent, + target_ulong address, int flags, + MMUAccessType access_type, bool enable) +{ + if (enable) { + address |= flags & TLB_FLAGS_MASK; + flags &= TLB_SLOW_FLAGS_MASK; + if (flags) { + address |= TLB_FORCE_SLOW; + } + } else { + address = -1; + flags = 0; + } + ent->addr_idx[access_type] = address; + full->slow_flags[access_type] = flags; +} + /* * Add a new TLB entry. At most one entry for a given virtual address * is permitted. Only a single TARGET_PAGE_SIZE region is mapped, the @@ -1125,9 +1143,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, CPUTLB *tlb = env_tlb(env); CPUTLBDesc *desc = &tlb->d[mmu_idx]; MemoryRegionSection *section; - unsigned int index; - target_ulong address; - target_ulong write_address; + unsigned int index, read_flags, write_flags; uintptr_t addend; CPUTLBEntry *te, tn; hwaddr iotlb, xlat, sz, paddr_page; @@ -1156,13 +1172,13 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, " prot=%x idx=%d\n", vaddr, full->phys_addr, prot, mmu_idx); - address = vaddr_page; + read_flags = 0; if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ - address |= TLB_INVALID_MASK; + read_flags |= TLB_INVALID_MASK; } if (full->attrs.byte_swap) { - address |= TLB_BSWAP; + read_flags |= TLB_BSWAP; } is_ram = memory_region_is_ram(section->mr); @@ -1176,7 +1192,7 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, addend = 0; } - write_address = address; + write_flags = read_flags; if (is_ram) { iotlb = memory_region_get_ram_addr(section->mr) + xlat; /* @@ -1185,9 +1201,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, */ if (prot & PAGE_WRITE) { if (section->readonly) { - write_address |= TLB_DISCARD_WRITE; + write_flags |= TLB_DISCARD_WRITE; } else if (cpu_physical_memory_is_clean(iotlb)) { - write_address |= TLB_NOTDIRTY; + write_flags |= TLB_NOTDIRTY; } } } else { @@ -1198,9 +1214,9 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, * Reads to romd devices go through the ram_ptr found above, * but of course reads to I/O must go through MMIO. */ - write_address |= TLB_MMIO; + write_flags |= TLB_MMIO; if (!is_romd) { - address = write_address; + read_flags = write_flags; } } @@ -1253,36 +1269,30 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, * vaddr we add back in io_readx()/io_writex()/get_page_addr_code(). */ desc->fulltlb[index] = *full; - desc->fulltlb[index].xlat_section = iotlb - vaddr_page; - desc->fulltlb[index].phys_addr = paddr_page; + full = &desc->fulltlb[index]; + full->xlat_section = iotlb - vaddr_page; + full->phys_addr = paddr_page; /* Now calculate the new entry */ tn.addend = addend - vaddr_page; - if (prot & PAGE_READ) { - tn.addr_read = address; - if (wp_flags & BP_MEM_READ) { - tn.addr_read |= TLB_WATCHPOINT; - } - } else { - tn.addr_read = -1; - } - if (prot & PAGE_EXEC) { - tn.addr_code = address; - } else { - tn.addr_code = -1; - } + tlb_set_compare(full, &tn, vaddr_page, read_flags, + MMU_INST_FETCH, prot & PAGE_EXEC); - tn.addr_write = -1; - if (prot & PAGE_WRITE) { - tn.addr_write = write_address; - if (prot & PAGE_WRITE_INV) { - tn.addr_write |= TLB_INVALID_MASK; - } - if (wp_flags & BP_MEM_WRITE) { - tn.addr_write |= TLB_WATCHPOINT; - } + if (wp_flags & BP_MEM_READ) { + read_flags |= TLB_WATCHPOINT; } + tlb_set_compare(full, &tn, vaddr_page, read_flags, + MMU_DATA_LOAD, prot & PAGE_READ); + + if (prot & PAGE_WRITE_INV) { + write_flags |= TLB_INVALID_MASK; + } + if (wp_flags & BP_MEM_WRITE) { + write_flags |= TLB_WATCHPOINT; + } + tlb_set_compare(full, &tn, vaddr_page, write_flags, + MMU_DATA_STORE, prot & PAGE_WRITE); copy_tlb_helper_locked(te, &tn); tlb_n_used_entries_inc(env, mmu_idx); @@ -1512,7 +1522,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); target_ulong tlb_addr = tlb_read_idx(entry, access_type); target_ulong page_addr = addr & TARGET_PAGE_MASK; - int flags = TLB_FLAGS_MASK; + int flags = TLB_FLAGS_MASK & ~TLB_FORCE_SLOW; + CPUTLBEntryFull *full; if (!tlb_hit_page(tlb_addr, page_addr)) { if (!victim_tlb_hit(env, mmu_idx, index, access_type, page_addr)) { @@ -1541,7 +1552,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, } flags &= tlb_addr; - *pfull = &env_tlb(env)->d[mmu_idx].fulltlb[index]; + *pfull = full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; + flags |= full->slow_flags[access_type]; /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { @@ -1764,6 +1776,8 @@ static bool mmu_lookup1(CPUArchState *env, MMULookupPageData *data, CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); target_ulong tlb_addr = tlb_read_idx(entry, access_type); bool maybe_resized = false; + CPUTLBEntryFull *full; + int flags; /* If the TLB entry is for a different page, reload and try again. */ if (!tlb_hit(tlb_addr, addr)) { @@ -1777,8 +1791,12 @@ static bool mmu_lookup1(CPUArchState *env, MMULookupPageData *data, tlb_addr = tlb_read_idx(entry, access_type) & ~TLB_INVALID_MASK; } - data->flags = tlb_addr & TLB_FLAGS_MASK; - data->full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; + full = &env_tlb(env)->d[mmu_idx].fulltlb[index]; + flags = tlb_addr & (TLB_FLAGS_MASK & ~TLB_FORCE_SLOW); + flags |= full->slow_flags[access_type]; + + data->full = full; + data->flags = flags; /* Compute haddr speculatively; depending on flags it might be invalid. */ data->haddr = (void *)((uintptr_t)addr + entry->addend); From patchwork Wed Jun 21 12:18:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694767 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp816302wrm; Wed, 21 Jun 2023 05:21:08 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ54A2TpPaFPWWYtz26yJUP2IGxsHZ6QQUEc10jTM/E2+YKq1Imfd5+kZLnlIbt77UjSI4g8 X-Received: by 2002:a05:622a:11c3:b0:3ff:3046:e43f with SMTP id n3-20020a05622a11c300b003ff3046e43fmr4712396qtk.58.1687350068593; Wed, 21 Jun 2023 05:21:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687350068; cv=none; d=google.com; s=arc-20160816; b=dYKAhfQPgI2v5xuBoPuKA+KkVjAAS72aJYM3tshCLU3xVOAvDmaQHHQZB7U2j5PluY 3MW9oPuydTxWI4qyzZ53K03+CC2viQFD+Pewz47a51s+HYtu7T4ac1T4kSpJW553BBYj rwX3qp/TmI57glBW99lZQONp/h803oEdywXsi/XXY4HBZ14uSkOaBJ1ZaV4YL3rl9lqx Ng5Wy4C9ffjc7yW6bhG7DUSguVvucYt1o53DSTho8wzY2hFb9pNycYxE8lPHoODxqUvF b8yzYCRxGc8NuozimGPsWmUy4W56sVZX5E23+3JNtMmmE3Yk9/f8s0mITxtzfv2vGutf otPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QVkh9ElQYXuU3m7U9rfp/idF7Etsc4zRDhZIcGQ6L9k=; b=mOwng3TaaH+lUEu+oxOLK4ueqT+Mgbq5ADb61oL+xuxaBM6pLweUpweiAhPcAjCzzA D2/2sRWUm+CzZHkntkGdwa5ojaMaPukeZydJO9GmPS24LEjJUxcYmHVWqRUQW8okpsRa ywfpX+/2NMQr7g7/Kdy9hZJh3CqxSVGru1d52poG7jVlaEWx8hbIgVtNhIBfMA0FnGjz u3CLmgd01xvz3Fd18wfNAmovH8D82842iAI9BIoiu+29z3LiBOOK6d3aIcNvU5fjABqI M51rHZYQyMiyn8ivtcL0bE6CbuyGzGU3NQcgWsn5p9i4BS09i1otwkpW9Pv8uFIRk8tx 4/kg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Qc5NLrDS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/exec/cpu-all.h | 8 ++++---- accel/tcg/cputlb.c | 18 ++++++++++++++---- 2 files changed, 18 insertions(+), 8 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 4422f4bb07..b5618613cc 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -325,8 +325,6 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) /* Set if TLB entry is an IO callback. */ #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) -/* Set if TLB entry contains a watchpoint. */ -#define TLB_WATCHPOINT (1 << (TARGET_PAGE_BITS_MIN - 4)) /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ #define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) /* Set if TLB entry writes ignored. */ @@ -338,7 +336,7 @@ CPUArchState *cpu_copy(CPUArchState *env); */ #define TLB_FLAGS_MASK \ (TLB_INVALID_MASK | TLB_NOTDIRTY | TLB_MMIO \ - | TLB_WATCHPOINT | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) + | TLB_FORCE_SLOW | TLB_DISCARD_WRITE) /* * Flags stored in CPUTLBEntryFull.slow_flags[x]. @@ -346,8 +344,10 @@ CPUArchState *cpu_copy(CPUArchState *env); */ /* Set if TLB entry requires byte swap. */ #define TLB_BSWAP (1 << 0) +/* Set if TLB entry contains a watchpoint. */ +#define TLB_WATCHPOINT (1 << 1) -#define TLB_SLOW_FLAGS_MASK TLB_BSWAP +#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT) /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index b40ce5ea0f..152c4e9994 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1984,7 +1984,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, */ goto stop_the_world; } - /* Collect TLB_WATCHPOINT for read. */ + /* Collect tlb flags for read. */ tlb_addr |= tlbe->addr_read; /* Notice an IO access or a needs-MMU-lookup access */ @@ -2001,9 +2001,19 @@ static void *atomic_mmu_lookup(CPUArchState *env, target_ulong addr, notdirty_write(env_cpu(env), addr, size, full, retaddr); } - if (unlikely(tlb_addr & TLB_WATCHPOINT)) { - cpu_check_watchpoint(env_cpu(env), addr, size, full->attrs, - BP_MEM_READ | BP_MEM_WRITE, retaddr); + if (unlikely(tlb_addr & TLB_FORCE_SLOW)) { + int wp_flags = 0; + + if (full->slow_flags[MMU_DATA_STORE] & TLB_WATCHPOINT) { + wp_flags |= BP_MEM_WRITE; + } + if (full->slow_flags[MMU_DATA_LOAD] & TLB_WATCHPOINT) { + wp_flags |= BP_MEM_READ; + } + if (wp_flags) { + cpu_check_watchpoint(env_cpu(env), addr, size, + full->attrs, wp_flags, retaddr); + } } return hostaddr; From patchwork Wed Jun 21 12:18:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694764 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp815710wrm; Wed, 21 Jun 2023 05:20:07 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ62r7q/88HESA4li58iKP9GD42sm29DaC5+UgDwhj9HnrQvNO3i8u+NTDshs90sPrymv6Y0 X-Received: by 2002:ad4:5cea:0:b0:631:f49a:6d34 with SMTP id iv10-20020ad45cea000000b00631f49a6d34mr5811874qvb.64.1687350006978; Wed, 21 Jun 2023 05:20:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687350006; cv=none; d=google.com; s=arc-20160816; b=smmeLtT7rJVOSZB72igRbhtWCHOHeMhE6YzsqjWnH+vTp9471CoainiBk8F94aS3dB xiEnG+bUS7zyydw4pULp3rmbBREFqU84d84oO/JAuVnP+b3NAxlbksW6+dqPaQDteuSL KT5pVUsyzuJH/M8KE/F0g8luT8TAs25Fhmuh4hTyrnqBNBYg37m2HcOo9KVBjxQe8QU0 qFr7+CfUg1he0zB3wXkdW8BmF4c4LBFyY1Hithm6+hQ/Ch/StN10YqC00K9EHKM4Bhey cXPww5iMD2mY0PmYZYBtDlBStEZr+ysstlK22ybyewiaGAYkORGKutJ1wE2UPvJyvh6C CWLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WgK1EIUfPfmDl3mDe16euilTLpZ88cE9U2pqwrFaRA8=; b=tbqYlFRJpM3fCxNqYOr1uxBSlKn8ONeyOO2luY3O71dyeZA8fw9GvIVq8bdmKETU/8 VZeNkB+qHyN8+pOcfGn8uGaQ665w4cRa3RB1xtyZwNZ8jT57AhFgz/uIn8ZfPhjSwENs QqTaSXwALmGWO4WTBAE4/VVRWV2NfPywx91edcAcscDIC89+E9lc9HexPzBB8wU1UXdB cCgt5nkuWLyc4KmkNX9EDR+sQi9RELVLqMycifEQ/64iNi2tNhTw8vKNtVJfs9i5N4Cd pbCR2nKo+rAl1F6zWPFmGOtIvWeTgNHpiVdiaCYtVPyz3YcuRd20Lo3FPsyfSSP1lACu v4SA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lacepKTW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reduce the total number of tlb bits by 1. Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/exec/cpu-all.h | 4 ++-- tcg/tcg-op-ldst.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index b5618613cc..8018ce783e 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -325,10 +325,10 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_NOTDIRTY (1 << (TARGET_PAGE_BITS_MIN - 2)) /* Set if TLB entry is an IO callback. */ #define TLB_MMIO (1 << (TARGET_PAGE_BITS_MIN - 3)) +/* Set if TLB entry writes ignored. */ +#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 4)) /* Set if the slow path must be used; more flags in CPUTLBEntryFull. */ #define TLB_FORCE_SLOW (1 << (TARGET_PAGE_BITS_MIN - 5)) -/* Set if TLB entry writes ignored. */ -#define TLB_DISCARD_WRITE (1 << (TARGET_PAGE_BITS_MIN - 6)) /* * Use this mask to check interception with an alignment mask diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index a4f51bfb6e..0fcc1618e5 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -39,7 +39,7 @@ static void check_max_alignment(unsigned a_bits) * The requested alignment cannot overlap the TLB flags. * FIXME: Must keep the count up-to-date with "exec/cpu-all.h". */ - tcg_debug_assert(a_bits + 6 <= tcg_ctx->page_bits); + tcg_debug_assert(a_bits + 5 <= tcg_ctx->page_bits); #endif } From patchwork Wed Jun 21 12:18:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694763 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp815670wrm; Wed, 21 Jun 2023 05:20:04 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4+X/9yII5YuuQ9Dw0SJ9dLRqpi2uyH+ury+hyqqH/VR3BN+2R5d/eswZcP8vQbMvkM1PGa X-Received: by 2002:a05:6214:1d08:b0:626:1e95:2feb with SMTP id e8-20020a0562141d0800b006261e952febmr20677776qvd.19.1687350004049; Wed, 21 Jun 2023 05:20:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687350004; cv=none; d=google.com; s=arc-20160816; b=AFIgGFMRTUuRs1eyc6gW0ZIah7JIQOkwOTy/kxX7YFYftd331BiEozVhLKhIyCVN4S Mq3Mk6KDYNctWpZyp1reElWYPJ89YmK8TkwZTIEDxp2gEo0JKem+ZNwqfmkgJary34Gl VHLPXGd6qhWFTvE+8Mn+QtwfVugSZa12OuwDHwHY313sP7SFR5SdRWeWpYSa9O559jzh THJZhUJOdQwILSRYOutpMBIHos0qIGb9SArNwcl0DwisfhdCLrX+VvUJP0parCkneMUg Ur7iQjlfhmqLPgb8AfXmmCTst3i+tIIGTNF6y2+P5fiRfNGyl+Q4MricvNTOv2MKgKts kHUQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GpguwOP2tBZG1Q3kxp3nwyx4GamestPy42HvjJG3rb4=; b=ZExDEemZ/9yDGx1fLV88gltMcsuIa3ARnotdPEA/Ccu0GwIUH60Bea7/yh3iBybrRE 0APrQvWBuT/AmZh4fKzWAKrGpuxUG2mGcdJxl5MnAjgL0cmQeDAGIP1ZuxcKrcWRMs2J 3QcHjcaNNEuHEeWkbmfH3beNNp/JpxHtPX0vxmM/+2aaaz2Fk7MGHJHvxiEy83JFqPUw U18Oq0k882Tlk6l9NuDejjQu6zi+BrOpT6KEIeVTK/bnnwXD9+AskAK9SufxiexuFVtx wdwAjDeip6Po+ltc9wLGKGpZzL5WPKaNRMsvxd81IbTjxwtWG7JSAyX0uljlhmUnGv/9 2Jkg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z1y6dCSE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- target/arm/tcg/translate.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 13c88ba1b9..286497ebf9 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -900,13 +900,7 @@ static inline void store_reg_from_load(DisasContext *s, int reg, TCGv_i32 var) MemOp pow2_align(unsigned i) { static const MemOp mop_align[] = { - 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, - /* - * FIXME: TARGET_PAGE_BITS_MIN affects TLB_FLAGS_MASK such - * that 256-bit alignment (MO_ALIGN_32) cannot be supported: - * see get_alignment_bits(). Enforce only 128-bit alignment for now. - */ - MO_ALIGN_16 + 0, MO_ALIGN_2, MO_ALIGN_4, MO_ALIGN_8, MO_ALIGN_16, MO_ALIGN_32 }; g_assert(i < ARRAY_SIZE(mop_align)); return mop_align[i]; From patchwork Wed Jun 21 12:18:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694770 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp817235wrm; Wed, 21 Jun 2023 05:23:06 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4z+FQQ2iDMQzes2D2xCfxtNKhwRfecy84LRxOPGEXU6gcTO814/QUW9rQmJZKdX2VB63ZF X-Received: by 2002:a05:620a:384f:b0:763:ae07:9715 with SMTP id po15-20020a05620a384f00b00763ae079715mr4587468qkn.46.1687350185963; Wed, 21 Jun 2023 05:23:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687350185; cv=none; d=google.com; s=arc-20160816; b=BD5VMNMhxI3Y1/D5g6bzTGxmseC49oiotpG2j9bfrpaPKJi7Ya7Z2w02zbF9Xr+rPu TFD3ZjJob2KMEasiyN9ZSBgUjPrq9drab1nVOOyKj2nz03PukRvcyRKdJcVJnMGCUJ7t 1qDZrWb9PM5f8XvgWsJz0S/XgYhf8r5/9VnVEl4zv50g/nu9wSjwiloaMGvNHVC+8pSj DIvKNB20tQBKUcJcYqsn4MvpuzA+rxsEGy9eZK8vCdII1N62rZ4lZTuSbQT1LcsU3Qhm LZBXbBOyLZAtTqBvow6Rz5nblqWh1XDJ4p8B6BgXBjCyGZ5r1RvbqHjUls/tdfZDeMcE fatQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=dTPy8thSqYZgAKDn29KvnLtMmsCZ90i/2T3uJj/CEGM=; b=kIFuD31/IjY53Vrt2CqOQTTY5SDqQpwsNMj/vPPkb2gzM4nfu7RaYzkqTWy6kp5Aor pYwxt/m6Eg9uja+0bxstLdrwoxAIgEaMtBA9AJvjLB7ePrxcHkv3d1G+oqhg/xAGiQSQ QfufB+NTUZXWjRdVYIGFaiohdgTBl1gO1Xzi/G0p1poPSs4DwkbU10X6Oe1CpaUQBIAT 6Jnyr3M9/d8tmBcYHCirD0uN/iICQYS2eFmCjy83MfRdzNJB0gGZiqbS8Pn7RNcGfhiJ k9vtcUeBbqlXnkzKI0HGsA6kRiGECXtIeCLmYdMDfh1zkekldYxp7eL9EL1hySvzuZ/v 4j0A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iQf0GyV4; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Target specific extensions to the page tables should be done with TARGET_PAGE_ENTRY_EXTRA. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/memattrs.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 9fb98bc1ef..1bd7b6c5ca 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -47,16 +47,6 @@ typedef struct MemTxAttrs { unsigned int requester_id:16; /* Invert endianness for this page */ unsigned int byte_swap:1; - /* - * The following are target-specific page-table bits. These are not - * related to actual memory transactions at all. However, this structure - * is part of the tlb_fill interface, cached in the cputlb structure, - * and has unused bits. These fields will be read by target-specific - * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. - */ - unsigned int target_tlb_bit0 : 1; - unsigned int target_tlb_bit1 : 1; - unsigned int target_tlb_bit2 : 1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, From patchwork Wed Jun 21 12:18:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694768 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp816319wrm; Wed, 21 Jun 2023 05:21:10 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6a9kJZ/+psXdx364kFX19GYP/5uRp3CcNtxv7Sx2rZlbjAKr7QpcyaOm5l3TJBFe6WqHnv X-Received: by 2002:a05:6214:4105:b0:618:e1d9:75b8 with SMTP id kc5-20020a056214410500b00618e1d975b8mr17137176qvb.34.1687350070462; Wed, 21 Jun 2023 05:21:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687350070; cv=none; d=google.com; s=arc-20160816; b=Sgju0sTRFGEuemmtyvpNmlcEesAFF4AQKx3tD9buZ8a2rZVzfcvP+lysYQOCX0mgEf W+WuL5YJ3Hbh0kRV/uBpFFlElS3SthaD320TqFgJAbj9tNFgWeuQXK5znPW6/7cH9EgT LFx8Kx3uFvl0qfwIo+MEBDtBP8lZ3TrGxmrjYMJul1Xg0C5Ezk3YsgCSlpag79RwbMYy RYISuyeI81lFLe1URoWAx2m/PcBsuF/L53FRQG+ooSer+DyFEFMCYSI0zu/cpOvZwgpJ si2e3rCgnoHqHW6eYgWiwz288dcgGrj9yE9TOgLSu/5l+7wJ0YyAEyxtgzy0T2RHDZkZ jKEQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+bycXui2RuZ2kW1i70HcWSrb541nDGsMKgy0HbURvr0=; b=NW1Pvw4zMfR7EAgoCvUBrvNu4kHlJAwRe9WXarCLLLnsWaySyx0okfcZ0F3ezCIB9j +/oeMhe16pA5NhAZKyDBshW2dK5Xe/fPVZXIhnMf37RsUHL1vFK1zz7zvuNZS9dbBOiw Z5ExxFmGLNdwywzj3nlqxeENVsxEXw/ZMRc2uRyX6tGj6gl3R4uErT84pCm1sTShbpY4 sgny1Zt16fC5KrIFUIXytP0BsmHDsKm9FVQsjTkqIOfa+8OETv82o9HT6vniKKd7b/z4 GvGf1iya900tpyOuV7yTamQza0ONvGgqGDeL3iXZpMjIhXD1Qnln41439AH1vZS7ABQI ym+Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=npFYVs4V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Remove MemTxAttrs.byte_swap, as the bit is not relevant to memory transactions, only the page mapping. Adjust target/sparc to set TLB_BSWAP directly. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 3 +++ include/exec/memattrs.h | 2 -- accel/tcg/cputlb.c | 5 +---- target/sparc/mmu_helper.c | 2 +- 4 files changed, 5 insertions(+), 7 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index c174d5371a..9d39252271 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -124,6 +124,9 @@ typedef struct CPUTLBEntryFull { /* @lg_page_size contains the log2 of the page size. */ uint8_t lg_page_size; + /* Additional tlb flags requested by tlb_fill. */ + uint8_t tlb_fill_flags; + /* * Additional tlb flags for use by the slow path. If non-zero, * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h index 1bd7b6c5ca..5300649c8c 100644 --- a/include/exec/memattrs.h +++ b/include/exec/memattrs.h @@ -45,8 +45,6 @@ typedef struct MemTxAttrs { unsigned int memory:1; /* Requester ID (for MSI for example) */ unsigned int requester_id:16; - /* Invert endianness for this page */ - unsigned int byte_swap:1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this, diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 152c4e9994..61f4d94a4d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1172,14 +1172,11 @@ void tlb_set_page_full(CPUState *cpu, int mmu_idx, " prot=%x idx=%d\n", vaddr, full->phys_addr, prot, mmu_idx); - read_flags = 0; + read_flags = full->tlb_fill_flags; if (full->lg_page_size < TARGET_PAGE_BITS) { /* Repeat the MMU check and TLB fill on every access. */ read_flags |= TLB_INVALID_MASK; } - if (full->attrs.byte_swap) { - read_flags |= TLB_BSWAP; - } is_ram = memory_region_is_ram(section->mr); is_romd = memory_region_is_romd(section->mr); diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 453498c670..11f03b74d2 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -580,7 +580,7 @@ static int get_physical_address_data(CPUSPARCState *env, CPUTLBEntryFull *full, int do_fault = 0; if (TTE_IS_IE(env->dtlb[i].tte)) { - full->attrs.byte_swap = true; + full->tlb_fill_flags |= TLB_BSWAP; } /* access ok? */ From patchwork Wed Jun 21 12:19:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694762 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp815596wrm; Wed, 21 Jun 2023 05:19:56 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5UjMrNgMgAX5AMDDImg+seMSgfNFPQDDOpclrOjcA1aP5hf6ojNbBuUjpYVslT9OWHskBs X-Received: by 2002:ac8:5955:0:b0:3ff:26ca:b5cc with SMTP id 21-20020ac85955000000b003ff26cab5ccmr8152959qtz.37.1687349996550; Wed, 21 Jun 2023 05:19:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687349996; cv=none; d=google.com; s=arc-20160816; b=brn9FvlVLWordTjiAJI60ymUbEBDtF0fwgZ+0gkrYrj7nqZwyJ51frSGm7sy3gW72D BTaard/OukGVsubXCTOGEA4LWox4+DJfeUdC83e58WPmJvVO0neil04eY5PQte2mThhd LAcw8AI8vi3+2MbwlJ/t4Lfh+M8awl8rn+gbsT2MBdgMLxWlimq8KsG6jT94AURolMqn oIM56gjgbRbhUqxoqL4N4N6Cj0OcaF8z13qYiHH0dZY0dGRRUM3hAC7HOIJKv5JrjK7Y SrpNJi2MJOWG8Y34Q69iFgQ3djHeoN58kKDluHBPJtlSErX1SAS+8Tk/3bqL6xd+VNld LuWw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yJm2HHOE+JbF1SBBMy6pxmjuiMpXMHdJ6dJJZMNNmag=; b=zrDJ2G2ToBOlJUL1i+CFPbFGc/tmrFZbgzgtkGzpgA/hF24O5b/FalFTi4FVjKP9PO Yk/gO0VdIoSHWxAecVSLEsRdWIcpp9qaOB4X16ZkYb61a0igeRh8Px95cT1Mom5ksFWJ lW8aeaTojZ4K3nn45DXDa++owA70DmeWfLgfC9Nuwqk2CSjqJEhAqjwgaZMJVFI2Geir KwOLfDxP6Vt7feAA25+0QUKkBjPWfF9H50wAsQ5qivWDW1jutOqSKFSKQ9p1U40Rpidk LG2HPITBLXyeFzOjpMnE+Dr3PkAnfyzFRqd6PKGVL7rNNmN9URq3YjYVqJiXjKH/Luz/ JIMg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RGV+bKP2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé --- include/exec/cpu-all.h | 4 +++- accel/tcg/cputlb.c | 27 ++++++++++++++++++++++++++- 2 files changed, 29 insertions(+), 2 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 8018ce783e..e61100fc80 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -346,8 +346,10 @@ CPUArchState *cpu_copy(CPUArchState *env); #define TLB_BSWAP (1 << 0) /* Set if TLB entry contains a watchpoint. */ #define TLB_WATCHPOINT (1 << 1) +/* Set if TLB entry requires aligned accesses. */ +#define TLB_CHECK_ALIGNED (1 << 2) -#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT) +#define TLB_SLOW_FLAGS_MASK (TLB_BSWAP | TLB_WATCHPOINT | TLB_CHECK_ALIGNED) /* The two sets of flags must not overlap. */ QEMU_BUILD_BUG_ON(TLB_FLAGS_MASK & TLB_SLOW_FLAGS_MASK); diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 61f4d94a4d..cb7b4b01e9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1553,7 +1553,7 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, flags |= full->slow_flags[access_type]; /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ - if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY))) { + if (flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY | TLB_CHECK_ALIGNED)) { *phost = NULL; return TLB_MMIO; } @@ -1909,6 +1909,31 @@ static bool mmu_lookup(CPUArchState *env, target_ulong addr, MemOpIdx oi, tcg_debug_assert((flags & TLB_BSWAP) == 0); } + /* + * This alignment check differs from the one above, in that this is + * based on the atomicity of the operation. The intended use case is + * the ARM memory type field of each PTE, where access to pages with + * Device memory type require alignment. + */ + if (unlikely(flags & TLB_CHECK_ALIGNED)) { + MemOp size = l->memop & MO_SIZE; + + switch (l->memop & MO_ATOM_MASK) { + case MO_ATOM_NONE: + size = MO_8; + break; + case MO_ATOM_IFALIGN_PAIR: + case MO_ATOM_WITHIN16_PAIR: + size = size ? size - 1 : 0; + break; + default: + break; + } + if (addr & ((1 << size) - 1)) { + cpu_unaligned_access(env_cpu(env), addr, type, l->mmu_idx, ra); + } + } + return crosspage; } From patchwork Wed Jun 21 12:19:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694769 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp817234wrm; Wed, 21 Jun 2023 05:23:05 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6l+Mi8eZMrYpHzLveL+Hr4t+bC5Vw+PSYVRbxO5exKfPpqHx7zTuVYP8WmyEnR1K9gl+/j X-Received: by 2002:a67:e9c5:0:b0:440:b21c:dbc8 with SMTP id q5-20020a67e9c5000000b00440b21cdbc8mr4055868vso.1.1687350185669; Wed, 21 Jun 2023 05:23:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687350185; cv=none; d=google.com; s=arc-20160816; b=eV41rcmQy//fwEOFZGMQ2lr2AIU21OWugNPtZ+50hKicPK0DkQgM04YLALhtOc0WPb EvarBDusRVqMIUFGrTPYAlldIEvf0dRgYbfFXNhDUGxpZNHjsrCWqkRyaVlFrfHePwFZ SR9PbZ/PknpK+ZTebpb8ABDm+ntFneXkOGx64s1Wb3aaQM6UWZ6YTINZbA6hL6lI3UP4 JvcdeK2xCHOmTexjipCH7nj4s0hb1DMLnPtxL6geMD4h9boO+0jp8gl/ish2DeriaCT0 dE6xtKKyaLliW/VTCYXa2pZ8byKCHRl8ehjuwZa7iMvjodo/uK56xDiPTQYPxojKzLry 7Y9w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=opjDePJW5lJazIvQT1fEtG6FPEXvhJQNv9O3cjFs/vU=; b=VhJI4hii9ai6O9HPbtm+Ws/lmFi+nInQqTX7rGnmDm5P5woCC9ec9xYl0sPQpM50qi FRWHFxh0GA5HREvQEkgq7vPiy20oc1w36yw/J1hZ2fT9SmsLpIaAmFpfdF3HKYWAlAXi 4GWOCuKQJX28NdxWQmD1xoWZ4jQxQzHjBKCueA3NpJhJcCQBuRhcgb7Q0RiVifngx7zC vbSozBWj2pJhi/JzrcZGIjA95OGa8srxah7VE2qLZncHWswRQ8hdpxoOIZzyKYWkZRtv blpgOp0AqhnEyqKjyQZGMFDHmI4lwuzGIHBcn1vEJNrHEfpxvtglM0A9hIZrB/vPk0HK IeKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="R7+5/dqf"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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This is more optimally done early via the MemOp given to the TCG memory operation. Reviewed-by: Philippe Mathieu-Daudé Reported-by: Idan Horowitz Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1204 Signed-off-by: Richard Henderson --- target/arm/tcg/hflags.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 616c5fa723..56d7db150a 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -25,6 +25,35 @@ static inline bool fgt_svc(CPUARMState *env, int el) FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], HFGITR_EL2, SVC_EL1); } +/* Return true if memory alignment should be enforced. */ +static bool aprofile_require_alignment(CPUARMState *env, int el, uint64_t sctlr) +{ +#ifdef CONFIG_USER_ONLY + return false; +#else + /* Check the alignment enable bit. */ + if (sctlr & SCTLR_A) { + return true; + } + + /* + * If translation is disabled, then the default memory type is + * Device(-nGnRnE) instead of Normal, which requires that alignment + * be enforced. Since this affects all ram, it is most efficient + * to handle this during translation. + */ + if (sctlr & SCTLR_M) { + /* Translation enabled: memory type in PTE via MAIR_ELx. */ + return false; + } + if (el < 2 && (arm_hcr_el2_eff(env) & (HCR_DC | HCR_VM))) { + /* Stage 2 translation enabled: memory type in PTE. */ + return false; + } + return true; +#endif +} + static CPUARMTBFlags rebuild_hflags_common(CPUARMState *env, int fp_el, ARMMMUIdx mmu_idx, CPUARMTBFlags flags) @@ -120,8 +149,9 @@ static CPUARMTBFlags rebuild_hflags_a32(CPUARMState *env, int fp_el, { CPUARMTBFlags flags = {}; int el = arm_current_el(env); + uint64_t sctlr = arm_sctlr(env, el); - if (arm_sctlr(env, el) & SCTLR_A) { + if (aprofile_require_alignment(env, el, sctlr)) { DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); } @@ -221,7 +251,7 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, sctlr = regime_sctlr(env, stage1); - if (sctlr & SCTLR_A) { + if (aprofile_require_alignment(env, el, sctlr)) { DP_TBFLAG_ANY(flags, ALIGN_MEM, 1); } From patchwork Wed Jun 21 12:19:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 694766 Delivered-To: patch@linaro.org Received: by 2002:adf:e885:0:0:0:0:0 with SMTP id d5csp815991wrm; Wed, 21 Jun 2023 05:20:36 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5FM8/vjcRUfdiJoo/xZyjj7vCmhVLZM4BKhPAiv8cLQ5WkcwCrRLws7OjsGgrI6QahnXk3 X-Received: by 2002:a05:620a:2b10:b0:762:3d71:dd4e with SMTP id do16-20020a05620a2b1000b007623d71dd4emr14009967qkb.76.1687350036503; Wed, 21 Jun 2023 05:20:36 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1687350036; cv=none; d=google.com; s=arc-20160816; b=EbTMYE+4MHh1NIX1Fb0Iao6vBfVeZNMxMcZQmyAbIxSGD9SnwwOmZi4At4Gt7lWKOK SW8AkcCyGAL+jc9h9rsxXwix9C+tVBIGhfM3VKyUYA3pzoGz313j1SYduFkSthJogYG5 p2C/tKUgxU4qm/ALfTqN7+UWP7GFL109QVhkf9Nlryxah17PtM8ouq1e79F6Bbxgs9RL 0dtgVWQwTQgrtQI0xFw6b1s08J28bcGj6pxOMLrvavoC+eefDZi5dubziRedmsa5H+1h 8f2tHZzWqegDMSRCpsc31JKm7EqmMBADT9YG6aFyD3gsmnUdzLkDCf0TydyTKsEaXQv5 jpOg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=D1z7ZijI3noWzsrc+wKPRkU7wte4eSKNmnXzrL2G2aM=; b=bjD6rca/zcIzd8PrwUFyWMiu6l6TMzVFz8L7noM4VaT5jhiwROHvgyFC5k6tqftL54 ihD0bCPOBWWGLjEliIqlwH3Ink06tdVvmdBBQ73CtEY7serGB+K+Q5NE1UG7U44erm7g t/gG62NPS2pHbOQPKr9M/Py2U/jfrYIZVpk5eAEgDlWuhPFp/tzRCJQrOaJp8g1Qxqqu tb7ZxSVvZO2mKfhgGn3MZmnOFxuAGJ4+3/7CgQQj8zGZGGcvubHJzQuoLFNW43vW7n3B 0FGQog5JvHthP02pMa5IDuU8jMOt4MJIuRrZPwgredJlR5kpDlhjBGowqWKKcQWVYssD MOqw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lBMODMeT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u3-20020a05620a120300b00763bb24fe13si926763qkj.295.2023.06.21.05.20.36 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 21 Jun 2023 05:20:36 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=lBMODMeT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1qBwo8-0006mh-0d; Wed, 21 Jun 2023 08:19:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1qBwnv-0006eF-Ow for qemu-devel@nongnu.org; Wed, 21 Jun 2023 08:19:21 -0400 Received: from mail-ed1-x52f.google.com ([2a00:1450:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1qBwnt-0000Lz-1y for qemu-devel@nongnu.org; Wed, 21 Jun 2023 08:19:19 -0400 Received: by mail-ed1-x52f.google.com with SMTP id 4fb4d7f45d1cf-5147e40bbbbso6151790a12.3 for ; Wed, 21 Jun 2023 05:19:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1687349953; x=1689941953; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=D1z7ZijI3noWzsrc+wKPRkU7wte4eSKNmnXzrL2G2aM=; b=lBMODMeTg+hkkn1GjjmH97sp2IKxM4gKQuMkdF6Ats712MlbtTnZeHgMaBjBHmD1CJ 3qRhjx4HgX4I3e/PTBCNGDjquVryQxbaSpSn4f4wb+nGTyZ94qltqv20rXS3v/Iuu6ro X/uxEca+FMStJYQwqO4lNOd9k5U930zX5U4BcsWiDHy87tFMKIrmSUPuVx/k+YNhoDbF 0AlYwjNBvn2U9Q0aXCxbHIcP8qUHuyEbxyjEX0jXr/E9jUgpNRpTqV3ue9w3rD0vcz7M 3QqAL8VxZNvyEBQFrSpoOKFv75Q1nJtl0B7F7uHWXQQW7jFKSqYe6clunBzHQFDhMK8k 1xZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1687349953; x=1689941953; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=D1z7ZijI3noWzsrc+wKPRkU7wte4eSKNmnXzrL2G2aM=; b=EE3YltcYJ+FXYSjQWIPY1xNQzIvSKylaycD77P7Ie4DpaT0e6gYFp55qWSu/RkVjO5 xcqffbU7RA0zPhfviJhuhZYiwRehTRBtVEHGaLNj9gVSt6IBl9CFzbJ3R8VVDMSWxJfx LjHc9s+hgJ8Uf31TF0rWThEbyDiHsRDObkpOEoovAqWtZojIkBwrpW4wAPuAP+jy02QG +Mp69PCXM19Q83rXQp6Y0F3P/V7mtZ5wGqE6WeCFyH3Dzf49zE/jiVvZ+STZabPcnVtg 5QnPwTVEvb5Oc+o7bQfST6I+96gItEWrPArLeOcLXD+y1t10uRFtv5W6n75Mbdu7duKD TzgQ== X-Gm-Message-State: AC+VfDxA/QGXMMcC6WFyJnonmDLDflkR0XMbHa/S7D0S5O/lvhDxBZni TfJ4DDzY+BWz2p2uS58y3iuO4G79jcix8L8/cUJn9I3W X-Received: by 2002:aa7:d78d:0:b0:51a:4557:2caf with SMTP id s13-20020aa7d78d000000b0051a45572cafmr6666542edq.34.1687349953386; Wed, 21 Jun 2023 05:19:13 -0700 (PDT) Received: from stoup.lan ([176.176.128.70]) by smtp.gmail.com with ESMTPSA id s6-20020a056402014600b0051bdf152295sm543176edu.76.2023.06.21.05.19.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Jun 2023 05:19:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 9/9] target/arm: Do memory type alignment check when translation enabled Date: Wed, 21 Jun 2023 14:19:02 +0200 Message-Id: <20230621121902.1392277-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230621121902.1392277-1-richard.henderson@linaro.org> References: <20230621121902.1392277-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-ed1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If translation is enabled, and the PTE memory type is Device, enable checking alignment via TLB_CHECK_ALIGNMENT. While the check is done later than it should be per the ARM, it's better than not performing the check at all. Signed-off-by: Richard Henderson --- target/arm/ptw.c | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 37bcb17a9e..8dcd5d80ce 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -227,6 +227,16 @@ static bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx, return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0; } +static bool S1_attrs_are_device(uint8_t attrs) +{ + /* + * This slightly under-decodes the MAIR_ELx field: + * 0b0000dd01 is Device with FEAT_XS, otherwise UNPREDICTABLE; + * 0b0000dd1x is UNPREDICTABLE. + */ + return (attrs & 0xf0) == 0; +} + static bool S2_attrs_are_device(uint64_t hcr, uint8_t attrs) { /* @@ -1274,6 +1284,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, bool aarch64 = arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; bool nstable; + bool device; /* TODO: This code does not support shareability levels. */ if (aarch64) { @@ -1623,6 +1634,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, if (regime_is_stage2(mmu_idx)) { result->cacheattrs.is_s2_format = true; result->cacheattrs.attrs = extract32(attrs, 2, 4); + device = S2_attrs_are_device(arm_hcr_el2_eff_secstate(env, is_secure), + result->cacheattrs.attrs); } else { /* Index into MAIR registers for cache attributes */ uint8_t attrindx = extract32(attrs, 2, 3); @@ -1635,6 +1648,21 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Translate *ptw, if (aarch64 && cpu_isar_feature(aa64_bti, cpu)) { result->f.guarded = extract64(attrs, 50, 1); /* GP */ } + device = S1_attrs_are_device(result->cacheattrs.attrs); + } + + /* + * Enable alignment checks on Device memory. + * + * Per R_XCHFJ, this check is mis-ordered, in that this alignment check + * should have priority 30, while the permission check should be next at + * priority 31 and stage2 translation faults come after that. + * Due to the way the TCG softmmu TLB operates, we will have implicitly + * done the permission check and the stage2 lookup in finding the TLB + * entry, so the alignment check cannot be done sooner. + */ + if (device) { + result->f.tlb_fill_flags |= TLB_CHECK_ALIGNED; } /*