From patchwork Mon Jun 19 20:11:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 694722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 480A2EB64D9 for ; Mon, 19 Jun 2023 20:12:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230151AbjFSUM2 (ORCPT ); Mon, 19 Jun 2023 16:12:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229964AbjFSUM0 (ORCPT ); Mon, 19 Jun 2023 16:12:26 -0400 X-Greylist: delayed 61 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 19 Jun 2023 13:12:24 PDT Received: from h1.cmg2.smtp.forpsi.com (h1.cmg2.smtp.forpsi.com [81.2.195.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CAC881B4 for ; Mon, 19 Jun 2023 13:12:24 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id BLDbqAqZEv5uIBLDcqiBGn; Mon, 19 Jun 2023 22:11:21 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205481; bh=3L8XUUElAukUJ5zvUpBIUvwYMZnIT3tvRsfA6+l1vsw=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=sjY46GMJJ9aBL1igxyo2GL1gAHMytf3AM6yXE2TiZ5HsU4YzE2CCpETvk+bbpAZM/ DInQE+mrryfztnUfiOG5MZsza6mTWNDZZ+LmRwfwzzK5G+7Jc/N/O+6nuLdNiguPlb VBE26QNKwYGYev+zVD7o6XH3uEg/5wm0FckcwjFqBnyUwKRGWSYFGWJk3GqI/nEl/0 IQOVFUPhYUrpx1vYtIxEa0U/75Xc/mPJF64lKpqoPI4IcjeuUGltLsSff+vSqmyarG yPBgIfsSRV2x5sG8849F4a02OGkl4VZYIPLinETjAowxpyQ+osPVSgUlpgZeTNKvpA pTxTGIfiX8I6A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205481; bh=3L8XUUElAukUJ5zvUpBIUvwYMZnIT3tvRsfA6+l1vsw=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=sjY46GMJJ9aBL1igxyo2GL1gAHMytf3AM6yXE2TiZ5HsU4YzE2CCpETvk+bbpAZM/ DInQE+mrryfztnUfiOG5MZsza6mTWNDZZ+LmRwfwzzK5G+7Jc/N/O+6nuLdNiguPlb VBE26QNKwYGYev+zVD7o6XH3uEg/5wm0FckcwjFqBnyUwKRGWSYFGWJk3GqI/nEl/0 IQOVFUPhYUrpx1vYtIxEa0U/75Xc/mPJF64lKpqoPI4IcjeuUGltLsSff+vSqmyarG yPBgIfsSRV2x5sG8849F4a02OGkl4VZYIPLinETjAowxpyQ+osPVSgUlpgZeTNKvpA pTxTGIfiX8I6A== Date: Mon, 19 Jun 2023 22:11:19 +0200 From: Ladislav Michl To: Thinh Nguyen Cc: linux-usb@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 01/11] MIPS: OCTEON: octeon-usb: add all register offsets Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfKk8v0+7ZgbvNuwIc8ABro7BZEnu3BHjxX6N5rGCmKRluPHTOntpr1uQq49VYVteWJbdFq40FUMS0P0Tna/NER5lHHIyOGlN1WND1+UwDOQOxjYcQGLu rkj9TGZzMQd9VnhDx3beZXifXWtTax1Fw3Ny7CtRkYk4UXF+oR4fqBJqf3B7k3POzLSBuY+lz5Xgu1OZcSBfG62yz9flOliVbJiDoGyKbk6Z3FeEzthHQyaE snVTeNZOVT1+UhSwMk3u9A== Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Glue code uses a mix of offset and absolute address register definition. Define all of them as offsets and use them consistently. Signed-off-by: Ladislav Michl --- arch/mips/cavium-octeon/octeon-usb.c | 35 +++++++++++++++++----------- 1 file changed, 21 insertions(+), 14 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c index 28677c615175..4d22eaa8a644 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/arch/mips/cavium-octeon/octeon-usb.c @@ -17,6 +17,19 @@ #include +#define USBDRD_UCTL_CTL 0x00 +#define USBDRD_UCTL_BIST_STATUS 0x08 +#define USBDRD_UCTL_SPARE0 0x10 +#define USBDRD_UCTL_INTSTAT 0x30 +#define USBDRD_UCTL_PORT_CFG_HS(port) (0x40 + (0x20 * port)) +#define USBDRD_UCTL_PORT_CFG_SS(port) (0x48 + (0x20 * port)) +#define USBDRD_UCTL_PORT_CR_DBG_CFG(port) (0x50 + (0x20 * port)) +#define USBDRD_UCTL_PORT_CR_DBG_STATUS(port) (0x58 + (0x20 * port)) +#define USBDRD_UCTL_HOST_CFG 0xe0 +#define USBDRD_UCTL_SHIM_CFG 0xe8 +#define USBDRD_UCTL_ECC 0xf0 +#define USBDRD_UCTL_SPARE1 0xf8 + /* USB Control Register */ union cvm_usbdrd_uctl_ctl { uint64_t u64; @@ -227,7 +240,6 @@ static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32}; static int dwc3_octeon_config_power(struct device *dev, u64 base) { -#define UCTL_HOST_CFG 0xe0 union cvm_usbdrd_uctl_host_cfg uctl_host_cfg; union cvmx_gpio_bit_cfgx gpio_bit; uint32_t gpio_pwr[3]; @@ -268,16 +280,16 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base) } /* Enable XHCI power control and set if active high or low. */ - uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); + uctl_host_cfg.u64 = cvmx_read_csr(base + USBDRD_UCTL_HOST_CFG); uctl_host_cfg.s.ppc_en = 1; uctl_host_cfg.s.ppc_active_high_en = !power_active_low; - cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); + cvmx_write_csr(base + USBDRD_UCTL_HOST_CFG, uctl_host_cfg.u64); } else { /* Disable XHCI power control and set if active high. */ - uctl_host_cfg.u64 = cvmx_read_csr(base + UCTL_HOST_CFG); + uctl_host_cfg.u64 = cvmx_read_csr(base + USBDRD_UCTL_HOST_CFG); uctl_host_cfg.s.ppc_en = 0; uctl_host_cfg.s.ppc_active_high_en = 0; - cvmx_write_csr(base + UCTL_HOST_CFG, uctl_host_cfg.u64); + cvmx_write_csr(base + USBDRD_UCTL_HOST_CFG, uctl_host_cfg.u64); dev_info(dev, "power control disabled\n"); } return 0; @@ -464,10 +476,9 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) static void __init dwc3_octeon_set_endian_mode(u64 base) { -#define UCTL_SHIM_CFG 0xe8 union cvm_usbdrd_uctl_shim_cfg shim_cfg; - shim_cfg.u64 = cvmx_read_csr(base + UCTL_SHIM_CFG); + shim_cfg.u64 = cvmx_read_csr(base + USBDRD_UCTL_SHIM_CFG); #ifdef __BIG_ENDIAN shim_cfg.s.dma_endian_mode = 1; shim_cfg.s.csr_endian_mode = 1; @@ -475,20 +486,16 @@ static void __init dwc3_octeon_set_endian_mode(u64 base) shim_cfg.s.dma_endian_mode = 0; shim_cfg.s.csr_endian_mode = 0; #endif - cvmx_write_csr(base + UCTL_SHIM_CFG, shim_cfg.u64); + cvmx_write_csr(base + USBDRD_UCTL_SHIM_CFG, shim_cfg.u64); } -#define CVMX_USBDRDX_UCTL_CTL(index) \ - (CVMX_ADD_IO_SEG(0x0001180068000000ull) + \ - ((index & 1) * 0x1000000ull)) static void __init dwc3_octeon_phy_reset(u64 base) { union cvm_usbdrd_uctl_ctl uctl_ctl; - int index = (base >> 24) & 1; - uctl_ctl.u64 = cvmx_read_csr(CVMX_USBDRDX_UCTL_CTL(index)); + uctl_ctl.u64 = cvmx_read_csr(base + USBDRD_UCTL_CTL); uctl_ctl.s.uphy_rst = 0; - cvmx_write_csr(CVMX_USBDRDX_UCTL_CTL(index), uctl_ctl.u64); + cvmx_write_csr(base + USBDRD_UCTL_CTL, uctl_ctl.u64); } static int __init dwc3_octeon_device_init(void) From patchwork Mon Jun 19 20:11:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 694721 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60C64EB64D9 for ; Mon, 19 Jun 2023 20:12:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230252AbjFSUMu (ORCPT ); Mon, 19 Jun 2023 16:12:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229852AbjFSUMt (ORCPT ); Mon, 19 Jun 2023 16:12:49 -0400 Received: from h1.cmg2.smtp.forpsi.com (h1.cmg2.smtp.forpsi.com [81.2.195.188]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 43BA213D for ; Mon, 19 Jun 2023 13:12:47 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id BLDzqAqfXv5uIBLE1qiBIR; Mon, 19 Jun 2023 22:11:45 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205505; bh=KWAwmoxUPL4fboAB5flSZfvLEvkHjPU5FTttzMCJ6lE=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=oq8mejCUrt4+k8qd/UmMZ8ruqY01BxwvA7aITRU7DJJMZgFWc7K6iTscVmiD4EUlr 2d3qXfqHanydOdTbUaOMpG6edASnezjGjHO0Iq8LH+fNpyU7bXmo+Dt5rNja/tAtKk 6FooE4p0gPy8HFvKbrmwg1EjqBeCprNsUCMR30akMWFEsk+n90mobmaqr+IY6kyy0/ LyPSdl6sm7wHltdIIOA0odobng52bduqPdwd/hKdxVO/Tm2Mg0Anfi6mGv9iXD489J //5N80Lh2lEYv0JihGFhhSs6+VXIOnUxaxLE75E1E3IuQdcWm9UtG6kXmKTbnVfwmw xkxiQ18RKOK6A== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205505; bh=KWAwmoxUPL4fboAB5flSZfvLEvkHjPU5FTttzMCJ6lE=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=oq8mejCUrt4+k8qd/UmMZ8ruqY01BxwvA7aITRU7DJJMZgFWc7K6iTscVmiD4EUlr 2d3qXfqHanydOdTbUaOMpG6edASnezjGjHO0Iq8LH+fNpyU7bXmo+Dt5rNja/tAtKk 6FooE4p0gPy8HFvKbrmwg1EjqBeCprNsUCMR30akMWFEsk+n90mobmaqr+IY6kyy0/ LyPSdl6sm7wHltdIIOA0odobng52bduqPdwd/hKdxVO/Tm2Mg0Anfi6mGv9iXD489J //5N80Lh2lEYv0JihGFhhSs6+VXIOnUxaxLE75E1E3IuQdcWm9UtG6kXmKTbnVfwmw xkxiQ18RKOK6A== Date: Mon, 19 Jun 2023 22:11:43 +0200 From: Ladislav Michl To: Thinh Nguyen Cc: linux-usb@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 02/11] MIPS: OCTEON: octeon-usb: use bitfields for control register Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfAoX8pCNtDqtycWU8qB+qs0lZHpTf0pM96pXKafPFzMdMQfX4Wr+6cv5I+Kh3sNakhjjZQawWOQ/9Rx8N+rbI8WkNAg/yCAsCkn1VQeX6F5SQRtFUoy8 LpQSZ0DFZf+A2dfVMWZlB3jsetMghbhwi0Nfr3+mnDTnwGXNWqqJywal4zIDfkNNQwinVniAaP5dIjpCofBjPw/jqTXuKt0UBb085qg0T746oubDGlmsWZP6 QQfYAlxlomJo8w5+Y/RKXg== Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Code needs to compile for all platforms in order to move it to drivers/usb/dwc3. Use Linux standard bitfield access macros to manipulate control register. Signed-off-by: Ladislav Michl --- arch/mips/cavium-octeon/octeon-usb.c | 330 +++++++++++++-------------- 1 file changed, 159 insertions(+), 171 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c index 4d22eaa8a644..e8e57d0c3b14 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/arch/mips/cavium-octeon/octeon-usb.c @@ -8,16 +8,117 @@ * for more details. */ -#include +#include +#include #include -#include #include -#include #include +#include +#include +#include #include +/* + * USB Control Register + */ #define USBDRD_UCTL_CTL 0x00 +/* BIST fast-clear mode select. A BIST run with this bit set + * clears all entries in USBH RAMs to 0x0. + */ +# define USBDRD_UCTL_CTL_CLEAR_BIST BIT(63) +/* 1 = Start BIST and cleared by hardware */ +# define USBDRD_UCTL_CTL_START_BIST BIT(62) +/* Reference clock select for SuperSpeed and HighSpeed PLLs: + * 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock + * 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock + * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock & + * HighSpeed PLL uses PLL_REF_CLK for reference clck + * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock & + * HighSpeed PLL uses PLL_REF_CLK for reference clck + */ +# define USBDRD_UCTL_CTL_REF_CLK_SEL GENMASK(61, 60) +/* 1 = Spread-spectrum clock enable, 0 = SS clock disable */ +# define USBDRD_UCTL_CTL_SSC_EN BIT(59) +/* Spread-spectrum clock modulation range: + * 0x0 = -4980 ppm downspread + * 0x1 = -4492 ppm downspread + * 0x2 = -4003 ppm downspread + * 0x3 - 0x7 = Reserved + */ +# define USBDRD_UCTL_CTL_SSC_RANGE GENMASK(58, 56) +/* Enable non-standard oscillator frequencies: + * [55:53] = modules -1 + * [52:47] = 2's complement push amount, 0 = Feature disabled + */ +# define USBDRD_UCTL_CTL_SSC_REF_CLK_SEL GENMASK(55, 47) +/* Reference clock multiplier for non-standard frequencies: + * 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 + * 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 + * 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 + * Other Values = Reserved + */ +# define USBDRD_UCTL_CTL_MPLL_MULTIPLIER GENMASK(46, 40) +/* Enable reference clock to prescaler for SuperSpeed functionality. + * Should always be set to "1" + */ +# define USBDRD_UCTL_CTL_REF_SSP_EN BIT(39) +/* Divide the reference clock by 2 before entering the + * REF_CLK_FSEL divider: + * If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal + * If REF_CLK_SEL = 0x2 or 0x3, then: + * 0x1 = DLMC_REF_CLK* is 125MHz + * 0x0 = DLMC_REF_CLK* is another supported frequency + */ +# define USBDRD_UCTL_CTL_REF_CLK_DIV2 BIT(38) +/* Select reference clock freqnuency for both PLL blocks: + * 0x27 = REF_CLK_SEL is 0x0 or 0x1 + * 0x07 = REF_CLK_SEL is 0x2 or 0x3 + */ +# define USBDRD_UCTL_CTL_REF_CLK_FSEL GENMASK(37, 32) +/* Controller clock enable. */ +# define USBDRD_UCTL_CTL_H_CLK_EN BIT(30) +/* Select bypass input to controller clock divider: + * 0x0 = Use divided coprocessor clock from H_CLKDIV + * 0x1 = Use clock from GPIO pins + */ +# define USBDRD_UCTL_CTL_H_CLK_BYP_SEL BIT(29) +/* Reset controller clock divider. */ +# define USBDRD_UCTL_CTL_H_CLKDIV_RST BIT(28) +/* Clock divider select: + * 0x0 = divide by 1 + * 0x1 = divide by 2 + * 0x2 = divide by 4 + * 0x3 = divide by 6 + * 0x4 = divide by 8 + * 0x5 = divide by 16 + * 0x6 = divide by 24 + * 0x7 = divide by 32 + */ +# define USBDRD_UCTL_CTL_H_CLKDIV_SEL GENMASK(26, 24) +/* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_USB3_PORT_PERM_ATTACH BIT(21) +/* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_USB2_PORT_PERM_ATTACH BIT(20) +/* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_USB3_PORT_DISABLE BIT(18) +/* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_USB2_PORT_DISABLE BIT(16) +/* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_SS_POWER_EN BIT(14) +/* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_HS_POWER_EN BIT(12) +/* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */ +# define USBDRD_UCTL_CTL_CSCLK_EN BIT(4) +/* Controller mode: 0x0 = Host, 0x1 = Device */ +# define USBDRD_UCTL_CTL_DRD_MODE BIT(3) +/* PHY reset */ +# define USBDRD_UCTL_CTL_UPHY_RST BIT(2) +/* Software reset UAHC */ +# define USBDRD_UCTL_CTL_UAHC_RST BIT(1) +/* Software resets UCTL */ +# define USBDRD_UCTL_CTL_UCTL_RST BIT(0) + #define USBDRD_UCTL_BIST_STATUS 0x08 #define USBDRD_UCTL_SPARE0 0x10 #define USBDRD_UCTL_INTSTAT 0x30 @@ -30,123 +131,6 @@ #define USBDRD_UCTL_ECC 0xf0 #define USBDRD_UCTL_SPARE1 0xf8 -/* USB Control Register */ -union cvm_usbdrd_uctl_ctl { - uint64_t u64; - struct cvm_usbdrd_uctl_ctl_s { - /* 1 = BIST and set all USB RAMs to 0x0, 0 = BIST */ - __BITFIELD_FIELD(uint64_t clear_bist:1, - /* 1 = Start BIST and cleared by hardware */ - __BITFIELD_FIELD(uint64_t start_bist:1, - /* Reference clock select for SuperSpeed and HighSpeed PLLs: - * 0x0 = Both PLLs use DLMC_REF_CLK0 for reference clock - * 0x1 = Both PLLs use DLMC_REF_CLK1 for reference clock - * 0x2 = SuperSpeed PLL uses DLMC_REF_CLK0 for reference clock & - * HighSpeed PLL uses PLL_REF_CLK for reference clck - * 0x3 = SuperSpeed PLL uses DLMC_REF_CLK1 for reference clock & - * HighSpeed PLL uses PLL_REF_CLK for reference clck - */ - __BITFIELD_FIELD(uint64_t ref_clk_sel:2, - /* 1 = Spread-spectrum clock enable, 0 = SS clock disable */ - __BITFIELD_FIELD(uint64_t ssc_en:1, - /* Spread-spectrum clock modulation range: - * 0x0 = -4980 ppm downspread - * 0x1 = -4492 ppm downspread - * 0x2 = -4003 ppm downspread - * 0x3 - 0x7 = Reserved - */ - __BITFIELD_FIELD(uint64_t ssc_range:3, - /* Enable non-standard oscillator frequencies: - * [55:53] = modules -1 - * [52:47] = 2's complement push amount, 0 = Feature disabled - */ - __BITFIELD_FIELD(uint64_t ssc_ref_clk_sel:9, - /* Reference clock multiplier for non-standard frequencies: - * 0x19 = 100MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 - * 0x28 = 125MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 - * 0x32 = 50MHz on DLMC_REF_CLK* if REF_CLK_SEL = 0x0 or 0x1 - * Other Values = Reserved - */ - __BITFIELD_FIELD(uint64_t mpll_multiplier:7, - /* Enable reference clock to prescaler for SuperSpeed functionality. - * Should always be set to "1" - */ - __BITFIELD_FIELD(uint64_t ref_ssp_en:1, - /* Divide the reference clock by 2 before entering the - * REF_CLK_FSEL divider: - * If REF_CLK_SEL = 0x0 or 0x1, then only 0x0 is legal - * If REF_CLK_SEL = 0x2 or 0x3, then: - * 0x1 = DLMC_REF_CLK* is 125MHz - * 0x0 = DLMC_REF_CLK* is another supported frequency - */ - __BITFIELD_FIELD(uint64_t ref_clk_div2:1, - /* Select reference clock freqnuency for both PLL blocks: - * 0x27 = REF_CLK_SEL is 0x0 or 0x1 - * 0x07 = REF_CLK_SEL is 0x2 or 0x3 - */ - __BITFIELD_FIELD(uint64_t ref_clk_fsel:6, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_31_31:1, - /* Controller clock enable. */ - __BITFIELD_FIELD(uint64_t h_clk_en:1, - /* Select bypass input to controller clock divider: - * 0x0 = Use divided coprocessor clock from H_CLKDIV - * 0x1 = Use clock from GPIO pins - */ - __BITFIELD_FIELD(uint64_t h_clk_byp_sel:1, - /* Reset controller clock divider. */ - __BITFIELD_FIELD(uint64_t h_clkdiv_rst:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_27_27:1, - /* Clock divider select: - * 0x0 = divide by 1 - * 0x1 = divide by 2 - * 0x2 = divide by 4 - * 0x3 = divide by 6 - * 0x4 = divide by 8 - * 0x5 = divide by 16 - * 0x6 = divide by 24 - * 0x7 = divide by 32 - */ - __BITFIELD_FIELD(uint64_t h_clkdiv_sel:3, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_22_23:2, - /* USB3 port permanently attached: 0x0 = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t usb3_port_perm_attach:1, - /* USB2 port permanently attached: 0x0 = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t usb2_port_perm_attach:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_19_19:1, - /* Disable SuperSpeed PHY: 0x0 = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t usb3_port_disable:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_17_17:1, - /* Disable HighSpeed PHY: 0x0 = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t usb2_port_disable:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_15_15:1, - /* Enable PHY SuperSpeed block power: 0x0 = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t ss_power_en:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_13_13:1, - /* Enable PHY HighSpeed block power: 0x0 = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t hs_power_en:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_5_11:7, - /* Enable USB UCTL interface clock: 0xx = No, 0x1 = Yes */ - __BITFIELD_FIELD(uint64_t csclk_en:1, - /* Controller mode: 0x0 = Host, 0x1 = Device */ - __BITFIELD_FIELD(uint64_t drd_mode:1, - /* PHY reset */ - __BITFIELD_FIELD(uint64_t uphy_rst:1, - /* Software reset UAHC */ - __BITFIELD_FIELD(uint64_t uahc_rst:1, - /* Software resets UCTL */ - __BITFIELD_FIELD(uint64_t uctl_rst:1, - ;))))))))))))))))))))))))))))))))) - } s; -}; - /* UAHC Configuration Register */ union cvm_usbdrd_uctl_host_cfg { uint64_t u64; @@ -297,14 +281,10 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base) static int dwc3_octeon_clocks_start(struct device *dev, u64 base) { - union cvm_usbdrd_uctl_ctl uctl_ctl; - int ref_clk_sel = 2; - u64 div; + int i, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; u32 clock_rate; - int mpll_mul; - int i; - u64 h_clk_rate; - u64 uctl_ctl_reg = base; + u64 div, h_clk_rate, val; + u64 uctl_ctl_reg = base + USBDRD_UCTL_CTL; if (dev->of_node) { const char *ss_clock_type; @@ -368,16 +348,16 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */ /* Step 3: Assert all resets. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.uphy_rst = 1; - uctl_ctl.s.uahc_rst = 1; - uctl_ctl.s.uctl_rst = 1; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val = cvmx_read_csr(uctl_ctl_reg); + val |= USBDRD_UCTL_CTL_UPHY_RST | + USBDRD_UCTL_CTL_UAHC_RST | + USBDRD_UCTL_CTL_UCTL_RST; + cvmx_write_csr(uctl_ctl_reg, val); /* Step 4a: Reset the clock dividers. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.h_clkdiv_rst = 1; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val = cvmx_read_csr(uctl_ctl_reg); + val |= USBDRD_UCTL_CTL_H_CLKDIV_RST; + cvmx_write_csr(uctl_ctl_reg, val); /* Step 4b: Select controller clock frequency. */ for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) { @@ -386,26 +366,29 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) h_clk_rate >= OCTEON_MIN_H_CLK_RATE) break; } - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.h_clkdiv_sel = div; - uctl_ctl.s.h_clk_en = 1; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - if ((div != uctl_ctl.s.h_clkdiv_sel) || (!uctl_ctl.s.h_clk_en)) { + val = cvmx_read_csr(uctl_ctl_reg); + val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL; + val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div); + val |= USBDRD_UCTL_CTL_H_CLK_EN; + cvmx_write_csr(uctl_ctl_reg, val); + val = cvmx_read_csr(uctl_ctl_reg); + if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) || + (!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) { dev_err(dev, "dwc3 controller clock init failure.\n"); return -EINVAL; } /* Step 4c: Deassert the controller clock divider reset. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.h_clkdiv_rst = 0; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val &= ~USBDRD_UCTL_CTL_H_CLKDIV_RST; + cvmx_write_csr(uctl_ctl_reg, val); /* Step 5a: Reference clock configuration. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.ref_clk_sel = ref_clk_sel; - uctl_ctl.s.ref_clk_fsel = 0x07; - uctl_ctl.s.ref_clk_div2 = 0; + val = cvmx_read_csr(uctl_ctl_reg); + val &= ~USBDRD_UCTL_CTL_REF_CLK_DIV2; + val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL; + val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel); + + ref_clk_fsel = 0x07; switch (clock_rate) { default: dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", @@ -414,7 +397,7 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) case 100000000: mpll_mul = 0x19; if (ref_clk_sel < 2) - uctl_ctl.s.ref_clk_fsel = 0x27; + ref_clk_fsel = 0x27; break; case 50000000: mpll_mul = 0x32; @@ -423,28 +406,32 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) mpll_mul = 0x28; break; } - uctl_ctl.s.mpll_multiplier = mpll_mul; + val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL; + val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel); + + val &= ~USBDRD_UCTL_CTL_MPLL_MULTIPLIER; + val |= FIELD_PREP(USBDRD_UCTL_CTL_MPLL_MULTIPLIER, mpll_mul); /* Step 5b: Configure and enable spread-spectrum for SuperSpeed. */ - uctl_ctl.s.ssc_en = 1; + val |= USBDRD_UCTL_CTL_SSC_EN; /* Step 5c: Enable SuperSpeed. */ - uctl_ctl.s.ref_ssp_en = 1; + val |= USBDRD_UCTL_CTL_REF_SSP_EN; /* Step 5d: Configure PHYs. SKIP */ /* Step 6a & 6b: Power up PHYs. */ - uctl_ctl.s.hs_power_en = 1; - uctl_ctl.s.ss_power_en = 1; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val |= USBDRD_UCTL_CTL_HS_POWER_EN; + val |= USBDRD_UCTL_CTL_SS_POWER_EN; + cvmx_write_csr(uctl_ctl_reg, val); /* Step 7: Wait 10 controller-clock cycles to take effect. */ udelay(10); /* Step 8a: Deassert UCTL reset signal. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.uctl_rst = 0; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val = cvmx_read_csr(uctl_ctl_reg); + val &= ~USBDRD_UCTL_CTL_UCTL_RST; + cvmx_write_csr(uctl_ctl_reg, val); /* Step 8b: Wait 10 controller-clock cycles. */ udelay(10); @@ -454,22 +441,22 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) return -EINVAL; /* Step 8d: Deassert UAHC reset signal. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.uahc_rst = 0; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val = cvmx_read_csr(uctl_ctl_reg); + val &= ~USBDRD_UCTL_CTL_UAHC_RST; + cvmx_write_csr(uctl_ctl_reg, val); /* Step 8e: Wait 10 controller-clock cycles. */ udelay(10); /* Step 9: Enable conditional coprocessor clock of UCTL. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.csclk_en = 1; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val = cvmx_read_csr(uctl_ctl_reg); + val |= USBDRD_UCTL_CTL_CSCLK_EN; + cvmx_write_csr(uctl_ctl_reg, val); /*Step 10: Set for host mode only. */ - uctl_ctl.u64 = cvmx_read_csr(uctl_ctl_reg); - uctl_ctl.s.drd_mode = 0; - cvmx_write_csr(uctl_ctl_reg, uctl_ctl.u64); + val = cvmx_read_csr(uctl_ctl_reg); + val &= ~USBDRD_UCTL_CTL_DRD_MODE; + cvmx_write_csr(uctl_ctl_reg, val); return 0; } @@ -491,11 +478,12 @@ static void __init dwc3_octeon_set_endian_mode(u64 base) static void __init dwc3_octeon_phy_reset(u64 base) { - union cvm_usbdrd_uctl_ctl uctl_ctl; + u64 val; + u64 uctl_ctl_reg = base + USBDRD_UCTL_CTL; - uctl_ctl.u64 = cvmx_read_csr(base + USBDRD_UCTL_CTL); - uctl_ctl.s.uphy_rst = 0; - cvmx_write_csr(base + USBDRD_UCTL_CTL, uctl_ctl.u64); + val = cvmx_read_csr(uctl_ctl_reg); + val &= ~USBDRD_UCTL_CTL_UPHY_RST; + cvmx_write_csr(uctl_ctl_reg, val); } static int __init dwc3_octeon_device_init(void) From patchwork Mon Jun 19 20:12:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 694417 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 28D51EB64D9 for ; Mon, 19 Jun 2023 20:12:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230132AbjFSUMS (ORCPT ); Mon, 19 Jun 2023 16:12:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58942 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229964AbjFSUMR (ORCPT ); Mon, 19 Jun 2023 16:12:17 -0400 Received: from h3.cmg1.smtp.forpsi.com (h3.cmg1.smtp.forpsi.com [185.129.138.162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C11B813D for ; Mon, 19 Jun 2023 13:12:13 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id BLEQq51TSPm6CBLESqL6zD; Mon, 19 Jun 2023 22:12:12 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205532; bh=5ANEcQq0rsjguuLgM80u50gslNI6pWw0/tkjtsmRLGM=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=iFiXn9cJtUIFKouaxwHWHbWoFOrO37QB43xmqqmI9S14yrLNvOcV/w9sPlAyFZZh7 +RMrnGKLNnbR1XhD+hj4horMotuVcEOkfsBWraycyj6/K8hnwVhjfPXcVtEAs2NIjI ugA1c7B6ARHaXSK9ZiUJL91GHqAg0PGaNmiTy5wKgbhIBHQBRSXSyIPALGzDPG1+Ex Iz8jc6Fqo0ok2ItYKz4JqEg4b7CnlZ+HPW4QDCa5rhYVNOTBkojtuZe7sDSu9RNhvY SPmi6yLmWeUxcOOZ87hW7KdMMmToJbK7k7Ev7NcWfbgJm7dHuuSeUe+/x34Dfpi9JR N/AGn1pI3GglQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205532; bh=5ANEcQq0rsjguuLgM80u50gslNI6pWw0/tkjtsmRLGM=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=iFiXn9cJtUIFKouaxwHWHbWoFOrO37QB43xmqqmI9S14yrLNvOcV/w9sPlAyFZZh7 +RMrnGKLNnbR1XhD+hj4horMotuVcEOkfsBWraycyj6/K8hnwVhjfPXcVtEAs2NIjI ugA1c7B6ARHaXSK9ZiUJL91GHqAg0PGaNmiTy5wKgbhIBHQBRSXSyIPALGzDPG1+Ex Iz8jc6Fqo0ok2ItYKz4JqEg4b7CnlZ+HPW4QDCa5rhYVNOTBkojtuZe7sDSu9RNhvY SPmi6yLmWeUxcOOZ87hW7KdMMmToJbK7k7Ev7NcWfbgJm7dHuuSeUe+/x34Dfpi9JR N/AGn1pI3GglQ== Date: Mon, 19 Jun 2023 22:12:10 +0200 From: Ladislav Michl To: Thinh Nguyen Cc: linux-usb@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 03/11] MIPS: OCTEON: octeon-usb: use bitfields for host config register Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfIOkLxTZTF1ppV4iRn78iHlJuJT8Z6t65ryY8TxRiK+tUak6y/ThvNe4oSoGyIoslGZXGBfNyGkI+YLi2bXIhw5CI3SouQXOjC+RoFSm1t500qYVho4h aavfPimB0sbpOsIl/n1w9JG7dztFuf/BdD5b5vHUUfZdacNpHCxlvmvj6kSiFfIOKpc/uKeYiFzg+7Td16TwQgg9Eu/kd8pKI/WsUIZbx2XQSQNXAxVb/+cM 4p4xWvvPpe3MhRT4AfiUOQ== Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Use Linux standard bitfield access macros to manipulate host config register. Signed-off-by: Ladislav Michl --- arch/mips/cavium-octeon/octeon-usb.c | 83 +++++++++++++--------------- 1 file changed, 38 insertions(+), 45 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c index e8e57d0c3b14..17051aee491d 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/arch/mips/cavium-octeon/octeon-usb.c @@ -126,47 +126,36 @@ #define USBDRD_UCTL_PORT_CFG_SS(port) (0x48 + (0x20 * port)) #define USBDRD_UCTL_PORT_CR_DBG_CFG(port) (0x50 + (0x20 * port)) #define USBDRD_UCTL_PORT_CR_DBG_STATUS(port) (0x58 + (0x20 * port)) + +/* + * UCTL Configuration Register + */ #define USBDRD_UCTL_HOST_CFG 0xe0 +/* Indicates minimum value of all received BELT values */ +# define USBDRD_UCTL_HOST_CFG_HOST_CURRENT_BELT GENMASK(59, 48) +/* HS jitter adjustment */ +# define USBDRD_UCTL_HOST_CFG_FLA GENMASK(37, 32) +/* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */ +# define USBDRD_UCTL_HOST_CFG_BME BIT(28) +/* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */ +# define USBDRD_UCTL_HOST_OCI_EN BIT(27) +/* Overcurrent sene selection: + * 0x0 = Overcurrent indication from off-chip is active-low + * 0x1 = Overcurrent indication from off-chip is active-high + */ +# define USBDRD_UCTL_HOST_OCI_ACTIVE_HIGH_EN BIT(26) +/* Port power control enable: 0x0 = unavailable, 0x1 = available */ +# define USBDRD_UCTL_HOST_PPC_EN BIT(25) +/* Port power control sense selection: + * 0x0 = Port power to off-chip is active-low + * 0x1 = Port power to off-chip is active-high + */ +# define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN BIT(24) + #define USBDRD_UCTL_SHIM_CFG 0xe8 #define USBDRD_UCTL_ECC 0xf0 #define USBDRD_UCTL_SPARE1 0xf8 -/* UAHC Configuration Register */ -union cvm_usbdrd_uctl_host_cfg { - uint64_t u64; - struct cvm_usbdrd_uctl_host_cfg_s { - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_60_63:4, - /* Indicates minimum value of all received BELT values */ - __BITFIELD_FIELD(uint64_t host_current_belt:12, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_38_47:10, - /* HS jitter adjustment */ - __BITFIELD_FIELD(uint64_t fla:6, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_29_31:3, - /* Bus-master enable: 0x0 = Disabled (stall DMAs), 0x1 = enabled */ - __BITFIELD_FIELD(uint64_t bme:1, - /* Overcurrent protection enable: 0x0 = unavailable, 0x1 = available */ - __BITFIELD_FIELD(uint64_t oci_en:1, - /* Overcurrent sene selection: - * 0x0 = Overcurrent indication from off-chip is active-low - * 0x1 = Overcurrent indication from off-chip is active-high - */ - __BITFIELD_FIELD(uint64_t oci_active_high_en:1, - /* Port power control enable: 0x0 = unavailable, 0x1 = available */ - __BITFIELD_FIELD(uint64_t ppc_en:1, - /* Port power control sense selection: - * 0x0 = Port power to off-chip is active-low - * 0x1 = Port power to off-chip is active-high - */ - __BITFIELD_FIELD(uint64_t ppc_active_high_en:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_0_23:24, - ;))))))))))) - } s; -}; - /* UCTL Shim Features Register */ union cvm_usbdrd_uctl_shim_cfg { uint64_t u64; @@ -224,12 +213,13 @@ static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32}; static int dwc3_octeon_config_power(struct device *dev, u64 base) { - union cvm_usbdrd_uctl_host_cfg uctl_host_cfg; union cvmx_gpio_bit_cfgx gpio_bit; uint32_t gpio_pwr[3]; int gpio, len, power_active_low; struct device_node *node = dev->of_node; int index = (base >> 24) & 1; + u64 val; + u64 uctl_host_cfg_reg = base + USBDRD_UCTL_HOST_CFG; if (of_find_property(node, "power", &len) != NULL) { if (len == 12) { @@ -264,16 +254,19 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base) } /* Enable XHCI power control and set if active high or low. */ - uctl_host_cfg.u64 = cvmx_read_csr(base + USBDRD_UCTL_HOST_CFG); - uctl_host_cfg.s.ppc_en = 1; - uctl_host_cfg.s.ppc_active_high_en = !power_active_low; - cvmx_write_csr(base + USBDRD_UCTL_HOST_CFG, uctl_host_cfg.u64); + val = cvmx_read_csr(uctl_host_cfg_reg); + val |= USBDRD_UCTL_HOST_PPC_EN; + if (power_active_low) + val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; + else + val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; + cvmx_write_csr(uctl_host_cfg_reg, val); } else { /* Disable XHCI power control and set if active high. */ - uctl_host_cfg.u64 = cvmx_read_csr(base + USBDRD_UCTL_HOST_CFG); - uctl_host_cfg.s.ppc_en = 0; - uctl_host_cfg.s.ppc_active_high_en = 0; - cvmx_write_csr(base + USBDRD_UCTL_HOST_CFG, uctl_host_cfg.u64); + val = cvmx_read_csr(uctl_host_cfg_reg); + val &= ~USBDRD_UCTL_HOST_PPC_EN; + val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; + cvmx_write_csr(uctl_host_cfg_reg, val); dev_info(dev, "power control disabled\n"); } return 0; From patchwork Mon Jun 19 20:12:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 694416 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8CC93EB64DA for ; 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a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205556; bh=lyCbjqHo7qkwYB9OohFbhbYIko9aM20GhJlzYuX2OhY=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=rMTeh3n0tWsPXHQGL7oVdumJ8UPBh8msvZNzAEEWpiVjDNiOWDecvvgVyC1D+XCjS GPAZnYHFBBRwhiWOW791fP6rmZOYlF25DT2EvnlcNosYzW7IAgdTsYmcB/lY8ULfvr hAy93ejCaI05jF1jfe9jVBNEqN/aTvt0SCt9RVqhGXzjGfAV4P0uW3BX0gVLqGPE3q T0cvQXcEVhSHp0MSniyqsTNbROt4QkYSsr6+2Z21JHtBKm+RgWVPjFvYvJqCILPAgK 48PJHpDHIG4dh2C2AiQBZO/2FHFF/+93OJBdyo2/sPqK0OQ3yWdKNl3G7mbtCXj7uq pIjwoetHhH+4w== Date: Mon, 19 Jun 2023 22:12:34 +0200 From: Ladislav Michl To: Thinh Nguyen Cc: linux-usb@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 04/11] MIPS: OCTEON: octeon-usb: use bitfields for shim register Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfOQoUkTR/cfOd95jOLfVwC6n+t1GYeXJD8XUFvnQY46yvUrjKYLc3q/fQNiDOm9Kmp1TvXon6sCiV1J9/WOzPVHnC11qHegcf448WKMW2trGZXBFzzOl MGKCjxHzqehjuF0OTpX9XmqIAFeewY4wC1POc3jKJ09oKLoeOMzFGfXKBFJd5+KArGtmqTJsSGLax5qRjc1CVk/L6/OykHKMMHqnx8Atn9H/nI/okvapCwI8 32a///sr6rjLtdXjEmAeCA== Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Use Linux standard bitfield access macros to manipulate shim register. Signed-off-by: Ladislav Michl --- arch/mips/cavium-octeon/octeon-usb.c | 96 ++++++++++++---------------- 1 file changed, 41 insertions(+), 55 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c index 17051aee491d..1c48ee77125a 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/arch/mips/cavium-octeon/octeon-usb.c @@ -152,57 +152,43 @@ */ # define USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN BIT(24) +/* + * UCTL Shim Features Register + */ #define USBDRD_UCTL_SHIM_CFG 0xe8 +/* Out-of-bound UAHC register access: 0 = read, 1 = write */ +# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_WRN BIT(63) +/* SRCID error log for out-of-bound UAHC register access: + * [59:58] = chipID + * [57] = Request source: 0 = core, 1 = NCB-device + * [56:51] = Core/NCB-device number, [56] always 0 for NCB devices + * [50:48] = SubID + */ +# define USBDRD_UCTL_SHIM_CFG_XS_NCB_OOB_OSRC GENMASK(59, 48) +/* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */ +# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_WRN BIT(47) +/* Encoded error type for bad UAHC DMA */ +# define USBDRD_UCTL_SHIM_CFG_XM_BAD_DMA_TYPE GENMASK(43, 40) +/* Select the IOI read command used by DMA accesses */ +# define USBDRD_UCTL_SHIM_CFG_DMA_READ_CMD BIT(12) +/* Select endian format for DMA accesses to the L2C: + * 0x0 = Little endian + * 0x1 = Big endian + * 0x2 = Reserved + * 0x3 = Reserved + */ +# define USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE GENMASK(9, 8) +/* Select endian format for IOI CSR access to UAHC: + * 0x0 = Little endian + * 0x1 = Big endian + * 0x2 = Reserved + * 0x3 = Reserved + */ +# define USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE GENMASK(1, 0) + #define USBDRD_UCTL_ECC 0xf0 #define USBDRD_UCTL_SPARE1 0xf8 -/* UCTL Shim Features Register */ -union cvm_usbdrd_uctl_shim_cfg { - uint64_t u64; - struct cvm_usbdrd_uctl_shim_cfg_s { - /* Out-of-bound UAHC register access: 0 = read, 1 = write */ - __BITFIELD_FIELD(uint64_t xs_ncb_oob_wrn:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_60_62:3, - /* SRCID error log for out-of-bound UAHC register access: - * [59:58] = chipID - * [57] = Request source: 0 = core, 1 = NCB-device - * [56:51] = Core/NCB-device number, [56] always 0 for NCB devices - * [50:48] = SubID - */ - __BITFIELD_FIELD(uint64_t xs_ncb_oob_osrc:12, - /* Error log for bad UAHC DMA access: 0 = Read log, 1 = Write log */ - __BITFIELD_FIELD(uint64_t xm_bad_dma_wrn:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_44_46:3, - /* Encoded error type for bad UAHC DMA */ - __BITFIELD_FIELD(uint64_t xm_bad_dma_type:4, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_13_39:27, - /* Select the IOI read command used by DMA accesses */ - __BITFIELD_FIELD(uint64_t dma_read_cmd:1, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_10_11:2, - /* Select endian format for DMA accesses to the L2c: - * 0x0 = Little endian - *` 0x1 = Big endian - * 0x2 = Reserved - * 0x3 = Reserved - */ - __BITFIELD_FIELD(uint64_t dma_endian_mode:2, - /* Reserved */ - __BITFIELD_FIELD(uint64_t reserved_2_7:6, - /* Select endian format for IOI CSR access to UAHC: - * 0x0 = Little endian - *` 0x1 = Big endian - * 0x2 = Reserved - * 0x3 = Reserved - */ - __BITFIELD_FIELD(uint64_t csr_endian_mode:2, - ;)))))))))))) - } s; -}; - #define OCTEON_H_CLKDIV_SEL 8 #define OCTEON_MIN_H_CLK_RATE 150000000 #define OCTEON_MAX_H_CLK_RATE 300000000 @@ -456,17 +442,17 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) static void __init dwc3_octeon_set_endian_mode(u64 base) { - union cvm_usbdrd_uctl_shim_cfg shim_cfg; + u64 val; + u64 uctl_shim_cfg_reg = base + USBDRD_UCTL_SHIM_CFG; - shim_cfg.u64 = cvmx_read_csr(base + USBDRD_UCTL_SHIM_CFG); + val = cvmx_read_csr(uctl_shim_cfg_reg); + val &= ~USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE; + val &= ~USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE; #ifdef __BIG_ENDIAN - shim_cfg.s.dma_endian_mode = 1; - shim_cfg.s.csr_endian_mode = 1; -#else - shim_cfg.s.dma_endian_mode = 0; - shim_cfg.s.csr_endian_mode = 0; + val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1); + val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1); #endif - cvmx_write_csr(base + USBDRD_UCTL_SHIM_CFG, shim_cfg.u64); + cvmx_write_csr(uctl_shim_cfg_reg, val); } static void __init dwc3_octeon_phy_reset(u64 base) From patchwork Mon Jun 19 20:13:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 694415 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CE8CEB64DB for ; Mon, 19 Jun 2023 20:13:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230229AbjFSUNV (ORCPT ); Mon, 19 Jun 2023 16:13:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59294 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230256AbjFSUNT (ORCPT ); Mon, 19 Jun 2023 16:13:19 -0400 Received: from h3.cmg1.smtp.forpsi.com (h3.cmg1.smtp.forpsi.com [185.129.138.162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BA9F4D3 for ; Mon, 19 Jun 2023 13:13:18 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id BLFTq51krPm6CBLFUqL76A; Mon, 19 Jun 2023 22:13:17 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205597; bh=La5RVvh62/rh2LKqh8/r8tTls0RHx4TgLGa6q6WIl7g=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=nxN1eeaOBMm4vLOJm4c4W+M4x5AuV5Ol4VWv5QGpQOBBC+GCFP+Y3yFUvOyLN7tyT rszT/0xKpEdfMscDXpVUsh3PzETBiuHPTqX4f5hT/L09az0XSN26NRNWMw7GfGtR+R VD/ZvpalDUmxGOAKrg9xX/H/c2FXUI/SXb3TatnAS5c2E7xvYSLe3lex2CwmWvNz8H BmonnCBsBVX01I2J6tBPoA27W0q3lqZi84NmB6jf8ZOTOxz6ywYDNN93yh/VUoNvI7 qW4gCzUvVMYTwpRWAH6oHjkCA0Aq8zfoaXcDhY6vl2LcG+0DFcMbu5QcBtu8t4Hyea SotDa+3/rWj8g== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205597; bh=La5RVvh62/rh2LKqh8/r8tTls0RHx4TgLGa6q6WIl7g=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=nxN1eeaOBMm4vLOJm4c4W+M4x5AuV5Ol4VWv5QGpQOBBC+GCFP+Y3yFUvOyLN7tyT rszT/0xKpEdfMscDXpVUsh3PzETBiuHPTqX4f5hT/L09az0XSN26NRNWMw7GfGtR+R VD/ZvpalDUmxGOAKrg9xX/H/c2FXUI/SXb3TatnAS5c2E7xvYSLe3lex2CwmWvNz8H BmonnCBsBVX01I2J6tBPoA27W0q3lqZi84NmB6jf8ZOTOxz6ywYDNN93yh/VUoNvI7 qW4gCzUvVMYTwpRWAH6oHjkCA0Aq8zfoaXcDhY6vl2LcG+0DFcMbu5QcBtu8t4Hyea SotDa+3/rWj8g== Date: Mon, 19 Jun 2023 22:13:14 +0200 From: Ladislav Michl To: Thinh Nguyen Cc: linux-usb@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 05/11] MIPS: OCTEON: octeon-usb: move gpio config to separate function Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfHEMptSr/xQTLVSvx4YLnxQfTwq4AfmkXmluBzlj5HV4LagHlBTN9ng0H6DBzlQp2RhZcI1cjmienFcjYKVEg90aioEz6UlVOIZZjPy4gyEj/pEZ9YZ4 60P5Lubzc99dYKfU3wdRJaaPZKKWhsI/KlhZ1IsaqaJCUfwJxB0EXRkubKNTLwVZTV9MiEP3DBx5N70Pd9lhqEnIF28EehrCa/543n6PkA+oJsfSKDOpyRp8 hJr0U6glvZ4uP6/VwVk+Xw== Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org Power gpio configuration is using Octeon specific code, so move it to separate function, that can later be guarded with ifdefs. Signed-off-by: Ladislav Michl --- arch/mips/cavium-octeon/octeon-usb.c | 45 +++++++++++++++------------- 1 file changed, 25 insertions(+), 20 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c index 1c48ee77125a..0f9800b3d373 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/arch/mips/cavium-octeon/octeon-usb.c @@ -197,13 +197,35 @@ static DEFINE_MUTEX(dwc3_octeon_clocks_mutex); static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32}; -static int dwc3_octeon_config_power(struct device *dev, u64 base) +static void dwc3_octeon_config_gpio(int index, int gpio) { union cvmx_gpio_bit_cfgx gpio_bit; + + if ((OCTEON_IS_MODEL(OCTEON_CN73XX) || + OCTEON_IS_MODEL(OCTEON_CNF75XX)) + && gpio <= 31) { + gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); + gpio_bit.s.tx_oe = 1; + gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); + } else if (gpio <= 15) { + gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); + gpio_bit.s.tx_oe = 1; + gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); + cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); + } else { + gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio)); + gpio_bit.s.tx_oe = 1; + gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); + cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64); + } +} + +static int dwc3_octeon_config_power(struct device *dev, u64 base) +{ uint32_t gpio_pwr[3]; int gpio, len, power_active_low; struct device_node *node = dev->of_node; - int index = (base >> 24) & 1; u64 val; u64 uctl_host_cfg_reg = base + USBDRD_UCTL_HOST_CFG; @@ -220,24 +242,7 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base) dev_err(dev, "invalid power configuration\n"); return -EINVAL; } - if ((OCTEON_IS_MODEL(OCTEON_CN73XX) || - OCTEON_IS_MODEL(OCTEON_CNF75XX)) - && gpio <= 31) { - gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); - gpio_bit.s.tx_oe = 1; - gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x15); - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); - } else if (gpio <= 15) { - gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_BIT_CFGX(gpio)); - gpio_bit.s.tx_oe = 1; - gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); - cvmx_write_csr(CVMX_GPIO_BIT_CFGX(gpio), gpio_bit.u64); - } else { - gpio_bit.u64 = cvmx_read_csr(CVMX_GPIO_XBIT_CFGX(gpio)); - gpio_bit.s.tx_oe = 1; - gpio_bit.s.output_sel = (index == 0 ? 0x14 : 0x19); - cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64); - } + dwc3_octeon_config_gpio((base >> 24) & 1, gpio); /* Enable XHCI power control and set if active high or low. */ val = cvmx_read_csr(uctl_host_cfg_reg); From patchwork Mon Jun 19 20:13:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 694720 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE344EB64D9 for ; Mon, 19 Jun 2023 20:13:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230302AbjFSUNn (ORCPT ); Mon, 19 Jun 2023 16:13:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59362 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230256AbjFSUNl (ORCPT ); Mon, 19 Jun 2023 16:13:41 -0400 Received: from h3.cmg1.smtp.forpsi.com (h3.cmg1.smtp.forpsi.com [185.129.138.162]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 40B38D3 for ; Mon, 19 Jun 2023 13:13:40 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id BLFqq51rDPm6CBLFrqL77g; Mon, 19 Jun 2023 22:13:39 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205619; bh=sJgByPYaHelCEmPEMcq6UGvIHEgdEeueJysFidIRM4o=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=OewVUyO9XbVdoTJeFWJX5DcTz+mQkWpbK1cTRZMD9hG13el+TOB2Z+uEsg7+kPqm8 vI5A+PgaI2gu0pvgzG2csulvBIhMkQTyTo9Cy9q3LgOFi2EkQ78UD+lTXeRaGCSwSh +5BMBoQ/lAP8c3wfkchiE50nfgPmHDi3mZV6pfSIGwerbrfh9pU7dfFUJQglFlLI4z 1WUJC+IEQ08HCFjPOUyYEW2JG7hCHJi4wFv0AVWHfKYW3TzB4qys++kXCrt9g5N5fz 3EWrxxxxoPHe8fjV5bG/fldT96jHFqmMlMhynIeQltm2Lmt3vBR+LHfaCuH0wWiFpX ERrlUvROKvapQ== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205619; bh=sJgByPYaHelCEmPEMcq6UGvIHEgdEeueJysFidIRM4o=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=OewVUyO9XbVdoTJeFWJX5DcTz+mQkWpbK1cTRZMD9hG13el+TOB2Z+uEsg7+kPqm8 vI5A+PgaI2gu0pvgzG2csulvBIhMkQTyTo9Cy9q3LgOFi2EkQ78UD+lTXeRaGCSwSh +5BMBoQ/lAP8c3wfkchiE50nfgPmHDi3mZV6pfSIGwerbrfh9pU7dfFUJQglFlLI4z 1WUJC+IEQ08HCFjPOUyYEW2JG7hCHJi4wFv0AVWHfKYW3TzB4qys++kXCrt9g5N5fz 3EWrxxxxoPHe8fjV5bG/fldT96jHFqmMlMhynIeQltm2Lmt3vBR+LHfaCuH0wWiFpX ERrlUvROKvapQ== Date: Mon, 19 Jun 2023 22:13:38 +0200 From: Ladislav Michl To: Thinh Nguyen Cc: linux-usb@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 06/11] MIPS: OCTEON: octeon-usb: introduce dwc3_octeon_{read,write}q Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfBQ53SS9WPg3VQw92CtWaBW3pXL5WYrSTuPtOyPKFQAh6to+mGgQdQjKSZOJLpKKfUyYsmuawgsrLnmEtxdip40lmNtE7cyeYHMhlMQtVqJRkbiD+KhB pT6mJOJu/ZKBJhl/f4PJ0b+syjwxc2qk/T9onXuFCQhZPxm56q7BDx1bhNDdf5h9Eg6QuGMvU8eLcmsaazWwsncFTbSeT0JzxrXxUCoDOfwW3c11X35DjAZO p+N5g7K65la95SCHgrq8bA== Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Move all register access code into separate functions and provide their no-op version for non Octeon platforms. Later it might be possible to replace them with standard Linux functions, however datasheets are not publicly available and I have only one Octeon board to test, so lets stay on safe side for now. Signed-off-by: Ladislav Michl --- arch/mips/cavium-octeon/octeon-usb.c | 99 +++++++++++++++++----------- 1 file changed, 59 insertions(+), 40 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c index 0f9800b3d373..aaddc874f0ca 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/arch/mips/cavium-octeon/octeon-usb.c @@ -17,8 +17,6 @@ #include #include -#include - /* * USB Control Register */ @@ -196,6 +194,17 @@ static DEFINE_MUTEX(dwc3_octeon_clocks_mutex); static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32}; +#ifdef CONFIG_CAVIUM_OCTEON_SOC +#include +static inline uint64_t dwc3_octeon_readq(void __iomem *addr) +{ + return cvmx_readq_csr(addr); +} + +static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) +{ + cvmx_writeq_csr(base, val); +} static void dwc3_octeon_config_gpio(int index, int gpio) { @@ -220,14 +229,24 @@ static void dwc3_octeon_config_gpio(int index, int gpio) cvmx_write_csr(CVMX_GPIO_XBIT_CFGX(gpio), gpio_bit.u64); } } +#else +static inline uint64_t dwc3_octeon_readq(void __iomem *addr) +{ + return 0; +} + +static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { } + +static inline void dwc3_octeon_config_gpio(int index, int gpio) { } +#endif -static int dwc3_octeon_config_power(struct device *dev, u64 base) +static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) { uint32_t gpio_pwr[3]; int gpio, len, power_active_low; struct device_node *node = dev->of_node; u64 val; - u64 uctl_host_cfg_reg = base + USBDRD_UCTL_HOST_CFG; + void __iomem *uctl_host_cfg_reg = base + USBDRD_UCTL_HOST_CFG; if (of_find_property(node, "power", &len) != NULL) { if (len == 12) { @@ -242,33 +261,33 @@ static int dwc3_octeon_config_power(struct device *dev, u64 base) dev_err(dev, "invalid power configuration\n"); return -EINVAL; } - dwc3_octeon_config_gpio((base >> 24) & 1, gpio); + dwc3_octeon_config_gpio(((u64)base >> 24) & 1, gpio); /* Enable XHCI power control and set if active high or low. */ - val = cvmx_read_csr(uctl_host_cfg_reg); + val = dwc3_octeon_readq(uctl_host_cfg_reg); val |= USBDRD_UCTL_HOST_PPC_EN; if (power_active_low) val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; else val |= USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; - cvmx_write_csr(uctl_host_cfg_reg, val); + dwc3_octeon_writeq(uctl_host_cfg_reg, val); } else { /* Disable XHCI power control and set if active high. */ - val = cvmx_read_csr(uctl_host_cfg_reg); + val = dwc3_octeon_readq(uctl_host_cfg_reg); val &= ~USBDRD_UCTL_HOST_PPC_EN; val &= ~USBDRD_UCTL_HOST_PPC_ACTIVE_HIGH_EN; - cvmx_write_csr(uctl_host_cfg_reg, val); + dwc3_octeon_writeq(uctl_host_cfg_reg, val); dev_info(dev, "power control disabled\n"); } return 0; } -static int dwc3_octeon_clocks_start(struct device *dev, u64 base) +static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) { int i, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; u32 clock_rate; u64 div, h_clk_rate, val; - u64 uctl_ctl_reg = base + USBDRD_UCTL_CTL; + void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; if (dev->of_node) { const char *ss_clock_type; @@ -332,16 +351,16 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) /* Step 2: Select GPIO for overcurrent indication, if desired. SKIP */ /* Step 3: Assert all resets. */ - val = cvmx_read_csr(uctl_ctl_reg); + val = dwc3_octeon_readq(uctl_ctl_reg); val |= USBDRD_UCTL_CTL_UPHY_RST | USBDRD_UCTL_CTL_UAHC_RST | USBDRD_UCTL_CTL_UCTL_RST; - cvmx_write_csr(uctl_ctl_reg, val); + dwc3_octeon_writeq(uctl_ctl_reg, val); /* Step 4a: Reset the clock dividers. */ - val = cvmx_read_csr(uctl_ctl_reg); + val = dwc3_octeon_readq(uctl_ctl_reg); val |= USBDRD_UCTL_CTL_H_CLKDIV_RST; - cvmx_write_csr(uctl_ctl_reg, val); + dwc3_octeon_writeq(uctl_ctl_reg, val); /* Step 4b: Select controller clock frequency. */ for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) { @@ -350,12 +369,12 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) h_clk_rate >= OCTEON_MIN_H_CLK_RATE) break; } - val = cvmx_read_csr(uctl_ctl_reg); + val = dwc3_octeon_readq(uctl_ctl_reg); val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div); val |= USBDRD_UCTL_CTL_H_CLK_EN; - cvmx_write_csr(uctl_ctl_reg, val); - val = cvmx_read_csr(uctl_ctl_reg); + dwc3_octeon_writeq(uctl_ctl_reg, val); + val = dwc3_octeon_readq(uctl_ctl_reg); if ((div != FIELD_GET(USBDRD_UCTL_CTL_H_CLKDIV_SEL, val)) || (!(FIELD_GET(USBDRD_UCTL_CTL_H_CLK_EN, val)))) { dev_err(dev, "dwc3 controller clock init failure.\n"); @@ -364,10 +383,10 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) /* Step 4c: Deassert the controller clock divider reset. */ val &= ~USBDRD_UCTL_CTL_H_CLKDIV_RST; - cvmx_write_csr(uctl_ctl_reg, val); + dwc3_octeon_writeq(uctl_ctl_reg, val); /* Step 5a: Reference clock configuration. */ - val = cvmx_read_csr(uctl_ctl_reg); + val = dwc3_octeon_readq(uctl_ctl_reg); val &= ~USBDRD_UCTL_CTL_REF_CLK_DIV2; val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel); @@ -407,15 +426,15 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) /* Step 6a & 6b: Power up PHYs. */ val |= USBDRD_UCTL_CTL_HS_POWER_EN; val |= USBDRD_UCTL_CTL_SS_POWER_EN; - cvmx_write_csr(uctl_ctl_reg, val); + dwc3_octeon_writeq(uctl_ctl_reg, val); /* Step 7: Wait 10 controller-clock cycles to take effect. */ udelay(10); /* Step 8a: Deassert UCTL reset signal. */ - val = cvmx_read_csr(uctl_ctl_reg); + val = dwc3_octeon_readq(uctl_ctl_reg); val &= ~USBDRD_UCTL_CTL_UCTL_RST; - cvmx_write_csr(uctl_ctl_reg, val); + dwc3_octeon_writeq(uctl_ctl_reg, val); /* Step 8b: Wait 10 controller-clock cycles. */ udelay(10); @@ -425,49 +444,49 @@ static int dwc3_octeon_clocks_start(struct device *dev, u64 base) return -EINVAL; /* Step 8d: Deassert UAHC reset signal. */ - val = cvmx_read_csr(uctl_ctl_reg); + val = dwc3_octeon_readq(uctl_ctl_reg); val &= ~USBDRD_UCTL_CTL_UAHC_RST; - cvmx_write_csr(uctl_ctl_reg, val); + dwc3_octeon_writeq(uctl_ctl_reg, val); /* Step 8e: Wait 10 controller-clock cycles. */ udelay(10); /* Step 9: Enable conditional coprocessor clock of UCTL. */ - val = cvmx_read_csr(uctl_ctl_reg); + val = dwc3_octeon_readq(uctl_ctl_reg); val |= USBDRD_UCTL_CTL_CSCLK_EN; - cvmx_write_csr(uctl_ctl_reg, val); + dwc3_octeon_writeq(uctl_ctl_reg, val); /*Step 10: Set for host mode only. */ - val = cvmx_read_csr(uctl_ctl_reg); + val = dwc3_octeon_readq(uctl_ctl_reg); val &= ~USBDRD_UCTL_CTL_DRD_MODE; - cvmx_write_csr(uctl_ctl_reg, val); + dwc3_octeon_writeq(uctl_ctl_reg, val); return 0; } -static void __init dwc3_octeon_set_endian_mode(u64 base) +static void __init dwc3_octeon_set_endian_mode(void __iomem *base) { u64 val; - u64 uctl_shim_cfg_reg = base + USBDRD_UCTL_SHIM_CFG; + void __iomem *uctl_shim_cfg_reg = base + USBDRD_UCTL_SHIM_CFG; - val = cvmx_read_csr(uctl_shim_cfg_reg); + val = dwc3_octeon_readq(uctl_shim_cfg_reg); val &= ~USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE; val &= ~USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE; #ifdef __BIG_ENDIAN val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_DMA_ENDIAN_MODE, 1); val |= FIELD_PREP(USBDRD_UCTL_SHIM_CFG_CSR_ENDIAN_MODE, 1); #endif - cvmx_write_csr(uctl_shim_cfg_reg, val); + dwc3_octeon_writeq(uctl_shim_cfg_reg, val); } -static void __init dwc3_octeon_phy_reset(u64 base) +static void __init dwc3_octeon_phy_reset(void __iomem *base) { u64 val; - u64 uctl_ctl_reg = base + USBDRD_UCTL_CTL; + void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; - val = cvmx_read_csr(uctl_ctl_reg); + val = dwc3_octeon_readq(uctl_ctl_reg); val &= ~USBDRD_UCTL_CTL_UPHY_RST; - cvmx_write_csr(uctl_ctl_reg, val); + dwc3_octeon_writeq(uctl_ctl_reg, val); } static int __init dwc3_octeon_device_init(void) @@ -506,10 +525,10 @@ static int __init dwc3_octeon_device_init(void) } mutex_lock(&dwc3_octeon_clocks_mutex); - if (dwc3_octeon_clocks_start(&pdev->dev, (u64)base) == 0) + if (dwc3_octeon_clocks_start(&pdev->dev, base) == 0) dev_info(&pdev->dev, "clocks initialized.\n"); - dwc3_octeon_set_endian_mode((u64)base); - dwc3_octeon_phy_reset((u64)base); + dwc3_octeon_set_endian_mode(base); + dwc3_octeon_phy_reset(base); mutex_unlock(&dwc3_octeon_clocks_mutex); devm_iounmap(&pdev->dev, base); devm_release_mem_region(&pdev->dev, res->start, From patchwork Mon Jun 19 20:14:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 694414 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4FED6EB64DB for ; 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a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205644; bh=NN3sMROPSk+1aWuzxy0eMWXQTX8wAQ/HmoruSCWv9hs=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=JjnpOKvZnw9FY/N3spVaJoDTbX9d8+k45MMQeJ5sRffUAYAjkLYEnPebefkIba4Iy X8e4u9eOGCYyoNCNTZSoJlg4WDSqbRD2cN/M7ZvFtiM824U1r2aWTTtPLALZbvEh0p DzMfWOkUL7FfRyx9Rt1zfPadL7YTXBwk0QZ8oY5Zl8W21VLj9CGNIh9G+tAbK4LWyN 3W20L2rQZIq5Xq6NGmvmnn05t6QazqSrx/T0P0ezyX1TkJ/ldFj/fGxYLR0d13SEmO 1LcNtmr1SUSmcuNfuEN3CA+NpVsxXGs8YhQUJVJACyb8B0Jss/2m7nKAIyn/sGGfRd 1hetqp6hACc0A== Date: Mon, 19 Jun 2023 22:14:03 +0200 From: Ladislav Michl To: Thinh Nguyen Cc: linux-usb@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 07/11] MIPS: OCTEON: octeon-usb: cleanup divider calculation Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfPzEkbw4klkTN/+pprv6eUIKlF0uA+gWSx42M8Dua9PCWO/8tVWkGUCjuKcM2JKSKWi8GJMB4MjPOcf1/owdFG5JepzE0CnNb9C0csd6fWMQd/cHGXEV zWjVbqajVIMn8kfrCjfqWZKTEp/8/1ByvodOGzwsfl9tGjTQEUSaHdfWpYknvNGcY52SLaqjAVWxw2L9tSoXjxu4dmwroM1yqIa5N7Sfkj0N7WT+RpM9wxaU 2YjAMdrBVqshpXQ85ZRe7A== Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Simple self-contained function is easier to review. Signed-off-by: Ladislav Michl --- arch/mips/cavium-octeon/octeon-usb.c | 31 ++++++++++++++++------------ 1 file changed, 18 insertions(+), 13 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/arch/mips/cavium-octeon/octeon-usb.c index aaddc874f0ca..2add435ad038 100644 --- a/arch/mips/cavium-octeon/octeon-usb.c +++ b/arch/mips/cavium-octeon/octeon-usb.c @@ -187,12 +187,7 @@ #define USBDRD_UCTL_ECC 0xf0 #define USBDRD_UCTL_SPARE1 0xf8 -#define OCTEON_H_CLKDIV_SEL 8 -#define OCTEON_MIN_H_CLK_RATE 150000000 -#define OCTEON_MAX_H_CLK_RATE 300000000 - static DEFINE_MUTEX(dwc3_octeon_clocks_mutex); -static uint8_t clk_div[OCTEON_H_CLKDIV_SEL] = {1, 2, 4, 6, 8, 16, 24, 32}; #ifdef CONFIG_CAVIUM_OCTEON_SOC #include @@ -240,6 +235,21 @@ static inline void dwc3_octeon_writeq(void __iomem *base, uint64_t val) { } static inline void dwc3_octeon_config_gpio(int index, int gpio) { } #endif +static int dwc3_octeon_get_divider(void) +{ + static const uint8_t clk_div[] = { 1, 2, 4, 6, 8, 16, 24, 32 }; + int div = 0; + + while (div < ARRAY_SIZE(clk_div)) { + uint64_t rate = octeon_get_io_clock_rate() / clk_div[div]; + if (rate <= 300000000 && rate >= 150000000) + break; + div++; + } + + return div; +} + static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) { uint32_t gpio_pwr[3]; @@ -284,9 +294,9 @@ static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) { - int i, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; + int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; u32 clock_rate; - u64 div, h_clk_rate, val; + u64 val; void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; if (dev->of_node) { @@ -363,12 +373,7 @@ static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) dwc3_octeon_writeq(uctl_ctl_reg, val); /* Step 4b: Select controller clock frequency. */ - for (div = 0; div < OCTEON_H_CLKDIV_SEL; div++) { - h_clk_rate = octeon_get_io_clock_rate() / clk_div[div]; - if (h_clk_rate <= OCTEON_MAX_H_CLK_RATE && - h_clk_rate >= OCTEON_MIN_H_CLK_RATE) - break; - } + div = dwc3_octeon_get_divider(); val = dwc3_octeon_readq(uctl_ctl_reg); val &= ~USBDRD_UCTL_CTL_H_CLKDIV_SEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_H_CLKDIV_SEL, div); From patchwork Mon Jun 19 20:14:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 694719 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D0104EB64DA for ; Mon, 19 Jun 2023 20:14:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229558AbjFSUOm (ORCPT ); Mon, 19 Jun 2023 16:14:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59866 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229812AbjFSUOk (ORCPT ); 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h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=0PUxHHojJmE0m/qfxAFhNlQTJJ0WUa4BvhQmg/HaK6/RLBVyzGcXtrKK6HmZCm4xz iS+d1d7xCLVF2fBu4Zl6olKmkzbtFcNqvGZcKlRY+mSfHWLfkFtOkvYwQ1SynHRDnr QLsYZFAQgzHALyG38AzP+ERG2ztla/35WFpEGrbpMUMWaAovxjLdZiwLw/C+2jtpst ZB7z/1hZ9Ti2gJ09F4eC+dmMvsvUa5YPdPKQMy24UaY9tJUEa7pH/H0YgTjYv7PzTj a9lDcGZyesR/j3WhkMPchsRtUo8t8lkQm7+wIayRHEZEQPX1hjOJ3awIQfGrffhM2K IK1NL09HBuoWw== Date: Mon, 19 Jun 2023 22:14:36 +0200 From: Ladislav Michl To: Thinh Nguyen Cc: linux-usb@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 08/11] usb: dwc3: Move Octeon glue code from arch/mips Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfLVNMqCzFDWyvZFUcgMmG/XXz0DNGTs4zXP19WofCqFuPW9ChA2kqx7ZOXqM4tOqxSSfBW6sijhduTAeIxAA4OUxkkItKswf6RNskyInr5VlFnn5z5UN RHQ5BYeUECrqQ9BeN3qU49yPBvNXRGXIoVUIC5Hq5iCdn0ZY+/YsjO9zgktZIpOfS9kGZk+qJ1HQqsymAPbM4CAAuNXEoJ03Hj+Y+K4SLU9qEUcp/J+TEHLl tFABXKtItGBygSpUcw7B8Q== Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Octeon DWC3 glue code now compiles on all platforms, so move it to drivers/usb/dwc3. No functional changes. Signed-off-by: Ladislav Michl Acked-By: Thomas Bogendoerfer --- arch/mips/cavium-octeon/Makefile | 1 - drivers/usb/dwc3/Kconfig | 9 +++++++++ drivers/usb/dwc3/Makefile | 1 + .../octeon-usb.c => drivers/usb/dwc3/dwc3-octeon.c | 0 4 files changed, 10 insertions(+), 1 deletion(-) rename arch/mips/cavium-octeon/octeon-usb.c => drivers/usb/dwc3/dwc3-octeon.c (100%) diff --git a/arch/mips/cavium-octeon/Makefile b/arch/mips/cavium-octeon/Makefile index 7c02e542959a..2a5926578841 100644 --- a/arch/mips/cavium-octeon/Makefile +++ b/arch/mips/cavium-octeon/Makefile @@ -18,4 +18,3 @@ obj-y += crypto/ obj-$(CONFIG_MTD) += flash_setup.o obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_OCTEON_ILM) += oct_ilm.o -obj-$(CONFIG_USB) += octeon-usb.o diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig index be954a9abbe0..8fc7b7ff7f16 100644 --- a/drivers/usb/dwc3/Kconfig +++ b/drivers/usb/dwc3/Kconfig @@ -168,4 +168,13 @@ config USB_DWC3_AM62 The Designware Core USB3 IP is programmed to operate in in USB 2.0 mode only. Say 'Y' or 'M' here if you have one such device + +config USB_DWC3_OCTEON + tristate "Cavium Octeon Platforms" + depends on CAVIUM_OCTEON_SOC || COMPILE_TEST + default USB_DWC3 + help + Support Cavium Octeon platforms with DesignWare Core USB3 IP. + Say 'Y' or 'M' here if you have one such device. + endif diff --git a/drivers/usb/dwc3/Makefile b/drivers/usb/dwc3/Makefile index 9f66bd82b639..fe1493d4bbe5 100644 --- a/drivers/usb/dwc3/Makefile +++ b/drivers/usb/dwc3/Makefile @@ -54,3 +54,4 @@ obj-$(CONFIG_USB_DWC3_ST) += dwc3-st.o obj-$(CONFIG_USB_DWC3_QCOM) += dwc3-qcom.o obj-$(CONFIG_USB_DWC3_IMX8MP) += dwc3-imx8mp.o obj-$(CONFIG_USB_DWC3_XILINX) += dwc3-xilinx.o +obj-$(CONFIG_USB_DWC3_OCTEON) += dwc3-octeon.o diff --git a/arch/mips/cavium-octeon/octeon-usb.c b/drivers/usb/dwc3/dwc3-octeon.c similarity index 100% rename from arch/mips/cavium-octeon/octeon-usb.c rename to drivers/usb/dwc3/dwc3-octeon.c From patchwork Mon Jun 19 20:15:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 694413 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F134EB64DB for ; Mon, 19 Jun 2023 20:15:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229998AbjFSUPQ (ORCPT ); Mon, 19 Jun 2023 16:15:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60016 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229554AbjFSUPO (ORCPT ); Mon, 19 Jun 2023 16:15:14 -0400 Received: from h4.cmg1.smtp.forpsi.com (h4.cmg1.smtp.forpsi.com [185.129.138.163]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CADF130 for ; Mon, 19 Jun 2023 13:15:12 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id BLHKq52GkPm6CBLHLqL7EX; Mon, 19 Jun 2023 22:15:11 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205711; bh=WMJ3+35eA39OpL7FYZeQOMS96PRO2jxUPQicwsKhheI=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=Xtx8rv4oWjXzZXdY1U/y202rpfKDtWStQOEWH6yrR3saqWx7bcOqF6vel/Bc5MdFi fraxZm61J2qPdpkF5AA4wSj91pPos/37T6+mUNC/Fq1HUlU/1P8EiRye93J1HMbD4E w2LQS2TIO8qybnBIr1gUuwkXm4r9Mv5GE2LsEjrV+aidKsXvKa22O2xqnFffA5j27I V4XjsySDKFW3IgDs1SoXl4tD6YqxGgaUFRYCRdWA9HjNe1vMczEa+k4I3uV8ofdXuD 12lkTM+OGgPdEMJ23WJul0LIpMkE/sZGFQMUBBdgQbIySWmwosbmlGz22myEUTig5k PHRwJ/hAXRxmA== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205711; bh=WMJ3+35eA39OpL7FYZeQOMS96PRO2jxUPQicwsKhheI=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=Xtx8rv4oWjXzZXdY1U/y202rpfKDtWStQOEWH6yrR3saqWx7bcOqF6vel/Bc5MdFi fraxZm61J2qPdpkF5AA4wSj91pPos/37T6+mUNC/Fq1HUlU/1P8EiRye93J1HMbD4E w2LQS2TIO8qybnBIr1gUuwkXm4r9Mv5GE2LsEjrV+aidKsXvKa22O2xqnFffA5j27I V4XjsySDKFW3IgDs1SoXl4tD6YqxGgaUFRYCRdWA9HjNe1vMczEa+k4I3uV8ofdXuD 12lkTM+OGgPdEMJ23WJul0LIpMkE/sZGFQMUBBdgQbIySWmwosbmlGz22myEUTig5k PHRwJ/hAXRxmA== Date: Mon, 19 Jun 2023 22:15:10 +0200 From: Ladislav Michl To: Thinh Nguyen Cc: linux-usb@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 09/11] usb: dwc3: dwc3-octeon: Convert to glue driver Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfCHtnYnAgZ9GhS+LrvtkGDdA1Yxz2F3FqQolpafnaKheAJcZMZMYXBsyqY0/2eK40yjKgaIJ1RMQpvLQDQf4f0iRR8tEpy0mJzqY/vc65PTUvj2xmMXy VwzZAm11I4WMefBP8oQ1p7rqvSlQbX3Z9c+5PTtJh55M214H2iNjPSBtRD58RJPvW1mHDycwRFo73/ENmm/y2A6A9GZnHdiM6a9SHJJeQsM6EHv0CVx79Kz2 NM/+RvBu9A9JD0WpRP8+Eg== Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Use Octeon specific DWC3 glue instead of dwc3-of-simple. Signed-off-by: Ladislav Michl --- arch/mips/cavium-octeon/octeon-platform.c | 1 - drivers/usb/dwc3/dwc3-octeon.c | 100 +++++++++++----------- drivers/usb/dwc3/dwc3-of-simple.c | 1 - 3 files changed, 52 insertions(+), 50 deletions(-) diff --git a/arch/mips/cavium-octeon/octeon-platform.c b/arch/mips/cavium-octeon/octeon-platform.c index ce05c0dd3acd..235c77ce7b18 100644 --- a/arch/mips/cavium-octeon/octeon-platform.c +++ b/arch/mips/cavium-octeon/octeon-platform.c @@ -450,7 +450,6 @@ static const struct of_device_id octeon_ids[] __initconst = { { .compatible = "cavium,octeon-3860-bootbus", }, { .compatible = "cavium,mdio-mux", }, { .compatible = "gpio-leds", }, - { .compatible = "cavium,octeon-7130-usb-uctl", }, {}, }; diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 2add435ad038..3ebcf2a61233 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -187,7 +187,10 @@ #define USBDRD_UCTL_ECC 0xf0 #define USBDRD_UCTL_SPARE1 0xf8 -static DEFINE_MUTEX(dwc3_octeon_clocks_mutex); +struct dwc3_data { + struct device *dev; + void __iomem *base; +}; #ifdef CONFIG_CAVIUM_OCTEON_SOC #include @@ -494,58 +499,57 @@ static void __init dwc3_octeon_phy_reset(void __iomem *base) dwc3_octeon_writeq(uctl_ctl_reg, val); } -static int __init dwc3_octeon_device_init(void) +static int dwc3_octeon_probe(struct platform_device *pdev) { - const char compat_node_name[] = "cavium,octeon-7130-usb-uctl"; - struct platform_device *pdev; - struct device_node *node; - struct resource *res; - void __iomem *base; + struct device *dev = &pdev->dev; + struct dwc3_data *data; + int err; - /* - * There should only be three universal controllers, "uctl" - * in the device tree. Two USB and a SATA, which we ignore. - */ - node = NULL; - do { - node = of_find_node_by_name(node, "uctl"); - if (!node) - return -ENODEV; - - if (of_device_is_compatible(node, compat_node_name)) { - pdev = of_find_device_by_node(node); - if (!pdev) - return -ENODEV; - - /* - * The code below maps in the registers necessary for - * setting up the clocks and reseting PHYs. We must - * release the resources so the dwc3 subsystem doesn't - * know the difference. - */ - base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); - if (IS_ERR(base)) { - put_device(&pdev->dev); - return PTR_ERR(base); - } + data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; - mutex_lock(&dwc3_octeon_clocks_mutex); - if (dwc3_octeon_clocks_start(&pdev->dev, base) == 0) - dev_info(&pdev->dev, "clocks initialized.\n"); - dwc3_octeon_set_endian_mode(base); - dwc3_octeon_phy_reset(base); - mutex_unlock(&dwc3_octeon_clocks_mutex); - devm_iounmap(&pdev->dev, base); - devm_release_mem_region(&pdev->dev, res->start, - resource_size(res)); - put_device(&pdev->dev); - } - } while (node != NULL); + data->dev = dev; + platform_set_drvdata(pdev, data); - return 0; + data->base = devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(data->base)) + return PTR_ERR(data->base); + + err = dwc3_octeon_clocks_start(dev, data->base); + if (err) + return err; + + dwc3_octeon_set_endian_mode(data->base); + dwc3_octeon_phy_reset(data->base); + + return of_platform_populate(node, NULL, NULL, dev); +} + +static void dwc3_octeon_remove(struct platform_device *pdev) +{ + struct dwc3_data *data = platform_get_drvdata(pdev); + + of_platform_depopulate(data->dev); } -device_initcall(dwc3_octeon_device_init); +static const struct of_device_id dwc3_octeon_of_match[] = { + { .compatible = "cavium,octeon-7130-usb-uctl" }, + { }, +}; +MODULE_DEVICE_TABLE(of, dwc3_octeon_of_match); + +static struct platform_driver dwc3_octeon_driver = { + .probe = dwc3_octeon_probe, + .remove_new = dwc3_octeon_remove, + .driver = { + .name = "dwc3-octeon", + .of_match_table = dwc3_octeon_of_match, + }, +}; +module_platform_driver(dwc3_octeon_driver); + +MODULE_ALIAS("platform:dwc3-octeon"); MODULE_AUTHOR("David Daney "); MODULE_LICENSE("GPL"); -MODULE_DESCRIPTION("USB driver for OCTEON III SoC"); +MODULE_DESCRIPTION("DesignWare USB3 OCTEON III Glue Layer"); diff --git a/drivers/usb/dwc3/dwc3-of-simple.c b/drivers/usb/dwc3/dwc3-of-simple.c index 71fd620c5161..e3423fbea3ed 100644 --- a/drivers/usb/dwc3/dwc3-of-simple.c +++ b/drivers/usb/dwc3/dwc3-of-simple.c @@ -172,7 +172,6 @@ static const struct dev_pm_ops dwc3_of_simple_dev_pm_ops = { static const struct of_device_id of_dwc3_simple_match[] = { { .compatible = "rockchip,rk3399-dwc3" }, - { .compatible = "cavium,octeon-7130-usb-uctl" }, { .compatible = "sprd,sc9860-dwc3" }, { .compatible = "allwinner,sun50i-h6-dwc3" }, { .compatible = "hisilicon,hi3670-dwc3" }, From patchwork Mon Jun 19 20:15:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 694718 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B2678EB64DB for ; Mon, 19 Jun 2023 20:15:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229887AbjFSUP6 (ORCPT ); Mon, 19 Jun 2023 16:15:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60180 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229601AbjFSUP6 (ORCPT ); Mon, 19 Jun 2023 16:15:58 -0400 Received: from h2.cmg2.smtp.forpsi.com (h2.cmg2.smtp.forpsi.com [81.2.195.189]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6CB5B130 for ; Mon, 19 Jun 2023 13:15:56 -0700 (PDT) Received: from lenoch ([91.218.190.200]) by cmgsmtp with ESMTPSA id BLI0qArmnv5uIBLI2qiBaV; Mon, 19 Jun 2023 22:15:54 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205754; bh=kCW1OvVhiRLcDIqlNc8IFhO8A4j05h0+3MdDtVLQLHE=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=l2yaE0hR4ACg4u+JlQsSiQ9QcKnU6Yaqu1EBbo5BYO4rVhPHdHjkBD82PNPnpCg0L pD2ohs3erEoYEsrMf7b0JAmOD2vHMtoRnDMtfWRMIhDRYCBVCIOlZfjg9qIYCWtDmO OrTitZ3fDJb3GooW1FdoWWPfajuY5YW6doEBwn0nnyT6GU7mmBfG1OGUVToOkEyG0r mRcvnWsDFr2rEndgJZu6d0xQsToaRXuADDgXhwUTHxWFNcwMNTt+OAAtrT3u9UV2GG zd/jkaB7jUWWJEZMgOyqUAyix37U7FCc+vklK9pyZSDgldtL0BADVYLk2e0D0xyc/P c3ccwZC8XvuNw== DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205754; bh=kCW1OvVhiRLcDIqlNc8IFhO8A4j05h0+3MdDtVLQLHE=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=l2yaE0hR4ACg4u+JlQsSiQ9QcKnU6Yaqu1EBbo5BYO4rVhPHdHjkBD82PNPnpCg0L pD2ohs3erEoYEsrMf7b0JAmOD2vHMtoRnDMtfWRMIhDRYCBVCIOlZfjg9qIYCWtDmO OrTitZ3fDJb3GooW1FdoWWPfajuY5YW6doEBwn0nnyT6GU7mmBfG1OGUVToOkEyG0r mRcvnWsDFr2rEndgJZu6d0xQsToaRXuADDgXhwUTHxWFNcwMNTt+OAAtrT3u9UV2GG zd/jkaB7jUWWJEZMgOyqUAyix37U7FCc+vklK9pyZSDgldtL0BADVYLk2e0D0xyc/P c3ccwZC8XvuNw== Date: Mon, 19 Jun 2023 22:15:52 +0200 From: Ladislav Michl To: Thinh Nguyen Cc: linux-usb@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 10/11] usb: dwc3: dwc3-octeon: Move node parsing into driver probe Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfD791L9CvcO2cS3ct+H45CrfbSuJTNIWMjVNFohBfHcQmbrU9HksRbPHgnALDptbzoZYNz8O45hh5l7K2O3F8CSpD3bZey5SfnmOwkj677Vl7IZDRkRB JvIBw6Hazy0iqeoINgj/Ijc7V+SPKt6x0e5dThYWbJolsCcr/W9AbO1JIvvhvx29W8AjIZRstOpyPjtPMwjH6N8iQRGMHNf8PQfFwLbZ1rlMystemUSquMnQ bKXJPhq6acwbPJ00fkoHWg== Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl Make dwc3_octeon_clocks_start just start the clocks. Signed-off-by: Ladislav Michl --- drivers/usb/dwc3/dwc3-octeon.c | 150 ++++++++++++++++----------------- 1 file changed, 71 insertions(+), 79 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 3ebcf2a61233..4ad2d8887cf0 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -295,67 +295,14 @@ static int dwc3_octeon_config_power(struct device *dev, void __iomem *base) return 0; } -static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) +static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base, + int ref_clk_sel, int ref_clk_fsel, + int mpll_mul) { - int i, div, mpll_mul, ref_clk_fsel, ref_clk_sel = 2; - u32 clock_rate; + int div; u64 val; void __iomem *uctl_ctl_reg = base + USBDRD_UCTL_CTL; - if (dev->of_node) { - const char *ss_clock_type; - const char *hs_clock_type; - - i = of_property_read_u32(dev->of_node, - "refclk-frequency", &clock_rate); - if (i) { - dev_err(dev, "No UCTL \"refclk-frequency\"\n"); - return -EINVAL; - } - i = of_property_read_string(dev->of_node, - "refclk-type-ss", &ss_clock_type); - if (i) { - dev_err(dev, "No UCTL \"refclk-type-ss\"\n"); - return -EINVAL; - } - i = of_property_read_string(dev->of_node, - "refclk-type-hs", &hs_clock_type); - if (i) { - dev_err(dev, "No UCTL \"refclk-type-hs\"\n"); - return -EINVAL; - } - if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { - if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) - ref_clk_sel = 0; - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) - ref_clk_sel = 2; - else - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", - hs_clock_type); - } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { - if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) - ref_clk_sel = 1; - else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) - ref_clk_sel = 3; - else { - dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", - hs_clock_type); - ref_clk_sel = 3; - } - } else - dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", - ss_clock_type); - - if ((ref_clk_sel == 0 || ref_clk_sel == 1) && - (clock_rate != 100000000)) - dev_warn(dev, "Invalid UCTL clock rate of %u, using 100000000 instead\n", - clock_rate); - - } else { - dev_err(dev, "No USB UCTL device node\n"); - return -EINVAL; - } - /* * Step 1: Wait for all voltages to be stable...that surely * happened before starting the kernel. SKIP @@ -399,24 +346,6 @@ static int dwc3_octeon_clocks_start(struct device *dev, void __iomem *base) val &= ~USBDRD_UCTL_CTL_REF_CLK_SEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_SEL, ref_clk_sel); - ref_clk_fsel = 0x07; - switch (clock_rate) { - default: - dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", - clock_rate); - fallthrough; - case 100000000: - mpll_mul = 0x19; - if (ref_clk_sel < 2) - ref_clk_fsel = 0x27; - break; - case 50000000: - mpll_mul = 0x32; - break; - case 125000000: - mpll_mul = 0x28; - break; - } val &= ~USBDRD_UCTL_CTL_REF_CLK_FSEL; val |= FIELD_PREP(USBDRD_UCTL_CTL_REF_CLK_FSEL, ref_clk_fsel); @@ -502,8 +429,72 @@ static void __init dwc3_octeon_phy_reset(void __iomem *base) static int dwc3_octeon_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; struct dwc3_data *data; - int err; + int err, ref_clk_sel, ref_clk_fsel, mpll_mul; + uint32_t clock_rate; + const char *hs_clock_type, *ss_clock_type; + + if (!node) { + dev_err(dev, "No USB UCTL device node\n"); + return -EINVAL; + } + + if (of_property_read_u32(node, "refclk-frequency", &clock_rate)) { + dev_err(dev, "No UCTL \"refclk-frequency\"\n"); + return -EINVAL; + } + if (of_property_read_string(node, "refclk-type-ss", &ss_clock_type)) { + dev_err(dev, "No UCTL \"refclk-type-ss\"\n"); + return -EINVAL; + } + if (of_property_read_string(node, "refclk-type-hs", &hs_clock_type)) { + dev_err(dev, "No UCTL \"refclk-type-hs\"\n"); + return -EINVAL; + } + + ref_clk_sel = 2; + if (strcmp("dlmc_ref_clk0", ss_clock_type) == 0) { + if (strcmp(hs_clock_type, "dlmc_ref_clk0") == 0) + ref_clk_sel = 0; + else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) + ref_clk_sel = 2; + else + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", + hs_clock_type); + } else if (strcmp(ss_clock_type, "dlmc_ref_clk1") == 0) { + if (strcmp(hs_clock_type, "dlmc_ref_clk1") == 0) + ref_clk_sel = 1; + else if (strcmp(hs_clock_type, "pll_ref_clk") == 0) + ref_clk_sel = 3; + else { + dev_warn(dev, "Invalid HS clock type %s, using pll_ref_clk instead\n", + hs_clock_type); + ref_clk_sel = 3; + } + } else { + dev_warn(dev, "Invalid SS clock type %s, using dlmc_ref_clk0 instead\n", + ss_clock_type); + } + + ref_clk_fsel = 0x07; + switch (clock_rate) { + default: + dev_warn(dev, "Invalid ref_clk %u, using 100000000 instead\n", + clock_rate); + fallthrough; + case 100000000: + mpll_mul = 0x19; + if (ref_clk_sel < 2) + ref_clk_fsel = 0x27; + break; + case 50000000: + mpll_mul = 0x32; + break; + case 125000000: + mpll_mul = 0x28; + break; + } data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); if (!data) @@ -516,7 +507,8 @@ static int dwc3_octeon_probe(struct platform_device *pdev) if (IS_ERR(data->base)) return PTR_ERR(data->base); - err = dwc3_octeon_clocks_start(dev, data->base); + err = dwc3_octeon_clocks_start(dev, data->base, + ref_clk_sel, ref_clk_fsel, mpll_mul); if (err) return err; From patchwork Mon Jun 19 20:16:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ladislav Michl X-Patchwork-Id: 694412 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 901D3EB64DA for ; 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a=rsa-sha256; c=relaxed/relaxed; d=triops.cz; s=f2019; t=1687205783; bh=K9MvvSB44/NAwPzUv3A6w1ipANWPhZ+J7Fw+3w/YxmQ=; h=Date:From:To:Subject:Message-ID:MIME-Version:Content-Type; b=Yds0iDJ00rtqBvolFxDm5ZgtaEJAm9dg0cmkkc5d+lbDmFSvTMpq8mzbbFKErYbo2 VHbYYi874uV/dvXjn/MhjN5X4mjOVm103PtJZlx4L1u/a0kce6BXXhNld+NLUYY0l9 QnelYh4Q84k4d8lVdBzLMQBg2YjZb4S2Dmnb+v/bZEDDdS/UWt3jTRIuQ7tZ1XLxck 4+xtbuz2OYq2a0XCDHjhnp1c0Eg2Pi1pvNPNeGXqNekMmQlAck2FPwjrIFPREWudr5 1D933UCPJQPTGzOeCRakXZlmAHkb0gu+aex7gRYHe/OIOktuTi9ZGic4EaTRWj5Vls 6jDofvnGORPAw== Date: Mon, 19 Jun 2023 22:16:21 +0200 From: Ladislav Michl To: Thinh Nguyen Cc: linux-usb@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 11/11] usb: dwc3: Add SPDX header and copyright Message-ID: References: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CMAE-Envelope: MS4wfKT14AIUFGIofVKyXtsTGI8XNvGTl/IpaMKz8UMtyAjwgqfKS4Ll2tsH7X8iJFLOzv0LhOvUBDwDp1gt32zIWI4kOWMEmUe4oj5hUpmHj/0Gtccj7S8I 3v/09Nve7DZFXSZ2SiijodI9L79YjHOi4p64o0XPjhQ0mDdWoPhF2LyYhfExhuRIP2owghzOEiezjCuu8GjeMbdtkj5OQp1Vh51YtPLF1scGV5N/dB98qQ/5 5rXFfyZN+Nk+wSwFxuEQ7Q== Precedence: bulk List-ID: X-Mailing-List: linux-usb@vger.kernel.org From: Ladislav Michl As driver is rewritten and David no longer works for Marvell (Cavium), I'm to blame for breakage. Signed-off-by: Ladislav Michl --- drivers/usb/dwc3/dwc3-octeon.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/usb/dwc3/dwc3-octeon.c b/drivers/usb/dwc3/dwc3-octeon.c index 4ad2d8887cf0..1776bbaf28c0 100644 --- a/drivers/usb/dwc3/dwc3-octeon.c +++ b/drivers/usb/dwc3/dwc3-octeon.c @@ -1,11 +1,9 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * XHCI HCD glue for Cavium Octeon III SOCs. + * DWC3 glue for Cavium Octeon III SOCs. * * Copyright (C) 2010-2017 Cavium Networks - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. + * Copyright (C) 2023 Ladislav Michl */ #include @@ -542,6 +540,6 @@ static struct platform_driver dwc3_octeon_driver = { module_platform_driver(dwc3_octeon_driver); MODULE_ALIAS("platform:dwc3-octeon"); -MODULE_AUTHOR("David Daney "); +MODULE_AUTHOR("Ladislav Michl "); MODULE_LICENSE("GPL"); MODULE_DESCRIPTION("DesignWare USB3 OCTEON III Glue Layer");