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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On some Qcom SoCs, the Altmode event mode is set to 0xff when the Type-C port is disconnected. Handle this specific mode and translate it as the SAFE mode. Signed-off-by: Neil Armstrong --- drivers/soc/qcom/pmic_glink_altmode.c | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/drivers/soc/qcom/pmic_glink_altmode.c b/drivers/soc/qcom/pmic_glink_altmode.c index df48fbea4b68..007d308e2f15 100644 --- a/drivers/soc/qcom/pmic_glink_altmode.c +++ b/drivers/soc/qcom/pmic_glink_altmode.c @@ -173,6 +173,20 @@ static void pmic_glink_altmode_enable_usb(struct pmic_glink_altmode *altmode, dev_err(altmode->dev, "failed to switch mux to USB\n"); } +static void pmic_glink_altmode_safe(struct pmic_glink_altmode *altmode, + struct pmic_glink_altmode_port *port) +{ + int ret; + + port->state.alt = NULL; + port->state.data = NULL; + port->state.mode = TYPEC_STATE_SAFE; + + ret = typec_mux_set(port->typec_mux, &port->state); + if (ret) + dev_err(altmode->dev, "failed to switch mux to safe mode\n"); +} + static void pmic_glink_altmode_worker(struct work_struct *work) { struct pmic_glink_altmode_port *alt_port = work_to_altmode_port(work); @@ -180,7 +194,9 @@ static void pmic_glink_altmode_worker(struct work_struct *work) typec_switch_set(alt_port->typec_switch, alt_port->orientation); - if (alt_port->svid == USB_TYPEC_DP_SID) + if (alt_port->svid == USB_TYPEC_DP_SID && alt_port->mode == 0xff) + pmic_glink_altmode_safe(altmode, alt_port); + else if (alt_port->svid == USB_TYPEC_DP_SID) pmic_glink_altmode_enable_dp(altmode, alt_port, alt_port->mode, alt_port->hpd_state, alt_port->hpd_irq); else From patchwork Mon Jun 19 08:07:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Neil Armstrong X-Patchwork-Id: 694297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5CDCDEB64D9 for ; Mon, 19 Jun 2023 08:07:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230251AbjFSIHz (ORCPT ); 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Mon, 19 Jun 2023 01:07:20 -0700 (PDT) From: Neil Armstrong Date: Mon, 19 Jun 2023 10:07:15 +0200 Subject: [PATCH v5 3/6] qcom: pmic_glink: enable altmode for SM8550 MIME-Version: 1.0 Message-Id: <20230601-topic-sm8550-upstream-type-c-v5-3-9221cd300903@linaro.org> References: <20230601-topic-sm8550-upstream-type-c-v5-0-9221cd300903@linaro.org> In-Reply-To: <20230601-topic-sm8550-upstream-type-c-v5-0-9221cd300903@linaro.org> To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1227; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=kJ8k1s4YhbZeghfNqa2GuV3vcB5ikSdP7IhrDDYjGGI=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBkkAyzydKg6gsMsLtHSbgGjR+C7u4iF05goQRd/Jzx QhtdG3qJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZJAMswAKCRB33NvayMhJ0d3dEA ChOwiXYTap6dr8Ut5wRdHm79uAP4pqQBSHeL9pLB+bn6ar8+uKklL7FkDYH72bHxniJflLSvgGHky2 rMBpIIrSo+kunMXtrcwObgsO+sxsW2ATkh2780MCHlTSJ8cEduD0Nr/24rUBzq5IyPi4mRGaMpz+t0 TSZ8lMy5nLwwsVOfEvgEyaiw+UwwjZx0zs+B+GDw77qMbG4+bSmQKnRhpqD+obGul/S39qHW7kJQr1 dw3nTcAUSKhty2Y8iszohIkq0M2nP7bGJrnWpAKcXjkd+0EVaM+Wn21KTVGTb6GjrYyr4djLM7wpQJ xjbsxacq6JEajfN44h1IyzBe4tIsvlV83sD+CI5Hcw4NtFov3wdKFcr6rjw9dP4D2gXb0y89BoNLGT sZ+dmEhBq9jSNc6U14d0wr5cOKRMMiSi3V+fwM0sp8CJj9q250otz8F5bPDNcTiIWKhnm3Lr7GYNU+ GHp8KcXWhGIAPcx6vw2r3D9E9JPae1HKmya3w62rV6f7q2Cuvmmbl3dwn1zZb6kSVjwn+WGE+IKIC0 cUtbs68bMyMF9xn0WaSPrmv3PMcQPIc086sZKfa5vkW+m3/kOth8esjfN5leHgIknfe2DDx0BgOHpy tk5uRemk5JKadGnmw40Le7bYg6X2OKFPAdhOQ5B0DxyT6DM8VlILS0uOH/Ew== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Altmode is also supported for SM8550, allow it. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- drivers/soc/qcom/pmic_glink.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/soc/qcom/pmic_glink.c b/drivers/soc/qcom/pmic_glink.c index c87056769ebd..8af06bdc6f5a 100644 --- a/drivers/soc/qcom/pmic_glink.c +++ b/drivers/soc/qcom/pmic_glink.c @@ -342,13 +342,9 @@ static const unsigned long pmic_glink_sm8450_client_mask = BIT(PMIC_GLINK_CLIENT BIT(PMIC_GLINK_CLIENT_ALTMODE) | BIT(PMIC_GLINK_CLIENT_UCSI); -/* Do not handle altmode for now on those platforms */ -static const unsigned long pmic_glink_sm8550_client_mask = BIT(PMIC_GLINK_CLIENT_BATT) | - BIT(PMIC_GLINK_CLIENT_UCSI); - static const struct of_device_id pmic_glink_of_match[] = { { .compatible = "qcom,sm8450-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, - { .compatible = "qcom,sm8550-pmic-glink", .data = &pmic_glink_sm8550_client_mask }, + { .compatible = "qcom,sm8550-pmic-glink", .data = &pmic_glink_sm8450_client_mask }, { .compatible = "qcom,pmic-glink" }, {} }; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the USB3+DP Combo QMP PHY port subnodes in the SM8550 SoC DTSI to avoid duplication in the devices DTs. Reviewed-by: Konrad Dybcio Signed-off-by: Neil Armstrong --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index 41d60af93692..54636f475306 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -2838,6 +2838,32 @@ usb_dp_qmpphy: phy@88e8000 { #phy-cells = <1>; status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + usb_dp_qmpphy_out: endpoint { + }; + }; + + port@1 { + reg = <1>; + + usb_dp_qmpphy_usb_ss_in: endpoint { + }; + }; + + port@2 { + reg = <2>; + + usb_dp_qmpphy_dp_in: endpoint { + }; + }; + }; }; usb_1: usb@a6f8800 {