From patchwork Mon Jun 19 08:35:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 694292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5FD72EB64DD for ; Mon, 19 Jun 2023 08:48:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230234AbjFSIsP convert rfc822-to-8bit (ORCPT ); Mon, 19 Jun 2023 04:48:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47658 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231322AbjFSIr7 (ORCPT ); Mon, 19 Jun 2023 04:47:59 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1524610C0; Mon, 19 Jun 2023 01:46:19 -0700 (PDT) Received: from EXMBX166.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX166", Issuer "EXMBX166" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id 6561C8480; Mon, 19 Jun 2023 16:35:19 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX166.cuchost.com (172.16.6.76) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 19 Jun 2023 16:35:19 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 19 Jun 2023 16:35:18 +0800 From: William Qiu To: , , , CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Ziv Xu , William Qiu Subject: [PATCH v3 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC Date: Mon, 19 Jun 2023 16:35:15 +0800 Message-ID: <20230619083517.415597-2-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619083517.415597-1-william.qiu@starfivetech.com> References: <20230619083517.415597-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The QSPI controller needs three clock items to work properly on StarFive JH7110 SoC, so there is need to change the maxItems's value to 3. Other platforms do not have this constraint. Signed-off-by: William Qiu Reviewed-by: Hal Feng Reviewed-by: Conor Dooley --- .../bindings/spi/cdns,qspi-nor.yaml | 20 ++++++++++++++++++- 1 file changed, 19 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml index b310069762dd..1b83cbb9a086 100644 --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml @@ -26,6 +26,15 @@ allOf: const: starfive,jh7110-qspi then: properties: + clocks: + maxItems: 3 + + clock-names: + items: + - const: ref + - const: ahb + - const: apb + resets: minItems: 2 maxItems: 3 @@ -38,6 +47,9 @@ allOf: else: properties: + clocks: + maxItems: 1 + resets: maxItems: 2 @@ -70,7 +82,13 @@ properties: maxItems: 1 clocks: - maxItems: 1 + maxItems: 3 + + clock-names: + items: + - const: ref + - const: ahb + - const: apb cdns,fifo-depth: description: From patchwork Mon Jun 19 08:35:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: William Qiu X-Patchwork-Id: 694295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42016EB64DB for ; Mon, 19 Jun 2023 08:46:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229732AbjFSIqH convert rfc822-to-8bit (ORCPT ); Mon, 19 Jun 2023 04:46:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47970 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229648AbjFSIpq (ORCPT ); Mon, 19 Jun 2023 04:45:46 -0400 Received: from fd01.gateway.ufhost.com (fd01.gateway.ufhost.com [61.152.239.71]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 575CB1991; Mon, 19 Jun 2023 01:44:05 -0700 (PDT) Received: from EXMBX165.cuchost.com (unknown [175.102.18.54]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client CN "EXMBX165", Issuer "EXMBX165" (not verified)) by fd01.gateway.ufhost.com (Postfix) with ESMTP id D8A338485; Mon, 19 Jun 2023 16:35:19 +0800 (CST) Received: from EXMBX068.cuchost.com (172.16.6.68) by EXMBX165.cuchost.com (172.16.6.75) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 19 Jun 2023 16:35:19 +0800 Received: from williamqiu-virtual-machine.starfivetech.com (171.223.208.138) by EXMBX068.cuchost.com (172.16.6.68) with Microsoft SMTP Server (TLS) id 15.0.1497.42; Mon, 19 Jun 2023 16:35:19 +0800 From: William Qiu To: , , , CC: Mark Brown , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Emil Renner Berthing , Ziv Xu , William Qiu Subject: [PATCH v3 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI Date: Mon, 19 Jun 2023 16:35:16 +0800 Message-ID: <20230619083517.415597-3-william.qiu@starfivetech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230619083517.415597-1-william.qiu@starfivetech.com> References: <20230619083517.415597-1-william.qiu@starfivetech.com> MIME-Version: 1.0 X-Originating-IP: [171.223.208.138] X-ClientProxiedBy: EXCAS062.cuchost.com (172.16.6.22) To EXMBX068.cuchost.com (172.16.6.68) X-YovoleRuleAgent: yovoleflag Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add QSPI clock operation in device probe. Signed-off-by: William Qiu Reviewed-by: Hal Feng Reported-by: kernel test robot Closes: https://lore.kernel.org/oe-kbuild-all/202306022017.UbwjjWRN-lkp@intel.com/ Reported-by: Julia Lawall Closes: https://lore.kernel.org/r/202306040644.6ZHs55x4-lkp@intel.com/ --- drivers/spi/spi-cadence-quadspi.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/drivers/spi/spi-cadence-quadspi.c b/drivers/spi/spi-cadence-quadspi.c index 6ddb2dfc0f00..8774f9aaff61 100644 --- a/drivers/spi/spi-cadence-quadspi.c +++ b/drivers/spi/spi-cadence-quadspi.c @@ -63,6 +63,8 @@ struct cqspi_st { struct platform_device *pdev; struct spi_master *master; struct clk *clk; + struct clk_bulk_data *clks; + int num_clks; unsigned int sclk; void __iomem *iobase; @@ -1715,6 +1717,16 @@ static int cqspi_probe(struct platform_device *pdev) } if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) { + cqspi->num_clks = devm_clk_bulk_get_all(dev, &cqspi->clks); + if (cqspi->num_clks < 0) { + dev_err(dev, "Cannot claim clock: %u\n", cqspi->num_clks); + return -EINVAL; + } + + ret = clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks); + if (ret) + dev_err(dev, "Cannot enable clock clks\n"); + rstc_ref = devm_reset_control_get_optional_exclusive(dev, "rstc_ref"); if (IS_ERR(rstc_ref)) { ret = PTR_ERR(rstc_ref); @@ -1816,6 +1828,9 @@ static void cqspi_remove(struct platform_device *pdev) clk_disable_unprepare(cqspi->clk); + if (of_device_is_compatible(pdev->dev.of_node, "starfive,jh7110-qspi")) + clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks); + pm_runtime_put_sync(&pdev->dev); pm_runtime_disable(&pdev->dev); } @@ -1831,6 +1846,9 @@ static int cqspi_suspend(struct device *dev) clk_disable_unprepare(cqspi->clk); + if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi")) + clk_bulk_disable_unprepare(cqspi->num_clks, cqspi->clks); + return ret; } @@ -1840,6 +1858,8 @@ static int cqspi_resume(struct device *dev) struct spi_master *master = dev_get_drvdata(dev); clk_prepare_enable(cqspi->clk); + if (of_device_is_compatible(dev->of_node, "starfive,jh7110-qspi")) + clk_bulk_prepare_enable(cqspi->num_clks, cqspi->clks); cqspi_wait_idle(cqspi); cqspi_controller_init(cqspi);