From patchwork Tue Jun 20 00:03:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 694212 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D5FFEC001B3 for ; Tue, 20 Jun 2023 00:04:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229520AbjFTAEJ (ORCPT ); Mon, 19 Jun 2023 20:04:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229726AbjFTAEJ (ORCPT ); Mon, 19 Jun 2023 20:04:09 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e5ab]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2179E4A; Mon, 19 Jun 2023 17:04:07 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id 16D756606F6C; Tue, 20 Jun 2023 01:04:03 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1687219446; bh=9a46aNnESj501/E03oYlm9sAjEXaazXllJOV13stIS8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=NOzUtIjFSr2clm3a6T2fzUKteoU+kcoP8OHu2+TsI5DEmtENrpe47KpB4ST2XlTxl gYRKarP7wiyatbDwaUrJ/a5wAlZdBwOETlaxwCWNZ7GFqC0bam9Z35QzSIx3sThSIa 57Pu5JP/JYQ2r+C/ip82AyPj4CH1XL+dNR4Y4u1ulkEwcLbx4SiCipehQpUOzev3Dv myhMTJcFCBZYPTLpkT5RnHFTALqDEkws3p6BfEPIPMLH2VkZaMdtortpaF040ZByu4 SSWbxojrlVU8Vhiw/x+hDgy/DBguU9wBaGs37ERXh6aMLMazs6yR9sY8FRNlO6V9YF PBB4SUHth9svg== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= , Andrew-CT Chen , Conor Dooley , Krzysztof Kozlowski , Mauro Carvalho Chehab , Rob Herring , Tiffany Lin , Yunfei Dong , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 2/6] media: dt-bindings: mediatek,vcodec: Don't require assigned-clocks Date: Mon, 19 Jun 2023 20:03:35 -0400 Message-ID: <20230620000349.2122191-3-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230620000349.2122191-1-nfraprado@collabora.com> References: <20230620000349.2122191-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On MT8183 it's not necessary to configure the parent for the clocks. Remove the assigned-clocks and assigned-clock-parents from the required list. Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: Matthias Brugger Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Krzysztof Kozlowski --- (no changes since v1) .../devicetree/bindings/media/mediatek,vcodec-decoder.yaml | 2 -- 1 file changed, 2 deletions(-) diff --git a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml index 1506d2693f7d..1e56ece44aee 100644 --- a/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml +++ b/Documentation/devicetree/bindings/media/mediatek,vcodec-decoder.yaml @@ -67,8 +67,6 @@ required: - clocks - clock-names - iommus - - assigned-clocks - - assigned-clock-parents allOf: - if: From patchwork Tue Jun 20 00:03:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= X-Patchwork-Id: 694211 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A6A2EB64DA for ; Tue, 20 Jun 2023 00:04:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229934AbjFTAEm (ORCPT ); Mon, 19 Jun 2023 20:04:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57500 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229929AbjFTAEZ (ORCPT ); Mon, 19 Jun 2023 20:04:25 -0400 Received: from madras.collabora.co.uk (madras.collabora.co.uk [46.235.227.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64DEF10FF; Mon, 19 Jun 2023 17:04:18 -0700 (PDT) Received: from notapiano.myfiosgateway.com (zone.collabora.co.uk [167.235.23.81]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: nfraprado) by madras.collabora.co.uk (Postfix) with ESMTPSA id F20856606EEE; Tue, 20 Jun 2023 01:04:14 +0100 (BST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1687219457; bh=6ATRDxpWwig7hs2izlUcfXHh022ClevxNi5+pW49c5o=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=gdkTnWe7EPdZV3Ex0X/89hfVYFf8wjg/7j2bhi/M2/cPEe1uFSdURA4G/FwGQq4sK 0GvzNCTtduir6CK40KruY72Fk9Ky9ugf09L/Hkd4XICtpcq+uqg60bnRyWelCwp9dY ZxOqHkAV6cccHLjBb5Ufeh0KjIaAtHh2rZZbNcXGswnPS5ujhxOTC8NY+4hhtgj4iY aZpoMfLyjkebPwYSrIRT4ekFKpb72JV6E60ypFT19Gbm1vRhwVXUvKCdQxwGHBkZ2U GmkgFkUkQP+0VaITJcRHr3r1aI1JX2jSt3gDBvzXyJaYNmdu2K32/gzpK6VKfyQcsS m9dErKbBTlC7A== From: =?utf-8?b?TsOtY29sYXMgRi4gUi4gQS4gUHJhZG8=?= To: Matthias Brugger , Hans Verkuil Cc: AngeloGioacchino Del Regno , kernel@collabora.com, Yunfei Dong , =?utf-8?q?N?= =?utf-8?q?=C3=ADcolas_F_=2E_R_=2E_A_=2E_Prado?= , Conor Dooley , Krzysztof Kozlowski , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org Subject: [PATCH v3 6/6] arm64: dts: mediatek: mt8183: Add decoder Date: Mon, 19 Jun 2023 20:03:39 -0400 Message-ID: <20230620000349.2122191-7-nfraprado@collabora.com> X-Mailer: git-send-email 2.41.0 In-Reply-To: <20230620000349.2122191-1-nfraprado@collabora.com> References: <20230620000349.2122191-1-nfraprado@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Yunfei Dong Add node for the hardware decoder present on the MT8183 SoC. Signed-off-by: Yunfei Dong Signed-off-by: Qianqian Yan Signed-off-by: Frederic Chen Signed-off-by: Alexandre Courbot Signed-off-by: Nícolas F. R. A. Prado Reviewed-by: AngeloGioacchino Del Regno --- Changes in v3: - Dropped 'active' clock and added the 'mediatek,vdecsys' syscon phandle property instead Changes in v2: - Reformatted reg-names to fit in fewer lines arch/arm64/boot/dts/mediatek/mt8183.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 5169779d01df..4144f1ed3ff0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -2019,6 +2019,36 @@ vdecsys: syscon@16000000 { #clock-cells = <1>; }; + vcodec_dec: video-codec@16020000 { + compatible = "mediatek,mt8183-vcodec-dec"; + reg = <0 0x16020000 0 0x1000>, /* VDEC_MISC */ + <0 0x16021000 0 0x800>, /* VDEC_VLD */ + <0 0x16021800 0 0x800>, /* VDEC_TOP */ + <0 0x16022000 0 0x1000>, /* VDEC_MC */ + <0 0x16023000 0 0x1000>, /* VDEC_AVCVLD */ + <0 0x16024000 0 0x1000>, /* VDEC_AVCMV */ + <0 0x16025000 0 0x1000>, /* VDEC_PP */ + <0 0x16026800 0 0x800>, /* VP8_VD */ + <0 0x16027000 0 0x800>, /* VP6_VD */ + <0 0x16027800 0 0x800>, /* VP8_VL */ + <0 0x16028400 0 0x400>; /* VP9_VD */ + reg-names = "misc", "ld", "top", "cm", "ad", "av", "pp", + "hwd", "hwq", "hwb", "hwg"; + interrupts = ; + iommus = <&iommu M4U_PORT_HW_VDEC_MC_EXT>, + <&iommu M4U_PORT_HW_VDEC_PP_EXT>, + <&iommu M4U_PORT_HW_VDEC_VLD_EXT>, + <&iommu M4U_PORT_HW_VDEC_AVC_MV_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_RD_EXT>, + <&iommu M4U_PORT_HW_VDEC_PRED_WR_EXT>, + <&iommu M4U_PORT_HW_VDEC_PPWRAP_EXT>; + mediatek,scp = <&scp>; + mediatek,vdecsys = <&vdecsys>; + power-domains = <&spm MT8183_POWER_DOMAIN_VDEC>; + clocks = <&vdecsys CLK_VDEC_VDEC>; + clock-names = "vdec"; + }; + larb1: larb@16010000 { compatible = "mediatek,mt8183-smi-larb"; reg = <0 0x16010000 0 0x1000>;