From patchwork Wed Jun 14 01:57:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 692697 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAA78EB64DB for ; Wed, 14 Jun 2023 01:57:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231799AbjFNB5m (ORCPT ); Tue, 13 Jun 2023 21:57:42 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241230AbjFNB5l (ORCPT ); Tue, 13 Jun 2023 21:57:41 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC867E79; Tue, 13 Jun 2023 18:57:40 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35E1VfKX028571; Wed, 14 Jun 2023 01:57:34 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=FxN4q8QkuXQA9+ihr4vdcYVvQmloxqXodO9sRtCiP/Q=; b=Abz82k1eI+0QG4xxu2w7sicfUyXuAHg9YzTVwDIi7V6g5swpllBSLlW5opPSdVz2Nf7L VpdtEtPmeCkTkVth2pUt2OoPmhhgsAfGmkFhpbBiZxHcxRIg30tXk4sYECXc4OBgdE2J MR/vXa74ozUUbO7tIiNWXNR+9VabKavA5o9+QJYv6oNWY8/p17FYeg08dEBejEK3fbY1 QvrERfG1XR0BIbEqksg8m0Ie01ErHC0S3APmPSX4Lzz5tIOmmChDJNhXyw1q0kTviWo0 Dr0MIZ+5hW3nlRsgtX02XIyp1Mbk7BJ/4xP9X+SRW3n6D9F0mL7RKJuvSN2UmXdPh7xb Hw== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3r6f7a2q2h-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 Jun 2023 01:57:34 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35E1vXcn002131 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 Jun 2023 01:57:33 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 13 Jun 2023 18:57:32 -0700 From: Jessica Zhang To: Rob Clark , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Marijn Suijten CC: Jessica Zhang , , , , , Subject: [PATCH 1/3] drm/msm/dpu: Add DPU_INTF_DATABUS_WIDEN feature flag for DPU >= 5.0 Date: Tue, 13 Jun 2023 18:57:11 -0700 Message-ID: <20230525-add-widebus-support-v1-1-c7069f2efca1@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230525-add-widebus-support-v1-0-c7069f2efca1@quicinc.com> References: <20230525-add-widebus-support-v1-0-c7069f2efca1@quicinc.com> MIME-Version: 1.0 X-Mailer: b4 0.13-dev-c6835 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686707625; l=1689; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=iRagepNFxcgqldgaoKxCA+/LlTZz5r2cTXQldmjd+dQ=; b=2Sr9stxHFZUtYWy8LoQKZ4AWf1sMgk25MNnyre2yHS2T2zqINpYJy4FDVAjIwWeOBcp+wvesJ hThXXk/dyYODjcnx9KEfiB2LKKsa6fxHsPno1qz8OJ2I5Pse9H/JIHn X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: bEVnjnNvsl4oZABEfDyN_hRAPUDP6uHM X-Proofpoint-ORIG-GUID: bEVnjnNvsl4oZABEfDyN_hRAPUDP6uHM X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-13_24,2023-06-12_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 mlxlogscore=845 clxscore=1015 priorityscore=1501 phishscore=0 adultscore=0 impostorscore=0 bulkscore=0 malwarescore=0 mlxscore=0 spamscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306140012 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DPU 5.x+ supports a databus widen mode that allows more data to be sent per pclk. Enable this feature flag on all relevant chipsets. Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 3 ++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 ++ 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index 36ba3f58dcdf..0be7bf0bfc41 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -103,7 +103,8 @@ (BIT(DPU_INTF_INPUT_CTRL) | \ BIT(DPU_INTF_TE) | \ BIT(DPU_INTF_STATUS_SUPPORTED) | \ - BIT(DPU_DATA_HCTL_EN)) + BIT(DPU_DATA_HCTL_EN) | \ + BIT(DPU_INTF_DATABUS_WIDEN)) #define INTF_SC7280_MASK (INTF_SC7180_MASK | BIT(DPU_INTF_DATA_COMPRESS)) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index b860784ade72..b9939e00f5e0 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -182,6 +182,7 @@ enum { * than video timing * @DPU_INTF_STATUS_SUPPORTED INTF block has INTF_STATUS register * @DPU_INTF_DATA_COMPRESS INTF block has DATA_COMPRESS register + * @DPU_INTF_DATABUS_WIDEN INTF block has DATABUS_WIDEN register * @DPU_INTF_MAX */ enum { @@ -190,6 +191,7 @@ enum { DPU_DATA_HCTL_EN, DPU_INTF_STATUS_SUPPORTED, DPU_INTF_DATA_COMPRESS, + DPU_INTF_DATABUS_WIDEN, DPU_INTF_MAX }; From patchwork Wed Jun 14 01:57:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 692696 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D242EB64D8 for ; Wed, 14 Jun 2023 01:58:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231937AbjFNB6P (ORCPT ); Tue, 13 Jun 2023 21:58:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52478 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S241664AbjFNB6N (ORCPT ); Tue, 13 Jun 2023 21:58:13 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 620611BF9; Tue, 13 Jun 2023 18:58:00 -0700 (PDT) Received: from pps.filterd (m0279868.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 35E1s1lI030547; Wed, 14 Jun 2023 01:57:55 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type : content-transfer-encoding; s=qcppdkim1; bh=7IuSoxzYw9GT1ObCc/Ng+kegCxk9VlhIFuB5I2kbQ3Q=; b=XgcbdrvevbRN5aaN2stOACzynOrEwgKTN8c2Wy7nYD+oISBQyVPzMwaER79S3g9o40+h HOUsE8T3cfOc60yepif8XKWAzfLc7J3dtdZhEEv9a92W86sgtQEzs1CVx3leYUxYVMHN BdO0/jFd9b0hI/ZU+ucPtGB7b/31EFieqU29eb+OX5XMHIOYfuiPZZxtn5p8xv0kQCCI THIAKXx0T2DdolWVCysGQjyFerj5nhxSWBO3GKi9VIJN/Mmz+ewWkY18uvLzQTaEPTgQ 7BJ+JS8PgCzjaYJX49Sf/NNtD3RjeqVUPAUcpVzR6gyI0ZCGbZi76W01d4CHIjHIEU1v Jw== Received: from nasanppmta02.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3r6s3wsgjn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 Jun 2023 01:57:54 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA02.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 35E1vrVB002740 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 14 Jun 2023 01:57:53 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 13 Jun 2023 18:57:53 -0700 From: Jessica Zhang To: Rob Clark , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Marijn Suijten CC: Jessica Zhang , , , , , Subject: [PATCH 3/3] drm/msm/dsi: Enable DATABUS_WIDEN for DSI command mode Date: Tue, 13 Jun 2023 18:57:13 -0700 Message-ID: <20230525-add-widebus-support-v1-3-c7069f2efca1@quicinc.com> X-Mailer: git-send-email 2.40.1 In-Reply-To: <20230525-add-widebus-support-v1-0-c7069f2efca1@quicinc.com> References: <20230525-add-widebus-support-v1-0-c7069f2efca1@quicinc.com> MIME-Version: 1.0 X-Mailer: b4 0.13-dev-c6835 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686707625; l=3041; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=Ot5W85+n2wSTIxyhW7ySIwhaJ3NO/jx9Yep4NiTXQiA=; b=unTYKp7curlQIui91ILgtf7E8XxrRmddLFh5QbVXblSyPFSY77q7yQVlmKpdADQEchfm/ffls XekqlBYArvwBkMWQbww+HeIdL8ypjtKsGst/dF0lLJqgRW2/+qN3tl3 X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: bY4MKNSQfFzApHCdzXE94bzKJIJ5kXWm X-Proofpoint-GUID: bY4MKNSQfFzApHCdzXE94bzKJIJ5kXWm X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-06-13_24,2023-06-12_02,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 bulkscore=0 adultscore=0 mlxscore=0 mlxlogscore=706 clxscore=1015 impostorscore=0 lowpriorityscore=0 suspectscore=0 priorityscore=1501 phishscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2305260000 definitions=main-2306140012 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org DSI 6G v2.5.x+ supports a data-bus widen mode that allows DSI to send 48 bits of compressed data per pclk instead of 24. For all chipsets that support this mode, enable it whenever DSC is enabled as recommend by the hardware programming guide. Only enable this for command mode as we are currently unable to validate it for video mode. Signed-off-by: Jessica Zhang --- Note: The dsi.xml.h changes were generated using the headergen2 script in envytools [1], but the changes to the copyright and rules-ng-ng source file paths were dropped. [1] https://github.com/freedreno/envytools/ drivers/gpu/drm/msm/dsi/dsi.xml.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 19 ++++++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) -- 2.40.1 diff --git a/drivers/gpu/drm/msm/dsi/dsi.xml.h b/drivers/gpu/drm/msm/dsi/dsi.xml.h index a4a154601114..2a7d980e12c3 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.xml.h +++ b/drivers/gpu/drm/msm/dsi/dsi.xml.h @@ -664,6 +664,7 @@ static inline uint32_t DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP(enum dsi_rgb_swap v return ((val) << DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__SHIFT) & DSI_CMD_MODE_MDP_CTRL2_INPUT_RGB_SWAP__MASK; } #define DSI_CMD_MODE_MDP_CTRL2_BURST_MODE 0x00010000 +#define DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN 0x00100000 #define REG_DSI_CMD_MODE_MDP_STREAM2_CTRL 0x000001b8 #define DSI_CMD_MODE_MDP_STREAM2_CTRL_DATA_TYPE__MASK 0x0000003f diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 5d7b4409e4e9..1da5238e7105 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -927,6 +927,9 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) u32 hdisplay = mode->hdisplay; u32 wc; int ret; + bool widebus_supported = msm_host->cfg_hnd->major == MSM_DSI_VER_MAJOR_6G && + msm_host->cfg_hnd->minor >= MSM_DSI_6G_VER_MINOR_V2_5_0; + DBG(""); @@ -973,8 +976,15 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) * * hdisplay will be divided by 3 here to account for the fact * that DPU sends 3 bytes per pclk cycle to DSI. + * + * If widebus is supported, set DATABUS_WIDEN register and divide hdisplay by 6 + * instead of 3 */ - hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3); + if (!(msm_host->mode_flags & MIPI_DSI_MODE_VIDEO) && widebus_supported) + hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 6); + else + hdisplay = DIV_ROUND_UP(msm_dsc_get_bytes_per_line(msm_host->dsc), 3); + h_total += hdisplay; ha_end = ha_start + hdisplay; } @@ -1027,6 +1037,13 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) dsi_write(msm_host, REG_DSI_CMD_MDP_STREAM0_TOTAL, DSI_CMD_MDP_STREAM0_TOTAL_H_TOTAL(hdisplay) | DSI_CMD_MDP_STREAM0_TOTAL_V_TOTAL(mode->vdisplay)); + + if (msm_host->dsc && widebus_supported) { + u32 mdp_ctrl2 = dsi_read(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2); + + mdp_ctrl2 |= DSI_CMD_MODE_MDP_CTRL2_DATABUS_WIDEN; + dsi_write(msm_host, REG_DSI_CMD_MODE_MDP_CTRL2, mdp_ctrl2); + } } }