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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:24 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 01/18] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs Date: Mon, 12 Jun 2023 08:39:05 +0300 Message-Id: <20230612053922.3284394-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Exted the opp-v2-kryo-cpu.yaml to support defining OPP tables for the previous generation of Qualcomm CPUs, 32-bit Krait-based platforms. It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node for the Krait cores. Add support for the Krait-specific 'operating-points-v2-krait-cpu' compatibility string and the relevant opp-microvolt subclasses properties. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/opp/opp-v2-kryo-cpu.yaml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml index bbbad31ae4ca..93ec778bf333 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml @@ -26,7 +26,9 @@ description: | properties: compatible: - const: operating-points-v2-kryo-cpu + enum: + - operating-points-v2-krait-cpu + - operating-points-v2-kryo-cpu nvmem-cells: description: | @@ -63,14 +65,15 @@ patternProperties: 5: MSM8996SG, speedbin 1 6: MSM8996SG, speedbin 2 7-31: unused - enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, - 0x9, 0xd, 0xe, 0xf, - 0x10, 0x20, 0x30, 0x70] + $ref: /schemas/types.yaml#/definitions/uint32 clock-latency-ns: true required-opps: true + patternProperties: + '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true + required: - opp-hz From patchwork Mon Jun 12 05:39:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691896 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 15053C87FDE for ; Mon, 12 Jun 2023 05:39:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234941AbjFLFjb (ORCPT ); Mon, 12 Jun 2023 01:39:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235152AbjFLFj3 (ORCPT ); Mon, 12 Jun 2023 01:39:29 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6DA7AE73 for ; Sun, 11 Jun 2023 22:39:27 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4f642a24555so4544384e87.3 for ; Sun, 11 Jun 2023 22:39:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548365; x=1689140365; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ie3JO8CZXhE1zFeG17UDNEd3HgBOEPkrNja1n95d20o=; b=d1FMaQVl/IPYQ4/s+v240NLK0h3A+WZwj13cXYx/38rdH/IdKNSJ9PQPqQ1KRaMdy6 xxfTg7S745/dsOAbfiHF7Ykjx2RQv377tyWYd0liXnwkdu/FMauTeUh+mmSLd2plgD9N wXK++k/8YitboVA69BLWm0tnfEyhBXneebgcPwX91AHWRXf7JI8M4BQVIJNL9LVpk52G fvNcXWhayjh65jn9rXN0B0wvWGiQj59kg4zpRXEAf1zIkhpvqbnyOYssCel8X+O+1ouB Y5Pox/sQMl2eSfwcay1gQB/AYUyKm5AtgCip4ZZJvjoz1E4xt6KZYdgM4rnsB6pkw/vn HPDQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548365; x=1689140365; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ie3JO8CZXhE1zFeG17UDNEd3HgBOEPkrNja1n95d20o=; b=DnzucXlzM8blFGYln5fEBuvcXbNNtB46i0IN+4c0cMxkpXogPr1XMekhD1obU41S+q 8b0WnOT4444c99fAcsAqXgZwwzplau3qOBF5x6F4AaMj7hSh6PUFJvUdCxuTDwmT5IoF L8JVtU+2LwGS8f/51bY+E76QwM/nlD0DZYwwyEE0ARvjzx4qSVUqLg6RALZb42LU7PG9 lnJx89fNBJOUKaffxgyTPrIo2vDicgY55PXrF/H1Z7FuhRMM8iNNjhMRwD8Pg7UnALwC KoCLuxxeO9D4g93PiugzPEmCjUsbHwIgfKssSACifUg6m4ZK063SR7A4GOQb49Xv7Dai FV9w== X-Gm-Message-State: AC+VfDx06m14TE6Md1m/s9q0BX0qPKqP7lpeAIx/wdhmq2Bf9lakk9Lz wUCMSKrwPidxotLCJrdaXUjQGg== X-Google-Smtp-Source: ACHHUZ516kKUn6b1fekH4G/Gnj9kFxtlDoXwMpeX+bx7lhmwwGONEYmuNGzeirc+5+Q3+KjLlJ9BGA== X-Received: by 2002:a19:914e:0:b0:4f4:deee:efaf with SMTP id y14-20020a19914e000000b004f4deeeefafmr3226962lfj.4.1686548365625; Sun, 11 Jun 2023 22:39:25 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:25 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 02/18] dt-bindings: soc: qcom: merge qcom,saw2.txt into qcom,spm.yaml Date: Mon, 12 Jun 2023 08:39:06 +0300 Message-Id: <20230612053922.3284394-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The Qualcomm SPM / SAW2 device is described in two bindigns files: arm/msm/qcom,saw2.txt and soc/qcom/qcom,spm.yaml. Merge the former into the latter, adding detailed device node description. While we are at it, also rename qcom,spm.yaml to qcom,saw2.yaml to follow the actual compatible used for these devices. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/arm/msm/qcom,saw2.txt | 58 ------------------- .../qcom/{qcom,spm.yaml => qcom,saw2.yaml} | 22 +++++-- 2 files changed, 16 insertions(+), 64 deletions(-) delete mode 100644 Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt rename Documentation/devicetree/bindings/soc/qcom/{qcom,spm.yaml => qcom,saw2.yaml} (68%) diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt b/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt deleted file mode 100644 index c0e3c3a42bea..000000000000 --- a/Documentation/devicetree/bindings/arm/msm/qcom,saw2.txt +++ /dev/null @@ -1,58 +0,0 @@ -SPM AVS Wrapper 2 (SAW2) - -The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the -Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable -power-controller that transitions a piece of hardware (like a processor or -subsystem) into and out of low power modes via a direct connection to -the PMIC. It can also be wired up to interact with other processors in the -system, notifying them when a low power state is entered or exited. - -Multiple revisions of the SAW hardware are supported using these Device Nodes. -SAW2 revisions differ in the register offset and configuration data. Also, the -same revision of the SAW in different SoCs may have different configuration -data due the differences in hardware capabilities. Hence the SoC name, the -version of the SAW hardware in that SoC and the distinction between cpu (big -or Little) or cache, may be needed to uniquely identify the SAW register -configuration and initialization data. The compatible string is used to -indicate this parameter. - -PROPERTIES - -- compatible: - Usage: required - Value type: - Definition: Must have - "qcom,saw2" - A more specific value could be one of: - "qcom,apq8064-saw2-v1.1-cpu" - "qcom,msm8226-saw2-v2.1-cpu" - "qcom,msm8974-saw2-v2.1-cpu" - "qcom,apq8084-saw2-v2.1-cpu" - -- reg: - Usage: required - Value type: - Definition: the first element specifies the base address and size of - the register region. An optional second element specifies - the base address and size of the alias register region. - -- regulator: - Usage: optional - Value type: boolean - Definition: Indicates that this SPM device acts as a regulator device - device for the core (CPU or Cache) the SPM is attached - to. - -Example 1: - - power-controller@2099000 { - compatible = "qcom,saw2"; - reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; - }; - -Example 2: - saw0: power-controller@f9089000 { - compatible = "qcom,apq8084-saw2-v2.1-cpu", "qcom,saw2"; - reg = <0xf9089000 0x1000>, <0xf9009000 0x1000>; - }; diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml similarity index 68% rename from Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml rename to Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index 20c8cd38ff0d..a016242367b9 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,spm.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -1,18 +1,26 @@ # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/soc/qcom/qcom,spm.yaml# +$id: http://devicetree.org/schemas/soc/qcom/qcom,saw2.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Qualcomm Subsystem Power Manager +title: Qualcomm Subsystem Power Manager / SPM AVS Wrapper 2 (SAW2) maintainers: - Andy Gross - Bjorn Andersson description: | - This binding describes the Qualcomm Subsystem Power Manager, used to control - the peripheral logic surrounding the application cores in Qualcomm platforms. + The Qualcomm Subsystem Power Manager is used to control the peripheral logic + surrounding the application cores in Qualcomm platforms. + + The SAW2 is a wrapper around the Subsystem Power Manager (SPM) and the + Adaptive Voltage Scaling (AVS) hardware. The SPM is a programmable + power-controller that transitions a piece of hardware (like a processor or + subsystem) into and out of low power modes via a direct connection to + the PMIC. It can also be wired up to interact with other processors in the + system, notifying them when a low power state is entered or exited. + properties: compatible: @@ -34,8 +42,10 @@ properties: - const: qcom,saw2 reg: - description: Base address and size of the SPM register region - maxItems: 1 + items: + - description: Base address and size of the SPM register region + - description: Base address and size of the alias register region + minItems: 1 required: - compatible From patchwork Mon Jun 12 05:39:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 692483 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E1CA2C7EE37 for ; Mon, 12 Jun 2023 05:39:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234564AbjFLFjc (ORCPT ); Mon, 12 Jun 2023 01:39:32 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40166 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235296AbjFLFj3 (ORCPT ); Mon, 12 Jun 2023 01:39:29 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8158C9B for ; Sun, 11 Jun 2023 22:39:28 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4f62b552751so4387502e87.3 for ; Sun, 11 Jun 2023 22:39:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548367; x=1689140367; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dMOlASi6Vn7FuOtPlAWq0wcXxa6OXt0yvMgulLt9t1o=; b=IV8FDM+6e4Z39+oOM8sjRpG3VvvvmAOZ8gMDk7zdBAmjnB+SsPmUQmCLhFnguUgHro 76uQmXPGHiJgqYlVjGZcGw+qIui3DiyMFz+08rMwB3DddQRB6KufN0UCj6LmHbVmBso7 mqhiX/UqO8nts1x7HK4S1hdK6hjgrMD6mVUEyzxojJfmOzaSU7X0iqtLCg3IV0yGek44 o09F9PRowfOWNWKEq6ri0L5D35Xpe/UYdfwt6TrifQY0IvULhrCq1DwEA8J8b1zXrrmJ +1eK+E6gzmaY+NKIXyvvd3CaXND36uyS+ubOwGbUwH3BAKt2RrwboDu6zpLWSF4dHe1A 9cFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548367; x=1689140367; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dMOlASi6Vn7FuOtPlAWq0wcXxa6OXt0yvMgulLt9t1o=; b=AEQft8G3goEjUaGTd+DVa6pOOYIV9pROkV9swNGrNHjKaO7wrtJWwOSAZlNexVwLC9 NmQGFoTLDz0KU4kMgKwyghRqw2Xeeut0G4IJjVGHkah48jAUnSRI7dPVpJRzS09cH6sN I9KG30hwPYshzWVbwK0eUclYLphcVE8fKGLC5akMPI5nC+rDASWif74g9nIeLY7YuNlF Snl9sQdWreS5bY9a1O4GKK7L4fneQgvFZv9vr3W6/zp/29vZXCn/P8Nldb3qyl81btzD iwypQvzYbPS6+isYXDhXnn95LGgu8figxC1RkHu97q06DKyLmTq9dXYHA8P+9+tLxafG omGw== X-Gm-Message-State: AC+VfDw2JHwyxmx86DXepP8GjJYdwnizo6mZsPbSRjw0VQCLjI19GNOA MxJe1p6Kw2zL3H+RNR2oMdhSKg== X-Google-Smtp-Source: ACHHUZ7H3956rhfTawL9EpVswr7uTvrdfyXBUKNseJKKQL3/JBkBOF8qACWgtiDyHOJyr9DSD07jrw== X-Received: by 2002:a19:670d:0:b0:4ed:ca3b:40f0 with SMTP id b13-20020a19670d000000b004edca3b40f0mr3389008lfc.9.1686548366927; Sun, 11 Jun 2023 22:39:26 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:26 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 03/18] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node Date: Mon, 12 Jun 2023 08:39:07 +0300 Message-Id: <20230612053922.3284394-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The SAW2 device can optionally provide a voltage regulator supplying the CPU core, cluster or L2 cache. Describe it in the device bindings. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/soc/qcom/qcom,saw2.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index a016242367b9..b809a9cc0916 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -47,6 +47,10 @@ properties: - description: Base address and size of the alias register region minItems: 1 + regulator: + $ref: /schemas/regulator/regulator.yaml# + description: corresponding core, cluster or cache voltage supply regulator + required: - compatible - reg @@ -92,4 +96,17 @@ examples: reg = <0x17912000 0x1000>; }; + - | + /* + * Example 3: SAW2 with the bundled regulator definition. + */ + power-manager@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + + regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; ... 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:27 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 04/18] dt-bindings: clock: qcom,krait-cc: Krait core clock controller Date: Mon, 12 Jun 2023 08:39:08 +0300 Message-Id: <20230612053922.3284394-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Define bindings for the Qualcomm Krait CPU and L2 clock controller. This device is used on old Qualcomm SoCs (APQ8064, MSM8960) and supports up to 4 core clocks and a separate L2 clock. Furthermore, L2 clock is represented as the interconnect to facilitate L2 frequency scaling together with scaling the CPU frequencies. Signed-off-by: Dmitry Baryshkov --- include/dt-bindings/clock/qcom,krait-cc.h | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) create mode 100644 include/dt-bindings/clock/qcom,krait-cc.h diff --git a/include/dt-bindings/clock/qcom,krait-cc.h b/include/dt-bindings/clock/qcom,krait-cc.h new file mode 100644 index 000000000000..c3542b6d73e2 --- /dev/null +++ b/include/dt-bindings/clock/qcom,krait-cc.h @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2023 Linaro Ltd. All rights reserved. + */ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_KRAIT_CC_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_KRAIT_CC_H + +#define KRAIT_CPU_0 0 +#define KRAIT_CPU_1 1 +#define KRAIT_CPU_2 2 +#define KRAIT_CPU_3 3 +#define KRAIT_L2 4 + +#define KRAIT_NUM_CLOCKS 5 + +#define MASTER_KRAIT_L2 0 +#define SLAVE_KRAIT_L2 1 + +#endif From patchwork Mon Jun 12 05:39:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691895 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65105C7EE23 for ; Mon, 12 Jun 2023 05:39:41 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235767AbjFLFjh (ORCPT ); Mon, 12 Jun 2023 01:39:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40172 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235296AbjFLFjd (ORCPT ); Mon, 12 Jun 2023 01:39:33 -0400 Received: from mail-lf1-x12e.google.com (mail-lf1-x12e.google.com [IPv6:2a00:1450:4864:20::12e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BEDDFE6E for ; Sun, 11 Jun 2023 22:39:30 -0700 (PDT) Received: by mail-lf1-x12e.google.com with SMTP id 2adb3069b0e04-4f61735676fso4547835e87.2 for ; Sun, 11 Jun 2023 22:39:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548369; x=1689140369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cDdlePg3Sn8YINuebkJx+v93mjzRedks9PRDH1dCPko=; b=xYZDDPVkv6AH2Kkb9tFrtWvXPv2XnOSe/zGZNtQbzci50/kQmHF4Jh9lA/Dq3+sPSI RWoMPo+BLYzB5S6+vA4WUU6rlxYX5ZPnrKqDzfAvgD6W8VC+YbIfi2I/kvkvdxrL7MQO jsXsocxwY1ljG3OjSwjUNDeeGRenGD1XZL+QYxn+VRj4SsZM0e67hsYo6VUUXZ/y9sgB gm7deEG+xfzLjpEEbM04hrFX0oECN6bL4mgIFfHzvFpoNjegeTshnQJRILcfLs7tsrSh l9e0gOFW1zFZO2bu6s/koHGpi65MtEIHjqiM4M2yUUZSqi/KrcWTvTZUDuEpHNjZQAJf jaPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548369; x=1689140369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cDdlePg3Sn8YINuebkJx+v93mjzRedks9PRDH1dCPko=; b=l7CooHe5eMqTCiUqRZvseOTR1cuVioZaqjNh7UVXzcokJq4XGzh8FGWckeeWRgg8xr G20RYHmYo/FQMslUMgTBRO3X3yHJm4owpOYI4oZg7a7ry0ZzdDie7TWMYMH55+TFl/g0 VHc8mFH73QaPJLhMXiTTuivKWSCK9bjRiz5yifR1dp1xxILTOYEKIu1inpbEb7H1gGQw e5KThUnFGY7uofhShxZOWlt5WEfW22/ElJX0gNX9d0bHRTgxkC11TpPneTcS8FdTh9zU SMYjP6bQ3o0TEUZXTFjumO+bLzyh1CCnZjyB/5TsUxk6I9Udk3JTINebaBEiV9d0q3rf +4Dg== X-Gm-Message-State: AC+VfDz2j9ELW9CvJGzaH0IDS60inE4davmkk4Z/YkuQmg9ibQ5gjII/ /iVoz1AbgAgT1g3FXPmDNxlhTg== X-Google-Smtp-Source: ACHHUZ4LTOFfPGev5zoHP7rx1ABSRmDImHgAbMSrsCCO1UezjhfBEJg7oiacR5PNSzrSktuIUtrmIg== X-Received: by 2002:a19:5f0e:0:b0:4dd:9f86:859d with SMTP id t14-20020a195f0e000000b004dd9f86859dmr3314338lfb.13.1686548369065; Sun, 11 Jun 2023 22:39:29 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:28 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 05/18] clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk Date: Mon, 12 Jun 2023 08:39:09 +0300 Message-Id: <20230612053922.3284394-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The krait-cc driver still uses struct clk internally. Rewrite it to allocate and register struct clk_hw instead. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/krait-cc.c | 122 ++++++++++++++++-------------------- 1 file changed, 54 insertions(+), 68 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 410ae8390f1c..2ce38024dc0d 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -235,7 +235,7 @@ krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *s .parent_data = p_data, .num_parents = ARRAY_SIZE(p_data), .ops = &krait_mux_clk_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, }; struct clk_hw *clk; char *hfpll_name; @@ -324,19 +324,6 @@ static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux return pri_mux; } -static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data) -{ - unsigned int idx = clkspec->args[0]; - struct clk **clks = data; - - if (idx >= clks_max) { - pr_err("%s: invalid clock index %d\n", __func__, idx); - return ERR_PTR(-EINVAL); - } - - return clks[idx] ? : ERR_PTR(-ENODEV); -} - static const struct of_device_id krait_cc_match_table[] = { { .compatible = "qcom,krait-cc-v1", (void *)1UL }, { .compatible = "qcom,krait-cc-v2" }, @@ -344,60 +331,81 @@ static const struct of_device_id krait_cc_match_table[] = { }; MODULE_DEVICE_TABLE(of, krait_cc_match_table); +static int krait_clk_reinit(struct clk_hw *hw, int cpu) +{ + struct clk *clk; + unsigned long cur_rate, aux_rate; + char name[5]; /* CPUn */ + + if (cpu == -1) + strcpy(name, "L2"); + else + snprintf(name, sizeof(name), "CPU%d", cpu); + + clk = clk_hw_get_clk(hw, clk_hw_get_name(hw)); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + aux_rate = 384000000; + + cur_rate = clk_get_rate(clk); + if (cur_rate < aux_rate) { + pr_info("%s @ Undefined rate %lu. Forcing new rate.\n", + name, cur_rate / 1000); + cur_rate = aux_rate; + } + + clk_set_rate(clk, aux_rate); + clk_set_rate(clk, 2); + clk_set_rate(clk, cur_rate); + pr_info("%s @ %lu KHz\n", name, clk_get_rate(clk) / 1000); + + clk_put(clk); + + return 0; +} + static int krait_cc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct of_device_id *id; - unsigned long cur_rate, aux_rate; int cpu; - struct clk_hw *mux, *l2_pri_mux; - struct clk *clk, **clks; + struct clk_hw *clk; + struct clk_hw_onecell_data *clks; id = of_match_device(krait_cc_match_table, dev); if (!id) return -ENODEV; /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + clk = clk_hw_register_fixed_rate(dev, "qsb", NULL, 0, 1); if (IS_ERR(clk)) return PTR_ERR(clk); if (!id->data) { - clk = clk_register_fixed_factor(dev, "acpu_aux", - "gpll0_vote", 0, 1, 2); + clk = clk_hw_register_fixed_factor(dev, "acpu_aux", "gpll0_vote", 0, 1, 2); if (IS_ERR(clk)) return PTR_ERR(clk); } /* Krait configurations have at most 4 CPUs and one L2 */ - clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL); + clks = devm_kzalloc(dev, struct_size(clks, hws, clks_max), GFP_KERNEL); if (!clks) return -ENOMEM; + clks->num = clks_max; + for_each_possible_cpu(cpu) { - mux = krait_add_clks(dev, cpu, id->data); - if (IS_ERR(mux)) - return PTR_ERR(mux); - clks[cpu] = mux->clk; + clk = krait_add_clks(dev, cpu, id->data); + if (IS_ERR(clk)) + return PTR_ERR(clk); + clks->hws[cpu] = clk; } - l2_pri_mux = krait_add_clks(dev, -1, id->data); - if (IS_ERR(l2_pri_mux)) - return PTR_ERR(l2_pri_mux); - clks[l2_mux] = l2_pri_mux->clk; - - /* - * We don't want the CPU or L2 clocks to be turned off at late init - * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the - * refcount of these clocks. Any cpufreq/hotplug manager can assume - * that the clocks have already been prepared and enabled by the time - * they take over. - */ - for_each_online_cpu(cpu) { - clk_prepare_enable(clks[l2_mux]); - WARN(clk_prepare_enable(clks[cpu]), - "Unable to turn on CPU%d clock", cpu); - } + clk = krait_add_clks(dev, -1, id->data); + if (IS_ERR(clk)) + return PTR_ERR(clk); + clks->hws[l2_mux] = clk; /* * Force reinit of HFPLLs and muxes to overwrite any potential @@ -410,33 +418,11 @@ static int krait_cc_probe(struct platform_device *pdev) * two different rates to force a HFPLL reinit under all * circumstances. */ - cur_rate = clk_get_rate(clks[l2_mux]); - aux_rate = 384000000; - if (cur_rate < aux_rate) { - pr_info("L2 @ Undefined rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } - clk_set_rate(clks[l2_mux], aux_rate); - clk_set_rate(clks[l2_mux], 2); - clk_set_rate(clks[l2_mux], cur_rate); - pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); - for_each_possible_cpu(cpu) { - clk = clks[cpu]; - cur_rate = clk_get_rate(clk); - if (cur_rate < aux_rate) { - pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu); - cur_rate = aux_rate; - } - - clk_set_rate(clk, aux_rate); - clk_set_rate(clk, 2); - clk_set_rate(clk, cur_rate); - pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); - } + krait_clk_reinit(clks->hws[l2_mux], -1); + for_each_possible_cpu(cpu) + krait_clk_reinit(clks->hws[cpu], cpu); - of_clk_add_provider(dev->of_node, krait_of_get, clks); - - return 0; + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clks); } static struct platform_driver krait_cc_driver = { From patchwork Mon Jun 12 05:39:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 692481 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7231CC7EE37 for ; Mon, 12 Jun 2023 05:39:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235784AbjFLFjq (ORCPT ); Mon, 12 Jun 2023 01:39:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40248 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235528AbjFLFjd (ORCPT ); Mon, 12 Jun 2023 01:39:33 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C812FE77 for ; Sun, 11 Jun 2023 22:39:31 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-4f60a27c4a2so4240293e87.2 for ; Sun, 11 Jun 2023 22:39:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548370; x=1689140370; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2TlZyzRwY/o/e9xVkO7KMsj7n4flvbaCYZ7tv2gefqg=; b=H21XnBOKHaVHqsY8z2ryRf0/MFJ1LDTIf0Yrmruye0wvVcQPM8SkLhqbAiChKWF6e0 9KcH94jX0zlZXEQTP/uccEF2rvDg2Q7c7jZ1wHJqLE01bsQUFw54t9XjAKajGWjiF9G1 r3rK8D96eU+Y04ZOqiOv/66moueROEutCgdV7mlCalvj/kkbjt26yMdJVyf/kzoy/mRX yHh7uXTmjTa8ds7NMLhW4FGyfnWhlWa6r8SbAB0yWPBP2ZNDu3h3PQn2ssvqMNbr3/i0 4qk+zFz/WbnOW46g73o00+7gTrx01lLtcCngPSKg3aQc/CIBqstN0uiO1Lfj2GkIfPql 5NyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548370; x=1689140370; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2TlZyzRwY/o/e9xVkO7KMsj7n4flvbaCYZ7tv2gefqg=; b=UBJ3sNEGDeqPdqk4CwGIo3sZU588zjAoGveoU55YqZSjSLDS6tM12Co+8jX2WlRf6e D1hxxGN4Gi2EaJ0zqTBqHbg1XoCZWYKfky8BSst7bhi+rX4WOnA44RoaP25/fKDlee5E 6Trp1/Kdh2rj2wBzB3CPpNT2WfZoAEFz7FRXcbuF+w1awzUEWzPV3L1u/YZDbbAEPanE tNpUJ3E2+xI9F6gwuxuycO2D6MyzyYJizhW8hOCQBOkojG9/gcH2NIQrQUgFHatsYSip 0YlJ1EUbINFBe+ScMfZY0wBetC86BvN9Wj+9HGx8Wjvb0n951e8NqeelE66UUFXfK2L4 BmsA== X-Gm-Message-State: AC+VfDxbr8S+c05NNvDUoU56kWsX6T7hT4Kqu6Dd6gJzM02BJXxlyjf6 90xK2ecby/R7Ovxr/cJW/XbVrg== X-Google-Smtp-Source: ACHHUZ6Iw2ZktZqzXHMcaz1jO66ChxfM2TSNrLUjN2r41QjXZTdMjJY2VsagodYpSArFVnnc3EoNzw== X-Received: by 2002:a05:6512:32ad:b0:4f4:b3a6:4140 with SMTP id q13-20020a05651232ad00b004f4b3a64140mr2202507lfe.42.1686548370162; Sun, 11 Jun 2023 22:39:30 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:29 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 06/18] clk: qcom: krait-cc: export L2 clock as an interconnect Date: Mon, 12 Jun 2023 08:39:10 +0300 Message-Id: <20230612053922.3284394-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org While scaling the CPU frequency, L2 frequency should also be scaled following the CPU frequency. To simplify such scaling, export the L2 clock as an interconnect, to facilitate aggregating CPU votes and selecting the maximum vote. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/Kconfig | 1 + drivers/clk/qcom/krait-cc.c | 75 +++++++++++++++++++++++++++++-------- 2 files changed, 60 insertions(+), 16 deletions(-) diff --git a/drivers/clk/qcom/Kconfig b/drivers/clk/qcom/Kconfig index 97f23f978343..3d56263ce494 100644 --- a/drivers/clk/qcom/Kconfig +++ b/drivers/clk/qcom/Kconfig @@ -1065,6 +1065,7 @@ config KRAITCC tristate "Krait Clock Controller" depends on ARM select KRAIT_CLOCKS + select INTERCONNECT_CLK if INTERCONNECT help Support for the Krait CPU clocks on Qualcomm devices. Say Y if you want to support CPU frequency scaling. diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 2ce38024dc0d..f16321fc6dd7 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -11,19 +11,13 @@ #include #include #include +#include +#include #include -#include "clk-krait.h" - -enum { - cpu0_mux = 0, - cpu1_mux, - cpu2_mux, - cpu3_mux, - l2_mux, +#include - clks_max, -}; +#include "clk-krait.h" static unsigned int sec_mux_map[] = { 2, @@ -365,11 +359,54 @@ static int krait_clk_reinit(struct clk_hw *hw, int cpu) return 0; } +#ifdef CONFIG_INTERCONNECT + +/* Random ID that doesn't clash with main qnoc and OSM */ +#define L2_MASTER_NODE 2000 + +static int krait_cc_icc_register(struct platform_device *pdev, struct clk_hw *l2_hw) +{ + struct device *dev = &pdev->dev; + struct clk *clk = devm_clk_hw_get_clk(dev, l2_hw, "l2"); + const struct icc_clk_data data[] = { + { .clk = clk, .name = "l2", }, + }; + struct icc_provider *provider; + + provider = icc_clk_register(dev, L2_MASTER_NODE, ARRAY_SIZE(data), data); + if (IS_ERR(provider)) + return PTR_ERR(provider); + + platform_set_drvdata(pdev, provider); + + return 0; +} + +static int krait_cc_icc_remove(struct platform_device *pdev) +{ + struct icc_provider *provider = platform_get_drvdata(pdev); + + icc_clk_unregister(provider); + + return 0; +} +#define krait_cc_icc_sync_state icc_sync_state +#else +static int krait_cc_icc_register(struct platform_device *pdev, struct clk_hw *l2_hw) +{ + dev_warn(&pdev->dev, "CONFIG_INTERCONNECT is disabled, L2 clock is fixed\n"); + + return 0; +} +#define krait_cc_icc_remove(pdev) (0) +#define krait_cc_icc_sync_state NULL +#endif + static int krait_cc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct of_device_id *id; - int cpu; + int cpu, ret; struct clk_hw *clk; struct clk_hw_onecell_data *clks; @@ -389,11 +426,11 @@ static int krait_cc_probe(struct platform_device *pdev) } /* Krait configurations have at most 4 CPUs and one L2 */ - clks = devm_kzalloc(dev, struct_size(clks, hws, clks_max), GFP_KERNEL); + clks = devm_kzalloc(dev, struct_size(clks, hws, KRAIT_NUM_CLOCKS), GFP_KERNEL); if (!clks) return -ENOMEM; - clks->num = clks_max; + clks->num = KRAIT_NUM_CLOCKS; for_each_possible_cpu(cpu) { clk = krait_add_clks(dev, cpu, id->data); @@ -405,7 +442,7 @@ static int krait_cc_probe(struct platform_device *pdev) clk = krait_add_clks(dev, -1, id->data); if (IS_ERR(clk)) return PTR_ERR(clk); - clks->hws[l2_mux] = clk; + clks->hws[KRAIT_L2] = clk; /* * Force reinit of HFPLLs and muxes to overwrite any potential @@ -418,18 +455,24 @@ static int krait_cc_probe(struct platform_device *pdev) * two different rates to force a HFPLL reinit under all * circumstances. */ - krait_clk_reinit(clks->hws[l2_mux], -1); + krait_clk_reinit(clks->hws[KRAIT_L2], -1); for_each_possible_cpu(cpu) krait_clk_reinit(clks->hws[cpu], cpu); - return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clks); + ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clks); + if (ret) + return ret; + + return krait_cc_icc_register(pdev, clks->hws[KRAIT_L2]); } static struct platform_driver krait_cc_driver = { .probe = krait_cc_probe, + .remove = krait_cc_icc_remove, .driver = { .name = "krait-cc", .of_match_table = krait_cc_match_table, + .sync_state = krait_cc_icc_sync_state, }, }; module_platform_driver(krait_cc_driver); From patchwork Mon Jun 12 05:39:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691894 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EB8AC7EE37 for ; Mon, 12 Jun 2023 05:39:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235840AbjFLFjt (ORCPT ); Mon, 12 Jun 2023 01:39:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40146 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235688AbjFLFjf (ORCPT ); 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:30 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 07/18] soc: qcom: spm: add support for voltage regulator Date: Mon, 12 Jun 2023 08:39:11 +0300 Message-Id: <20230612053922.3284394-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The SPM / SAW2 device also provides a voltage regulator functionality with optional AVS (Adaptive Voltage Scaling) support. The exact register sequence and voltage ranges differs from device to device. Signed-off-by: Dmitry Baryshkov --- drivers/soc/qcom/spm.c | 205 ++++++++++++++++++++++++++++++++++++++++- include/soc/qcom/spm.h | 9 ++ 2 files changed, 212 insertions(+), 2 deletions(-) diff --git a/drivers/soc/qcom/spm.c b/drivers/soc/qcom/spm.c index a6cbeb40831b..3c16a7e1710c 100644 --- a/drivers/soc/qcom/spm.c +++ b/drivers/soc/qcom/spm.c @@ -9,19 +9,31 @@ #include #include #include +#include +#include #include #include #include #include #include +#include #include #include +#include +#include #include +#define FIELD_SET(current, mask, val) \ + (((current) & ~(mask)) | FIELD_PREP((mask), (val))) + #define SPM_CTL_INDEX 0x7f #define SPM_CTL_INDEX_SHIFT 4 #define SPM_CTL_EN BIT(0) +#define SPM_1_1_AVS_CTL_AVS_ENABLED BIT(27) +#define SPM_AVS_CTL_MIN_VLVL (0x3f << 10) +#define SPM_AVS_CTL_MAX_VLVL (0x3f << 17) + enum spm_reg { SPM_REG_CFG, SPM_REG_SPM_CTL, @@ -31,10 +43,12 @@ enum spm_reg { SPM_REG_PMIC_DATA_1, SPM_REG_VCTL, SPM_REG_SEQ_ENTRY, - SPM_REG_SPM_STS, + SPM_REG_STS0, + SPM_REG_STS1, SPM_REG_PMIC_STS, SPM_REG_AVS_CTL, SPM_REG_AVS_LIMIT, + SPM_REG_RST, SPM_REG_NR, }; @@ -171,6 +185,10 @@ static const struct spm_reg_data spm_reg_8226_cpu = { static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_CFG] = 0x08, + [SPM_REG_STS0] = 0x0c, + [SPM_REG_STS1] = 0x10, + [SPM_REG_VCTL] = 0x14, + [SPM_REG_AVS_CTL] = 0x18, [SPM_REG_SPM_CTL] = 0x20, [SPM_REG_PMIC_DLY] = 0x24, [SPM_REG_PMIC_DATA_0] = 0x28, @@ -178,7 +196,12 @@ static const u16 spm_reg_offset_v1_1[SPM_REG_NR] = { [SPM_REG_SEQ_ENTRY] = 0x80, }; +static void smp_set_vdd_v1_1(void *data); + /* SPM register data for 8064 */ +static struct linear_range spm_v1_1_regulator_range = + REGULATOR_LINEAR_RANGE(700000, 0, 56, 12500); + static const struct spm_reg_data spm_reg_8064_cpu = { .reg_offset = spm_reg_offset_v1_1, .spm_cfg = 0x1F, @@ -189,6 +212,10 @@ static const struct spm_reg_data spm_reg_8064_cpu = { 0x10, 0x54, 0x30, 0x0C, 0x24, 0x30, 0x0F }, .start_index[PM_SLEEP_MODE_STBY] = 0, .start_index[PM_SLEEP_MODE_SPC] = 2, + .set_vdd = smp_set_vdd_v1_1, + .range = &spm_v1_1_regulator_range, + .init_uV = 1300000, + .ramp_delay = 1250, }; static inline void spm_register_write(struct spm_driver_data *drv, @@ -240,6 +267,179 @@ void spm_set_low_power_mode(struct spm_driver_data *drv, spm_register_write_sync(drv, SPM_REG_SPM_CTL, ctl_val); } +static int spm_set_voltage_sel(struct regulator_dev *rdev, unsigned int selector) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + drv->volt_sel = selector; + + /* Always do the SAW register writes on the corresponding CPU */ + return smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); +} + +static int spm_get_voltage_sel(struct regulator_dev *rdev) +{ + struct spm_driver_data *drv = rdev_get_drvdata(rdev); + + return drv->volt_sel; +} + +static const struct regulator_ops spm_reg_ops = { + .set_voltage_sel = spm_set_voltage_sel, + .get_voltage_sel = spm_get_voltage_sel, + .list_voltage = regulator_list_voltage_linear_range, + .set_voltage_time_sel = regulator_set_voltage_time_sel, +}; + +static void smp_set_vdd_v1_1(void *data) +{ + struct spm_driver_data *drv = data; + unsigned int vlevel = drv->volt_sel; + unsigned int vctl, data0, data1, avs_ctl, sts; + bool avs_enabled; + + vlevel |= 0x80; /* band */ + + avs_ctl = spm_register_read(drv, SPM_REG_AVS_CTL); + vctl = spm_register_read(drv, SPM_REG_VCTL); + data0 = spm_register_read(drv, SPM_REG_PMIC_DATA_0); + data1 = spm_register_read(drv, SPM_REG_PMIC_DATA_1); + + avs_enabled = avs_ctl & SPM_1_1_AVS_CTL_AVS_ENABLED; + + /* If AVS is enabled, switch it off during the voltage change */ + if (avs_enabled) { + avs_ctl &= ~SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + + /* Kick the state machine back to idle */ + spm_register_write(drv, SPM_REG_RST, 1); + + vctl = FIELD_SET(vctl, 0xff, vlevel); + data0 = FIELD_SET(data0, 0xff, vlevel); + data1 = FIELD_SET(data1, 0x3f, vlevel); + data1 = FIELD_SET(data1, 0x3f << 16, vlevel); + + spm_register_write(drv, SPM_REG_VCTL, vctl); + spm_register_write(drv, SPM_REG_PMIC_DATA_0, data0); + spm_register_write(drv, SPM_REG_PMIC_DATA_1, data1); + + if (read_poll_timeout_atomic(spm_register_read, + sts, sts == vlevel, + 1, 200, false, + drv, SPM_REG_STS1)) { + dev_err_ratelimited(drv->dev, "timeout setting the voltage (%x %x)!\n", sts, vlevel); + goto enable_avs; + } + + if (avs_enabled) { + unsigned int max_avs = vlevel & 0x3f; + unsigned int min_avs = max(max_avs, 4U) - 4; + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MIN_VLVL, min_avs); + avs_ctl = FIELD_SET(avs_ctl, SPM_AVS_CTL_MAX_VLVL, max_avs); + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } + +enable_avs: + if (avs_enabled) { + avs_ctl |= SPM_1_1_AVS_CTL_AVS_ENABLED; + spm_register_write(drv, SPM_REG_AVS_CTL, avs_ctl); + } +} + +static int spm_get_cpu(struct device *dev) +{ + int cpu; + bool found; + + for_each_possible_cpu(cpu) { + struct device_node *cpu_node, *saw_node; + + cpu_node = of_cpu_device_node_get(cpu); + if (!cpu_node) + continue; + + saw_node = of_parse_phandle(cpu_node, "qcom,saw", 0); + found = (saw_node == dev->of_node); + of_node_put(saw_node); + of_node_put(cpu_node); + + if (found) + return cpu; + } + + /* L2 SPM is not bound to any CPU, tie it to CPU0 */ + + return 0; +} + +#ifdef CONFIG_REGULATOR +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + struct regulator_config config = { + .dev = dev, + .driver_data = drv, + }; + struct regulator_desc *rdesc; + struct regulator_dev *rdev; + int ret; + bool found; + + if (!drv->reg_data->set_vdd) + return 0; + + rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL); + if (!rdesc) + return -ENOMEM; + + rdesc->name = "spm"; + rdesc->of_match = of_match_ptr("regulator"); + rdesc->type = REGULATOR_VOLTAGE; + rdesc->owner = THIS_MODULE; + rdesc->ops = &spm_reg_ops; + + rdesc->linear_ranges = drv->reg_data->range; + rdesc->n_linear_ranges = 1; + rdesc->n_voltages = rdesc->linear_ranges[rdesc->n_linear_ranges - 1].max_sel + 1; + rdesc->ramp_delay = drv->reg_data->ramp_delay; + + drv->reg_cpu = spm_get_cpu(dev); + dev_dbg(dev, "SAW2 bound to CPU %d\n", drv->reg_cpu); + + /* + * Program initial voltage, otherwise registration will also try + * setting the voltage, which might result in undervolting the CPU. + */ + drv->volt_sel = DIV_ROUND_UP(drv->reg_data->init_uV - rdesc->min_uV, + rdesc->uV_step); + ret = linear_range_get_selector_high(drv->reg_data->range, + drv->reg_data->init_uV, + &drv->volt_sel, + &found); + if (ret) { + dev_err(dev, "Initial uV value out of bounds\n"); + return ret; + } + + /* Always do the SAW register writes on the corresponding CPU */ + smp_call_function_single(drv->reg_cpu, drv->reg_data->set_vdd, drv, true); + + rdev = devm_regulator_register(dev, rdesc, &config); + if (IS_ERR(rdev)) { + dev_err(dev, "failed to register regulator\n"); + return PTR_ERR(rdev); + } + + return 0; +} +#else +static int spm_register_regulator(struct device *dev, struct spm_driver_data *drv) +{ + return 0; +} +#endif + static const struct of_device_id spm_match_table[] = { { .compatible = "qcom,sdm660-gold-saw2-v4.1-l2", .data = &spm_reg_660_gold_l2 }, @@ -292,6 +492,7 @@ static int spm_dev_probe(struct platform_device *pdev) return -ENODEV; drv->reg_data = match_id->data; + drv->dev = &pdev->dev; platform_set_drvdata(pdev, drv); /* Write the SPM sequences first.. */ @@ -319,7 +520,7 @@ static int spm_dev_probe(struct platform_device *pdev) if (drv->reg_data->reg_offset[SPM_REG_SPM_CTL]) spm_set_low_power_mode(drv, PM_SLEEP_MODE_STBY); - return 0; + return spm_register_regulator(&pdev->dev, drv); } static struct platform_driver spm_driver = { diff --git a/include/soc/qcom/spm.h b/include/soc/qcom/spm.h index 4951f9d8b0bd..9859ebe42003 100644 --- a/include/soc/qcom/spm.h +++ b/include/soc/qcom/spm.h @@ -30,11 +30,20 @@ struct spm_reg_data { u32 avs_limit; u8 seq[MAX_SEQ_DATA]; u8 start_index[PM_SLEEP_MODE_NR]; + + smp_call_func_t set_vdd; + /* for now we support only a single range */ + struct linear_range *range; + unsigned int ramp_delay; + unsigned int init_uV; }; struct spm_driver_data { void __iomem *reg_base; const struct spm_reg_data *reg_data; + struct device *dev; + unsigned int volt_sel; + int reg_cpu; }; void spm_set_low_power_mode(struct spm_driver_data *drv, From patchwork Mon Jun 12 05:39:12 2023 Content-Type: text/plain; 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:31 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 08/18] cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu Date: Mon, 12 Jun 2023 08:39:12 +0300 Message-Id: <20230612053922.3284394-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org the qcom-cpufreq-nvmem driver attempts to support both Qualcomm Kryo (newer 64-bit ARMv8 cores) and Krait (older 32-bit ARMv7 cores). It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node for the Krait cores. Add support for 'operating-points-v2-krait-cpu' compatibility string. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index a88b6fe5db50..fee9736f7326 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -238,7 +238,8 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) if (!np) return -ENOENT; - ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); + ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") || + of_device_is_compatible(np, "operating-points-v2-krait-cpu"); if (!ret) { of_node_put(np); return -ENOENT; From patchwork Mon Jun 12 05:39:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 692479 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21A3BC7EE45 for ; Mon, 12 Jun 2023 05:40:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235900AbjFLFkB (ORCPT ); Mon, 12 Jun 2023 01:40:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234802AbjFLFjg (ORCPT ); Mon, 12 Jun 2023 01:39:36 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C042E10D9 for ; Sun, 11 Jun 2023 22:39:34 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-4f4e71a09a7so4761960e87.1 for ; Sun, 11 Jun 2023 22:39:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548373; x=1689140373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hcxDwDZfbo/85khIYBSZuraP26/4wkWE6EMGE9oVioQ=; b=xO8QvMEbbpDd73N5wYMdhNxf48iGu0aWOhr6Al47xOuHsTdWUOla0Qm2Iov3fSJYxK iKPuOLaApFe5S8HaV2vas+g+6hK+fPhANh8DbvbfNp9UbdVIsfRQBjKdyfMdX0kYe9ds lpFMJh3wJ0pFM6P3L5e86Qd1HY/7J+zjchux515AFXZN2NeAruWI1oTRkzIMHBp8abbp PrO4rCqrGorIEjio732nTIIE4MYdfPd1/x/5lT8JXsFDlGismbbWGwXr+g9zD8aAI7T4 2bOO5dCr3GCwxitQ87/WP3xlFTIMZseENFY9RKrU+c3LED13UarNTirx1qvvrRnMiYTZ RDyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548373; x=1689140373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hcxDwDZfbo/85khIYBSZuraP26/4wkWE6EMGE9oVioQ=; b=ftoLPtMjEJoPcuyi5uAMwN6a4WJTu0VuttRnjarSeY510c2K8fSg9Gggq/q5fW7h0P G9/dG1PwmdLWXcb4aG5AW+W+Ch7rUdGKEZmxuQmposekAFL5VHsLKh2CkxMSs9jhtQ6y vlT0uYaMOa84lVMS6mLHlQBy3rNbYKiJFsSnMg5S4o3nMXk7MjN1zH+QdOco9PZX9QcZ 1npPEmsXCWs3HZVwppzCjBDy32we2eMDbCJ62dpNa7bIwjt1VZVvnZmAeOpkS119SuuB eFTRrCC7+IEp2zaPaVkIFVDcCGp2ttThfMhbrOrLKz0S9fluRQ3Q5qD058RjbrkvoBm4 Al8g== X-Gm-Message-State: AC+VfDynyVKnOes2Ov5ns8+fks+ZVfWD87aJNfyFw/qW6oahgRJEdahW vNoHIVtsKcmFyYrkF8sqlRp71Q== X-Google-Smtp-Source: ACHHUZ6JnnQBqlWQ8vytyKIbJhtuEgKzCTcCctpgOK6LyFqsrxBZP42pngw+Hq4/WeyQZLSy35XlZA== X-Received: by 2002:a19:791d:0:b0:4f3:a9a8:8d84 with SMTP id u29-20020a19791d000000b004f3a9a88d84mr2557182lfc.6.1686548372932; Sun, 11 Jun 2023 22:39:32 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:32 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 09/18] cpufreq: qcom-nvmem: Add support for voltage scaling Date: Mon, 12 Jun 2023 08:39:13 +0300 Message-Id: <20230612053922.3284394-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org If requested by the platform, scale voltages according to data specified in the OPP tables. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 115 ++++++++++++++++++++++++++- 1 file changed, 114 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index fee9736f7326..18d6e6ed1bd0 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -39,6 +40,7 @@ struct qcom_cpufreq_match_data { char **pvs_name, struct qcom_cpufreq_drv *drv); const char **genpd_names; + const char * const *regulator_names; }; struct qcom_cpufreq_drv { @@ -218,6 +220,110 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = { .genpd_names = qcs404_genpd_names, }; +#define NUM_SUPPLIES 2 +static int qcom_cpufreq_config_regulators(struct device *dev, + struct dev_pm_opp *old_opp, + struct dev_pm_opp *new_opp, + struct regulator **regulators, + unsigned int count) +{ + struct dev_pm_opp_supply supplies[NUM_SUPPLIES]; + unsigned long old_freq, freq; + unsigned int i; + int ret; + + if (WARN_ON_ONCE(count != NUM_SUPPLIES)) + return -EINVAL; + + ret = dev_pm_opp_get_supplies(new_opp, supplies); + if (WARN_ON(ret)) + return ret; + + old_freq = dev_pm_opp_get_freq(old_opp); + freq = dev_pm_opp_get_freq(new_opp); + + WARN_ON(!old_freq || !freq); + if (freq > old_freq) { + for (i = 0; i < count; i++) { + struct regulator *reg = regulators[i]; + struct dev_pm_opp_supply *supply = &supplies[i]; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + ret = regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + if (ret) { + dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n", + __func__, supply->u_volt_min, supply->u_volt, + supply->u_volt_max, ret); + goto restore_backwards; + } + } + } else { + for (i = count; i > 0; i--) { + struct regulator *reg = regulators[i - 1]; + struct dev_pm_opp_supply *supply = &supplies[i - 1]; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + ret = regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + if (ret) { + dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n", + __func__, supply->u_volt_min, supply->u_volt, + supply->u_volt_max, ret); + goto restore_forward; + } + } + } + + return 0; + +restore_backwards: + + dev_pm_opp_get_supplies(old_opp, supplies); + + for (; i > 0; i--) { + struct regulator *reg = regulators[i - 1]; + struct dev_pm_opp_supply *supply = &supplies[i - 1]; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + } + + return ret; + +restore_forward: + + dev_pm_opp_get_supplies(old_opp, supplies); + + for ( ; i < count; i++) { + struct regulator *reg = regulators[i]; + struct dev_pm_opp_supply *supply = &supplies[i]; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + } + + return ret; +} + static int qcom_cpufreq_probe(struct platform_device *pdev) { struct qcom_cpufreq_drv *drv; @@ -305,7 +411,14 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) config.virt_devs = NULL; } - if (config.supported_hw || config.genpd_names) { + if (drv->data->regulator_names) { + config.config_regulators = qcom_cpufreq_config_regulators; + config.regulator_names = drv->data->regulator_names; + } + + if (config.supported_hw || + config.genpd_names || + config.regulator_names) { drv->opp_tokens[cpu] = dev_pm_opp_set_config(cpu_dev, &config); if (drv->opp_tokens[cpu] < 0) { ret = drv->opp_tokens[cpu]; From patchwork Mon Jun 12 05:39:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691893 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93C50C87FDE for ; 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:33 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 10/18] cpufreq: qcom-nvmem: drop pvs_ver for format a fuses Date: Mon, 12 Jun 2023 08:39:14 +0300 Message-Id: <20230612053922.3284394-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The fuses used on msm8960 / apq8064 / ipq806x families of devices do not have the pvs version. Drop this argument from parsing function. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index 18d6e6ed1bd0..fc446acfda22 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -52,7 +52,7 @@ struct qcom_cpufreq_drv { static struct platform_device *cpufreq_dt_pdev, *cpufreq_pdev; static void get_krait_bin_format_a(struct device *cpu_dev, - int *speed, int *pvs, int *pvs_ver, + int *speed, int *pvs, u8 *buf) { u32 pte_efuse; @@ -183,7 +183,7 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, switch (len) { case 4: - get_krait_bin_format_a(cpu_dev, &speed, &pvs, &pvs_ver, + get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); break; case 8: From patchwork Mon Jun 12 05:39:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691892 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37AABC87FF2 for ; Mon, 12 Jun 2023 05:40:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233238AbjFLFkD (ORCPT ); Mon, 12 Jun 2023 01:40:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235781AbjFLFjq (ORCPT ); Mon, 12 Jun 2023 01:39:46 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8849310E0 for ; Sun, 11 Jun 2023 22:39:36 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4f649db9b25so4445474e87.0 for ; Sun, 11 Jun 2023 22:39:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548374; x=1689140374; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=I6BmIz26haO/gRx19tTS+BciZJfoAnK1MSrY6sI/V8k=; b=QFY8ZBjlIVAsQYNCRm8MpmPXZt8qZvcVP/Xp6qxReozaztaxZg7fJnMQn+sWoPexl9 lVyLgMPyldymmgl5IlxcX5fEHMqF8xfjpOspd3OxolLhopC4daJ8H4miHbq+JmYAgy26 Ft8WoX1Bu4u9ifYn76NX0k1cgmaYLdytTikYLnGQPtWjDAxj33uhwM/J2C45qIKOE1P5 wVS11E+YUo0ON7OFTblPyQtBmdt5+QnrSvFe3BvbuqL/cw5ihzpSh+sLeV5p/M7Ibbul 1LWl9pUdciY1p2jRT9xsYdagj9EaWBFFCKh4fnwKXB+1sjS4a4Yf34JcK5KTHJ+eSJMX 0IkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548374; x=1689140374; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=I6BmIz26haO/gRx19tTS+BciZJfoAnK1MSrY6sI/V8k=; b=I//mybW4AEpK5vhd+YLURTM037xlM5YfJD3IoBtxeU3cL/9peNCy8gKsEhbnwXSmO8 aTVaMgtqjQEjgZKOXE54pOe/rtoYjvZMk3m5VkQstufSQUvbDLVmO2qnWIT2NBz/L/oM VgSESFLZwLb8aFkPAoRhGVPnohpkha8ZtTpz3jlLK2gS24scgkp5JNM9Xk2UUWQpP8Fh setLrm0QULqf8sNR3aZ4Q50oZohbv4Eus7lZbWJNBCGSr1JmTp4KSmSp6AyM2EcZVv20 zvoBQDwIVlqj3YJbf5hCMxgfBwTkVzmh0Dc0ncGOwTKPc+RBL8bfONCJ281Ubxhw7oS8 PYOA== X-Gm-Message-State: AC+VfDw+DpF60sUpbHjWNR6z+hsysD1bndeykJ00ZZ6xWjrJtdnN77/C qtjWbcH8ouPp6jRl4m8tyoOAIQ== X-Google-Smtp-Source: ACHHUZ7+Jem4hQArYg/4ZZ2o2xuhyXDoB47oVaMbUTualpRO95YO9Rlm7N0YUi+NM71qo45fUj/ibQ== X-Received: by 2002:a19:7101:0:b0:4f3:b61a:a94b with SMTP id m1-20020a197101000000b004f3b61aa94bmr3213076lfc.53.1686548374716; Sun, 11 Jun 2023 22:39:34 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:34 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 11/18] cpufreq: qcom-nvmem: provide separate configuration data for apq8064 Date: Mon, 12 Jun 2023 08:39:15 +0300 Message-Id: <20230612053922.3284394-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org APQ8064 can scale core and memory voltages according to the frequency needs. Rather than reusing the A/B format multiplexer, use a simple fuse parsing function and configure required regulators. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 44 ++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index fc446acfda22..e5fede594399 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -206,6 +206,34 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, return ret; } +static int qcom_cpufreq_apq8064_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + char **pvs_name, + struct qcom_cpufreq_drv *drv) +{ + int speed = 0, pvs = 0; + u8 *speedbin; + size_t len; + int ret = 0; + + speedbin = nvmem_cell_read(speedbin_nvmem, &len); + if (IS_ERR(speedbin)) + return PTR_ERR(speedbin); + + if (len != 4) + return -EINVAL; + + get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); + + snprintf(*pvs_name, sizeof("speedXX-pvsXX"), "speed%d-pvs%d", + speed, pvs); + + drv->versions = (1 << speed); + + kfree(speedbin); + return ret; +} + static const struct qcom_cpufreq_match_data match_data_kryo = { .get_version = qcom_cpufreq_kryo_name_version, }; @@ -220,7 +248,19 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = { .genpd_names = qcs404_genpd_names, }; -#define NUM_SUPPLIES 2 +static const char * apq8064_regulator_names[] = { + "vdd-mem", + "vdd-dig", + "vdd-core", + NULL +}; + +static const struct qcom_cpufreq_match_data match_data_apq8064 = { + .get_version = qcom_cpufreq_apq8064_name_version, + .regulator_names = apq8064_regulator_names, +}; + +#define NUM_SUPPLIES 3 static int qcom_cpufreq_config_regulators(struct device *dev, struct dev_pm_opp *old_opp, struct dev_pm_opp *new_opp, @@ -477,7 +517,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { { .compatible = "qcom,msm8996", .data = &match_data_kryo }, { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, { .compatible = "qcom,ipq8064", .data = &match_data_krait }, - { .compatible = "qcom,apq8064", .data = &match_data_krait }, + { .compatible = "qcom,apq8064", .data = &match_data_apq8064 }, { .compatible = "qcom,msm8974", .data = &match_data_krait }, { .compatible = "qcom,msm8960", .data = &match_data_krait }, {}, From patchwork Mon Jun 12 05:39:16 2023 Content-Type: text/plain; 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:35 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 12/18] ARM: dts: qcom: apq8064: rename SAW nodes to power-manager Date: Mon, 12 Jun 2023 08:39:16 +0300 Message-Id: <20230612053922.3284394-13-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Per the power-domain.yaml, the power-controller node name is reserved for power-domain providers. Rename SAW2 nodes to 'power-manager', the name which is suggested by qcom,spm.yaml Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index d2289205ff81..471eeca6a589 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -422,25 +422,25 @@ acc3: clock-controller@20b8000 { #clock-cells = <0>; }; - saw0: power-controller@2089000 { + saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw1: power-controller@2099000 { + saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw2: power-controller@20a9000 { + saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; regulator; }; - saw3: power-controller@20b9000 { + saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; regulator; From patchwork Mon Jun 12 05:39:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691891 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 04DC1C87FE7 for ; Mon, 12 Jun 2023 05:40:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235974AbjFLFkG (ORCPT ); Mon, 12 Jun 2023 01:40:06 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40602 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235855AbjFLFju (ORCPT ); Mon, 12 Jun 2023 01:39:50 -0400 Received: from mail-lf1-x135.google.com (mail-lf1-x135.google.com [IPv6:2a00:1450:4864:20::135]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 65E9B1700 for ; Sun, 11 Jun 2023 22:39:38 -0700 (PDT) Received: by mail-lf1-x135.google.com with SMTP id 2adb3069b0e04-4f62d93f38aso4561982e87.0 for ; Sun, 11 Jun 2023 22:39:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548376; x=1689140376; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6PALwgyHQ+TieQGPmUm7gjgazS+uJ8oClOdkRzim+GA=; b=WQ76T6AYO9iXreicPvFvTy8FGnJ5tlrR7zDNET/6ri723/Su8VflS/Ya1fq3VXZIyv PF2kCf5QUbyhkmHcqMlfxzh+G8NwJMyO0FbiKqZXYBZm3IxbRoGY6fs15ZWAmdf5f5BL 25m6veF+v2wBl5QA9bMu/cP6AXahqqKyslExU5EdJf6Qj9tWd6vswiHhvVTdS481Y+Ct gcPt/DMtrNOoSkU08ajqZMYuR59esp6YOPaD8tpJOEeQ/29rWJGWa8oYa4Vgddne+4V3 cOxk2QUS90j5H3VnVpONsq8IE1SRyJTfd+DY/VF08Qv7jIbtZPakplgYZozcdUN0QJgG 5fZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548376; x=1689140376; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6PALwgyHQ+TieQGPmUm7gjgazS+uJ8oClOdkRzim+GA=; b=dat2EPGbf5LzhTkqG+kTcg9qxFxT/+oDMmdV0lbRebmHoqQUr7OfO06wQ6ab72yVA/ glf3oSPAPcvkri32yTOP4nv3TYcEM9lqKjM8qZoRS2axE04fLHmZTuDckZhk7u1zBHTX 6A/hiRGXaFO1obAJdPB2+jDJG1k9cxgfybPN4dXydeobOxVCIjojDXVe/cvoxOYaIDy3 POpXZdinMordxSCRJLFpWkGIZG/YjjLwC7rNjArLHZbR/q194JTDRcSxqQgwEjBYCAZ5 fCRgML5mhaHr9ws8AcvVdVpHh2JtN+bpQizgRcIjk4M3FZC2Kvqu0+H3V9UTVvrWMJXq hNsA== X-Gm-Message-State: AC+VfDwvxas9MWRWa5DzwjmMEz0NJxavx403YuFr5IhbfxwHRV2UUt+p qBs0hIehb6tu8eW2DhDii4dYyw== X-Google-Smtp-Source: ACHHUZ70K7TIUhk3aWrow/GwcxAggY7k2lj2rDnC8KHQGKNXbohL/WhmjzvxUc2avAPBm2O4jSKpKQ== X-Received: by 2002:a05:6512:614:b0:4f4:aea9:2a2f with SMTP id b20-20020a056512061400b004f4aea92a2fmr4023869lfe.57.1686548376642; Sun, 11 Jun 2023 22:39:36 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:36 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 13/18] ARM: dts: qcom: apq8064: declare SAW2 regulators Date: Mon, 12 Jun 2023 08:39:17 +0300 Message-Id: <20230612053922.3284394-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org The SAW2 (SPM and AVS Wrapper) among other things is yet another way to handle CPU-related PMIC regulators. Provide a way to control voltage of these regulators. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 471eeca6a589..1eb6d752ebae 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -425,25 +425,41 @@ acc3: clock-controller@20b8000 { saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw2_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw3_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; sps_sic_non_secure: sps-sic-non-secure@12100000 { From patchwork Mon Jun 12 05:39:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 692477 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 38175C87FDC for ; Mon, 12 Jun 2023 05:40:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235669AbjFLFkJ (ORCPT ); Mon, 12 Jun 2023 01:40:09 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235911AbjFLFjw (ORCPT ); Mon, 12 Jun 2023 01:39:52 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 963271708 for ; Sun, 11 Jun 2023 22:39:39 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-4f655293a38so4112638e87.0 for ; Sun, 11 Jun 2023 22:39:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548377; x=1689140377; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2wt0ovU1UM+zA+dgM6wsatyMQXhOAKNo5+GG5VSQHHw=; b=EVq7+quentdGKbnYY/O8EK69vkcDvHM6X100UqLLPilN1h0Is54Tn0S1qjewyewmWY CcQy0k8MenfpDs4A5vxV5UkIU73xoLyRJnReJTxAuyG8TzPiYpGm97NLIOpiRxVWGdVi 37cNMEH8dmDQIOJHVCPzxUSqPB/s5kR0VhDc5y5kzeKKlMYa3IN3fV0k76J/Cp9esbzS +QgV8mMz/X4DsHRyJr2RbDI6I/HzYnrssT8kQqaNPDwSpceNClwxdZNr4o2LjOOen0vI GkMM1GmwMf/hzsFZ2ToFmlevF+1Xds9zTcKaWpHNrgF1CoW/mnFNyheDJiAvrvgyT0i4 NIhQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548377; x=1689140377; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2wt0ovU1UM+zA+dgM6wsatyMQXhOAKNo5+GG5VSQHHw=; b=AdmopcsUgG5X/AOYw7dqPlNgTOiGnebcZ7E2qVbLK/9cpa034KcEJTGRPvgjWGLDM/ 8XwlqTVMFi/39T7qKOjk3+kGhUBllrgPWvQKwT7RhnfDn4a83FkP7o8Sxqwb9Oxo4F7+ mbnM3XMgCiM1TZdHGyCVrXjYmectnwu6B0mfU4zVhTRe0JA9Lq17EMpvtv8qeCRrkvcF r71IvL7VlT+TuNRA/irC8erzPVnQNf4+PyBOA25YkE0C1k2uj99HQP5PqsCSfRCb8Fq0 c/ZzEsg13oSc6SZIHfmeVZw3/FsiDYvNMRed2K7rVb+KrdJy6OtUxu5Nx+daM368A9+7 dC0Q== X-Gm-Message-State: AC+VfDymnanFKYAfIU66T7utBRzxmS1Mte9nLWPy3foFJHxm2KUHuLAd fRzWtibTVSUm4XywMAkvuZSvTA== X-Google-Smtp-Source: ACHHUZ4PBTd1f3XY3VTSalfSjrcIfe4nVCYBRPFjlwpVAtsnRsA0U/XqOmpMYza/DdKIVdiCF65YdQ== X-Received: by 2002:a05:6512:1cd:b0:4f4:dd51:aec7 with SMTP id f13-20020a05651201cd00b004f4dd51aec7mr2721252lfp.54.1686548377591; Sun, 11 Jun 2023 22:39:37 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:37 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 14/18] ARM: dts: qcom: apq8064: add simple CPUFreq support Date: Mon, 12 Jun 2023 08:39:18 +0300 Message-Id: <20230612053922.3284394-15-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Declare CPU frequency-scaling properties. Each CPU has its own clock, how all CPUs have the same OPP table. Voltage scaling is not (yet) enabled with this patch. It will be enabled later. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 169 ++++++++++++++++++++++++++++ 1 file changed, 169 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 1eb6d752ebae..4ef13f3d702b 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -2,6 +2,7 @@ /dts-v1/; #include +#include #include #include #include @@ -45,6 +46,12 @@ CPU0: cpu@0 { qcom,acc = <&acc0>; qcom,saw = <&saw0>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_0>; + clock-names = "cpu"; + clock-latency = <100000>; + interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU1: cpu@1 { @@ -56,6 +63,12 @@ CPU1: cpu@1 { qcom,acc = <&acc1>; qcom,saw = <&saw1>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_1>; + clock-names = "cpu"; + clock-latency = <100000>; + interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU2: cpu@2 { @@ -67,6 +80,12 @@ CPU2: cpu@2 { qcom,acc = <&acc2>; qcom,saw = <&saw2>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_2>; + clock-names = "cpu"; + clock-latency = <100000>; + interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; CPU3: cpu@3 { @@ -78,6 +97,12 @@ CPU3: cpu@3 { qcom,acc = <&acc3>; qcom,saw = <&saw3>; cpu-idle-states = <&CPU_SPC>; + clocks = <&kraitcc KRAIT_CPU_3>; + clock-names = "cpu"; + clock-latency = <100000>; + interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>; + operating-points-v2 = <&cpu_opp_table>; + #cooling-cells = <2>; }; L2: l2-cache { @@ -97,6 +122,121 @@ CPU_SPC: spc { }; }; + cpu_opp_table: opp-table-cpu { + compatible = "operating-points-v2-krait-cpu"; + nvmem-cells = <&speedbin_efuse>; + + /* + * Voltage thresholds are + */ + opp-384000000 { + opp-hz = /bits/ 64 <384000000>; + opp-peak-kBps = <384000>; + opp-supported-hw = <0x4007>; + /* + * higher latency as it requires switching between + * clock sources + */ + clock-latency-ns = <244144>; + }; + + opp-486000000 { + opp-hz = /bits/ 64 <486000000>; + opp-peak-kBps = <648000>; + opp-supported-hw = <0x4007>; + }; + + opp-594000000 { + opp-hz = /bits/ 64 <594000000>; + opp-peak-kBps = <648000>; + opp-supported-hw = <0x4007>; + }; + + opp-702000000 { + opp-hz = /bits/ 64 <702000000>; + opp-peak-kBps = <648000>; + opp-supported-hw = <0x4007>; + }; + + opp-810000000 { + opp-hz = /bits/ 64 <810000000>; + opp-peak-kBps = <648000>; + opp-supported-hw = <0x4007>; + }; + + opp-918000000 { + opp-hz = /bits/ 64 <918000000>; + opp-peak-kBps = <648000>; + opp-supported-hw = <0x4007>; + }; + + opp-1026000000 { + opp-hz = /bits/ 64 <1026000000>; + opp-peak-kBps = <648000>; + opp-supported-hw = <0x4007>; + }; + + opp-1134000000 { + opp-hz = /bits/ 64 <1134000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x4007>; + }; + + opp-1242000000 { + opp-hz = /bits/ 64 <1242000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x4007>; + }; + + opp-1350000000 { + opp-hz = /bits/ 64 <1350000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x4007>; + }; + + opp-1458000000 { + opp-hz = /bits/ 64 <1458000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x4007>; + }; + + opp-1512000000 { + opp-hz = /bits/ 64 <1512000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x4001>; + }; + + opp-1566000000 { + opp-hz = /bits/ 64 <1566000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x06>; + }; + + opp-1674000000 { + opp-hz = /bits/ 64 <1674000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x06>; + }; + + opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x02>; + }; + + opp-1782000000 { + opp-hz = /bits/ 64 <1782000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x04>; + }; + + opp-1890000000 { + opp-hz = /bits/ 64 <1890000000>; + opp-peak-kBps = <1134000>; + opp-supported-hw = <0x04>; + }; + }; + memory@0 { device_type = "memory"; reg = <0x0 0x0>; @@ -213,6 +353,32 @@ sleep_clk: sleep_clk { }; }; + kraitcc: clock-controller { + compatible = "qcom,krait-cc-v1"; + clocks = <&gcc PLL9>, /* hfpll0 */ + <&gcc PLL10>, /* hfpll1 */ + <&gcc PLL16>, /* hfpll2 */ + <&gcc PLL17>, /* hfpll3 */ + <&gcc PLL12>, /* hfpll_l2 */ + <&acc0>, + <&acc1>, + <&acc2>, + <&acc3>, + <&l2cc>; + clock-names = "hfpll0", + "hfpll1", + "hfpll2", + "hfpll3", + "hfpll_l2", + "acpu0_aux", + "acpu1_aux", + "acpu2_aux", + "acpu3_aux", + "acpu_l2_aux"; + #clock-cells = <1>; + #interconnect-cells = <1>; + }; + sfpb_mutex: hwmutex { compatible = "qcom,sfpb-mutex"; syscon = <&sfpb_wrapper_mutex 0x604 0x4>; @@ -834,6 +1000,9 @@ qfprom: qfprom@700000 { #address-cells = <1>; #size-cells = <1>; ranges; + speedbin_efuse: speedbin@c0 { + reg = <0x0c0 0x4>; + }; tsens_calib: calib@404 { reg = <0x404 0x10>; }; From patchwork Mon Jun 12 05:39:19 2023 Content-Type: text/plain; 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:38 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 15/18] ARM: dts: qcom: apq8064: provide voltage scaling tables Date: Mon, 12 Jun 2023 08:39:19 +0300 Message-Id: <20230612053922.3284394-16-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org APQ8064 has 4 speed bins, each of them having from 4 to 6 categorization kinds. Provide tables necessary to handle voltage scaling on this SoC. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 1017 +++++++++++++++++++++++++++ 1 file changed, 1017 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 4ef13f3d702b..f35853b59544 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -49,6 +49,9 @@ CPU0: cpu@0 { clocks = <&kraitcc KRAIT_CPU_0>; clock-names = "cpu"; clock-latency = <100000>; + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; + vdd-core-supply = <&saw0_vreg>; interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -66,6 +69,9 @@ CPU1: cpu@1 { clocks = <&kraitcc KRAIT_CPU_1>; clock-names = "cpu"; clock-latency = <100000>; + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; + vdd-core-supply = <&saw1_vreg>; interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -83,6 +89,9 @@ CPU2: cpu@2 { clocks = <&kraitcc KRAIT_CPU_2>; clock-names = "cpu"; clock-latency = <100000>; + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; + vdd-core-supply = <&saw2_vreg>; interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -100,6 +109,9 @@ CPU3: cpu@3 { clocks = <&kraitcc KRAIT_CPU_3>; clock-names = "cpu"; clock-latency = <100000>; + vdd-mem-supply = <&pm8921_l24>; + vdd-dig-supply = <&pm8921_s3>; + vdd-core-supply = <&saw3_vreg>; interconnects = <&kraitcc MASTER_KRAIT_L2 &kraitcc SLAVE_KRAIT_L2>; operating-points-v2 = <&cpu_opp_table>; #cooling-cells = <2>; @@ -132,6 +144,81 @@ cpu_opp_table: opp-table-cpu { opp-384000000 { opp-hz = /bits/ 64 <384000000>; opp-peak-kBps = <384000>; + opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <950000 950000 975000>; + opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <875000 850000 900000>; + opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <875000 850000 900000>; + opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <950000 950000 975000>; + opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <950000 950000 975000>; + opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>, + <950000 950000 1150000>, + <900000 875000 925000>; opp-supported-hw = <0x4007>; /* * higher latency as it requires switching between @@ -143,96 +230,1026 @@ opp-384000000 { opp-486000000 { opp-hz = /bits/ 64 <486000000>; opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <975000 975000 1000000>; + opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 950000 975000>; + opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 950000 975000>; + opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <875000 875000 875000>; opp-supported-hw = <0x4007>; }; opp-594000000 { opp-hz = /bits/ 64 <594000000>; opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1000000 1000000 1025000>; + opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 950000 975000>; + opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 950000 975000>; + opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; opp-supported-hw = <0x4007>; }; opp-702000000 { opp-hz = /bits/ 64 <702000000>; opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1025000 1025000 1050000>; + opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <962500 962500 987500>; + opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <987500 962500 1012500>; + opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 950000 975000>; + opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 925000 925000>; + opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <962500 962500 987500>; + opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <987500 962500 1012500>; + opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; + opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <875000 875000 875000>; + opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 875000 925000>; opp-supported-hw = <0x4007>; }; opp-810000000 { opp-hz = /bits/ 64 <810000000>; opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1075000 1075000 1100000>; + opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1050000 1025000 1075000>; + opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <987500 962500 1012500>; + opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1000000 1000000 1025000>; + opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <962500 937500 987500>; + opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <912500 887500 937500>; + opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <912500 887500 937500>; + opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <912500 887500 937500>; + opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <962500 962500 987500>; + opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <937500 937500 937500>; + opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <937500 912500 962500>; + opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <912500 887500 937500>; + opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <912500 887500 937500>; + opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <912500 887500 937500>; + opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1000000 1000000 1025000>; + opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <962500 937500 987500>; + opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <912500 887500 937500>; + opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <887500 887500 887500>; + opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <912500 887500 937500>; opp-supported-hw = <0x4007>; }; opp-918000000 { opp-hz = /bits/ 64 <918000000>; opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1100000 1100000 1125000>; + opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1075000 1050000 1100000>; + opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1025000 1000000 1050000>; + opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1025000 1025000 1050000>; + opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <975000 975000 1000000>; + opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 950000 950000>; + opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <937500 912500 962500>; + opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1025000 1025000 1050000>; + opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; + opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <900000 900000 900000>; + opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 900000 950000>; opp-supported-hw = <0x4007>; }; opp-1026000000 { opp-hz = /bits/ 64 <1026000000>; opp-peak-kBps = <648000>; + opp-microvolt-speed0-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1125000 1125000 1150000>; + opp-microvolt-speed0-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1100000 1075000 1125000>; + opp-microvolt-speed0-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1050000 1025000 1075000>; + opp-microvolt-speed0-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1037500 1037500 1062500>; + opp-microvolt-speed1-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1037500 1012500 1062500>; + opp-microvolt-speed1-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed1-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed1-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed1-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed1-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed2-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1000000 1000000 1025000>; + opp-microvolt-speed2-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <975000 975000 975000>; + opp-microvolt-speed2-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed2-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <962500 937500 987500>; + opp-microvolt-speed2-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed2-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed2-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed14-pvs0 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1037500 1037500 1062500>; + opp-microvolt-speed14-pvs1 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1037500 1012500 1062500>; + opp-microvolt-speed14-pvs2 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed14-pvs3 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed14-pvs4 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; + opp-microvolt-speed14-pvs5 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <925000 925000 925000>; + opp-microvolt-speed14-pvs6 = <1050000 1050000 1150000>, + <1050000 1050000 1150000>, + <950000 925000 975000>; opp-supported-hw = <0x4007>; }; opp-1134000000 { opp-hz = /bits/ 64 <1134000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1175000 1175000 1200000>; + opp-microvolt-speed0-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1150000 1125000 1175000>; + opp-microvolt-speed0-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1100000 1075000 1125000>; + opp-microvolt-speed0-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1075000 1050000 1100000>; + opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1075000 1075000 1100000>; + opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <962500 937500 987500>; + opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <962500 937500 987500>; + opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1025000 1025000 1050000>; + opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1000000 1000000 1000000>; + opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <987500 962500 1012500>; + opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <962500 937500 987500>; + opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <962500 937500 987500>; + opp-microvolt-speed14-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1075000 1075000 1100000>; + opp-microvolt-speed14-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1062500 1037500 1087500>; + opp-microvolt-speed14-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed14-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed14-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <937500 937500 937500>; + opp-microvolt-speed14-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <962500 937500 987500>; opp-supported-hw = <0x4007>; }; opp-1242000000 { opp-hz = /bits/ 64 <1242000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1200000 1200000 1225000>; + opp-microvolt-speed0-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1175000 1150000 1200000>; + opp-microvolt-speed0-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1125000 1100000 1150000>; + opp-microvolt-speed0-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1087500 1087500 1112500>; + opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1075000 1050000 1100000>; + opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1037500 1012500 1062500>; + opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1012500 987500 1037500>; + opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <987500 962500 1012500>; + opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1037500 1037500 1062500>; + opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1012500 1012500 1012500>; + opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1012500 987500 1037500>; + opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <987500 962500 1012500>; + opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <975000 950000 1000000>; + opp-microvolt-speed14-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1087500 1087500 1112500>; + opp-microvolt-speed14-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1075000 1050000 1100000>; + opp-microvolt-speed14-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1037500 1012500 1062500>; + opp-microvolt-speed14-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1012500 987500 1037500>; + opp-microvolt-speed14-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <987500 962500 1012500>; + opp-microvolt-speed14-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <950000 950000 950000>; + opp-microvolt-speed14-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <975000 950000 1000000>; opp-supported-hw = <0x4007>; }; opp-1350000000 { opp-hz = /bits/ 64 <1350000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1225000 1225000 1250000>; + opp-microvolt-speed0-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1200000 1175000 1225000>; + opp-microvolt-speed0-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1150000 1125000 1175000>; + opp-microvolt-speed0-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1125000 1125000 1150000>; + opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1112500 1087500 1137500>; + opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <987500 962500 1012500>; + opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <987500 962500 1012500>; + opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1062500 1062500 1087500>; + opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1037500 1037500 1037500>; + opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1037500 1012500 1062500>; + opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1025000 1000000 1050000>; + opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <987500 962500 1012500>; + opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <987500 962500 1012500>; + opp-microvolt-speed14-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1125000 1125000 1150000>; + opp-microvolt-speed14-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1112500 1087500 1137500>; + opp-microvolt-speed14-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1062500 1037500 1087500>; + opp-microvolt-speed14-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed14-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <962500 962500 962500>; + opp-microvolt-speed14-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <987500 962500 1012500>; opp-supported-hw = <0x4007>; }; opp-1458000000 { opp-hz = /bits/ 64 <1458000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1237500 1237500 1262500>; + opp-microvolt-speed0-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1212500 1187500 1237500>; + opp-microvolt-speed0-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1162500 1137500 1187500>; + opp-microvolt-speed0-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1137500 1112500 1162500>; + opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1150000 1150000 1175000>; + opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1137500 1112500 1162500>; + opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1025000 1000000 1050000>; + opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1012500 987500 1037500>; + opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1100000 1100000 1125000>; + opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1075000 1075000 1075000>; + opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1075000 1050000 1100000>; + opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1050000 1025000 1075000>; + opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1025000 1000000 1050000>; + opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1012500 987500 1037500>; + opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1000000 975000 1025000>; + opp-microvolt-speed14-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1150000 1150000 1175000>; + opp-microvolt-speed14-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1137500 1112500 1162500>; + opp-microvolt-speed14-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1100000 1075000 1125000>; + opp-microvolt-speed14-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1062500 1037500 1087500>; + opp-microvolt-speed14-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1025000 1000000 1050000>; + opp-microvolt-speed14-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <987500 987500 987500>; + opp-microvolt-speed14-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1000000 975000 1025000>; opp-supported-hw = <0x4007>; }; opp-1512000000 { opp-hz = /bits/ 64 <1512000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed0-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1250000 1250000 1275000>; + opp-microvolt-speed0-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1225000 1200000 1250000>; + opp-microvolt-speed0-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1175000 1150000 1200000>; + opp-microvolt-speed0-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1150000 1125000 1175000>; + opp-microvolt-speed14-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1162500 1162500 1187500>; + opp-microvolt-speed14-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1150000 1125000 1175000>; + opp-microvolt-speed14-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1112500 1087500 1137500>; + opp-microvolt-speed14-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1075000 1050000 1100000>; + opp-microvolt-speed14-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1037500 1012500 1062500>; + opp-microvolt-speed14-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1000000 1000000 1000000>; + opp-microvolt-speed14-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1012500 987500 1037500>; opp-supported-hw = <0x4001>; }; opp-1566000000 { opp-hz = /bits/ 64 <1566000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1175000 1175000 1200000>; + opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1175000 1150000 1200000>; + opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1087500 1062500 1112500>; + opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1062500 1037500 1087500>; + opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1037500 1012500 1062500>; + opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1025000 1000000 1050000>; + opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1125000 1125000 1150000>; + opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1100000 1100000 1100000>; + opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1100000 1075000 1125000>; + opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1075000 1050000 1100000>; + opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1062500 1037500 1087500>; + opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1037500 1012500 1062500>; + opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1025000 1000000 1050000>; opp-supported-hw = <0x06>; }; opp-1674000000 { opp-hz = /bits/ 64 <1674000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1225000 1225000 1250000>; + opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1212500 1187500 1237500>; + opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1162500 1137500 1187500>; + opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1075000 1050000 1100000>; + opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1050000 1025000 1075000>; + opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1175000 1175000 1200000>; + opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1137500 1137500 1137500>; + opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1137500 1112500 1162500>; + opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1112500 1087500 1137500>; + opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1100000 1075000 1125000>; + opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1075000 1050000 1100000>; + opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1050000 1025000 1075000>; opp-supported-hw = <0x06>; }; opp-1728000000 { opp-hz = /bits/ 64 <1728000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed1-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1250000 1250000 1275000>; + opp-microvolt-speed1-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1225000 1200000 1250000>; + opp-microvolt-speed1-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1187500 1162500 1212500>; + opp-microvolt-speed1-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1150000 1125000 1175000>; + opp-microvolt-speed1-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1125000 1100000 1150000>; + opp-microvolt-speed1-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1100000 1075000 1125000>; + opp-microvolt-speed1-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1075000 1050000 1100000>; opp-supported-hw = <0x02>; }; opp-1782000000 { opp-hz = /bits/ 64 <1782000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1225000 1225000 1250000>; + opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1187500 1187500 1187500>; + opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1187500 1162500 1212500>; + opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1162500 1137500 1187500>; + opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1137500 1112500 1162500>; + opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1112500 1087500 1137500>; + opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1087500 1062500 1112500>; opp-supported-hw = <0x04>; }; opp-1890000000 { opp-hz = /bits/ 64 <1890000000>; opp-peak-kBps = <1134000>; + opp-microvolt-speed2-pvs0 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1287500 1287500 1312500>; + opp-microvolt-speed2-pvs1 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1250000 1250000 1250000>; + opp-microvolt-speed2-pvs2 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1237500 1212500 1262500>; + opp-microvolt-speed2-pvs3 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1200000 1175000 1225000>; + opp-microvolt-speed2-pvs4 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1175000 1150000 1200000>; + opp-microvolt-speed2-pvs5 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1150000 1125000 1175000>; + opp-microvolt-speed2-pvs6 = <1150000 1150000 1150000>, + <1150000 1150000 1150000>, + <1125000 1100000 1150000>; opp-supported-hw = <0x04>; }; }; From patchwork Mon Jun 12 05:39:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691890 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19EB5C7EE37 for ; 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:38 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 16/18] ARM: dts: qcom: apq8064: enable passive CPU cooling Date: Mon, 12 Jun 2023 08:39:20 +0300 Message-Id: <20230612053922.3284394-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Wire up CPUs and thermal trip points to save the SoC from overheating by lowering the CPU frequency. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index f35853b59544..82b381b66cfb 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { #address-cells = <1>; #size-cells = <1>; @@ -1279,6 +1280,13 @@ cpu_crit0: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { @@ -1300,6 +1308,13 @@ cpu_crit1: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { @@ -1321,6 +1336,13 @@ cpu_crit2: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert2>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { @@ -1342,6 +1364,13 @@ cpu_crit3: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert3>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; From patchwork Mon Jun 12 05:39:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691889 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 736A4C7EE25 for ; Mon, 12 Jun 2023 05:40:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236167AbjFLFkT (ORCPT ); Mon, 12 Jun 2023 01:40:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40680 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235986AbjFLFjz (ORCPT ); Mon, 12 Jun 2023 01:39:55 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AD444172D for ; Sun, 11 Jun 2023 22:39:45 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-4f004cc54f4so4511165e87.3 for ; Sun, 11 Jun 2023 22:39:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548380; x=1689140380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2COHoS0iCE7QlZQECIs2qMw+k4Ux9D95krl1smHPEhw=; b=vQtQ+YLvQaTeDMhfogpkzaIizdumMXgl+SwKny0ktMYFLMvzj5QzSSoHCBZgwdMhxe Pzg8JZjmdDDa28Mvp723hEtP41NXATAzox+CURgRFTRgRsTaaZDYKQ1rTC7soqgmJV7w ovKdjHvXwI1MQo/wxBQtIGI9juYnCPvDcJMrNP87DlwhuTbBkjJOrE6jabGUo6xf0aHI WDHFmJ+IrUMM7iNaMu7FFn/M86EnWnCQ1WG122UZdq01E2+8kUjLlhKa1c8veTDsCTnI VpdJD+merSWMi5vrJIpkegtGSWsJwc5RnGrkAwgHE35EGVbcqzzkAlqP+PAo4mjR02oc VeIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548380; x=1689140380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2COHoS0iCE7QlZQECIs2qMw+k4Ux9D95krl1smHPEhw=; b=TpV0gXUrq0DaQJJUJ2veaghctqLtixpZeRqH1X6/HZFfTzx+/XD51tHO/RzC2dUEkB KqwEqPoOM0rRq3SP6bz+PBdAZoXeDY6BYGSWaGKLDDxm3/ubTpz6AZcCo6WbQarS0Zma D5Yh1q4VD7bkf+qoiMQKzsjCczDJDy+4ooJjpQsHfoKAq1C11FGq+zAcUVRNbu0/WdSi jhzxkpiAAq5iOq3zegQ9bNZQsQlLgwypC9AGfowL4Khiz1hyLyLqTUmwjv/TG17d3K0p iUmec5MgPhNvHEw707aPM8z31Rz6r1xFJkJMRofjLd4m8R+boh/IoPn7H/o+0JQdIEBP prpg== X-Gm-Message-State: AC+VfDwOkKiNGu1U8a9CoiGcBP1Q1owVyZfhFwc8qkBaF8dp3vWV7nbR d71OUnbvoMuR7cbFmNL7oe9CS8kAH043ECurdTw= X-Google-Smtp-Source: ACHHUZ7jZf3YWi3Bhcxzz1FPeGdaumoZrreHjOvXVIwrZeVhijRftpqHNrSzCPUKmYTkPYHQrW2K2A== X-Received: by 2002:a05:6512:32b7:b0:4f4:e3fa:73d8 with SMTP id q23-20020a05651232b700b004f4e3fa73d8mr3408928lfe.62.1686548380316; Sun, 11 Jun 2023 22:39:40 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:39 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 17/18] ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators Date: Mon, 12 Jun 2023 08:39:21 +0300 Message-Id: <20230612053922.3284394-18-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add additional constraints to the CPUfreq-related regulators, it is better be safe than sorry there. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index c57c27cd8a20..9f5d72727356 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -218,9 +218,9 @@ s1 { bias-pull-down; }; - /* msm otg HSUSB_VDDCX */ + /* msm otg HSUSB_VDDCX and VDD_DIG */ s3 { - regulator-min-microvolt = <500000>; + regulator-min-microvolt = <950000>; regulator-max-microvolt = <1150000>; qcom,switch-mode-frequency = <4800000>; }; @@ -301,6 +301,12 @@ l23 { bias-pull-down; }; + /* VDD_MEM */ + l24 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + }; + /* * tabla2x-slim-CDC_VDDA_A_1P2V * tabla2x-slim-VDDD_CDC_D @@ -329,8 +335,12 @@ lvs6 { /* * mipi_dsi.1-dsi1_vddio * pil_riva-pll_vdd + * HFPLL regulator */ lvs7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; bias-pull-down; }; }; From patchwork Mon Jun 12 05:39:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 692475 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9EFD1C8300C for ; Mon, 12 Jun 2023 05:40:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236102AbjFLFkb (ORCPT ); Mon, 12 Jun 2023 01:40:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40756 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236127AbjFLFkA (ORCPT ); Mon, 12 Jun 2023 01:40:00 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 639F81986 for ; Sun, 11 Jun 2023 22:39:51 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-4f655293a38so4112689e87.0 for ; Sun, 11 Jun 2023 22:39:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548381; x=1689140381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w3KfhKRM2Bpo1zmKLCtOCcwF4OmfBaYvC1ZALMgeIRg=; b=blRhZQakA5n+RjIiR5NEcHL6LC6qslAhKpdeuaIHkvHQHfK6rIxzbBvzdRLu0qfWri OlCCQKAaJLC48lhY5LKbcmD3PAcA1Xjs5MFh913/Nu5NUTY7Cd+E7YUnvMzygVxLy3HI lw0tAtNXQiZjlziW5WJZsABt+WJrSAda2DlBPYCe83hZH/amcIdKnPZohdMrwqAVsj2W Ne8OSXV3sOqgtNQ8jkX6/z62UUVucMiNdTvI3NClcd5QPrB0He430+yeLN+fbH007zc0 ZdGrQMpb5r8f5re/FK17rhtUBoEQGX/Exa2haOZhXDodwDTGmYpf3dcm+v7hNoB2Cfj9 GvRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548381; x=1689140381; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w3KfhKRM2Bpo1zmKLCtOCcwF4OmfBaYvC1ZALMgeIRg=; b=MRM8RcPEixkCGfrjwUkf8+D5W+mf1ZY3V/bkK3GBdgz322dTXDqVm5ngqFARgjgSYe DmUx6s00As2mfy5lF/J1gziqwi+9aRLq044lK6iy6p16AFDLXMLsu7htjwyeOkXeYJBt qHDMAn05baUXJXddSv634r0oKWVg1p67TZSbKWqBgekYYEejG2o5VB0teckiJjcVIHcE fLQGPtN/daIXTwbXYyH5u7YMOiBO58EPqaMfp5NnuhQl6fjjEMDat6fwzQ/Jev2PgDZe 3PX+EhuqU2ATUkVy+/bJIhcxafgxEZXlfzK5ihTtsPqGgUAEjbSDIh9V2JKw2+6byiM9 Q/JQ== X-Gm-Message-State: AC+VfDwFs9jWKyYpg+M4FVRVvoevZxaPrc6zl+TJu1iMhlQDBVD8K9SV ILQVTfeSiB2FDirtx+X83ZxTAaiILtRjFsrp+Yw= X-Google-Smtp-Source: ACHHUZ7dBv7Ysw90aWXg/I3haPn5OIJokEnhwINFdBVz7hcuwd+ValiA2gmIiVcr/UwxlLUo1Pj4Zw== X-Received: by 2002:a19:5059:0:b0:4e9:59cd:416c with SMTP id z25-20020a195059000000b004e959cd416cmr3083458lfj.0.1686548381226; Sun, 11 Jun 2023 22:39:41 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:40 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 18/18] ARM: dts: qcom: apq8064-ifc6410: constraint cpufreq regulators Date: Mon, 12 Jun 2023 08:39:22 +0300 Message-Id: <20230612053922.3284394-19-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-pm@vger.kernel.org Add additional constraints to the CPUfreq-related regulators, it is better be safe than sorry there. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064-ifc6410.dts | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts index 96307550523a..ad3cd45362df 100644 --- a/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts +++ b/arch/arm/boot/dts/qcom-apq8064-ifc6410.dts @@ -215,8 +215,8 @@ s1 { }; s3 { - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1400000>; + regulator-min-microvolt = <950000>; + regulator-max-microvolt = <1150000>; qcom,switch-mode-frequency = <4800000>; }; @@ -262,6 +262,12 @@ l23 { bias-pull-down; }; + l24 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + bias-pull-down; + }; + lvs1 { bias-pull-down; }; @@ -269,6 +275,14 @@ lvs1 { lvs6 { bias-pull-down; }; + + /* HFPLL regulator */ + lvs7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; }; };