From patchwork Mon Jun 12 05:39:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691756 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 50D6EC83005 for ; Mon, 12 Jun 2023 05:39:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234848AbjFLFja (ORCPT ); Mon, 12 Jun 2023 01:39:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234867AbjFLFj1 (ORCPT ); Mon, 12 Jun 2023 01:39:27 -0400 Received: from mail-lf1-x12c.google.com (mail-lf1-x12c.google.com [IPv6:2a00:1450:4864:20::12c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 410E3E68 for ; Sun, 11 Jun 2023 22:39:26 -0700 (PDT) Received: by mail-lf1-x12c.google.com with SMTP id 2adb3069b0e04-4f629ccb8ebso4418565e87.1 for ; Sun, 11 Jun 2023 22:39:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548364; x=1689140364; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=K3XrlP3qxGGbuMeyHpbUTgn9VuSrjhayHzqHOlF2VRg=; b=cEMdGuL89H/fBK/hrDnEwKkZXZoJ0OUmsU+EQ/gwvB/yBFhGsoLuQrtxhGect2whhV TyMAeGFLPBdr1PC8ulLzzWPIb/jqu0lC+ZpV+/CqijhBFPqpCWZTQDLXji1UOojKsCcL vtEzDKdT+MDUm7pFuEOru2IE4keXIAVv0Zc9u0A0AIxdwnxSdhJjDkbtY+phXOSenYYX 9gdGouv88NjsyYBNosNOoCZ7z+7UyX3qQn38Y0YfQuYuF+z2UA+9CzIbMjmpaMzTU6zk hDnwjvB8FUEECO3+dL57pf9EkhP6KRIPKeWnxdibL1BAU5ofNFC0D/nLMXJPcflo0K3m n0+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548364; x=1689140364; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=K3XrlP3qxGGbuMeyHpbUTgn9VuSrjhayHzqHOlF2VRg=; b=TPe3ztYaB4IC2RG8fM64Cvph+kQBnThzZNUqENPYM+wb6vh4OCYLPHJu7NhbzKbFP5 9zgcdnemN0xTk3IWPHZyUaU2ufqrjwT4F01kuMkrAYBGbvF6rMU8cCUH+n104X33yBf5 GUD0f+z+SsZ299EBMg86a2j/Ruf1oASvlc4BDO9ueYzBoE/QiJdT0WS74EqJuvk8Z3jh b/Cy/4lKjB53xxenHU9p6Sj6LmnTNzOYLrsFAyIJyccbMRhM13H6rxERn0bWMBeNooHL 0WTKYusd4vwNbACLHwFt1voulBqIhHBEeYhCT1QhbeAD7Cuoy1/cei7qV7ZqKFuAYiu5 WO3A== X-Gm-Message-State: AC+VfDzhKZvkSaKJDSlk9ORk0M2nNA1QEQWBoExF8izpnB6z4Izj3Sv0 dqj6qiQTHfLGUuZHBx/VjtDXQrWh+V/tc3bDjcs= X-Google-Smtp-Source: ACHHUZ5Rt7kSjxAgZ2EuBEP9nABNPmD18A8ONgsSEqAa4+c/iDsem3zIxfurYPgYBJ2RN93F7jHrhQ== X-Received: by 2002:a19:2d58:0:b0:4f6:2a63:d3fc with SMTP id t24-20020a192d58000000b004f62a63d3fcmr2882685lft.32.1686548364629; Sun, 11 Jun 2023 22:39:24 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:24 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 01/18] dt-bindings: opp: opp-v2-kryo-cpu: support Qualcomm Krait SoCs Date: Mon, 12 Jun 2023 08:39:05 +0300 Message-Id: <20230612053922.3284394-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Exted the opp-v2-kryo-cpu.yaml to support defining OPP tables for the previous generation of Qualcomm CPUs, 32-bit Krait-based platforms. It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node for the Krait cores. Add support for the Krait-specific 'operating-points-v2-krait-cpu' compatibility string and the relevant opp-microvolt subclasses properties. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/opp/opp-v2-kryo-cpu.yaml | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml index bbbad31ae4ca..93ec778bf333 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-kryo-cpu.yaml @@ -26,7 +26,9 @@ description: | properties: compatible: - const: operating-points-v2-kryo-cpu + enum: + - operating-points-v2-krait-cpu + - operating-points-v2-kryo-cpu nvmem-cells: description: | @@ -63,14 +65,15 @@ patternProperties: 5: MSM8996SG, speedbin 1 6: MSM8996SG, speedbin 2 7-31: unused - enum: [0x1, 0x2, 0x3, 0x4, 0x5, 0x6, 0x7, - 0x9, 0xd, 0xe, 0xf, - 0x10, 0x20, 0x30, 0x70] + $ref: /schemas/types.yaml#/definitions/uint32 clock-latency-ns: true required-opps: true + patternProperties: + '^opp-microvolt-speed[0-9]+-pvs[0-9]+$': true + required: - opp-hz From patchwork Mon Jun 12 05:39:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691755 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 193AAC7EE25 for ; Mon, 12 Jun 2023 05:39:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235349AbjFLFjf (ORCPT ); Mon, 12 Jun 2023 01:39:35 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40138 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234802AbjFLFja (ORCPT ); Mon, 12 Jun 2023 01:39:30 -0400 Received: from mail-lf1-x136.google.com (mail-lf1-x136.google.com [IPv6:2a00:1450:4864:20::136]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FA22E7A for ; Sun, 11 Jun 2023 22:39:28 -0700 (PDT) Received: by mail-lf1-x136.google.com with SMTP id 2adb3069b0e04-4f620583bc2so4395743e87.1 for ; Sun, 11 Jun 2023 22:39:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548367; x=1689140367; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dMOlASi6Vn7FuOtPlAWq0wcXxa6OXt0yvMgulLt9t1o=; b=IV8FDM+6e4Z39+oOM8sjRpG3VvvvmAOZ8gMDk7zdBAmjnB+SsPmUQmCLhFnguUgHro 76uQmXPGHiJgqYlVjGZcGw+qIui3DiyMFz+08rMwB3DddQRB6KufN0UCj6LmHbVmBso7 mqhiX/UqO8nts1x7HK4S1hdK6hjgrMD6mVUEyzxojJfmOzaSU7X0iqtLCg3IV0yGek44 o09F9PRowfOWNWKEq6ri0L5D35Xpe/UYdfwt6TrifQY0IvULhrCq1DwEA8J8b1zXrrmJ +1eK+E6gzmaY+NKIXyvvd3CaXND36uyS+ubOwGbUwH3BAKt2RrwboDu6zpLWSF4dHe1A 9cFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548367; x=1689140367; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dMOlASi6Vn7FuOtPlAWq0wcXxa6OXt0yvMgulLt9t1o=; b=N5BA3YYKEzt8efYsjrv0N/IF1EvtvHZcu0+gYhaOGgBUkpd47qs74++bYPhvnQeVY1 RDXhTcLNO3XExYCHNxcfquNLvrOtLmkGFxub6stVqvGO1rti1u/eHgTQzDaNUdZaIWDE 9K30KZXvXXeFJRJnr3iPD/9UiRnq8EFKb6OBEBm+JzuUXq90YkXdjEO+2CBsoDKYPI40 V7RSKAvwmD4Asd67dp+63hWmtPf+bmvhYHWuzYTJvtsbMq2EmewWItULwAVTby8J2ewd qZKXIH2T6Apf2H8oOR+j1VqmVUQnq+DJG6erc2Ibii1nuUJceRtyHngfQTToRt6YaP1C aTxw== X-Gm-Message-State: AC+VfDz/uKJANZIqiAVvaQjR2GCje1A7ZI0GoxyOkA+yukNgYkq4TvfE faoftAMcnjusqkEojYci9XMu5w== X-Google-Smtp-Source: ACHHUZ7H3956rhfTawL9EpVswr7uTvrdfyXBUKNseJKKQL3/JBkBOF8qACWgtiDyHOJyr9DSD07jrw== X-Received: by 2002:a19:670d:0:b0:4ed:ca3b:40f0 with SMTP id b13-20020a19670d000000b004edca3b40f0mr3389008lfc.9.1686548366927; Sun, 11 Jun 2023 22:39:26 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:26 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 03/18] dt-bindings: soc: qcom: qcom,saw2: define optional regulator node Date: Mon, 12 Jun 2023 08:39:07 +0300 Message-Id: <20230612053922.3284394-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SAW2 device can optionally provide a voltage regulator supplying the CPU core, cluster or L2 cache. Describe it in the device bindings. Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/soc/qcom/qcom,saw2.yaml | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml index a016242367b9..b809a9cc0916 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,saw2.yaml @@ -47,6 +47,10 @@ properties: - description: Base address and size of the alias register region minItems: 1 + regulator: + $ref: /schemas/regulator/regulator.yaml# + description: corresponding core, cluster or cache voltage supply regulator + required: - compatible - reg @@ -92,4 +96,17 @@ examples: reg = <0x17912000 0x1000>; }; + - | + /* + * Example 3: SAW2 with the bundled regulator definition. + */ + power-manager@2089000 { + compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; + reg = <0x02089000 0x1000>, <0x02009000 0x1000>; + + regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; + }; ... 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:28 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 05/18] clk: qcom: krait-cc: rewrite driver to use clk_hw instead of clk Date: Mon, 12 Jun 2023 08:39:09 +0300 Message-Id: <20230612053922.3284394-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The krait-cc driver still uses struct clk internally. Rewrite it to allocate and register struct clk_hw instead. Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/krait-cc.c | 122 ++++++++++++++++-------------------- 1 file changed, 54 insertions(+), 68 deletions(-) diff --git a/drivers/clk/qcom/krait-cc.c b/drivers/clk/qcom/krait-cc.c index 410ae8390f1c..2ce38024dc0d 100644 --- a/drivers/clk/qcom/krait-cc.c +++ b/drivers/clk/qcom/krait-cc.c @@ -235,7 +235,7 @@ krait_add_pri_mux(struct device *dev, struct clk_hw *hfpll_div, struct clk_hw *s .parent_data = p_data, .num_parents = ARRAY_SIZE(p_data), .ops = &krait_mux_clk_ops, - .flags = CLK_SET_RATE_PARENT, + .flags = CLK_SET_RATE_PARENT | CLK_IS_CRITICAL, }; struct clk_hw *clk; char *hfpll_name; @@ -324,19 +324,6 @@ static struct clk_hw *krait_add_clks(struct device *dev, int id, bool unique_aux return pri_mux; } -static struct clk *krait_of_get(struct of_phandle_args *clkspec, void *data) -{ - unsigned int idx = clkspec->args[0]; - struct clk **clks = data; - - if (idx >= clks_max) { - pr_err("%s: invalid clock index %d\n", __func__, idx); - return ERR_PTR(-EINVAL); - } - - return clks[idx] ? : ERR_PTR(-ENODEV); -} - static const struct of_device_id krait_cc_match_table[] = { { .compatible = "qcom,krait-cc-v1", (void *)1UL }, { .compatible = "qcom,krait-cc-v2" }, @@ -344,60 +331,81 @@ static const struct of_device_id krait_cc_match_table[] = { }; MODULE_DEVICE_TABLE(of, krait_cc_match_table); +static int krait_clk_reinit(struct clk_hw *hw, int cpu) +{ + struct clk *clk; + unsigned long cur_rate, aux_rate; + char name[5]; /* CPUn */ + + if (cpu == -1) + strcpy(name, "L2"); + else + snprintf(name, sizeof(name), "CPU%d", cpu); + + clk = clk_hw_get_clk(hw, clk_hw_get_name(hw)); + if (IS_ERR(clk)) + return PTR_ERR(clk); + + aux_rate = 384000000; + + cur_rate = clk_get_rate(clk); + if (cur_rate < aux_rate) { + pr_info("%s @ Undefined rate %lu. Forcing new rate.\n", + name, cur_rate / 1000); + cur_rate = aux_rate; + } + + clk_set_rate(clk, aux_rate); + clk_set_rate(clk, 2); + clk_set_rate(clk, cur_rate); + pr_info("%s @ %lu KHz\n", name, clk_get_rate(clk) / 1000); + + clk_put(clk); + + return 0; +} + static int krait_cc_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; const struct of_device_id *id; - unsigned long cur_rate, aux_rate; int cpu; - struct clk_hw *mux, *l2_pri_mux; - struct clk *clk, **clks; + struct clk_hw *clk; + struct clk_hw_onecell_data *clks; id = of_match_device(krait_cc_match_table, dev); if (!id) return -ENODEV; /* Rate is 1 because 0 causes problems for __clk_mux_determine_rate */ - clk = clk_register_fixed_rate(dev, "qsb", NULL, 0, 1); + clk = clk_hw_register_fixed_rate(dev, "qsb", NULL, 0, 1); if (IS_ERR(clk)) return PTR_ERR(clk); if (!id->data) { - clk = clk_register_fixed_factor(dev, "acpu_aux", - "gpll0_vote", 0, 1, 2); + clk = clk_hw_register_fixed_factor(dev, "acpu_aux", "gpll0_vote", 0, 1, 2); if (IS_ERR(clk)) return PTR_ERR(clk); } /* Krait configurations have at most 4 CPUs and one L2 */ - clks = devm_kcalloc(dev, clks_max, sizeof(*clks), GFP_KERNEL); + clks = devm_kzalloc(dev, struct_size(clks, hws, clks_max), GFP_KERNEL); if (!clks) return -ENOMEM; + clks->num = clks_max; + for_each_possible_cpu(cpu) { - mux = krait_add_clks(dev, cpu, id->data); - if (IS_ERR(mux)) - return PTR_ERR(mux); - clks[cpu] = mux->clk; + clk = krait_add_clks(dev, cpu, id->data); + if (IS_ERR(clk)) + return PTR_ERR(clk); + clks->hws[cpu] = clk; } - l2_pri_mux = krait_add_clks(dev, -1, id->data); - if (IS_ERR(l2_pri_mux)) - return PTR_ERR(l2_pri_mux); - clks[l2_mux] = l2_pri_mux->clk; - - /* - * We don't want the CPU or L2 clocks to be turned off at late init - * if CPUFREQ or HOTPLUG configs are disabled. So, bump up the - * refcount of these clocks. Any cpufreq/hotplug manager can assume - * that the clocks have already been prepared and enabled by the time - * they take over. - */ - for_each_online_cpu(cpu) { - clk_prepare_enable(clks[l2_mux]); - WARN(clk_prepare_enable(clks[cpu]), - "Unable to turn on CPU%d clock", cpu); - } + clk = krait_add_clks(dev, -1, id->data); + if (IS_ERR(clk)) + return PTR_ERR(clk); + clks->hws[l2_mux] = clk; /* * Force reinit of HFPLLs and muxes to overwrite any potential @@ -410,33 +418,11 @@ static int krait_cc_probe(struct platform_device *pdev) * two different rates to force a HFPLL reinit under all * circumstances. */ - cur_rate = clk_get_rate(clks[l2_mux]); - aux_rate = 384000000; - if (cur_rate < aux_rate) { - pr_info("L2 @ Undefined rate. Forcing new rate.\n"); - cur_rate = aux_rate; - } - clk_set_rate(clks[l2_mux], aux_rate); - clk_set_rate(clks[l2_mux], 2); - clk_set_rate(clks[l2_mux], cur_rate); - pr_info("L2 @ %lu KHz\n", clk_get_rate(clks[l2_mux]) / 1000); - for_each_possible_cpu(cpu) { - clk = clks[cpu]; - cur_rate = clk_get_rate(clk); - if (cur_rate < aux_rate) { - pr_info("CPU%d @ Undefined rate. Forcing new rate.\n", cpu); - cur_rate = aux_rate; - } - - clk_set_rate(clk, aux_rate); - clk_set_rate(clk, 2); - clk_set_rate(clk, cur_rate); - pr_info("CPU%d @ %lu KHz\n", cpu, clk_get_rate(clk) / 1000); - } + krait_clk_reinit(clks->hws[l2_mux], -1); + for_each_possible_cpu(cpu) + krait_clk_reinit(clks->hws[cpu], cpu); - of_clk_add_provider(dev->of_node, krait_of_get, clks); - - return 0; + return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, clks); } static struct platform_driver krait_cc_driver = { From patchwork Mon Jun 12 05:39:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691753 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E4AEBC83005 for ; Mon, 12 Jun 2023 05:40:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236128AbjFLFkA (ORCPT ); Mon, 12 Jun 2023 01:40:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235719AbjFLFjf (ORCPT ); Mon, 12 Jun 2023 01:39:35 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DD42F10D0 for ; Sun, 11 Jun 2023 22:39:33 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-4f63ab1ac4aso4437988e87.0 for ; Sun, 11 Jun 2023 22:39:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548372; x=1689140372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/tfSMMNSy6Z3dTRBojoQkv78dxEs3QjtEnCrcqetfSI=; b=k3zZWbQ+mrX6ywklFiBilg2GTBEAOog51Qkh0SfDm3g3P0x6q940R5XH1Y/z/qMmR0 FaU+r6kvHVgbksBN2x/Nrpo/ifEZhx33FhDxnd+7HEJUarGb3GitITZk+OQfmbNnI1F2 Hr45+OjyPDLaabLGZkyRvFH2yiZ6A1b7eO0Rdz4D0rqJmh1E4P5uyVLyltCxdHlVWRHq 9E/8NpCy7yLQephAySALRgWGmQUQ2JJoLs8cf0OeoQHhpcGWF52etC1dgYtoB4JsFqkI jurHSTwEld5bHKnn1NUhWKroq7rl6Q0sSiHmDP+hvQK7905HCOe+4NKjcQBkREFzdwcI yN2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548372; x=1689140372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/tfSMMNSy6Z3dTRBojoQkv78dxEs3QjtEnCrcqetfSI=; b=YYXhhZV0/fIddYmJeRrVBRsYiA+5F5NMSusydZa8zuaAnz/9NeouyeV9kBGBzr0lyH W9q8b9MzKaZ90k7X7PRrFjhgR1ydJkXzMLhbH8EWwlirLOZTaPG8lBMutp5TZkOUmv7I cZlYjkimUi/eId1MPsLlC2+HnyMKTn9ghsvKJbTYi7azx78nYNN+wXs/qum6TxJu8+P7 dn8XP1vR9936kou3sYk7+aMPS3Vp6JP+1q55BYfzXoeIBti8mMbaQZlt+zTZFix7a+RF AGnMyi/+StiQVUFDqhRHH/enNvwg3AFTt4q1yUIkVg823/HSYAheosNko/6/zQGZtday i+Fw== X-Gm-Message-State: AC+VfDzn6znUlfqrr1qICaIQgFvbsauhN2E1DF4rGyksC80rE9Gz6cmh YdAh4otXR60TcAwMbH4sFoQiNQ== X-Google-Smtp-Source: ACHHUZ4qCMQazXgSyMWDZvV43fJKQEv4MABxank6FGdih0/Y3fZtg9SXjo0DRBP4FSZlc5uZwcHCMA== X-Received: by 2002:a19:4352:0:b0:4f1:4cdc:ec03 with SMTP id m18-20020a194352000000b004f14cdcec03mr2832595lfj.18.1686548372136; Sun, 11 Jun 2023 22:39:32 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:31 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 08/18] cpufreq: qcom-nvmem: also accept operating-points-v2-krait-cpu Date: Mon, 12 Jun 2023 08:39:12 +0300 Message-Id: <20230612053922.3284394-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org the qcom-cpufreq-nvmem driver attempts to support both Qualcomm Kryo (newer 64-bit ARMv8 cores) and Krait (older 32-bit ARMv7 cores). It makes no sense to use 'operating-points-v2-kryo-cpu' compatibility node for the Krait cores. Add support for 'operating-points-v2-krait-cpu' compatibility string. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index a88b6fe5db50..fee9736f7326 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -238,7 +238,8 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) if (!np) return -ENOENT; - ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu"); + ret = of_device_is_compatible(np, "operating-points-v2-kryo-cpu") || + of_device_is_compatible(np, "operating-points-v2-krait-cpu"); if (!ret) { of_node_put(np); return -ENOENT; From patchwork Mon Jun 12 05:39:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691752 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CCA7BC87FE2 for ; Mon, 12 Jun 2023 05:40:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235723AbjFLFkD (ORCPT ); Mon, 12 Jun 2023 01:40:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235745AbjFLFjg (ORCPT ); Mon, 12 Jun 2023 01:39:36 -0400 Received: from mail-lf1-x12f.google.com (mail-lf1-x12f.google.com [IPv6:2a00:1450:4864:20::12f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 91C7510D4 for ; Sun, 11 Jun 2023 22:39:34 -0700 (PDT) Received: by mail-lf1-x12f.google.com with SMTP id 2adb3069b0e04-4f4e71a09a7so4761959e87.1 for ; Sun, 11 Jun 2023 22:39:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548373; x=1689140373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hcxDwDZfbo/85khIYBSZuraP26/4wkWE6EMGE9oVioQ=; b=xO8QvMEbbpDd73N5wYMdhNxf48iGu0aWOhr6Al47xOuHsTdWUOla0Qm2Iov3fSJYxK iKPuOLaApFe5S8HaV2vas+g+6hK+fPhANh8DbvbfNp9UbdVIsfRQBjKdyfMdX0kYe9ds lpFMJh3wJ0pFM6P3L5e86Qd1HY/7J+zjchux515AFXZN2NeAruWI1oTRkzIMHBp8abbp PrO4rCqrGorIEjio732nTIIE4MYdfPd1/x/5lT8JXsFDlGismbbWGwXr+g9zD8aAI7T4 2bOO5dCr3GCwxitQ87/WP3xlFTIMZseENFY9RKrU+c3LED13UarNTirx1qvvrRnMiYTZ RDyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548373; x=1689140373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hcxDwDZfbo/85khIYBSZuraP26/4wkWE6EMGE9oVioQ=; b=jML5dqDBhhTHQJGlZAqLDhdLfOr43B/DcYiu3TVNPrbk/jSLnDZfHtljLtW/JwWpo7 MrMkVdXPaPamy3ZoqZswVEBV3r/ZwYXfaJt5iiAsXXH74T2FlziTxfLK+C2MghmIDnmj kCUR6TQUHV672euLeGIOvuqWa9tevCs0czOT+ArjOWcuK+weEDcwPwbLtU6kPzDM7VQ3 s+lRhR6VEjs357KgI/ctJ/h0OuxdAYh8KwfAB1SmQqpn6JkkU42DsZSqGyyk5AIW3wIF 3FxB4jyMLsXT170va72cv707UF7VUoYBiGk4jJP2DP9H1uaEpujYr8iCYs2uWEmGnXIo WwOg== X-Gm-Message-State: AC+VfDzjVChMrEJt6dy+6bo9zOFUgiF039zjHLkkxwMNgwHQTixhpquK SH/rFW64tOHC2473SGCYKl0Y9A== X-Google-Smtp-Source: ACHHUZ6JnnQBqlWQ8vytyKIbJhtuEgKzCTcCctpgOK6LyFqsrxBZP42pngw+Hq4/WeyQZLSy35XlZA== X-Received: by 2002:a19:791d:0:b0:4f3:a9a8:8d84 with SMTP id u29-20020a19791d000000b004f3a9a88d84mr2557182lfc.6.1686548372932; Sun, 11 Jun 2023 22:39:32 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:32 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 09/18] cpufreq: qcom-nvmem: Add support for voltage scaling Date: Mon, 12 Jun 2023 08:39:13 +0300 Message-Id: <20230612053922.3284394-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org If requested by the platform, scale voltages according to data specified in the OPP tables. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 115 ++++++++++++++++++++++++++- 1 file changed, 114 insertions(+), 1 deletion(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index fee9736f7326..18d6e6ed1bd0 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include @@ -39,6 +40,7 @@ struct qcom_cpufreq_match_data { char **pvs_name, struct qcom_cpufreq_drv *drv); const char **genpd_names; + const char * const *regulator_names; }; struct qcom_cpufreq_drv { @@ -218,6 +220,110 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = { .genpd_names = qcs404_genpd_names, }; +#define NUM_SUPPLIES 2 +static int qcom_cpufreq_config_regulators(struct device *dev, + struct dev_pm_opp *old_opp, + struct dev_pm_opp *new_opp, + struct regulator **regulators, + unsigned int count) +{ + struct dev_pm_opp_supply supplies[NUM_SUPPLIES]; + unsigned long old_freq, freq; + unsigned int i; + int ret; + + if (WARN_ON_ONCE(count != NUM_SUPPLIES)) + return -EINVAL; + + ret = dev_pm_opp_get_supplies(new_opp, supplies); + if (WARN_ON(ret)) + return ret; + + old_freq = dev_pm_opp_get_freq(old_opp); + freq = dev_pm_opp_get_freq(new_opp); + + WARN_ON(!old_freq || !freq); + if (freq > old_freq) { + for (i = 0; i < count; i++) { + struct regulator *reg = regulators[i]; + struct dev_pm_opp_supply *supply = &supplies[i]; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + ret = regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + if (ret) { + dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n", + __func__, supply->u_volt_min, supply->u_volt, + supply->u_volt_max, ret); + goto restore_backwards; + } + } + } else { + for (i = count; i > 0; i--) { + struct regulator *reg = regulators[i - 1]; + struct dev_pm_opp_supply *supply = &supplies[i - 1]; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + ret = regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + if (ret) { + dev_err(dev, "%s: failed to set voltage (%lu %lu %lu mV): %d\n", + __func__, supply->u_volt_min, supply->u_volt, + supply->u_volt_max, ret); + goto restore_forward; + } + } + } + + return 0; + +restore_backwards: + + dev_pm_opp_get_supplies(old_opp, supplies); + + for (; i > 0; i--) { + struct regulator *reg = regulators[i - 1]; + struct dev_pm_opp_supply *supply = &supplies[i - 1]; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + } + + return ret; + +restore_forward: + + dev_pm_opp_get_supplies(old_opp, supplies); + + for ( ; i < count; i++) { + struct regulator *reg = regulators[i]; + struct dev_pm_opp_supply *supply = &supplies[i]; + + dev_dbg(dev, "%s: voltages (mV): %lu %lu %lu\n", __func__, + supply->u_volt_min, supply->u_volt, supply->u_volt_max); + + regulator_set_voltage_triplet(reg, + supply->u_volt_min, + supply->u_volt, + supply->u_volt_max); + } + + return ret; +} + static int qcom_cpufreq_probe(struct platform_device *pdev) { struct qcom_cpufreq_drv *drv; @@ -305,7 +411,14 @@ static int qcom_cpufreq_probe(struct platform_device *pdev) config.virt_devs = NULL; } - if (config.supported_hw || config.genpd_names) { + if (drv->data->regulator_names) { + config.config_regulators = qcom_cpufreq_config_regulators; + config.regulator_names = drv->data->regulator_names; + } + + if (config.supported_hw || + config.genpd_names || + config.regulator_names) { drv->opp_tokens[cpu] = dev_pm_opp_set_config(cpu_dev, &config); if (drv->opp_tokens[cpu] < 0) { ret = drv->opp_tokens[cpu]; From patchwork Mon Jun 12 05:39:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691751 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65898C7EE37 for ; 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:34 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 11/18] cpufreq: qcom-nvmem: provide separate configuration data for apq8064 Date: Mon, 12 Jun 2023 08:39:15 +0300 Message-Id: <20230612053922.3284394-12-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org APQ8064 can scale core and memory voltages according to the frequency needs. Rather than reusing the A/B format multiplexer, use a simple fuse parsing function and configure required regulators. Signed-off-by: Dmitry Baryshkov --- drivers/cpufreq/qcom-cpufreq-nvmem.c | 44 ++++++++++++++++++++++++++-- 1 file changed, 42 insertions(+), 2 deletions(-) diff --git a/drivers/cpufreq/qcom-cpufreq-nvmem.c b/drivers/cpufreq/qcom-cpufreq-nvmem.c index fc446acfda22..e5fede594399 100644 --- a/drivers/cpufreq/qcom-cpufreq-nvmem.c +++ b/drivers/cpufreq/qcom-cpufreq-nvmem.c @@ -206,6 +206,34 @@ static int qcom_cpufreq_krait_name_version(struct device *cpu_dev, return ret; } +static int qcom_cpufreq_apq8064_name_version(struct device *cpu_dev, + struct nvmem_cell *speedbin_nvmem, + char **pvs_name, + struct qcom_cpufreq_drv *drv) +{ + int speed = 0, pvs = 0; + u8 *speedbin; + size_t len; + int ret = 0; + + speedbin = nvmem_cell_read(speedbin_nvmem, &len); + if (IS_ERR(speedbin)) + return PTR_ERR(speedbin); + + if (len != 4) + return -EINVAL; + + get_krait_bin_format_a(cpu_dev, &speed, &pvs, speedbin); + + snprintf(*pvs_name, sizeof("speedXX-pvsXX"), "speed%d-pvs%d", + speed, pvs); + + drv->versions = (1 << speed); + + kfree(speedbin); + return ret; +} + static const struct qcom_cpufreq_match_data match_data_kryo = { .get_version = qcom_cpufreq_kryo_name_version, }; @@ -220,7 +248,19 @@ static const struct qcom_cpufreq_match_data match_data_qcs404 = { .genpd_names = qcs404_genpd_names, }; -#define NUM_SUPPLIES 2 +static const char * apq8064_regulator_names[] = { + "vdd-mem", + "vdd-dig", + "vdd-core", + NULL +}; + +static const struct qcom_cpufreq_match_data match_data_apq8064 = { + .get_version = qcom_cpufreq_apq8064_name_version, + .regulator_names = apq8064_regulator_names, +}; + +#define NUM_SUPPLIES 3 static int qcom_cpufreq_config_regulators(struct device *dev, struct dev_pm_opp *old_opp, struct dev_pm_opp *new_opp, @@ -477,7 +517,7 @@ static const struct of_device_id qcom_cpufreq_match_list[] __initconst = { { .compatible = "qcom,msm8996", .data = &match_data_kryo }, { .compatible = "qcom,qcs404", .data = &match_data_qcs404 }, { .compatible = "qcom,ipq8064", .data = &match_data_krait }, - { .compatible = "qcom,apq8064", .data = &match_data_krait }, + { .compatible = "qcom,apq8064", .data = &match_data_apq8064 }, { .compatible = "qcom,msm8974", .data = &match_data_krait }, { .compatible = "qcom,msm8960", .data = &match_data_krait }, {}, From patchwork Mon Jun 12 05:39:17 2023 Content-Type: text/plain; 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:36 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 13/18] ARM: dts: qcom: apq8064: declare SAW2 regulators Date: Mon, 12 Jun 2023 08:39:17 +0300 Message-Id: <20230612053922.3284394-14-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The SAW2 (SPM and AVS Wrapper) among other things is yet another way to handle CPU-related PMIC regulators. Provide a way to control voltage of these regulators. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 24 ++++++++++++++++++++---- 1 file changed, 20 insertions(+), 4 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index 471eeca6a589..1eb6d752ebae 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -425,25 +425,41 @@ acc3: clock-controller@20b8000 { saw0: power-manager@2089000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02089000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw0_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw1: power-manager@2099000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x02099000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw1_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw2: power-manager@20a9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020a9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw2_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; saw3: power-manager@20b9000 { compatible = "qcom,apq8064-saw2-v1.1-cpu", "qcom,saw2"; reg = <0x020b9000 0x1000>, <0x02009000 0x1000>; - regulator; + + saw3_vreg: regulator { + regulator-min-microvolt = <850000>; + regulator-max-microvolt = <1300000>; + }; }; sps_sic_non_secure: sps-sic-non-secure@12100000 { From patchwork Mon Jun 12 05:39:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90F1FC87FDE for ; Mon, 12 Jun 2023 05:40:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235948AbjFLFkP (ORCPT ); Mon, 12 Jun 2023 01:40:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40338 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235960AbjFLFjy (ORCPT ); Mon, 12 Jun 2023 01:39:54 -0400 Received: from mail-lf1-x12b.google.com (mail-lf1-x12b.google.com [IPv6:2a00:1450:4864:20::12b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D27FB171A for ; Sun, 11 Jun 2023 22:39:43 -0700 (PDT) Received: by mail-lf1-x12b.google.com with SMTP id 2adb3069b0e04-4f4b2bc1565so4426469e87.2 for ; Sun, 11 Jun 2023 22:39:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548379; x=1689140379; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9UX7NK4V+9Hzbg8jKZOwQnFK6tOBZPs2ooDLmGE25jY=; b=AzpjJjf1rRnX9/8zALf3MesyN9OaLzUS92PcVFWMfUfz61cX6SINAyaN4rtAf0Cvp3 yJyHbyTKfbyg6l79QWpNVS+eG379IO/ympACeqdSJdwFhPQVHr2H4RZ56dOi4I9iO6dw WuGJV/Y9mOGgmqEeaAr7W0VAqENtiV/KfSD/cgk3OnxkiMOKGBGCjlsQos2JGxLxECB/ xNbH0a2IcBH25Byze5J6+IJi02GDsxQQaQ/SdW8iuubwTJxJTMp/L1smdcRqeWB18nU/ /ZnnudIsga+wsvHHLPFYCCmBUgH51cVLJJZFZ3htw6zTbzoSnxIKAT5rlmjmKthkD/tA 326A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548379; x=1689140379; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9UX7NK4V+9Hzbg8jKZOwQnFK6tOBZPs2ooDLmGE25jY=; b=kIKd4acbRRrorYWiCZrafWirr1YDeL9hm789EO947+I/oy7mUe+DkqgMljS1wxzUn1 cF/QokKXxceLOsJIBQkjgAJqsjUQnOr+kSPFqIWjgKdALD+T2JceatZEGmlxHFhI43mA 2KAGSo8o5GMouj2pjrmHYZ6BthNVqYiYe0voiN0nJjnWONn4FZXDKmyXCCeeYGdF/VZo JqQPSCKaBAzJrClHHptJm0cohtR3X6xGi6POQqKNApZMFE9EMrT2Fn0rZLpYi6Nrx6V8 1kIZb98lFM8REfKtchtCIItBK3Qdr+5fS6dThzx0XR3AbSvbWFViELp5jp1vI/+/20LU dfjA== X-Gm-Message-State: AC+VfDyM3W3iuojpZdg2EnPzIA+L/eUlV2YFhxy9aMnvjb1aSlZ9c7pD FR0vgmczbs4KOLSEtmNdyL9Rhw== X-Google-Smtp-Source: ACHHUZ4wzWtxLIONvLUsoHjLluwV+c2yaJibWU04gw+Iy3i1r8PtS/J7Hs69VzzP644zHXsD6fSuag== X-Received: by 2002:a19:6d1c:0:b0:4f6:424c:4fa8 with SMTP id i28-20020a196d1c000000b004f6424c4fa8mr2903128lfc.17.1686548379413; Sun, 11 Jun 2023 22:39:39 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:38 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 16/18] ARM: dts: qcom: apq8064: enable passive CPU cooling Date: Mon, 12 Jun 2023 08:39:20 +0300 Message-Id: <20230612053922.3284394-17-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Wire up CPUs and thermal trip points to save the SoC from overheating by lowering the CPU frequency. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064.dtsi | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) diff --git a/arch/arm/boot/dts/qcom-apq8064.dtsi b/arch/arm/boot/dts/qcom-apq8064.dtsi index f35853b59544..82b381b66cfb 100644 --- a/arch/arm/boot/dts/qcom-apq8064.dtsi +++ b/arch/arm/boot/dts/qcom-apq8064.dtsi @@ -10,6 +10,7 @@ #include #include #include +#include / { #address-cells = <1>; #size-cells = <1>; @@ -1279,6 +1280,13 @@ cpu_crit0: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert0>; + cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu1-thermal { @@ -1300,6 +1308,13 @@ cpu_crit1: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert1>; + cooling-device = <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu2-thermal { @@ -1321,6 +1336,13 @@ cpu_crit2: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert2>; + cooling-device = <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; cpu3-thermal { @@ -1342,6 +1364,13 @@ cpu_crit3: trip1 { type = "critical"; }; }; + + cooling-maps { + map0 { + trip = <&cpu_alert3>; + cooling-device = <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; + }; + }; }; }; From patchwork Mon Jun 12 05:39:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 691748 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D9DFC7EE45 for ; Mon, 12 Jun 2023 05:40:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236071AbjFLFk1 (ORCPT ); Mon, 12 Jun 2023 01:40:27 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:40126 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236065AbjFLFj6 (ORCPT ); Mon, 12 Jun 2023 01:39:58 -0400 Received: from mail-lf1-x12a.google.com (mail-lf1-x12a.google.com [IPv6:2a00:1450:4864:20::12a]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 46C0F173E for ; Sun, 11 Jun 2023 22:39:50 -0700 (PDT) Received: by mail-lf1-x12a.google.com with SMTP id 2adb3069b0e04-4f64fb05a8aso4535869e87.0 for ; Sun, 11 Jun 2023 22:39:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1686548380; x=1689140380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2COHoS0iCE7QlZQECIs2qMw+k4Ux9D95krl1smHPEhw=; b=vQtQ+YLvQaTeDMhfogpkzaIizdumMXgl+SwKny0ktMYFLMvzj5QzSSoHCBZgwdMhxe Pzg8JZjmdDDa28Mvp723hEtP41NXATAzox+CURgRFTRgRsTaaZDYKQ1rTC7soqgmJV7w ovKdjHvXwI1MQo/wxBQtIGI9juYnCPvDcJMrNP87DlwhuTbBkjJOrE6jabGUo6xf0aHI WDHFmJ+IrUMM7iNaMu7FFn/M86EnWnCQ1WG122UZdq01E2+8kUjLlhKa1c8veTDsCTnI VpdJD+merSWMi5vrJIpkegtGSWsJwc5RnGrkAwgHE35EGVbcqzzkAlqP+PAo4mjR02oc VeIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1686548380; x=1689140380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2COHoS0iCE7QlZQECIs2qMw+k4Ux9D95krl1smHPEhw=; b=clGKljfLj7dKrxOhZhfhzD8gEVQsHUwc/4Q58vCoXhxiwXQ/aC3tC7LmN2tzsvAV4s AR+n74ZGyGf6Qg7n7kp4eKU2fdT4GYFHojVlpQuy6XYkAJI6ZAznJrdiUIos/8zBQtQi DfAXxzsK8rNOe7dn194DnLxJzYXzf5G+ZLZcl7CEsEJQPRJWTPo4hTOLgMj3p+2IenKM ZjM+XOxYc7Eqa3SLr3rlFkzgTP6LFAb+GfI0qJkl9b7y+M1XwhSGdkbEUjOqJo2uMo3V nqGpq/04TbgV4ZsxBrQPyYJU/IGOckqPFxhxP7QELEQehd+q/S3pLwoe+VSdMh3wPL/s 7NJw== X-Gm-Message-State: AC+VfDyEuetgaelRRhGFSGt6xjQ5Oz5BLoZrAEzjfUs15CnyzDJZttyq pn5vhuFwxyDL0Xa6yEAXK6YqMg== X-Google-Smtp-Source: ACHHUZ7jZf3YWi3Bhcxzz1FPeGdaumoZrreHjOvXVIwrZeVhijRftpqHNrSzCPUKmYTkPYHQrW2K2A== X-Received: by 2002:a05:6512:32b7:b0:4f4:e3fa:73d8 with SMTP id q23-20020a05651232b700b004f4e3fa73d8mr3408928lfe.62.1686548380316; Sun, 11 Jun 2023 22:39:40 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id n6-20020a195506000000b004f38260f196sm1324125lfe.218.2023.06.11.22.39.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 11 Jun 2023 22:39:39 -0700 (PDT) From: Dmitry Baryshkov To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Andy Gross , Bjorn Andersson , Konrad Dybcio , Ilia Lin , Viresh Kumar , Nishanth Menon , Stephen Boyd , Michael Turquette , "Rafael J. Wysocki" Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-pm@vger.kernel.org, linux-clk@vger.kernel.org, Christian Marangi Subject: [PATCH 17/18] ARM: dts: qcom: apq8064-asus-nexus7-flo: constraint cpufreq regulators Date: Mon, 12 Jun 2023 08:39:21 +0300 Message-Id: <20230612053922.3284394-18-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> References: <20230612053922.3284394-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add additional constraints to the CPUfreq-related regulators, it is better be safe than sorry there. Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts | 14 ++++++++++++-- 1 file changed, 12 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts index c57c27cd8a20..9f5d72727356 100644 --- a/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts +++ b/arch/arm/boot/dts/qcom-apq8064-asus-nexus7-flo.dts @@ -218,9 +218,9 @@ s1 { bias-pull-down; }; - /* msm otg HSUSB_VDDCX */ + /* msm otg HSUSB_VDDCX and VDD_DIG */ s3 { - regulator-min-microvolt = <500000>; + regulator-min-microvolt = <950000>; regulator-max-microvolt = <1150000>; qcom,switch-mode-frequency = <4800000>; }; @@ -301,6 +301,12 @@ l23 { bias-pull-down; }; + /* VDD_MEM */ + l24 { + regulator-min-microvolt = <1050000>; + regulator-max-microvolt = <1150000>; + }; + /* * tabla2x-slim-CDC_VDDA_A_1P2V * tabla2x-slim-VDDD_CDC_D @@ -329,8 +335,12 @@ lvs6 { /* * mipi_dsi.1-dsi1_vddio * pil_riva-pll_vdd + * HFPLL regulator */ lvs7 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; bias-pull-down; }; };