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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id a11-20020a05600c224b00b003f8126bcf34sm3482776wmm.48.2023.06.11.01.58.51 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:58:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 01/26] plugins: Remove unused 'exec/helper-proto.h' header Date: Sun, 11 Jun 2023 10:58:21 +0200 Message-Id: <20230611085846.21415-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- plugins/core.c | 1 - 1 file changed, 1 deletion(-) diff --git a/plugins/core.c b/plugins/core.c index 9912f2cfdb..3c4e26c7ed 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -25,7 +25,6 @@ #include "exec/exec-all.h" #include "exec/tb-flush.h" -#include "exec/helper-proto.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" #include "plugin.h" From patchwork Sun Jun 11 08:58:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691344 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1570939wru; Sun, 11 Jun 2023 02:00:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5tswkdFX+Zir9cx5hYwkIQx5fDLAg6VZnE0BREngsDdFaYXlAQi1gUNYpBbIVRx8E7sZ3N X-Received: by 2002:a05:6214:2629:b0:5ef:d5b0:c33f with SMTP id gv9-20020a056214262900b005efd5b0c33fmr12103110qvb.2.1686474038667; Sun, 11 Jun 2023 02:00:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474038; cv=none; d=google.com; s=arc-20160816; b=nBW94vf9FkM/fcwxWh90fS8IPfSZSn5IYRSCYNN1d+b0ygdywBT/Cy6pbPGaxZmUtQ kkhR7TzXKOW9jBi42ThWuduPbbBfbpQ365rl5iDN33T2ZDa5gDAFxHYSe+Ku+VkqgjeB 1KBBxi7uwqYscr7cNjNyDsOeuESOo+WXaywUVUJHIGSeU+BguiyGSlbcYA+y9A2JhJE3 AdwivuQyQ51A8aIg/1xEpz50Mw3E93yVPeP2ATNsFCrbBfHSKKqGtWg/HWIeerUkMMM1 GQBHHrxif40/MgrIPHZKrx8f6v9FS2GePSWcjDHLglpDJyLwa+B8yju83/5oMxmfg4xz QQZA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=fOqRAxEV8Qalm9ZgxaBgc+XRBEy5Pw0OdcKw70bIFoY=; b=MwC7zVTAb3hsM8LZkjAKgNRIyUZYwiZAFwF/G6WxB7Dx11D/V7SSP7mbti7fQJma8h hUINoYRdobB9GZZ4TOAVLVWglM7URXqM/MwKPfgMy6NS5oKHqphWoRlQsKt9oDH7bjqu D7EC5LaaQqzhTZnwRKLU/7/ErBDAgJZQomcD+t1BP6K3YE/cZa0gIvst0OU1Vuiqwoau 17CD0tNSGpfW3fTQnCpeiRFPGP4YU6WGp2TL8L8ImSNPNNX+/WCTJjxb4BpALFOezqbd TSUJKMwVOBG7bTdA7zT5FhpQemSjOSbmOzh+NxiViYff8Bni/a5xUGjX3ozQAM8XJzkR cytQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=b7WmROGZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id u5-20020a5d5145000000b0030fa57d8064sm5839270wrt.52.2023.06.11.01.58.55 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:58:56 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 02/26] accel/tcg/cpu-exec: Use generic 'helper-proto-common.h' header Date: Sun, 11 Jun 2023 10:58:22 +0200 Message-Id: <20230611085846.21415-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=philmd@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org We only need lookup_tb_ptr() prototype. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- accel/tcg/cpu-exec.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 42086525d7..12362177af 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -38,7 +38,7 @@ #include "sysemu/cpu-timers.h" #include "exec/replay-core.h" #include "sysemu/tcg.h" -#include "exec/helper-proto.h" +#include "exec/helper-proto-common.h" #include "tb-jmp-cache.h" #include "tb-hash.h" #include "tb-context.h" From patchwork Sun Jun 11 08:58:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691348 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1571344wru; Sun, 11 Jun 2023 02:01:44 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7EeqKnaPYO+mPM2QChDtMzUM+0Df74Qr/MTcNbiHThUpk7P0dAoRjz9XYrsVqxMgraB47u X-Received: by 2002:a05:620a:4048:b0:75d:5803:a20 with SMTP id i8-20020a05620a404800b0075d58030a20mr7663392qko.68.1686474104568; Sun, 11 Jun 2023 02:01:44 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474104; cv=none; d=google.com; s=arc-20160816; b=nYfPu0R+j8+1PmYYYVqn9d+h+5J191XMBKCuYPbCH2Gq/V3l0m0EllRFwyjAonLi8u Vs7mt9sS3najCz7/iK9IPuqNTm5d8f/zvFm2+X0pqOpEm9Hmpeh33f7IQk06MiRiHBd1 9No4vjzk7mEzSYxAcFhfX/4B54xO8S03QBqqvmjOGxUj9SIG0QFO2ogkzNsNZIaPUtOI jmW2JAVRUoZS1BM4tMJFHbBcTFDkPeQ+QucRYf3MNYHS3CZxy/SwnPF4GIyq3STAgsK+ /E/6KrjBwBjcaXu5huFQ/oonHtRwE6PR2dgqv5q9oUxmu0c6XqPVC1Zb1SYkG/ct160u E2+w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8mp+80uEQkt8/jSa2bwpDOFe4dhC6+cPTb9ADdk/0oE=; b=Jn6vHZu1zseKULJxyjTdFTg7dMD8YwuPZR2JtlMXRX+kaEJbup8BHrpYTqsD0ZIoy3 cB9oFVGzH/NlBPcbCByrSPbh02zqddVUKwJpYhGTXPmmVVudi2RCiGSNXPb3E7/ych+V s0pDb4zcs38cN/7M2t9G6GRSjdmev1jhbo/XvwLH62wfjJG9PrBHSPQiWW4I0Q2o3X62 cI8cPaBeid5uAPifL9eD9MZEYmxUAt7jMcgdnsRxEoxeMZ5KWM2z3iGzgWaPfsCd8FN5 x+QrBagzkp8mjG0hsn5TLW3/5jWvVpjNGQqp5hJqCcEB8VjfTx/liGQVVmpWB5Srydcn 7Org== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="Lntpl/tL"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id f3-20020a7bc8c3000000b003f1958eeadcsm7734318wml.17.2023.06.11.01.59.00 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:00 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 03/26] target/arm/tcg: Remove CONFIG_TCG #ifdef'ry check Date: Sun, 11 Jun 2023 10:58:23 +0200 Message-Id: <20230611085846.21415-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org CONFIG_TCG is always defined within target/arm/tcg/. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/tcg/cpu32.c | 4 +--- target/arm/tcg/m_helper.c | 6 ------ 2 files changed, 1 insertion(+), 9 deletions(-) diff --git a/target/arm/tcg/cpu32.c b/target/arm/tcg/cpu32.c index 47d2e8e781..0672519b89 100644 --- a/target/arm/tcg/cpu32.c +++ b/target/arm/tcg/cpu32.c @@ -13,11 +13,9 @@ #include "hw/core/tcg-cpu-ops.h" #include "internals.h" #include "target/arm/idau.h" +#include "cpregs.h" #if !defined(CONFIG_USER_ONLY) #include "hw/boards.h" -#endif -#include "cpregs.h" -#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) #include "hw/intc/armv7m_nvic.h" #endif diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 9cef70e5c9..0891acc29c 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -15,10 +15,8 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "exec/exec-all.h" -#ifdef CONFIG_TCG #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" -#endif #if !defined(CONFIG_USER_ONLY) #include "hw/intc/armv7m_nvic.h" #endif @@ -2345,11 +2343,7 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "...handling as semihosting call 0x%x\n", env->regs[0]); -#ifdef CONFIG_TCG do_common_semihosting(cs); -#else - g_assert_not_reached(); -#endif env->regs[15] += env->thumb ? 2 : 4; return; case EXCP_BKPT: From patchwork Sun Jun 11 08:58:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691343 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1570603wru; Sun, 11 Jun 2023 01:59:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7HxUrGbJWa5l2BlxDlLwhX1ERYYRRiypa6XY0UXB9me54Wm8a1W5wab9ryOIhug7RcHbCK X-Received: by 2002:a05:620a:4484:b0:75f:414:1675 with SMTP id x4-20020a05620a448400b0075f04141675mr5822070qkp.18.1686473986067; Sun, 11 Jun 2023 01:59:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686473986; cv=none; d=google.com; s=arc-20160816; b=gHkc1yjWqmXdh0dy3/4Lkt866hU5nVK0+KNl5xz+QsgiFNT0xR3Yo4VepilUjmD/Oz fpjQKjDAW1jO+RjVzLZS68ING65o9smU6yj0FoUUwiWGnAzhBzqQ36xUfND3rOoCxLbE gY20SnckQV9BS/k4HkNqpj7pUaWqQHOLq+gSg8XhUgn2nvDNecdVhnHr+Fyr4Bn+DDS/ qwS+Fs6V/NMgBjsZJD0fosVYSVYsluWv0mMMwkkM7YPSbqUhCrA6bTNBkDd82F0D1dj0 aV8kkauNUCIr0Jixndz/CinJ4kTB/oYpQ7b/JZWi1kzeAa2pNsfFhZN14nxQHnt/6Vbw ocaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oIvtCmiWepPA7NXEFbXWWLePEDf5Lnkm5evgEG2zaNg=; b=fbsirCzDXJukWv2s7sL4OlKih2bVzGEaW/aP/pq05CvAhrUm8Ruh2HACClBmksGIuF 0W2ON5xjuhXm9QJUryLAyU6opPm2P6MRVqsfRVXl4OzWvisa1/j1AnYDqr4+sFgx41rL 6eZEkJ+16HTOVnoVcOR1vwnrlKTLmU7n3/vENKeipYROvXhknapVrmP7CI/RZ9fOdNis lsd8Zcbem4GH/o9sQVGNnZoXfWFQYeHGGd2/QjGfoZdVK5QFwFpu5q1OJq+XruSNaLSv jEdAaGPSKpphrEAzaTtfw0LAk/9hWw26j+XkagtB2bEsjVc5iv4V6lYqtFG/q60BCg61 UAeA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sAhBNdzB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id x22-20020a05600c21d600b003f70a7b4537sm7855052wmj.36.2023.06.11.01.59.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 04/26] target/arm/tcg: Rename helper template headers as '.h.inc' Date: Sun, 11 Jun 2023 10:58:24 +0200 Message-Id: <20230611085846.21415-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=philmd@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented as the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename the included templates as '.h.inc'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/helper.h | 8 ++++---- target/arm/tcg/{helper-a64.h => helper-a64.h.inc} | 0 target/arm/tcg/{helper-mve.h => helper-mve.h.inc} | 0 target/arm/tcg/{helper-sme.h => helper-sme.h.inc} | 0 target/arm/tcg/{helper-sve.h => helper-sve.h.inc} | 0 5 files changed, 4 insertions(+), 4 deletions(-) rename target/arm/tcg/{helper-a64.h => helper-a64.h.inc} (100%) rename target/arm/tcg/{helper-mve.h => helper-mve.h.inc} (100%) rename target/arm/tcg/{helper-sme.h => helper-sme.h.inc} (100%) rename target/arm/tcg/{helper-sve.h => helper-sve.h.inc} (100%) diff --git a/target/arm/helper.h b/target/arm/helper.h index 3335c2b10b..4218d98b51 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -1039,9 +1039,9 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) #ifdef TARGET_AARCH64 -#include "tcg/helper-a64.h" -#include "tcg/helper-sve.h" -#include "tcg/helper-sme.h" +#include "tcg/helper-a64.h.inc" +#include "tcg/helper-sve.h.inc" +#include "tcg/helper-sme.h.inc" #endif -#include "tcg/helper-mve.h" +#include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/helper-a64.h b/target/arm/tcg/helper-a64.h.inc similarity index 100% rename from target/arm/tcg/helper-a64.h rename to target/arm/tcg/helper-a64.h.inc diff --git a/target/arm/tcg/helper-mve.h b/target/arm/tcg/helper-mve.h.inc similarity index 100% rename from target/arm/tcg/helper-mve.h rename to target/arm/tcg/helper-mve.h.inc diff --git a/target/arm/tcg/helper-sme.h b/target/arm/tcg/helper-sme.h.inc similarity index 100% rename from target/arm/tcg/helper-sme.h rename to target/arm/tcg/helper-sme.h.inc diff --git a/target/arm/tcg/helper-sve.h b/target/arm/tcg/helper-sve.h.inc similarity index 100% rename from target/arm/tcg/helper-sve.h rename to target/arm/tcg/helper-sve.h.inc From patchwork Sun Jun 11 08:58:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691358 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1572572wru; Sun, 11 Jun 2023 02:05:48 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6hmuvYjtFEjpn5cTAwdxAMEpve6lI8uRa6dScJBYXKOr5nqwvoUoHPNuvfOrBC4uOdzGNC X-Received: by 2002:ac8:7d05:0:b0:3ef:2f92:464d with SMTP id g5-20020ac87d05000000b003ef2f92464dmr7814649qtb.28.1686474347868; Sun, 11 Jun 2023 02:05:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474347; cv=none; d=google.com; s=arc-20160816; b=EihbuuYdtssZ1dw7bEUBmBdSay4zMW0sBdUZccaZds6hhutND9m3++k+dNzqUXLq54 BBsu7LTm0xe4AQQu5VSW7Lpbr39O1ZFM548h2o/K7iB4pxys+7hTIf/znn2FEQ/jqzOl IuYb4/Mqr9JUDKRPX5Op2ndxmTWB3AYswO4Tkl/Pwhy/1fQSpmPQxdXGRZHEPlVV1KGh hHaCQJBmr7UTTVZPMijaRCynNRA1qpsb67JvuJ3HNYgVYX6lj9+cbSi/n92A+1nFqY2V cOwKchra+ivAxyuyEe/w7PwDbd49Wi81RuelC4tiy9CXfKd4/cWkJDUUL0BMDDIihjxW 43pw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lhArNuatDNYVRkaFGuTDa+3jxPD4OXoWAoXbKpvzLCo=; b=XmjWFm5yUohlinsYk1kHWYgCNMVzqclfHofpKbrEJ/98JZozLR00oEqNVVWEOlB/wP uwzYYun0Tb+HBsGPbgZ5HOYO6Yuq5CuJjCaWJrRm8lbjeioRO04tFs8ImRpdHkVntMec Lp6iW7u5FWC0JtT5K67JpvWPfz0EbcLYzDv9M55rgRHGYuupds9RG8DetqABBOtwLNIf 9LqQfTmsSE2MUTDEsk5dbtiZqzPBNkrNureThd/Jk/Wp7t7aRNqt5DeDi314hCzpLlPr b1CBBekqCxK9ECLOlS5438tfEfhU2PMEqeIJcy5UENtcoIkYCW5BmVTSLdvpUivt4yVI uiTA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GMss+rIB; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id gy15-20020a05600c880f00b003f7f475c3bcsm10193970wmb.1.2023.06.11.01.59.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:09 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 05/26] target/arm/tcg: Extract iwMMXt helpers from the generic 'helper.h' Date: Sun, 11 Jun 2023 10:58:25 +0200 Message-Id: <20230611085846.21415-6-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/helper.h | 96 +-------------------------- target/arm/tcg/helper-iwmmxt.h.inc | 103 +++++++++++++++++++++++++++++ 2 files changed, 104 insertions(+), 95 deletions(-) create mode 100644 target/arm/tcg/helper-iwmmxt.h.inc diff --git a/target/arm/helper.h b/target/arm/helper.h index 4218d98b51..c4a321c0ea 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -445,101 +445,6 @@ DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, ptr) DEF_HELPER_3(neon_acge_f64, i64, i64, i64, ptr) DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, ptr) -/* iwmmxt_helper.c */ -DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64) -DEF_HELPER_2(iwmmxt_madduq, i64, i64, i64) -DEF_HELPER_2(iwmmxt_sadb, i64, i64, i64) -DEF_HELPER_2(iwmmxt_sadw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mulslw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mulshw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_mululw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_muluhw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_macsw, i64, i64, i64) -DEF_HELPER_2(iwmmxt_macuw, i64, i64, i64) -DEF_HELPER_1(iwmmxt_setpsr_nz, i32, i64) - -#define DEF_IWMMXT_HELPER_SIZE_ENV(name) \ -DEF_HELPER_3(iwmmxt_##name##b, i64, env, i64, i64) \ -DEF_HELPER_3(iwmmxt_##name##w, i64, env, i64, i64) \ -DEF_HELPER_3(iwmmxt_##name##l, i64, env, i64, i64) \ - -DEF_IWMMXT_HELPER_SIZE_ENV(unpackl) -DEF_IWMMXT_HELPER_SIZE_ENV(unpackh) - -DEF_HELPER_2(iwmmxt_unpacklub, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackluw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklul, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhub, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhuw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhul, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsb, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpacklsl, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsb, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsw, i64, env, i64) -DEF_HELPER_2(iwmmxt_unpackhsl, i64, env, i64) - -DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq) -DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu) -DEF_IWMMXT_HELPER_SIZE_ENV(cmpgts) - -DEF_IWMMXT_HELPER_SIZE_ENV(mins) -DEF_IWMMXT_HELPER_SIZE_ENV(minu) -DEF_IWMMXT_HELPER_SIZE_ENV(maxs) -DEF_IWMMXT_HELPER_SIZE_ENV(maxu) - -DEF_IWMMXT_HELPER_SIZE_ENV(subn) -DEF_IWMMXT_HELPER_SIZE_ENV(addn) -DEF_IWMMXT_HELPER_SIZE_ENV(subu) -DEF_IWMMXT_HELPER_SIZE_ENV(addu) -DEF_IWMMXT_HELPER_SIZE_ENV(subs) -DEF_IWMMXT_HELPER_SIZE_ENV(adds) - -DEF_HELPER_3(iwmmxt_avgb0, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgb1, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgw0, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_avgw1, i64, env, i64, i64) - -DEF_HELPER_3(iwmmxt_align, i64, i64, i64, i32) -DEF_HELPER_4(iwmmxt_insr, i64, i64, i32, i32, i32) - -DEF_HELPER_1(iwmmxt_bcstb, i64, i32) -DEF_HELPER_1(iwmmxt_bcstw, i64, i32) -DEF_HELPER_1(iwmmxt_bcstl, i64, i32) - -DEF_HELPER_1(iwmmxt_addcb, i64, i64) -DEF_HELPER_1(iwmmxt_addcw, i64, i64) -DEF_HELPER_1(iwmmxt_addcl, i64, i64) - -DEF_HELPER_1(iwmmxt_msbb, i32, i64) -DEF_HELPER_1(iwmmxt_msbw, i32, i64) -DEF_HELPER_1(iwmmxt_msbl, i32, i64) - -DEF_HELPER_3(iwmmxt_srlw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_srll, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_srlq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sllw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_slll, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sllq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sraw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sral, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_sraq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorw, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorl, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_rorq, i64, env, i64, i32) -DEF_HELPER_3(iwmmxt_shufh, i64, env, i64, i32) - -DEF_HELPER_3(iwmmxt_packuw, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packul, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packuq, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsw, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsl, i64, env, i64, i64) -DEF_HELPER_3(iwmmxt_packsq, i64, env, i64, i64) - -DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32) -DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32) -DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32) - DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) @@ -1044,4 +949,5 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-sme.h.inc" #endif +#include "tcg/helper-iwmmxt.h.inc" #include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/helper-iwmmxt.h.inc b/target/arm/tcg/helper-iwmmxt.h.inc new file mode 100644 index 0000000000..955ab2365b --- /dev/null +++ b/target/arm/tcg/helper-iwmmxt.h.inc @@ -0,0 +1,103 @@ +/* + * XScale iwMMXt specific helper definitions + * + * Copyright (c) 2007 OpenedHand, Ltd. + * Written by Andrzej Zaborowski + * Copyright (c) 2008 CodeSourcery + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +DEF_HELPER_2(iwmmxt_maddsq, i64, i64, i64) +DEF_HELPER_2(iwmmxt_madduq, i64, i64, i64) +DEF_HELPER_2(iwmmxt_sadb, i64, i64, i64) +DEF_HELPER_2(iwmmxt_sadw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_mulslw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_mulshw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_mululw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_muluhw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_macsw, i64, i64, i64) +DEF_HELPER_2(iwmmxt_macuw, i64, i64, i64) +DEF_HELPER_1(iwmmxt_setpsr_nz, i32, i64) + +#define DEF_IWMMXT_HELPER_SIZE_ENV(name) \ +DEF_HELPER_3(iwmmxt_##name##b, i64, env, i64, i64) \ +DEF_HELPER_3(iwmmxt_##name##w, i64, env, i64, i64) \ +DEF_HELPER_3(iwmmxt_##name##l, i64, env, i64, i64) \ + +DEF_IWMMXT_HELPER_SIZE_ENV(unpackl) +DEF_IWMMXT_HELPER_SIZE_ENV(unpackh) + +DEF_HELPER_2(iwmmxt_unpacklub, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackluw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklul, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhub, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhuw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhul, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklsb, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklsw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpacklsl, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhsb, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhsw, i64, env, i64) +DEF_HELPER_2(iwmmxt_unpackhsl, i64, env, i64) + +DEF_IWMMXT_HELPER_SIZE_ENV(cmpeq) +DEF_IWMMXT_HELPER_SIZE_ENV(cmpgtu) +DEF_IWMMXT_HELPER_SIZE_ENV(cmpgts) + +DEF_IWMMXT_HELPER_SIZE_ENV(mins) +DEF_IWMMXT_HELPER_SIZE_ENV(minu) +DEF_IWMMXT_HELPER_SIZE_ENV(maxs) +DEF_IWMMXT_HELPER_SIZE_ENV(maxu) + +DEF_IWMMXT_HELPER_SIZE_ENV(subn) +DEF_IWMMXT_HELPER_SIZE_ENV(addn) +DEF_IWMMXT_HELPER_SIZE_ENV(subu) +DEF_IWMMXT_HELPER_SIZE_ENV(addu) +DEF_IWMMXT_HELPER_SIZE_ENV(subs) +DEF_IWMMXT_HELPER_SIZE_ENV(adds) + +DEF_HELPER_3(iwmmxt_avgb0, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_avgb1, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_avgw0, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_avgw1, i64, env, i64, i64) + +DEF_HELPER_3(iwmmxt_align, i64, i64, i64, i32) +DEF_HELPER_4(iwmmxt_insr, i64, i64, i32, i32, i32) + +DEF_HELPER_1(iwmmxt_bcstb, i64, i32) +DEF_HELPER_1(iwmmxt_bcstw, i64, i32) +DEF_HELPER_1(iwmmxt_bcstl, i64, i32) + +DEF_HELPER_1(iwmmxt_addcb, i64, i64) +DEF_HELPER_1(iwmmxt_addcw, i64, i64) +DEF_HELPER_1(iwmmxt_addcl, i64, i64) + +DEF_HELPER_1(iwmmxt_msbb, i32, i64) +DEF_HELPER_1(iwmmxt_msbw, i32, i64) +DEF_HELPER_1(iwmmxt_msbl, i32, i64) + +DEF_HELPER_3(iwmmxt_srlw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_srll, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_srlq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sllw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_slll, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sllq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sraw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sral, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_sraq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_rorw, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_rorl, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_rorq, i64, env, i64, i32) +DEF_HELPER_3(iwmmxt_shufh, i64, env, i64, i32) + +DEF_HELPER_3(iwmmxt_packuw, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packul, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packuq, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packsw, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packsl, i64, env, i64, i64) +DEF_HELPER_3(iwmmxt_packsq, i64, env, i64, i64) + +DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32) +DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32) +DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32) From patchwork Sun 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id k9-20020a7bc409000000b003f6050d35c9sm7820872wmi.20.2023.06.11.01.59.13 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 06/26] target/arm/tcg: Fix iwmmxt-related code style Date: Sun, 11 Jun 2023 10:58:26 +0200 Message-Id: <20230611085846.21415-7-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In order to be able to move the iwmmxt-related code, fix its style to avoid: ERROR: braces {} are necessary for all arms of this statement ERROR: space prohibited before that '++' (ctx:WxB) Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/tcg/translate.c | 227 +++++++++++++++++++++++-------------- 1 file changed, 141 insertions(+), 86 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 13c88ba1b9..3238463f13 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -1441,10 +1441,11 @@ static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, offset = (insn & 0xff) << ((insn >> 7) & 2); if (insn & (1 << 24)) { /* Pre indexed */ - if (insn & (1 << 23)) + if (insn & (1 << 23)) { tcg_gen_addi_i32(tmp, tmp, offset); - else + } else { tcg_gen_addi_i32(tmp, tmp, -offset); + } tcg_gen_mov_i32(dest, tmp); if (insn & (1 << 21)) { store_reg(s, rd, tmp); @@ -1452,13 +1453,15 @@ static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, } else if (insn & (1 << 21)) { /* Post indexed */ tcg_gen_mov_i32(dest, tmp); - if (insn & (1 << 23)) + if (insn & (1 << 23)) { tcg_gen_addi_i32(tmp, tmp, offset); - else + } else { tcg_gen_addi_i32(tmp, tmp, -offset); + } store_reg(s, rd, tmp); - } else if (!(insn & (1 << 23))) + } else if (!(insn & (1 << 23))) { return 1; + } return 0; } @@ -1483,8 +1486,10 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv_i32 dest) return 0; } -/* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred - (ie. an undefined instruction). */ +/* + * Disassemble an iwMMXt instruction. + * Returns nonzero if an error occurred (ie. an undefined instruction). + */ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) { int rd, wrd; @@ -1570,8 +1575,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) return 0; } - if ((insn & 0x0f000000) != 0x0e000000) + if ((insn & 0x0f000000) != 0x0e000000) { return 1; + } switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) { case 0x000: /* WOR */ @@ -1586,8 +1592,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) gen_op_iwmmxt_set_cup(); break; case 0x011: /* TMCR */ - if (insn & 0xf) + if (insn & 0xf) { return 1; + } rd = (insn >> 12) & 0xf; wrd = (insn >> 16) & 0xf; switch (wrd) { @@ -1627,8 +1634,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) gen_op_iwmmxt_set_cup(); break; case 0x111: /* TMRC */ - if (insn & 0xf) + if (insn & 0xf) { return 1; + } rd = (insn >> 12) & 0xf; wrd = (insn >> 16) & 0xf; tmp = iwmmxt_load_creg(wrd); @@ -1662,10 +1670,11 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) rd0 = (insn >> 0) & 0xf; rd1 = (insn >> 16) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_maddsq_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_madduq_M0_wRn(rd1); + } gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); break; @@ -1718,12 +1727,14 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) rd0 = (insn >> 16) & 0xf; rd1 = (insn >> 0) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 22)) + if (insn & (1 << 22)) { gen_op_iwmmxt_sadw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_sadb_M0_wRn(rd1); - if (!(insn & (1 << 20))) + } + if (!(insn & (1 << 20))) { gen_op_iwmmxt_addl_M0_wRn(wrd); + } gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); break; @@ -1733,15 +1744,17 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) rd1 = (insn >> 0) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); if (insn & (1 << 21)) { - if (insn & (1 << 20)) + if (insn & (1 << 20)) { gen_op_iwmmxt_mulshw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_mulslw_M0_wRn(rd1); + } } else { - if (insn & (1 << 20)) + if (insn & (1 << 20)) { gen_op_iwmmxt_muluhw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_mululw_M0_wRn(rd1); + } } gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); @@ -1751,10 +1764,11 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) rd0 = (insn >> 16) & 0xf; rd1 = (insn >> 0) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_macsw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_macuw_M0_wRn(rd1); + } if (!(insn & (1 << 20))) { iwmmxt_load_reg(cpu_V1, wrd); tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); @@ -1790,15 +1804,17 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) rd1 = (insn >> 0) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); if (insn & (1 << 22)) { - if (insn & (1 << 20)) + if (insn & (1 << 20)) { gen_op_iwmmxt_avgw1_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_avgw0_M0_wRn(rd1); + } } else { - if (insn & (1 << 20)) + if (insn & (1 << 20)) { gen_op_iwmmxt_avgb1_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_avgb0_M0_wRn(rd1); + } } gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); @@ -1817,8 +1833,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) gen_op_iwmmxt_set_mup(); break; case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */ - if (((insn >> 6) & 3) == 3) + if (((insn >> 6) & 3) == 3) { return 1; + } rd = (insn >> 12) & 0xf; wrd = (insn >> 16) & 0xf; tmp = load_reg(s, rd); @@ -1846,8 +1863,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */ rd = (insn >> 12) & 0xf; wrd = (insn >> 16) & 0xf; - if (rd == 15 || ((insn >> 22) & 3) == 3) + if (rd == 15 || ((insn >> 22) & 3) == 3) { return 1; + } gen_op_iwmmxt_movq_M0_wRn(wrd); tmp = tcg_temp_new_i32(); switch ((insn >> 22) & 3) { @@ -1877,8 +1895,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) store_reg(s, rd, tmp); break; case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */ - if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3) + if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3) { return 1; + } tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); switch ((insn >> 22) & 3) { case 0: @@ -1895,8 +1914,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) gen_set_nzcv(tmp); break; case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */ - if (((insn >> 6) & 3) == 3) + if (((insn >> 6) & 3) == 3) { return 1; + } rd = (insn >> 12) & 0xf; wrd = (insn >> 16) & 0xf; tmp = load_reg(s, rd); @@ -1915,20 +1935,21 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) gen_op_iwmmxt_set_mup(); break; case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */ - if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) + if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) { return 1; + } tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); tmp2 = tcg_temp_new_i32(); tcg_gen_mov_i32(tmp2, tmp); switch ((insn >> 22) & 3) { case 0: - for (i = 0; i < 7; i ++) { + for (i = 0; i < 7; i++) { tcg_gen_shli_i32(tmp2, tmp2, 4); tcg_gen_and_i32(tmp, tmp, tmp2); } break; case 1: - for (i = 0; i < 3; i ++) { + for (i = 0; i < 3; i++) { tcg_gen_shli_i32(tmp2, tmp2, 8); tcg_gen_and_i32(tmp, tmp, tmp2); } @@ -1961,20 +1982,21 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) gen_op_iwmmxt_set_mup(); break; case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */ - if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) + if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) { return 1; + } tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); tmp2 = tcg_temp_new_i32(); tcg_gen_mov_i32(tmp2, tmp); switch ((insn >> 22) & 3) { case 0: - for (i = 0; i < 7; i ++) { + for (i = 0; i < 7; i++) { tcg_gen_shli_i32(tmp2, tmp2, 4); tcg_gen_or_i32(tmp, tmp, tmp2); } break; case 1: - for (i = 0; i < 3; i ++) { + for (i = 0; i < 3; i++) { tcg_gen_shli_i32(tmp2, tmp2, 8); tcg_gen_or_i32(tmp, tmp, tmp2); } @@ -1989,8 +2011,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */ rd = (insn >> 12) & 0xf; rd0 = (insn >> 16) & 0xf; - if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3) + if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3) { return 1; + } gen_op_iwmmxt_movq_M0_wRn(rd0); tmp = tcg_temp_new_i32(); switch ((insn >> 22) & 3) { @@ -2014,22 +2037,25 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) gen_op_iwmmxt_movq_M0_wRn(rd0); switch ((insn >> 22) & 3) { case 0: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_cmpgtub_M0_wRn(rd1); + } break; case 1: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1); + } break; case 2: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_cmpgtul_M0_wRn(rd1); + } break; case 3: return 1; @@ -2045,22 +2071,25 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) gen_op_iwmmxt_movq_M0_wRn(rd0); switch ((insn >> 22) & 3) { case 0: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_unpacklsb_M0(); - else + } else { gen_op_iwmmxt_unpacklub_M0(); + } break; case 1: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_unpacklsw_M0(); - else + } else { gen_op_iwmmxt_unpackluw_M0(); + } break; case 2: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_unpacklsl_M0(); - else + } else { gen_op_iwmmxt_unpacklul_M0(); + } break; case 3: return 1; @@ -2076,22 +2105,25 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) gen_op_iwmmxt_movq_M0_wRn(rd0); switch ((insn >> 22) & 3) { case 0: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_unpackhsb_M0(); - else + } else { gen_op_iwmmxt_unpackhub_M0(); + } break; case 1: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_unpackhsw_M0(); - else + } else { gen_op_iwmmxt_unpackhuw_M0(); + } break; case 2: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_unpackhsl_M0(); - else + } else { gen_op_iwmmxt_unpackhul_M0(); + } break; case 3: return 1; @@ -2102,8 +2134,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) break; case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */ case 0x214: case 0x614: case 0xa14: case 0xe14: - if (((insn >> 22) & 3) == 0) + if (((insn >> 22) & 3) == 0) { return 1; + } wrd = (insn >> 12) & 0xf; rd0 = (insn >> 16) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); @@ -2128,8 +2161,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) break; case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */ case 0x014: case 0x414: case 0x814: case 0xc14: - if (((insn >> 22) & 3) == 0) + if (((insn >> 22) & 3) == 0) { return 1; + } wrd = (insn >> 12) & 0xf; rd0 = (insn >> 16) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); @@ -2154,8 +2188,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) break; case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */ case 0x114: case 0x514: case 0x914: case 0xd14: - if (((insn >> 22) & 3) == 0) + if (((insn >> 22) & 3) == 0) { return 1; + } wrd = (insn >> 12) & 0xf; rd0 = (insn >> 16) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); @@ -2180,8 +2215,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) break; case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */ case 0x314: case 0x714: case 0xb14: case 0xf14: - if (((insn >> 22) & 3) == 0) + if (((insn >> 22) & 3) == 0) { return 1; + } wrd = (insn >> 12) & 0xf; rd0 = (insn >> 16) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); @@ -2218,22 +2254,25 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) gen_op_iwmmxt_movq_M0_wRn(rd0); switch ((insn >> 22) & 3) { case 0: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_minsb_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_minub_M0_wRn(rd1); + } break; case 1: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_minsw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_minuw_M0_wRn(rd1); + } break; case 2: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_minsl_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_minul_M0_wRn(rd1); + } break; case 3: return 1; @@ -2249,22 +2288,25 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) gen_op_iwmmxt_movq_M0_wRn(rd0); switch ((insn >> 22) & 3) { case 0: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_maxsb_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_maxub_M0_wRn(rd1); + } break; case 1: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_maxsw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_maxuw_M0_wRn(rd1); + } break; case 2: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_maxsl_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_maxul_M0_wRn(rd1); + } break; case 3: return 1; @@ -2387,30 +2429,34 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) case 0x408: case 0x508: case 0x608: case 0x708: case 0x808: case 0x908: case 0xa08: case 0xb08: case 0xc08: case 0xd08: case 0xe08: case 0xf08: - if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0) + if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0) { return 1; + } wrd = (insn >> 12) & 0xf; rd0 = (insn >> 16) & 0xf; rd1 = (insn >> 0) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); switch ((insn >> 22) & 3) { case 1: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_packsw_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_packuw_M0_wRn(rd1); + } break; case 2: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_packsl_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_packul_M0_wRn(rd1); + } break; case 3: - if (insn & (1 << 21)) + if (insn & (1 << 21)) { gen_op_iwmmxt_packsq_M0_wRn(rd1); - else + } else { gen_op_iwmmxt_packuq_M0_wRn(rd1); + } break; } gen_op_iwmmxt_movq_wRn_M0(wrd); @@ -2424,8 +2470,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) wrd = (insn >> 5) & 0xf; rd0 = (insn >> 12) & 0xf; rd1 = (insn >> 0) & 0xf; - if (rd0 == 0xf || rd1 == 0xf) + if (rd0 == 0xf || rd1 == 0xf) { return 1; + } gen_op_iwmmxt_movq_M0_wRn(wrd); tmp = load_reg(s, rd0); tmp2 = load_reg(s, rd1); @@ -2437,10 +2484,12 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); break; case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */ - if (insn & (1 << 16)) + if (insn & (1 << 16)) { tcg_gen_shri_i32(tmp, tmp, 16); - if (insn & (1 << 17)) + } + if (insn & (1 << 17)) { tcg_gen_shri_i32(tmp2, tmp2, 16); + } gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); break; default: @@ -2456,8 +2505,10 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) return 0; } -/* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred - (ie. an undefined instruction). */ +/* + * Disassemble an XScale DSP instruction. + * Returns nonzero if an error occurred (ie. an undefined instruction). + */ static int disas_dsp_insn(DisasContext *s, uint32_t insn) { int acc, rd0, rd1, rdhi, rdlo; @@ -2469,8 +2520,9 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn) rd1 = insn & 0xf; acc = (insn >> 5) & 7; - if (acc != 0) + if (acc != 0) { return 1; + } tmp = load_reg(s, rd0); tmp2 = load_reg(s, rd1); @@ -2485,10 +2537,12 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn) case 0xd: /* MIABT */ case 0xe: /* MIATB */ case 0xf: /* MIATT */ - if (insn & (1 << 16)) + if (insn & (1 << 16)) { tcg_gen_shri_i32(tmp, tmp, 16); - if (insn & (1 << 17)) + } + if (insn & (1 << 17)) { tcg_gen_shri_i32(tmp2, tmp2, 16); + } gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); break; default: @@ -2505,8 +2559,9 @@ static int disas_dsp_insn(DisasContext *s, uint32_t insn) rdlo = (insn >> 12) & 0xf; acc = insn & 7; - if (acc != 0) + if (acc != 0) { return 1; + } if (insn & ARM_CP_RW_BIT) { /* MRA */ iwmmxt_load_reg(cpu_V0, acc); From patchwork Sun Jun 11 08:58:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691364 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1572825wru; Sun, 11 Jun 2023 02:06:56 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ67cVHKfP2xfAPKQ4J9GhjS9mb2tedTMjp6MAuz0En9W+PT4jhWLRJ8fan5iidLzpz9bQVt X-Received: by 2002:a05:622a:178e:b0:3f4:dec2:76cc with SMTP id s14-20020a05622a178e00b003f4dec276ccmr8616691qtk.49.1686474416812; Sun, 11 Jun 2023 02:06:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474416; cv=none; d=google.com; s=arc-20160816; b=dZPNuda4nQb4+OgE7hHHBxW9OdpjTy0kK6+jtohjsGqpph1CJ+lwsdLkZskPrtqVr3 NqX2Srzhkl0sGQitZhcRfLN+U6WAAvsH2qAEdjQOnSHhGcI6oKWgCG2P1jyYADj6Ql/S iOboQ3T14wVGw6zkR7c9vuB4eNjvM56/41CRJSFaf2o4Rx24UtytJtI3KZRc4qXwkwuH CpOSG38c7xB8ITy/Gxl708o6KbXZW5+gEXIeYQ6gJJo5RAUyQjlQFUBs5bvA9NfUf5XV gaPh5Lns5mD8pobNdtfM9rzoRIyi9ldrN1dVzU6G/7o7Fvk7tASlgkqH/A+rqvOtTUZF E60g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=PL1Zih1O88caRvf7sSFHzFYcTBs6PNvq9qmGaaGGlCI=; b=pMygRp15tjpdRXfesIZ2LkaJpAj6sGg3/SJSUIEdPcxotj+euJh8ue4ww8fcJ7kRXR loSEEa7QLBxz4dmtJuLzJ0DBqB8djD5OGTvnkw8ymK5rWmSq0dUETfTCSWng543tS6EP 6hQkt1JGuE8SWMu8jvB/9NlLnVptpGHDhJjr9MdUo5sn1p/QKpXm8YB5pplA3b3w7RYO 208v9RmuPiiSrtmzX2tEjj+Iv65S3nyktROp/9211NPrfCuhiBerJrS3Li6oHPL4P1V+ DUgLATgrVH/NrC2ZR/RYOdzvF4XWOjMAqlKvmve/FerjwjpCTxLQr1cTYrsWYm/RHlQr axKA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=NdbJcpQT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id b5-20020adff905000000b0030aedb8156esm8998995wrr.102.2023.06.11.01.59.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 07/26] target/arm/tcg: Expose some iwmmxt methods in 'translate.h' Date: Sun, 11 Jun 2023 10:58:27 +0200 Message-Id: <20230611085846.21415-8-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=philmd@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Expose a few methods and variables before extracting iwmmxt code from translate.c. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/tcg/translate.h | 6 ++++++ target/arm/tcg/translate.c | 8 ++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index d1cacff0b2..3d7c55d3b6 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -165,6 +165,7 @@ typedef struct DisasCompare { } DisasCompare; /* Share the TCG temporaries common between 32 and 64 bit modes. */ +extern TCGv_i32 cpu_R[16]; extern TCGv_i32 cpu_NF, cpu_ZF, cpu_CF, cpu_VF; extern TCGv_i64 cpu_exclusive_addr; extern TCGv_i64 cpu_exclusive_val; @@ -298,6 +299,11 @@ static inline int curr_insn_len(DisasContext *s) /* CPU state was modified dynamically; no need to exit, but do not chain. */ #define DISAS_UPDATE_NOCHAIN DISAS_TARGET_10 +/* These are TCG temporaries used only by the legacy iwMMXt decoder */ +extern TCGv_i64 cpu_V0, cpu_V1, cpu_M0; +int disas_iwmmxt_insn(DisasContext *s, uint32_t insn); +int disas_dsp_insn(DisasContext *s, uint32_t insn); + #ifdef TARGET_AARCH64 void a64_translate_init(void); void gen_a64_update_pc(DisasContext *s, target_long diff); diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 3238463f13..aaa479521e 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -45,9 +45,9 @@ #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) /* These are TCG temporaries used only by the legacy iwMMXt decoder */ -static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; +TCGv_i64 cpu_V0, cpu_V1, cpu_M0; /* These are TCG globals which alias CPUARMState fields */ -static TCGv_i32 cpu_R[16]; +TCGv_i32 cpu_R[16]; TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; TCGv_i64 cpu_exclusive_addr; TCGv_i64 cpu_exclusive_val; @@ -1490,7 +1490,7 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv_i32 dest) * Disassemble an iwMMXt instruction. * Returns nonzero if an error occurred (ie. an undefined instruction). */ -static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) +int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) { int rd, wrd; int rdhi, rdlo, rd0, rd1, i; @@ -2509,7 +2509,7 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) * Disassemble an XScale DSP instruction. * Returns nonzero if an error occurred (ie. an undefined instruction). */ -static int disas_dsp_insn(DisasContext *s, uint32_t insn) +int disas_dsp_insn(DisasContext *s, uint32_t insn) { int acc, rd0, rd1, rdhi, rdlo; TCGv_i32 tmp, tmp2; From patchwork Sun Jun 11 08:58:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691359 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1572570wru; Sun, 11 Jun 2023 02:05:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5Pp3JEyFD8ElPDjf896ciWs1Ww9R4x673dEJ+f48x7DH79Uuuy7uEr4vuYDjcYxIODpDeU X-Received: by 2002:a05:620a:6884:b0:760:7766:97e7 with SMTP id rv4-20020a05620a688400b00760776697e7mr502037qkn.52.1686474347718; Sun, 11 Jun 2023 02:05:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474347; cv=none; d=google.com; s=arc-20160816; b=CvemReP84JvpbJJOf9U0+QR108u1PoJa8h0BruCMC+j6wPTBFjkAh3rPIzAarTSKrG lj+yHiowCq7W/yQohhKMLsioad2YjX+/Em/gBDQijCkM90RRqNwlcj2i1I2rLFY3+0Ld p1ePXm8arE8Zu+eAwlu940hYYHTrKiIORCI7LEL0cQTTzFk6ghEHdzen9H4F0ZKpscus dkdsCU5S3UnjbGeSd1hszch85xvtExk5snbsSKwPTEZsb72lOysNjL3Gvqa01sPMjITJ Y/lPdmlCll7SRsjwF2qoigTW020OJ/c9dXwVPsuCiwhq3RWo5bBZ+/Bp8m40W4VBGSXE bebg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=oMLss41euDQaVYpSruIudxIhxmIApSvQmPEdVJISz5I=; b=MM4sk04mjEpNxOw7ytJcGtOS2BsoFy5r+ayCiCXTxu3KSphcd8gMS7Ts1kiB0d7xaR 1ZpCgpLyonEYlKURWArkBMUKGvtNRFc5JqtYi2wLds/PDxFNHp9jtxPk9uyS1F8/pQUx EaC9UARojXExoimQBa3+UOX+GLn0AB69tUJxjwxSzf93gdiGVqsYHuXc6qdXH2X2UU5B tpUXsV3kdDVyByXI9myMPXwhcecVP6Xd6gRmkH9dbP3h8uNGu4lOyo0JQ59xtGmc2a1d A2KJDy/Ktn82DWPvAFQfwVthkiv/tuMjL9+lrwSkmSw9IAibYhrMXWCwf4WxB9rOMm+q J9zw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="O5p/l2P0"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id f13-20020a056000036d00b0030aefa3a957sm9092135wrf.28.2023.06.11.01.59.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:23 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 08/26] target/arm/tcg: Extract iwmmxt code to translate-iwmmxt.c Date: Sun, 11 Jun 2023 10:58:28 +0200 Message-Id: <20230611085846.21415-9-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Extract 1300 lines from the big enough translate.c. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/tcg/translate-iwmmxt.c | 1325 +++++++++++++++++++++++++++++ target/arm/tcg/translate.c | 1312 ---------------------------- target/arm/tcg/meson.build | 1 + 3 files changed, 1326 insertions(+), 1312 deletions(-) create mode 100644 target/arm/tcg/translate-iwmmxt.c diff --git a/target/arm/tcg/translate-iwmmxt.c b/target/arm/tcg/translate-iwmmxt.c new file mode 100644 index 0000000000..57a924c578 --- /dev/null +++ b/target/arm/tcg/translate-iwmmxt.c @@ -0,0 +1,1325 @@ +/* + * XScale iwMMXt translation + * + * Copyright (c) 2007 OpenedHand, Ltd. + * Written by Andrzej Zaborowski + * Copyright (c) 2008 CodeSourcery + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +#include "qemu/osdep.h" +#include "translate.h" +#include "translate-a32.h" + +#define ARM_CP_RW_BIT (1 << 20) + +static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) +{ + tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); +} + +static inline void iwmmxt_store_reg(TCGv_i64 var, int reg) +{ + tcg_gen_st_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); +} + +static inline TCGv_i32 iwmmxt_load_creg(int reg) +{ + TCGv_i32 var = tcg_temp_new_i32(); + tcg_gen_ld_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); + return var; +} + +static inline void iwmmxt_store_creg(int reg, TCGv_i32 var) +{ + tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); +} + +static inline void gen_op_iwmmxt_movq_wRn_M0(int rn) +{ + iwmmxt_store_reg(cpu_M0, rn); +} + +static inline void gen_op_iwmmxt_movq_M0_wRn(int rn) +{ + iwmmxt_load_reg(cpu_M0, rn); +} + +static inline void gen_op_iwmmxt_orq_M0_wRn(int rn) +{ + iwmmxt_load_reg(cpu_V1, rn); + tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1); +} + +static inline void gen_op_iwmmxt_andq_M0_wRn(int rn) +{ + iwmmxt_load_reg(cpu_V1, rn); + tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1); +} + +static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn) +{ + iwmmxt_load_reg(cpu_V1, rn); + tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1); +} + +#define IWMMXT_OP(name) \ +static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ +{ \ + iwmmxt_load_reg(cpu_V1, rn); \ + gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \ +} + +#define IWMMXT_OP_ENV(name) \ +static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ +{ \ + iwmmxt_load_reg(cpu_V1, rn); \ + gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \ +} + +#define IWMMXT_OP_ENV_SIZE(name) \ +IWMMXT_OP_ENV(name##b) \ +IWMMXT_OP_ENV(name##w) \ +IWMMXT_OP_ENV(name##l) + +#define IWMMXT_OP_ENV1(name) \ +static inline void gen_op_iwmmxt_##name##_M0(void) \ +{ \ + gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \ +} + +IWMMXT_OP(maddsq) +IWMMXT_OP(madduq) +IWMMXT_OP(sadb) +IWMMXT_OP(sadw) +IWMMXT_OP(mulslw) +IWMMXT_OP(mulshw) +IWMMXT_OP(mululw) +IWMMXT_OP(muluhw) +IWMMXT_OP(macsw) +IWMMXT_OP(macuw) + +IWMMXT_OP_ENV_SIZE(unpackl) +IWMMXT_OP_ENV_SIZE(unpackh) + +IWMMXT_OP_ENV1(unpacklub) +IWMMXT_OP_ENV1(unpackluw) +IWMMXT_OP_ENV1(unpacklul) +IWMMXT_OP_ENV1(unpackhub) +IWMMXT_OP_ENV1(unpackhuw) +IWMMXT_OP_ENV1(unpackhul) +IWMMXT_OP_ENV1(unpacklsb) +IWMMXT_OP_ENV1(unpacklsw) +IWMMXT_OP_ENV1(unpacklsl) +IWMMXT_OP_ENV1(unpackhsb) +IWMMXT_OP_ENV1(unpackhsw) +IWMMXT_OP_ENV1(unpackhsl) + +IWMMXT_OP_ENV_SIZE(cmpeq) +IWMMXT_OP_ENV_SIZE(cmpgtu) +IWMMXT_OP_ENV_SIZE(cmpgts) + +IWMMXT_OP_ENV_SIZE(mins) +IWMMXT_OP_ENV_SIZE(minu) +IWMMXT_OP_ENV_SIZE(maxs) +IWMMXT_OP_ENV_SIZE(maxu) + +IWMMXT_OP_ENV_SIZE(subn) +IWMMXT_OP_ENV_SIZE(addn) +IWMMXT_OP_ENV_SIZE(subu) +IWMMXT_OP_ENV_SIZE(addu) +IWMMXT_OP_ENV_SIZE(subs) +IWMMXT_OP_ENV_SIZE(adds) + +IWMMXT_OP_ENV(avgb0) +IWMMXT_OP_ENV(avgb1) +IWMMXT_OP_ENV(avgw0) +IWMMXT_OP_ENV(avgw1) + +IWMMXT_OP_ENV(packuw) +IWMMXT_OP_ENV(packul) +IWMMXT_OP_ENV(packuq) +IWMMXT_OP_ENV(packsw) +IWMMXT_OP_ENV(packsl) +IWMMXT_OP_ENV(packsq) + +static void gen_op_iwmmxt_set_mup(void) +{ + TCGv_i32 tmp; + tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); + tcg_gen_ori_i32(tmp, tmp, 2); + store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); +} + +static void gen_op_iwmmxt_set_cup(void) +{ + TCGv_i32 tmp; + tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); + tcg_gen_ori_i32(tmp, tmp, 1); + store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); +} + +static void gen_op_iwmmxt_setpsr_nz(void) +{ + TCGv_i32 tmp = tcg_temp_new_i32(); + gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0); + store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]); +} + +static inline void gen_op_iwmmxt_addl_M0_wRn(int rn) +{ + iwmmxt_load_reg(cpu_V1, rn); + tcg_gen_ext32u_i64(cpu_V1, cpu_V1); + tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); +} + +static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, + TCGv_i32 dest) +{ + int rd; + uint32_t offset; + TCGv_i32 tmp; + + rd = (insn >> 16) & 0xf; + tmp = load_reg(s, rd); + + offset = (insn & 0xff) << ((insn >> 7) & 2); + if (insn & (1 << 24)) { + /* Pre indexed */ + if (insn & (1 << 23)) { + tcg_gen_addi_i32(tmp, tmp, offset); + } else { + tcg_gen_addi_i32(tmp, tmp, -offset); + } + tcg_gen_mov_i32(dest, tmp); + if (insn & (1 << 21)) { + store_reg(s, rd, tmp); + } + } else if (insn & (1 << 21)) { + /* Post indexed */ + tcg_gen_mov_i32(dest, tmp); + if (insn & (1 << 23)) { + tcg_gen_addi_i32(tmp, tmp, offset); + } else { + tcg_gen_addi_i32(tmp, tmp, -offset); + } + store_reg(s, rd, tmp); + } else if (!(insn & (1 << 23))) { + return 1; + } + return 0; +} + +static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv_i32 dest) +{ + int rd = (insn >> 0) & 0xf; + TCGv_i32 tmp; + + if (insn & (1 << 8)) { + if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) { + return 1; + } else { + tmp = iwmmxt_load_creg(rd); + } + } else { + tmp = tcg_temp_new_i32(); + iwmmxt_load_reg(cpu_V0, rd); + tcg_gen_extrl_i64_i32(tmp, cpu_V0); + } + tcg_gen_andi_i32(tmp, tmp, mask); + tcg_gen_mov_i32(dest, tmp); + return 0; +} + +/* + * Disassemble an iwMMXt instruction. + * Returns nonzero if an error occurred (ie. an undefined instruction). + */ +int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) +{ + int rd, wrd; + int rdhi, rdlo, rd0, rd1, i; + TCGv_i32 addr; + TCGv_i32 tmp, tmp2, tmp3; + + if ((insn & 0x0e000e00) == 0x0c000000) { + if ((insn & 0x0fe00ff0) == 0x0c400000) { + wrd = insn & 0xf; + rdlo = (insn >> 12) & 0xf; + rdhi = (insn >> 16) & 0xf; + if (insn & ARM_CP_RW_BIT) { /* TMRRC */ + iwmmxt_load_reg(cpu_V0, wrd); + tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0); + tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0); + } else { /* TMCRR */ + tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); + iwmmxt_store_reg(cpu_V0, wrd); + gen_op_iwmmxt_set_mup(); + } + return 0; + } + + wrd = (insn >> 12) & 0xf; + addr = tcg_temp_new_i32(); + if (gen_iwmmxt_address(s, insn, addr)) { + return 1; + } + if (insn & ARM_CP_RW_BIT) { + if ((insn >> 28) == 0xf) { /* WLDRW wCx */ + tmp = tcg_temp_new_i32(); + gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + iwmmxt_store_creg(wrd, tmp); + } else { + i = 1; + if (insn & (1 << 8)) { + if (insn & (1 << 22)) { /* WLDRD */ + gen_aa32_ld64(s, cpu_M0, addr, get_mem_index(s)); + i = 0; + } else { /* WLDRW wRd */ + tmp = tcg_temp_new_i32(); + gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); + } + } else { + tmp = tcg_temp_new_i32(); + if (insn & (1 << 22)) { /* WLDRH */ + gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); + } else { /* WLDRB */ + gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); + } + } + if (i) { + tcg_gen_extu_i32_i64(cpu_M0, tmp); + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + } + } else { + if ((insn >> 28) == 0xf) { /* WSTRW wCx */ + tmp = iwmmxt_load_creg(wrd); + gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + } else { + gen_op_iwmmxt_movq_M0_wRn(wrd); + tmp = tcg_temp_new_i32(); + if (insn & (1 << 8)) { + if (insn & (1 << 22)) { /* WSTRD */ + gen_aa32_st64(s, cpu_M0, addr, get_mem_index(s)); + } else { /* WSTRW wRd */ + tcg_gen_extrl_i64_i32(tmp, cpu_M0); + gen_aa32_st32(s, tmp, addr, get_mem_index(s)); + } + } else { + if (insn & (1 << 22)) { /* WSTRH */ + tcg_gen_extrl_i64_i32(tmp, cpu_M0); + gen_aa32_st16(s, tmp, addr, get_mem_index(s)); + } else { /* WSTRB */ + tcg_gen_extrl_i64_i32(tmp, cpu_M0); + gen_aa32_st8(s, tmp, addr, get_mem_index(s)); + } + } + } + } + return 0; + } + + if ((insn & 0x0f000000) != 0x0e000000) { + return 1; + } + + switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) { + case 0x000: /* WOR */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 0) & 0xf; + rd1 = (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + gen_op_iwmmxt_orq_M0_wRn(rd1); + gen_op_iwmmxt_setpsr_nz(); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x011: /* TMCR */ + if (insn & 0xf) { + return 1; + } + rd = (insn >> 12) & 0xf; + wrd = (insn >> 16) & 0xf; + switch (wrd) { + case ARM_IWMMXT_wCID: + case ARM_IWMMXT_wCASF: + break; + case ARM_IWMMXT_wCon: + gen_op_iwmmxt_set_cup(); + /* Fall through. */ + case ARM_IWMMXT_wCSSF: + tmp = iwmmxt_load_creg(wrd); + tmp2 = load_reg(s, rd); + tcg_gen_andc_i32(tmp, tmp, tmp2); + iwmmxt_store_creg(wrd, tmp); + break; + case ARM_IWMMXT_wCGR0: + case ARM_IWMMXT_wCGR1: + case ARM_IWMMXT_wCGR2: + case ARM_IWMMXT_wCGR3: + gen_op_iwmmxt_set_cup(); + tmp = load_reg(s, rd); + iwmmxt_store_creg(wrd, tmp); + break; + default: + return 1; + } + break; + case 0x100: /* WXOR */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 0) & 0xf; + rd1 = (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + gen_op_iwmmxt_xorq_M0_wRn(rd1); + gen_op_iwmmxt_setpsr_nz(); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x111: /* TMRC */ + if (insn & 0xf) { + return 1; + } + rd = (insn >> 12) & 0xf; + wrd = (insn >> 16) & 0xf; + tmp = iwmmxt_load_creg(wrd); + store_reg(s, rd, tmp); + break; + case 0x300: /* WANDN */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 0) & 0xf; + rd1 = (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tcg_gen_neg_i64(cpu_M0, cpu_M0); + gen_op_iwmmxt_andq_M0_wRn(rd1); + gen_op_iwmmxt_setpsr_nz(); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x200: /* WAND */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 0) & 0xf; + rd1 = (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + gen_op_iwmmxt_andq_M0_wRn(rd1); + gen_op_iwmmxt_setpsr_nz(); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x810: case 0xa10: /* WMADD */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 0) & 0xf; + rd1 = (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + if (insn & (1 << 21)) { + gen_op_iwmmxt_maddsq_M0_wRn(rd1); + } else { + gen_op_iwmmxt_madduq_M0_wRn(rd1); + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + gen_op_iwmmxt_unpacklb_M0_wRn(rd1); + break; + case 1: + gen_op_iwmmxt_unpacklw_M0_wRn(rd1); + break; + case 2: + gen_op_iwmmxt_unpackll_M0_wRn(rd1); + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + gen_op_iwmmxt_unpackhb_M0_wRn(rd1); + break; + case 1: + gen_op_iwmmxt_unpackhw_M0_wRn(rd1); + break; + case 2: + gen_op_iwmmxt_unpackhl_M0_wRn(rd1); + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + if (insn & (1 << 22)) { + gen_op_iwmmxt_sadw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_sadb_M0_wRn(rd1); + } + if (!(insn & (1 << 20))) { + gen_op_iwmmxt_addl_M0_wRn(wrd); + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + if (insn & (1 << 21)) { + if (insn & (1 << 20)) { + gen_op_iwmmxt_mulshw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_mulslw_M0_wRn(rd1); + } + } else { + if (insn & (1 << 20)) { + gen_op_iwmmxt_muluhw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_mululw_M0_wRn(rd1); + } + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + if (insn & (1 << 21)) { + gen_op_iwmmxt_macsw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_macuw_M0_wRn(rd1); + } + if (!(insn & (1 << 20))) { + iwmmxt_load_reg(cpu_V1, wrd); + tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + gen_op_iwmmxt_cmpeqb_M0_wRn(rd1); + break; + case 1: + gen_op_iwmmxt_cmpeqw_M0_wRn(rd1); + break; + case 2: + gen_op_iwmmxt_cmpeql_M0_wRn(rd1); + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + if (insn & (1 << 22)) { + if (insn & (1 << 20)) { + gen_op_iwmmxt_avgw1_M0_wRn(rd1); + } else { + gen_op_iwmmxt_avgw0_M0_wRn(rd1); + } + } else { + if (insn & (1 << 20)) { + gen_op_iwmmxt_avgb1_M0_wRn(rd1); + } else { + gen_op_iwmmxt_avgb0_M0_wRn(rd1); + } + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3)); + tcg_gen_andi_i32(tmp, tmp, 7); + iwmmxt_load_reg(cpu_V1, rd1); + gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */ + if (((insn >> 6) & 3) == 3) { + return 1; + } + rd = (insn >> 12) & 0xf; + wrd = (insn >> 16) & 0xf; + tmp = load_reg(s, rd); + gen_op_iwmmxt_movq_M0_wRn(wrd); + switch ((insn >> 6) & 3) { + case 0: + tmp2 = tcg_constant_i32(0xff); + tmp3 = tcg_constant_i32((insn & 7) << 3); + break; + case 1: + tmp2 = tcg_constant_i32(0xffff); + tmp3 = tcg_constant_i32((insn & 3) << 4); + break; + case 2: + tmp2 = tcg_constant_i32(0xffffffff); + tmp3 = tcg_constant_i32((insn & 1) << 5); + break; + default: + g_assert_not_reached(); + } + gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */ + rd = (insn >> 12) & 0xf; + wrd = (insn >> 16) & 0xf; + if (rd == 15 || ((insn >> 22) & 3) == 3) { + return 1; + } + gen_op_iwmmxt_movq_M0_wRn(wrd); + tmp = tcg_temp_new_i32(); + switch ((insn >> 22) & 3) { + case 0: + tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3); + tcg_gen_extrl_i64_i32(tmp, cpu_M0); + if (insn & 8) { + tcg_gen_ext8s_i32(tmp, tmp); + } else { + tcg_gen_andi_i32(tmp, tmp, 0xff); + } + break; + case 1: + tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4); + tcg_gen_extrl_i64_i32(tmp, cpu_M0); + if (insn & 8) { + tcg_gen_ext16s_i32(tmp, tmp); + } else { + tcg_gen_andi_i32(tmp, tmp, 0xffff); + } + break; + case 2: + tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5); + tcg_gen_extrl_i64_i32(tmp, cpu_M0); + break; + } + store_reg(s, rd, tmp); + break; + case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */ + if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3) { + return 1; + } + tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); + switch ((insn >> 22) & 3) { + case 0: + tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0); + break; + case 1: + tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4); + break; + case 2: + tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12); + break; + } + tcg_gen_shli_i32(tmp, tmp, 28); + gen_set_nzcv(tmp); + break; + case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */ + if (((insn >> 6) & 3) == 3) { + return 1; + } + rd = (insn >> 12) & 0xf; + wrd = (insn >> 16) & 0xf; + tmp = load_reg(s, rd); + switch ((insn >> 6) & 3) { + case 0: + gen_helper_iwmmxt_bcstb(cpu_M0, tmp); + break; + case 1: + gen_helper_iwmmxt_bcstw(cpu_M0, tmp); + break; + case 2: + gen_helper_iwmmxt_bcstl(cpu_M0, tmp); + break; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */ + if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) { + return 1; + } + tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); + tmp2 = tcg_temp_new_i32(); + tcg_gen_mov_i32(tmp2, tmp); + switch ((insn >> 22) & 3) { + case 0: + for (i = 0; i < 7; i++) { + tcg_gen_shli_i32(tmp2, tmp2, 4); + tcg_gen_and_i32(tmp, tmp, tmp2); + } + break; + case 1: + for (i = 0; i < 3; i++) { + tcg_gen_shli_i32(tmp2, tmp2, 8); + tcg_gen_and_i32(tmp, tmp, tmp2); + } + break; + case 2: + tcg_gen_shli_i32(tmp2, tmp2, 16); + tcg_gen_and_i32(tmp, tmp, tmp2); + break; + } + gen_set_nzcv(tmp); + break; + case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */ + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0); + break; + case 1: + gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0); + break; + case 2: + gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0); + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */ + if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) { + return 1; + } + tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); + tmp2 = tcg_temp_new_i32(); + tcg_gen_mov_i32(tmp2, tmp); + switch ((insn >> 22) & 3) { + case 0: + for (i = 0; i < 7; i++) { + tcg_gen_shli_i32(tmp2, tmp2, 4); + tcg_gen_or_i32(tmp, tmp, tmp2); + } + break; + case 1: + for (i = 0; i < 3; i++) { + tcg_gen_shli_i32(tmp2, tmp2, 8); + tcg_gen_or_i32(tmp, tmp, tmp2); + } + break; + case 2: + tcg_gen_shli_i32(tmp2, tmp2, 16); + tcg_gen_or_i32(tmp, tmp, tmp2); + break; + } + gen_set_nzcv(tmp); + break; + case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */ + rd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3) { + return 1; + } + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp = tcg_temp_new_i32(); + switch ((insn >> 22) & 3) { + case 0: + gen_helper_iwmmxt_msbb(tmp, cpu_M0); + break; + case 1: + gen_helper_iwmmxt_msbw(tmp, cpu_M0); + break; + case 2: + gen_helper_iwmmxt_msbl(tmp, cpu_M0); + break; + } + store_reg(s, rd, tmp); + break; + case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */ + case 0x906: case 0xb06: case 0xd06: case 0xf06: + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + if (insn & (1 << 21)) { + gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1); + } else { + gen_op_iwmmxt_cmpgtub_M0_wRn(rd1); + } + break; + case 1: + if (insn & (1 << 21)) { + gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1); + } + break; + case 2: + if (insn & (1 << 21)) { + gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1); + } else { + gen_op_iwmmxt_cmpgtul_M0_wRn(rd1); + } + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */ + case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e: + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + if (insn & (1 << 21)) { + gen_op_iwmmxt_unpacklsb_M0(); + } else { + gen_op_iwmmxt_unpacklub_M0(); + } + break; + case 1: + if (insn & (1 << 21)) { + gen_op_iwmmxt_unpacklsw_M0(); + } else { + gen_op_iwmmxt_unpackluw_M0(); + } + break; + case 2: + if (insn & (1 << 21)) { + gen_op_iwmmxt_unpacklsl_M0(); + } else { + gen_op_iwmmxt_unpacklul_M0(); + } + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */ + case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c: + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + if (insn & (1 << 21)) { + gen_op_iwmmxt_unpackhsb_M0(); + } else { + gen_op_iwmmxt_unpackhub_M0(); + } + break; + case 1: + if (insn & (1 << 21)) { + gen_op_iwmmxt_unpackhsw_M0(); + } else { + gen_op_iwmmxt_unpackhuw_M0(); + } + break; + case 2: + if (insn & (1 << 21)) { + gen_op_iwmmxt_unpackhsl_M0(); + } else { + gen_op_iwmmxt_unpackhul_M0(); + } + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */ + case 0x214: case 0x614: case 0xa14: case 0xe14: + if (((insn >> 22) & 3) == 0) { + return 1; + } + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp = tcg_temp_new_i32(); + if (gen_iwmmxt_shift(insn, 0xff, tmp)) { + return 1; + } + switch ((insn >> 22) & 3) { + case 1: + gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 2: + gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 3: + gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp); + break; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */ + case 0x014: case 0x414: case 0x814: case 0xc14: + if (((insn >> 22) & 3) == 0) { + return 1; + } + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp = tcg_temp_new_i32(); + if (gen_iwmmxt_shift(insn, 0xff, tmp)) { + return 1; + } + switch ((insn >> 22) & 3) { + case 1: + gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 2: + gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 3: + gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp); + break; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */ + case 0x114: case 0x514: case 0x914: case 0xd14: + if (((insn >> 22) & 3) == 0) { + return 1; + } + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp = tcg_temp_new_i32(); + if (gen_iwmmxt_shift(insn, 0xff, tmp)) { + return 1; + } + switch ((insn >> 22) & 3) { + case 1: + gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 2: + gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 3: + gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp); + break; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */ + case 0x314: case 0x714: case 0xb14: case 0xf14: + if (((insn >> 22) & 3) == 0) { + return 1; + } + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp = tcg_temp_new_i32(); + switch ((insn >> 22) & 3) { + case 1: + if (gen_iwmmxt_shift(insn, 0xf, tmp)) { + return 1; + } + gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 2: + if (gen_iwmmxt_shift(insn, 0x1f, tmp)) { + return 1; + } + gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp); + break; + case 3: + if (gen_iwmmxt_shift(insn, 0x3f, tmp)) { + return 1; + } + gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp); + break; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */ + case 0x916: case 0xb16: case 0xd16: case 0xf16: + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + if (insn & (1 << 21)) { + gen_op_iwmmxt_minsb_M0_wRn(rd1); + } else { + gen_op_iwmmxt_minub_M0_wRn(rd1); + } + break; + case 1: + if (insn & (1 << 21)) { + gen_op_iwmmxt_minsw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_minuw_M0_wRn(rd1); + } + break; + case 2: + if (insn & (1 << 21)) { + gen_op_iwmmxt_minsl_M0_wRn(rd1); + } else { + gen_op_iwmmxt_minul_M0_wRn(rd1); + } + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */ + case 0x816: case 0xa16: case 0xc16: case 0xe16: + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 0: + if (insn & (1 << 21)) { + gen_op_iwmmxt_maxsb_M0_wRn(rd1); + } else { + gen_op_iwmmxt_maxub_M0_wRn(rd1); + } + break; + case 1: + if (insn & (1 << 21)) { + gen_op_iwmmxt_maxsw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_maxuw_M0_wRn(rd1); + } + break; + case 2: + if (insn & (1 << 21)) { + gen_op_iwmmxt_maxsl_M0_wRn(rd1); + } else { + gen_op_iwmmxt_maxul_M0_wRn(rd1); + } + break; + case 3: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */ + case 0x402: case 0x502: case 0x602: case 0x702: + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + iwmmxt_load_reg(cpu_V1, rd1); + gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, + tcg_constant_i32((insn >> 20) & 3)); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */ + case 0x41a: case 0x51a: case 0x61a: case 0x71a: + case 0x81a: case 0x91a: case 0xa1a: case 0xb1a: + case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a: + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 20) & 0xf) { + case 0x0: + gen_op_iwmmxt_subnb_M0_wRn(rd1); + break; + case 0x1: + gen_op_iwmmxt_subub_M0_wRn(rd1); + break; + case 0x3: + gen_op_iwmmxt_subsb_M0_wRn(rd1); + break; + case 0x4: + gen_op_iwmmxt_subnw_M0_wRn(rd1); + break; + case 0x5: + gen_op_iwmmxt_subuw_M0_wRn(rd1); + break; + case 0x7: + gen_op_iwmmxt_subsw_M0_wRn(rd1); + break; + case 0x8: + gen_op_iwmmxt_subnl_M0_wRn(rd1); + break; + case 0x9: + gen_op_iwmmxt_subul_M0_wRn(rd1); + break; + case 0xb: + gen_op_iwmmxt_subsl_M0_wRn(rd1); + break; + default: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */ + case 0x41e: case 0x51e: case 0x61e: case 0x71e: + case 0x81e: case 0x91e: case 0xa1e: case 0xb1e: + case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e: + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + tmp = tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); + gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp); + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */ + case 0x418: case 0x518: case 0x618: case 0x718: + case 0x818: case 0x918: case 0xa18: case 0xb18: + case 0xc18: case 0xd18: case 0xe18: case 0xf18: + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 20) & 0xf) { + case 0x0: + gen_op_iwmmxt_addnb_M0_wRn(rd1); + break; + case 0x1: + gen_op_iwmmxt_addub_M0_wRn(rd1); + break; + case 0x3: + gen_op_iwmmxt_addsb_M0_wRn(rd1); + break; + case 0x4: + gen_op_iwmmxt_addnw_M0_wRn(rd1); + break; + case 0x5: + gen_op_iwmmxt_adduw_M0_wRn(rd1); + break; + case 0x7: + gen_op_iwmmxt_addsw_M0_wRn(rd1); + break; + case 0x8: + gen_op_iwmmxt_addnl_M0_wRn(rd1); + break; + case 0x9: + gen_op_iwmmxt_addul_M0_wRn(rd1); + break; + case 0xb: + gen_op_iwmmxt_addsl_M0_wRn(rd1); + break; + default: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */ + case 0x408: case 0x508: case 0x608: case 0x708: + case 0x808: case 0x908: case 0xa08: case 0xb08: + case 0xc08: case 0xd08: case 0xe08: case 0xf08: + if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0) { + return 1; + } + wrd = (insn >> 12) & 0xf; + rd0 = (insn >> 16) & 0xf; + rd1 = (insn >> 0) & 0xf; + gen_op_iwmmxt_movq_M0_wRn(rd0); + switch ((insn >> 22) & 3) { + case 1: + if (insn & (1 << 21)) { + gen_op_iwmmxt_packsw_M0_wRn(rd1); + } else { + gen_op_iwmmxt_packuw_M0_wRn(rd1); + } + break; + case 2: + if (insn & (1 << 21)) { + gen_op_iwmmxt_packsl_M0_wRn(rd1); + } else { + gen_op_iwmmxt_packul_M0_wRn(rd1); + } + break; + case 3: + if (insn & (1 << 21)) { + gen_op_iwmmxt_packsq_M0_wRn(rd1); + } else { + gen_op_iwmmxt_packuq_M0_wRn(rd1); + } + break; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + gen_op_iwmmxt_set_cup(); + break; + case 0x201: case 0x203: case 0x205: case 0x207: + case 0x209: case 0x20b: case 0x20d: case 0x20f: + case 0x211: case 0x213: case 0x215: case 0x217: + case 0x219: case 0x21b: case 0x21d: case 0x21f: + wrd = (insn >> 5) & 0xf; + rd0 = (insn >> 12) & 0xf; + rd1 = (insn >> 0) & 0xf; + if (rd0 == 0xf || rd1 == 0xf) { + return 1; + } + gen_op_iwmmxt_movq_M0_wRn(wrd); + tmp = load_reg(s, rd0); + tmp2 = load_reg(s, rd1); + switch ((insn >> 16) & 0xf) { + case 0x0: /* TMIA */ + gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); + break; + case 0x8: /* TMIAPH */ + gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); + break; + case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */ + if (insn & (1 << 16)) { + tcg_gen_shri_i32(tmp, tmp, 16); + } + if (insn & (1 << 17)) { + tcg_gen_shri_i32(tmp2, tmp2, 16); + } + gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); + break; + default: + return 1; + } + gen_op_iwmmxt_movq_wRn_M0(wrd); + gen_op_iwmmxt_set_mup(); + break; + default: + return 1; + } + + return 0; +} + +/* + * Disassemble an XScale DSP instruction. + * Returns nonzero if an error occurred (ie. an undefined instruction). + */ +int disas_dsp_insn(DisasContext *s, uint32_t insn) +{ + int acc, rd0, rd1, rdhi, rdlo; + TCGv_i32 tmp, tmp2; + + if ((insn & 0x0ff00f10) == 0x0e200010) { + /* Multiply with Internal Accumulate Format */ + rd0 = (insn >> 12) & 0xf; + rd1 = insn & 0xf; + acc = (insn >> 5) & 7; + + if (acc != 0) { + return 1; + } + + tmp = load_reg(s, rd0); + tmp2 = load_reg(s, rd1); + switch ((insn >> 16) & 0xf) { + case 0x0: /* MIA */ + gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); + break; + case 0x8: /* MIAPH */ + gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); + break; + case 0xc: /* MIABB */ + case 0xd: /* MIABT */ + case 0xe: /* MIATB */ + case 0xf: /* MIATT */ + if (insn & (1 << 16)) { + tcg_gen_shri_i32(tmp, tmp, 16); + } + if (insn & (1 << 17)) { + tcg_gen_shri_i32(tmp2, tmp2, 16); + } + gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); + break; + default: + return 1; + } + + gen_op_iwmmxt_movq_wRn_M0(acc); + return 0; + } + + if ((insn & 0x0fe00ff8) == 0x0c400000) { + /* Internal Accumulator Access Format */ + rdhi = (insn >> 16) & 0xf; + rdlo = (insn >> 12) & 0xf; + acc = insn & 7; + + if (acc != 0) { + return 1; + } + + if (insn & ARM_CP_RW_BIT) { /* MRA */ + iwmmxt_load_reg(cpu_V0, acc); + tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0); + tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0); + tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1); + } else { /* MAR */ + tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); + iwmmxt_store_reg(cpu_V0, acc); + } + return 0; + } + + return 1; +} diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index aaa479521e..a352fced6e 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -1266,1318 +1266,6 @@ void write_neon_element64(TCGv_i64 src, int reg, int ele, MemOp memop) } } -#define ARM_CP_RW_BIT (1 << 20) - -static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) -{ - tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); -} - -static inline void iwmmxt_store_reg(TCGv_i64 var, int reg) -{ - tcg_gen_st_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg])); -} - -static inline TCGv_i32 iwmmxt_load_creg(int reg) -{ - TCGv_i32 var = tcg_temp_new_i32(); - tcg_gen_ld_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); - return var; -} - -static inline void iwmmxt_store_creg(int reg, TCGv_i32 var) -{ - tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg])); -} - -static inline void gen_op_iwmmxt_movq_wRn_M0(int rn) -{ - iwmmxt_store_reg(cpu_M0, rn); -} - -static inline void gen_op_iwmmxt_movq_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_M0, rn); -} - -static inline void gen_op_iwmmxt_orq_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_V1, rn); - tcg_gen_or_i64(cpu_M0, cpu_M0, cpu_V1); -} - -static inline void gen_op_iwmmxt_andq_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_V1, rn); - tcg_gen_and_i64(cpu_M0, cpu_M0, cpu_V1); -} - -static inline void gen_op_iwmmxt_xorq_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_V1, rn); - tcg_gen_xor_i64(cpu_M0, cpu_M0, cpu_V1); -} - -#define IWMMXT_OP(name) \ -static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ -{ \ - iwmmxt_load_reg(cpu_V1, rn); \ - gen_helper_iwmmxt_##name(cpu_M0, cpu_M0, cpu_V1); \ -} - -#define IWMMXT_OP_ENV(name) \ -static inline void gen_op_iwmmxt_##name##_M0_wRn(int rn) \ -{ \ - iwmmxt_load_reg(cpu_V1, rn); \ - gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0, cpu_V1); \ -} - -#define IWMMXT_OP_ENV_SIZE(name) \ -IWMMXT_OP_ENV(name##b) \ -IWMMXT_OP_ENV(name##w) \ -IWMMXT_OP_ENV(name##l) - -#define IWMMXT_OP_ENV1(name) \ -static inline void gen_op_iwmmxt_##name##_M0(void) \ -{ \ - gen_helper_iwmmxt_##name(cpu_M0, cpu_env, cpu_M0); \ -} - -IWMMXT_OP(maddsq) -IWMMXT_OP(madduq) -IWMMXT_OP(sadb) -IWMMXT_OP(sadw) -IWMMXT_OP(mulslw) -IWMMXT_OP(mulshw) -IWMMXT_OP(mululw) -IWMMXT_OP(muluhw) -IWMMXT_OP(macsw) -IWMMXT_OP(macuw) - -IWMMXT_OP_ENV_SIZE(unpackl) -IWMMXT_OP_ENV_SIZE(unpackh) - -IWMMXT_OP_ENV1(unpacklub) -IWMMXT_OP_ENV1(unpackluw) -IWMMXT_OP_ENV1(unpacklul) -IWMMXT_OP_ENV1(unpackhub) -IWMMXT_OP_ENV1(unpackhuw) -IWMMXT_OP_ENV1(unpackhul) -IWMMXT_OP_ENV1(unpacklsb) -IWMMXT_OP_ENV1(unpacklsw) -IWMMXT_OP_ENV1(unpacklsl) -IWMMXT_OP_ENV1(unpackhsb) -IWMMXT_OP_ENV1(unpackhsw) -IWMMXT_OP_ENV1(unpackhsl) - -IWMMXT_OP_ENV_SIZE(cmpeq) -IWMMXT_OP_ENV_SIZE(cmpgtu) -IWMMXT_OP_ENV_SIZE(cmpgts) - -IWMMXT_OP_ENV_SIZE(mins) -IWMMXT_OP_ENV_SIZE(minu) -IWMMXT_OP_ENV_SIZE(maxs) -IWMMXT_OP_ENV_SIZE(maxu) - -IWMMXT_OP_ENV_SIZE(subn) -IWMMXT_OP_ENV_SIZE(addn) -IWMMXT_OP_ENV_SIZE(subu) -IWMMXT_OP_ENV_SIZE(addu) -IWMMXT_OP_ENV_SIZE(subs) -IWMMXT_OP_ENV_SIZE(adds) - -IWMMXT_OP_ENV(avgb0) -IWMMXT_OP_ENV(avgb1) -IWMMXT_OP_ENV(avgw0) -IWMMXT_OP_ENV(avgw1) - -IWMMXT_OP_ENV(packuw) -IWMMXT_OP_ENV(packul) -IWMMXT_OP_ENV(packuq) -IWMMXT_OP_ENV(packsw) -IWMMXT_OP_ENV(packsl) -IWMMXT_OP_ENV(packsq) - -static void gen_op_iwmmxt_set_mup(void) -{ - TCGv_i32 tmp; - tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); - tcg_gen_ori_i32(tmp, tmp, 2); - store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); -} - -static void gen_op_iwmmxt_set_cup(void) -{ - TCGv_i32 tmp; - tmp = load_cpu_field(iwmmxt.cregs[ARM_IWMMXT_wCon]); - tcg_gen_ori_i32(tmp, tmp, 1); - store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCon]); -} - -static void gen_op_iwmmxt_setpsr_nz(void) -{ - TCGv_i32 tmp = tcg_temp_new_i32(); - gen_helper_iwmmxt_setpsr_nz(tmp, cpu_M0); - store_cpu_field(tmp, iwmmxt.cregs[ARM_IWMMXT_wCASF]); -} - -static inline void gen_op_iwmmxt_addl_M0_wRn(int rn) -{ - iwmmxt_load_reg(cpu_V1, rn); - tcg_gen_ext32u_i64(cpu_V1, cpu_V1); - tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); -} - -static inline int gen_iwmmxt_address(DisasContext *s, uint32_t insn, - TCGv_i32 dest) -{ - int rd; - uint32_t offset; - TCGv_i32 tmp; - - rd = (insn >> 16) & 0xf; - tmp = load_reg(s, rd); - - offset = (insn & 0xff) << ((insn >> 7) & 2); - if (insn & (1 << 24)) { - /* Pre indexed */ - if (insn & (1 << 23)) { - tcg_gen_addi_i32(tmp, tmp, offset); - } else { - tcg_gen_addi_i32(tmp, tmp, -offset); - } - tcg_gen_mov_i32(dest, tmp); - if (insn & (1 << 21)) { - store_reg(s, rd, tmp); - } - } else if (insn & (1 << 21)) { - /* Post indexed */ - tcg_gen_mov_i32(dest, tmp); - if (insn & (1 << 23)) { - tcg_gen_addi_i32(tmp, tmp, offset); - } else { - tcg_gen_addi_i32(tmp, tmp, -offset); - } - store_reg(s, rd, tmp); - } else if (!(insn & (1 << 23))) { - return 1; - } - return 0; -} - -static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv_i32 dest) -{ - int rd = (insn >> 0) & 0xf; - TCGv_i32 tmp; - - if (insn & (1 << 8)) { - if (rd < ARM_IWMMXT_wCGR0 || rd > ARM_IWMMXT_wCGR3) { - return 1; - } else { - tmp = iwmmxt_load_creg(rd); - } - } else { - tmp = tcg_temp_new_i32(); - iwmmxt_load_reg(cpu_V0, rd); - tcg_gen_extrl_i64_i32(tmp, cpu_V0); - } - tcg_gen_andi_i32(tmp, tmp, mask); - tcg_gen_mov_i32(dest, tmp); - return 0; -} - -/* - * Disassemble an iwMMXt instruction. - * Returns nonzero if an error occurred (ie. an undefined instruction). - */ -int disas_iwmmxt_insn(DisasContext *s, uint32_t insn) -{ - int rd, wrd; - int rdhi, rdlo, rd0, rd1, i; - TCGv_i32 addr; - TCGv_i32 tmp, tmp2, tmp3; - - if ((insn & 0x0e000e00) == 0x0c000000) { - if ((insn & 0x0fe00ff0) == 0x0c400000) { - wrd = insn & 0xf; - rdlo = (insn >> 12) & 0xf; - rdhi = (insn >> 16) & 0xf; - if (insn & ARM_CP_RW_BIT) { /* TMRRC */ - iwmmxt_load_reg(cpu_V0, wrd); - tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0); - tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0); - } else { /* TMCRR */ - tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); - iwmmxt_store_reg(cpu_V0, wrd); - gen_op_iwmmxt_set_mup(); - } - return 0; - } - - wrd = (insn >> 12) & 0xf; - addr = tcg_temp_new_i32(); - if (gen_iwmmxt_address(s, insn, addr)) { - return 1; - } - if (insn & ARM_CP_RW_BIT) { - if ((insn >> 28) == 0xf) { /* WLDRW wCx */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - iwmmxt_store_creg(wrd, tmp); - } else { - i = 1; - if (insn & (1 << 8)) { - if (insn & (1 << 22)) { /* WLDRD */ - gen_aa32_ld64(s, cpu_M0, addr, get_mem_index(s)); - i = 0; - } else { /* WLDRW wRd */ - tmp = tcg_temp_new_i32(); - gen_aa32_ld32u(s, tmp, addr, get_mem_index(s)); - } - } else { - tmp = tcg_temp_new_i32(); - if (insn & (1 << 22)) { /* WLDRH */ - gen_aa32_ld16u(s, tmp, addr, get_mem_index(s)); - } else { /* WLDRB */ - gen_aa32_ld8u(s, tmp, addr, get_mem_index(s)); - } - } - if (i) { - tcg_gen_extu_i32_i64(cpu_M0, tmp); - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - } - } else { - if ((insn >> 28) == 0xf) { /* WSTRW wCx */ - tmp = iwmmxt_load_creg(wrd); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - } else { - gen_op_iwmmxt_movq_M0_wRn(wrd); - tmp = tcg_temp_new_i32(); - if (insn & (1 << 8)) { - if (insn & (1 << 22)) { /* WSTRD */ - gen_aa32_st64(s, cpu_M0, addr, get_mem_index(s)); - } else { /* WSTRW wRd */ - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - gen_aa32_st32(s, tmp, addr, get_mem_index(s)); - } - } else { - if (insn & (1 << 22)) { /* WSTRH */ - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - gen_aa32_st16(s, tmp, addr, get_mem_index(s)); - } else { /* WSTRB */ - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - gen_aa32_st8(s, tmp, addr, get_mem_index(s)); - } - } - } - } - return 0; - } - - if ((insn & 0x0f000000) != 0x0e000000) { - return 1; - } - - switch (((insn >> 12) & 0xf00) | ((insn >> 4) & 0xff)) { - case 0x000: /* WOR */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 0) & 0xf; - rd1 = (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - gen_op_iwmmxt_orq_M0_wRn(rd1); - gen_op_iwmmxt_setpsr_nz(); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x011: /* TMCR */ - if (insn & 0xf) { - return 1; - } - rd = (insn >> 12) & 0xf; - wrd = (insn >> 16) & 0xf; - switch (wrd) { - case ARM_IWMMXT_wCID: - case ARM_IWMMXT_wCASF: - break; - case ARM_IWMMXT_wCon: - gen_op_iwmmxt_set_cup(); - /* Fall through. */ - case ARM_IWMMXT_wCSSF: - tmp = iwmmxt_load_creg(wrd); - tmp2 = load_reg(s, rd); - tcg_gen_andc_i32(tmp, tmp, tmp2); - iwmmxt_store_creg(wrd, tmp); - break; - case ARM_IWMMXT_wCGR0: - case ARM_IWMMXT_wCGR1: - case ARM_IWMMXT_wCGR2: - case ARM_IWMMXT_wCGR3: - gen_op_iwmmxt_set_cup(); - tmp = load_reg(s, rd); - iwmmxt_store_creg(wrd, tmp); - break; - default: - return 1; - } - break; - case 0x100: /* WXOR */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 0) & 0xf; - rd1 = (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - gen_op_iwmmxt_xorq_M0_wRn(rd1); - gen_op_iwmmxt_setpsr_nz(); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x111: /* TMRC */ - if (insn & 0xf) { - return 1; - } - rd = (insn >> 12) & 0xf; - wrd = (insn >> 16) & 0xf; - tmp = iwmmxt_load_creg(wrd); - store_reg(s, rd, tmp); - break; - case 0x300: /* WANDN */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 0) & 0xf; - rd1 = (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tcg_gen_neg_i64(cpu_M0, cpu_M0); - gen_op_iwmmxt_andq_M0_wRn(rd1); - gen_op_iwmmxt_setpsr_nz(); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x200: /* WAND */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 0) & 0xf; - rd1 = (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - gen_op_iwmmxt_andq_M0_wRn(rd1); - gen_op_iwmmxt_setpsr_nz(); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x810: case 0xa10: /* WMADD */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 0) & 0xf; - rd1 = (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 21)) { - gen_op_iwmmxt_maddsq_M0_wRn(rd1); - } else { - gen_op_iwmmxt_madduq_M0_wRn(rd1); - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x10e: case 0x50e: case 0x90e: case 0xd0e: /* WUNPCKIL */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - gen_op_iwmmxt_unpacklb_M0_wRn(rd1); - break; - case 1: - gen_op_iwmmxt_unpacklw_M0_wRn(rd1); - break; - case 2: - gen_op_iwmmxt_unpackll_M0_wRn(rd1); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x10c: case 0x50c: case 0x90c: case 0xd0c: /* WUNPCKIH */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - gen_op_iwmmxt_unpackhb_M0_wRn(rd1); - break; - case 1: - gen_op_iwmmxt_unpackhw_M0_wRn(rd1); - break; - case 2: - gen_op_iwmmxt_unpackhl_M0_wRn(rd1); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x012: case 0x112: case 0x412: case 0x512: /* WSAD */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 22)) { - gen_op_iwmmxt_sadw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_sadb_M0_wRn(rd1); - } - if (!(insn & (1 << 20))) { - gen_op_iwmmxt_addl_M0_wRn(wrd); - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x010: case 0x110: case 0x210: case 0x310: /* WMUL */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 21)) { - if (insn & (1 << 20)) { - gen_op_iwmmxt_mulshw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_mulslw_M0_wRn(rd1); - } - } else { - if (insn & (1 << 20)) { - gen_op_iwmmxt_muluhw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_mululw_M0_wRn(rd1); - } - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x410: case 0x510: case 0x610: case 0x710: /* WMAC */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 21)) { - gen_op_iwmmxt_macsw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_macuw_M0_wRn(rd1); - } - if (!(insn & (1 << 20))) { - iwmmxt_load_reg(cpu_V1, wrd); - tcg_gen_add_i64(cpu_M0, cpu_M0, cpu_V1); - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x006: case 0x406: case 0x806: case 0xc06: /* WCMPEQ */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - gen_op_iwmmxt_cmpeqb_M0_wRn(rd1); - break; - case 1: - gen_op_iwmmxt_cmpeqw_M0_wRn(rd1); - break; - case 2: - gen_op_iwmmxt_cmpeql_M0_wRn(rd1); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x800: case 0x900: case 0xc00: case 0xd00: /* WAVG2 */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - if (insn & (1 << 22)) { - if (insn & (1 << 20)) { - gen_op_iwmmxt_avgw1_M0_wRn(rd1); - } else { - gen_op_iwmmxt_avgw0_M0_wRn(rd1); - } - } else { - if (insn & (1 << 20)) { - gen_op_iwmmxt_avgb1_M0_wRn(rd1); - } else { - gen_op_iwmmxt_avgb0_M0_wRn(rd1); - } - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x802: case 0x902: case 0xa02: case 0xb02: /* WALIGNR */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp = iwmmxt_load_creg(ARM_IWMMXT_wCGR0 + ((insn >> 20) & 3)); - tcg_gen_andi_i32(tmp, tmp, 7); - iwmmxt_load_reg(cpu_V1, rd1); - gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x601: case 0x605: case 0x609: case 0x60d: /* TINSR */ - if (((insn >> 6) & 3) == 3) { - return 1; - } - rd = (insn >> 12) & 0xf; - wrd = (insn >> 16) & 0xf; - tmp = load_reg(s, rd); - gen_op_iwmmxt_movq_M0_wRn(wrd); - switch ((insn >> 6) & 3) { - case 0: - tmp2 = tcg_constant_i32(0xff); - tmp3 = tcg_constant_i32((insn & 7) << 3); - break; - case 1: - tmp2 = tcg_constant_i32(0xffff); - tmp3 = tcg_constant_i32((insn & 3) << 4); - break; - case 2: - tmp2 = tcg_constant_i32(0xffffffff); - tmp3 = tcg_constant_i32((insn & 1) << 5); - break; - default: - g_assert_not_reached(); - } - gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x107: case 0x507: case 0x907: case 0xd07: /* TEXTRM */ - rd = (insn >> 12) & 0xf; - wrd = (insn >> 16) & 0xf; - if (rd == 15 || ((insn >> 22) & 3) == 3) { - return 1; - } - gen_op_iwmmxt_movq_M0_wRn(wrd); - tmp = tcg_temp_new_i32(); - switch ((insn >> 22) & 3) { - case 0: - tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 7) << 3); - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - if (insn & 8) { - tcg_gen_ext8s_i32(tmp, tmp); - } else { - tcg_gen_andi_i32(tmp, tmp, 0xff); - } - break; - case 1: - tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 3) << 4); - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - if (insn & 8) { - tcg_gen_ext16s_i32(tmp, tmp); - } else { - tcg_gen_andi_i32(tmp, tmp, 0xffff); - } - break; - case 2: - tcg_gen_shri_i64(cpu_M0, cpu_M0, (insn & 1) << 5); - tcg_gen_extrl_i64_i32(tmp, cpu_M0); - break; - } - store_reg(s, rd, tmp); - break; - case 0x117: case 0x517: case 0x917: case 0xd17: /* TEXTRC */ - if ((insn & 0x000ff008) != 0x0003f000 || ((insn >> 22) & 3) == 3) { - return 1; - } - tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); - switch ((insn >> 22) & 3) { - case 0: - tcg_gen_shri_i32(tmp, tmp, ((insn & 7) << 2) + 0); - break; - case 1: - tcg_gen_shri_i32(tmp, tmp, ((insn & 3) << 3) + 4); - break; - case 2: - tcg_gen_shri_i32(tmp, tmp, ((insn & 1) << 4) + 12); - break; - } - tcg_gen_shli_i32(tmp, tmp, 28); - gen_set_nzcv(tmp); - break; - case 0x401: case 0x405: case 0x409: case 0x40d: /* TBCST */ - if (((insn >> 6) & 3) == 3) { - return 1; - } - rd = (insn >> 12) & 0xf; - wrd = (insn >> 16) & 0xf; - tmp = load_reg(s, rd); - switch ((insn >> 6) & 3) { - case 0: - gen_helper_iwmmxt_bcstb(cpu_M0, tmp); - break; - case 1: - gen_helper_iwmmxt_bcstw(cpu_M0, tmp); - break; - case 2: - gen_helper_iwmmxt_bcstl(cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x113: case 0x513: case 0x913: case 0xd13: /* TANDC */ - if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) { - return 1; - } - tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); - tmp2 = tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp2, tmp); - switch ((insn >> 22) & 3) { - case 0: - for (i = 0; i < 7; i++) { - tcg_gen_shli_i32(tmp2, tmp2, 4); - tcg_gen_and_i32(tmp, tmp, tmp2); - } - break; - case 1: - for (i = 0; i < 3; i++) { - tcg_gen_shli_i32(tmp2, tmp2, 8); - tcg_gen_and_i32(tmp, tmp, tmp2); - } - break; - case 2: - tcg_gen_shli_i32(tmp2, tmp2, 16); - tcg_gen_and_i32(tmp, tmp, tmp2); - break; - } - gen_set_nzcv(tmp); - break; - case 0x01c: case 0x41c: case 0x81c: case 0xc1c: /* WACC */ - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - gen_helper_iwmmxt_addcb(cpu_M0, cpu_M0); - break; - case 1: - gen_helper_iwmmxt_addcw(cpu_M0, cpu_M0); - break; - case 2: - gen_helper_iwmmxt_addcl(cpu_M0, cpu_M0); - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x115: case 0x515: case 0x915: case 0xd15: /* TORC */ - if ((insn & 0x000ff00f) != 0x0003f000 || ((insn >> 22) & 3) == 3) { - return 1; - } - tmp = iwmmxt_load_creg(ARM_IWMMXT_wCASF); - tmp2 = tcg_temp_new_i32(); - tcg_gen_mov_i32(tmp2, tmp); - switch ((insn >> 22) & 3) { - case 0: - for (i = 0; i < 7; i++) { - tcg_gen_shli_i32(tmp2, tmp2, 4); - tcg_gen_or_i32(tmp, tmp, tmp2); - } - break; - case 1: - for (i = 0; i < 3; i++) { - tcg_gen_shli_i32(tmp2, tmp2, 8); - tcg_gen_or_i32(tmp, tmp, tmp2); - } - break; - case 2: - tcg_gen_shli_i32(tmp2, tmp2, 16); - tcg_gen_or_i32(tmp, tmp, tmp2); - break; - } - gen_set_nzcv(tmp); - break; - case 0x103: case 0x503: case 0x903: case 0xd03: /* TMOVMSK */ - rd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - if ((insn & 0xf) != 0 || ((insn >> 22) & 3) == 3) { - return 1; - } - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp = tcg_temp_new_i32(); - switch ((insn >> 22) & 3) { - case 0: - gen_helper_iwmmxt_msbb(tmp, cpu_M0); - break; - case 1: - gen_helper_iwmmxt_msbw(tmp, cpu_M0); - break; - case 2: - gen_helper_iwmmxt_msbl(tmp, cpu_M0); - break; - } - store_reg(s, rd, tmp); - break; - case 0x106: case 0x306: case 0x506: case 0x706: /* WCMPGT */ - case 0x906: case 0xb06: case 0xd06: case 0xf06: - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) { - gen_op_iwmmxt_cmpgtsb_M0_wRn(rd1); - } else { - gen_op_iwmmxt_cmpgtub_M0_wRn(rd1); - } - break; - case 1: - if (insn & (1 << 21)) { - gen_op_iwmmxt_cmpgtsw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_cmpgtuw_M0_wRn(rd1); - } - break; - case 2: - if (insn & (1 << 21)) { - gen_op_iwmmxt_cmpgtsl_M0_wRn(rd1); - } else { - gen_op_iwmmxt_cmpgtul_M0_wRn(rd1); - } - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x00e: case 0x20e: case 0x40e: case 0x60e: /* WUNPCKEL */ - case 0x80e: case 0xa0e: case 0xc0e: case 0xe0e: - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) { - gen_op_iwmmxt_unpacklsb_M0(); - } else { - gen_op_iwmmxt_unpacklub_M0(); - } - break; - case 1: - if (insn & (1 << 21)) { - gen_op_iwmmxt_unpacklsw_M0(); - } else { - gen_op_iwmmxt_unpackluw_M0(); - } - break; - case 2: - if (insn & (1 << 21)) { - gen_op_iwmmxt_unpacklsl_M0(); - } else { - gen_op_iwmmxt_unpacklul_M0(); - } - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x00c: case 0x20c: case 0x40c: case 0x60c: /* WUNPCKEH */ - case 0x80c: case 0xa0c: case 0xc0c: case 0xe0c: - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) { - gen_op_iwmmxt_unpackhsb_M0(); - } else { - gen_op_iwmmxt_unpackhub_M0(); - } - break; - case 1: - if (insn & (1 << 21)) { - gen_op_iwmmxt_unpackhsw_M0(); - } else { - gen_op_iwmmxt_unpackhuw_M0(); - } - break; - case 2: - if (insn & (1 << 21)) { - gen_op_iwmmxt_unpackhsl_M0(); - } else { - gen_op_iwmmxt_unpackhul_M0(); - } - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x204: case 0x604: case 0xa04: case 0xe04: /* WSRL */ - case 0x214: case 0x614: case 0xa14: case 0xe14: - if (((insn >> 22) & 3) == 0) { - return 1; - } - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp = tcg_temp_new_i32(); - if (gen_iwmmxt_shift(insn, 0xff, tmp)) { - return 1; - } - switch ((insn >> 22) & 3) { - case 1: - gen_helper_iwmmxt_srlw(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 2: - gen_helper_iwmmxt_srll(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 3: - gen_helper_iwmmxt_srlq(cpu_M0, cpu_env, cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x004: case 0x404: case 0x804: case 0xc04: /* WSRA */ - case 0x014: case 0x414: case 0x814: case 0xc14: - if (((insn >> 22) & 3) == 0) { - return 1; - } - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp = tcg_temp_new_i32(); - if (gen_iwmmxt_shift(insn, 0xff, tmp)) { - return 1; - } - switch ((insn >> 22) & 3) { - case 1: - gen_helper_iwmmxt_sraw(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 2: - gen_helper_iwmmxt_sral(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 3: - gen_helper_iwmmxt_sraq(cpu_M0, cpu_env, cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x104: case 0x504: case 0x904: case 0xd04: /* WSLL */ - case 0x114: case 0x514: case 0x914: case 0xd14: - if (((insn >> 22) & 3) == 0) { - return 1; - } - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp = tcg_temp_new_i32(); - if (gen_iwmmxt_shift(insn, 0xff, tmp)) { - return 1; - } - switch ((insn >> 22) & 3) { - case 1: - gen_helper_iwmmxt_sllw(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 2: - gen_helper_iwmmxt_slll(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 3: - gen_helper_iwmmxt_sllq(cpu_M0, cpu_env, cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x304: case 0x704: case 0xb04: case 0xf04: /* WROR */ - case 0x314: case 0x714: case 0xb14: case 0xf14: - if (((insn >> 22) & 3) == 0) { - return 1; - } - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp = tcg_temp_new_i32(); - switch ((insn >> 22) & 3) { - case 1: - if (gen_iwmmxt_shift(insn, 0xf, tmp)) { - return 1; - } - gen_helper_iwmmxt_rorw(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 2: - if (gen_iwmmxt_shift(insn, 0x1f, tmp)) { - return 1; - } - gen_helper_iwmmxt_rorl(cpu_M0, cpu_env, cpu_M0, tmp); - break; - case 3: - if (gen_iwmmxt_shift(insn, 0x3f, tmp)) { - return 1; - } - gen_helper_iwmmxt_rorq(cpu_M0, cpu_env, cpu_M0, tmp); - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x116: case 0x316: case 0x516: case 0x716: /* WMIN */ - case 0x916: case 0xb16: case 0xd16: case 0xf16: - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) { - gen_op_iwmmxt_minsb_M0_wRn(rd1); - } else { - gen_op_iwmmxt_minub_M0_wRn(rd1); - } - break; - case 1: - if (insn & (1 << 21)) { - gen_op_iwmmxt_minsw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_minuw_M0_wRn(rd1); - } - break; - case 2: - if (insn & (1 << 21)) { - gen_op_iwmmxt_minsl_M0_wRn(rd1); - } else { - gen_op_iwmmxt_minul_M0_wRn(rd1); - } - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x016: case 0x216: case 0x416: case 0x616: /* WMAX */ - case 0x816: case 0xa16: case 0xc16: case 0xe16: - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 0: - if (insn & (1 << 21)) { - gen_op_iwmmxt_maxsb_M0_wRn(rd1); - } else { - gen_op_iwmmxt_maxub_M0_wRn(rd1); - } - break; - case 1: - if (insn & (1 << 21)) { - gen_op_iwmmxt_maxsw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_maxuw_M0_wRn(rd1); - } - break; - case 2: - if (insn & (1 << 21)) { - gen_op_iwmmxt_maxsl_M0_wRn(rd1); - } else { - gen_op_iwmmxt_maxul_M0_wRn(rd1); - } - break; - case 3: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x002: case 0x102: case 0x202: case 0x302: /* WALIGNI */ - case 0x402: case 0x502: case 0x602: case 0x702: - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - iwmmxt_load_reg(cpu_V1, rd1); - gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, - tcg_constant_i32((insn >> 20) & 3)); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - case 0x01a: case 0x11a: case 0x21a: case 0x31a: /* WSUB */ - case 0x41a: case 0x51a: case 0x61a: case 0x71a: - case 0x81a: case 0x91a: case 0xa1a: case 0xb1a: - case 0xc1a: case 0xd1a: case 0xe1a: case 0xf1a: - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 20) & 0xf) { - case 0x0: - gen_op_iwmmxt_subnb_M0_wRn(rd1); - break; - case 0x1: - gen_op_iwmmxt_subub_M0_wRn(rd1); - break; - case 0x3: - gen_op_iwmmxt_subsb_M0_wRn(rd1); - break; - case 0x4: - gen_op_iwmmxt_subnw_M0_wRn(rd1); - break; - case 0x5: - gen_op_iwmmxt_subuw_M0_wRn(rd1); - break; - case 0x7: - gen_op_iwmmxt_subsw_M0_wRn(rd1); - break; - case 0x8: - gen_op_iwmmxt_subnl_M0_wRn(rd1); - break; - case 0x9: - gen_op_iwmmxt_subul_M0_wRn(rd1); - break; - case 0xb: - gen_op_iwmmxt_subsl_M0_wRn(rd1); - break; - default: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x01e: case 0x11e: case 0x21e: case 0x31e: /* WSHUFH */ - case 0x41e: case 0x51e: case 0x61e: case 0x71e: - case 0x81e: case 0x91e: case 0xa1e: case 0xb1e: - case 0xc1e: case 0xd1e: case 0xe1e: case 0xf1e: - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp = tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); - gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp); - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x018: case 0x118: case 0x218: case 0x318: /* WADD */ - case 0x418: case 0x518: case 0x618: case 0x718: - case 0x818: case 0x918: case 0xa18: case 0xb18: - case 0xc18: case 0xd18: case 0xe18: case 0xf18: - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 20) & 0xf) { - case 0x0: - gen_op_iwmmxt_addnb_M0_wRn(rd1); - break; - case 0x1: - gen_op_iwmmxt_addub_M0_wRn(rd1); - break; - case 0x3: - gen_op_iwmmxt_addsb_M0_wRn(rd1); - break; - case 0x4: - gen_op_iwmmxt_addnw_M0_wRn(rd1); - break; - case 0x5: - gen_op_iwmmxt_adduw_M0_wRn(rd1); - break; - case 0x7: - gen_op_iwmmxt_addsw_M0_wRn(rd1); - break; - case 0x8: - gen_op_iwmmxt_addnl_M0_wRn(rd1); - break; - case 0x9: - gen_op_iwmmxt_addul_M0_wRn(rd1); - break; - case 0xb: - gen_op_iwmmxt_addsl_M0_wRn(rd1); - break; - default: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x008: case 0x108: case 0x208: case 0x308: /* WPACK */ - case 0x408: case 0x508: case 0x608: case 0x708: - case 0x808: case 0x908: case 0xa08: case 0xb08: - case 0xc08: case 0xd08: case 0xe08: case 0xf08: - if (!(insn & (1 << 20)) || ((insn >> 22) & 3) == 0) { - return 1; - } - wrd = (insn >> 12) & 0xf; - rd0 = (insn >> 16) & 0xf; - rd1 = (insn >> 0) & 0xf; - gen_op_iwmmxt_movq_M0_wRn(rd0); - switch ((insn >> 22) & 3) { - case 1: - if (insn & (1 << 21)) { - gen_op_iwmmxt_packsw_M0_wRn(rd1); - } else { - gen_op_iwmmxt_packuw_M0_wRn(rd1); - } - break; - case 2: - if (insn & (1 << 21)) { - gen_op_iwmmxt_packsl_M0_wRn(rd1); - } else { - gen_op_iwmmxt_packul_M0_wRn(rd1); - } - break; - case 3: - if (insn & (1 << 21)) { - gen_op_iwmmxt_packsq_M0_wRn(rd1); - } else { - gen_op_iwmmxt_packuq_M0_wRn(rd1); - } - break; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - gen_op_iwmmxt_set_cup(); - break; - case 0x201: case 0x203: case 0x205: case 0x207: - case 0x209: case 0x20b: case 0x20d: case 0x20f: - case 0x211: case 0x213: case 0x215: case 0x217: - case 0x219: case 0x21b: case 0x21d: case 0x21f: - wrd = (insn >> 5) & 0xf; - rd0 = (insn >> 12) & 0xf; - rd1 = (insn >> 0) & 0xf; - if (rd0 == 0xf || rd1 == 0xf) { - return 1; - } - gen_op_iwmmxt_movq_M0_wRn(wrd); - tmp = load_reg(s, rd0); - tmp2 = load_reg(s, rd1); - switch ((insn >> 16) & 0xf) { - case 0x0: /* TMIA */ - gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); - break; - case 0x8: /* TMIAPH */ - gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); - break; - case 0xc: case 0xd: case 0xe: case 0xf: /* TMIAxy */ - if (insn & (1 << 16)) { - tcg_gen_shri_i32(tmp, tmp, 16); - } - if (insn & (1 << 17)) { - tcg_gen_shri_i32(tmp2, tmp2, 16); - } - gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); - break; - default: - return 1; - } - gen_op_iwmmxt_movq_wRn_M0(wrd); - gen_op_iwmmxt_set_mup(); - break; - default: - return 1; - } - - return 0; -} - -/* - * Disassemble an XScale DSP instruction. - * Returns nonzero if an error occurred (ie. an undefined instruction). - */ -int disas_dsp_insn(DisasContext *s, uint32_t insn) -{ - int acc, rd0, rd1, rdhi, rdlo; - TCGv_i32 tmp, tmp2; - - if ((insn & 0x0ff00f10) == 0x0e200010) { - /* Multiply with Internal Accumulate Format */ - rd0 = (insn >> 12) & 0xf; - rd1 = insn & 0xf; - acc = (insn >> 5) & 7; - - if (acc != 0) { - return 1; - } - - tmp = load_reg(s, rd0); - tmp2 = load_reg(s, rd1); - switch ((insn >> 16) & 0xf) { - case 0x0: /* MIA */ - gen_helper_iwmmxt_muladdsl(cpu_M0, cpu_M0, tmp, tmp2); - break; - case 0x8: /* MIAPH */ - gen_helper_iwmmxt_muladdsw(cpu_M0, cpu_M0, tmp, tmp2); - break; - case 0xc: /* MIABB */ - case 0xd: /* MIABT */ - case 0xe: /* MIATB */ - case 0xf: /* MIATT */ - if (insn & (1 << 16)) { - tcg_gen_shri_i32(tmp, tmp, 16); - } - if (insn & (1 << 17)) { - tcg_gen_shri_i32(tmp2, tmp2, 16); - } - gen_helper_iwmmxt_muladdswl(cpu_M0, cpu_M0, tmp, tmp2); - break; - default: - return 1; - } - - gen_op_iwmmxt_movq_wRn_M0(acc); - return 0; - } - - if ((insn & 0x0fe00ff8) == 0x0c400000) { - /* Internal Accumulator Access Format */ - rdhi = (insn >> 16) & 0xf; - rdlo = (insn >> 12) & 0xf; - acc = insn & 7; - - if (acc != 0) { - return 1; - } - - if (insn & ARM_CP_RW_BIT) { /* MRA */ - iwmmxt_load_reg(cpu_V0, acc); - tcg_gen_extrl_i64_i32(cpu_R[rdlo], cpu_V0); - tcg_gen_extrh_i64_i32(cpu_R[rdhi], cpu_V0); - tcg_gen_andi_i32(cpu_R[rdhi], cpu_R[rdhi], (1 << (40 - 32)) - 1); - } else { /* MAR */ - tcg_gen_concat_i32_i64(cpu_V0, cpu_R[rdlo], cpu_R[rdhi]); - iwmmxt_store_reg(cpu_V0, acc); - } - return 0; - } - - return 1; -} - static void gen_goto_ptr(void) { tcg_gen_lookup_and_goto_ptr(); diff --git a/target/arm/tcg/meson.build b/target/arm/tcg/meson.build index 130ed62fcd..fca9912a0a 100644 --- a/target/arm/tcg/meson.build +++ b/target/arm/tcg/meson.build @@ -21,6 +21,7 @@ arm_ss.add(gen) arm_ss.add(files( 'cpu32.c', 'translate.c', + 'translate-iwmmxt.c', 'translate-m-nocp.c', 'translate-mve.c', 'translate-neon.c', From patchwork Sun Jun 11 08:58:29 2023 Content-Type: text/plain; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id f10-20020adff8ca000000b0030fae7129e7sm3791910wrq.42.2023.06.11.01.59.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 09/26] target/arm/tcg: Reduce 'helper-iwmmxt.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:29 +0200 Message-Id: <20230611085846.21415-10-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of including helper-iwmmxt.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daudé --- target/arm/helper.h | 1 - target/arm/tcg/iwmmxt_helper.c | 5 ++++- target/arm/tcg/translate-iwmmxt.c | 6 ++++++ 3 files changed, 10 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index c4a321c0ea..dd12fee107 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -949,5 +949,4 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-sme.h.inc" #endif -#include "tcg/helper-iwmmxt.h.inc" #include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/iwmmxt_helper.c b/target/arm/tcg/iwmmxt_helper.c index 610b1b2103..ee607a3d3d 100644 --- a/target/arm/tcg/iwmmxt_helper.c +++ b/target/arm/tcg/iwmmxt_helper.c @@ -22,7 +22,10 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" + +#define HELPER_H "tcg/helper-iwmmxt.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H /* iwMMXt macros extracted from GNU gdb. */ diff --git a/target/arm/tcg/translate-iwmmxt.c b/target/arm/tcg/translate-iwmmxt.c index 57a924c578..9f6d717ee0 100644 --- a/target/arm/tcg/translate-iwmmxt.c +++ b/target/arm/tcg/translate-iwmmxt.c @@ -12,6 +12,12 @@ #include "translate.h" #include "translate-a32.h" +#define HELPER_H "tcg/helper-iwmmxt.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + #define ARM_CP_RW_BIT (1 << 20) static inline void iwmmxt_load_reg(TCGv_i64 var, int reg) From patchwork Sun Jun 11 08:58:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691345 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1570972wru; Sun, 11 Jun 2023 02:00:44 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7CN5YE4XtdHUaOlc6iWlFQlRz9HKui2lsBgYH56ougU/INWMbhVMGMa71sVMKoDZNbCaDX X-Received: by 2002:a05:622a:1454:b0:3f9:d70f:ff71 with SMTP id v20-20020a05622a145400b003f9d70fff71mr8849690qtx.56.1686474043721; Sun, 11 Jun 2023 02:00:43 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474043; cv=none; d=google.com; s=arc-20160816; b=rlBZgCfg4G4M0JWos986O63AqPOm8UpiwHX8z6cWNDITHvYffGuIUlbmv6h/eQ/b7W +H1giqXguLHXCj4z0FZ2EVNv26/0mknwwCoXHmsSM0231nQp1+HvfEMPFUkjWWCBXXLE UoJ5c+DUpOAioSHO7GzVA+WtMetfiNE7iM0Bz0VUWTWq5Pjr60JFuzrLex5K5BsxZmkC Pd+TajW6Tzz32W4TSw+J7EflG7gIjnMofEkPgI5CA3AlKsk+wzmkiAhoftjHbSdR4SAF 4+PLiUNuy0bfkH7X9MbmbfSPnsvMaOxNdmqwIj3j7fcrHsvUW2E2rlLaO8Yi+hDx/5YS AMGQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=VDBF5f6g3ss6zXACl4FvMit7Sn+wQR849UpnWHsvJfE=; b=yr+sasRXIsh6x7y8VZAxID1jjIfUMbU/OnguLWnvN+p/K2oe9WoS+L3p+E+/NXz+aq 6FltXs0Ssg9wlMLwoaVfzLwjdYqQxa6UvYTUV+yBt/TOxKs92OM/IdXwF9BtD5NiQ7NX ie6HyHCedln562Ae09mjZ0QwHuIDD0T3AYwOi37yHMYK4d4AvYHen0KMX3wFDjiUpkUR QKwc8gKQGXBghRJSWp3dFD+wcBvtWvht4VDMMB5d4mwK2865omW3R4vhZgN1xttzi+Jn sF/e6X/tUcG6sgO08s9roBdgtvQLvvsw5sh/vifH0jUqrH6Z0wU1e2VcP/YPgEWPokAq YcWw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=jCg5Bxq9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id m19-20020a7bcb93000000b003f7e75b053dsm7908106wmi.34.2023.06.11.01.59.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:31 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 10/26] target/arm/tcg: Extract VFP definitions to 'helper-vfp.h.inc' Date: Sun, 11 Jun 2023 10:58:30 +0200 Message-Id: <20230611085846.21415-11-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org helper.h is used by all units, but not all require the VFP definitions. Move them to a new header; the next commit will remove it from the common helper.h. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- TODO check recpe/rsqrte/rint* are VFP --- target/arm/helper.h | 155 +----------------------------- target/arm/tcg/helper-vfp.h.inc | 163 ++++++++++++++++++++++++++++++++ 2 files changed, 164 insertions(+), 154 deletions(-) create mode 100644 target/arm/tcg/helper-vfp.h.inc diff --git a/target/arm/helper.h b/target/arm/helper.h index dd12fee107..cdc453f040 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -103,155 +103,8 @@ DEF_HELPER_FLAGS_2(rebuild_hflags_a64, TCG_CALL_NO_RWG, void, env, int) DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, i32) -DEF_HELPER_1(vfp_get_fpscr, i32, env) -DEF_HELPER_2(vfp_set_fpscr, void, env, i32) - -DEF_HELPER_3(vfp_addh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_adds, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_addd, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_subh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_subs, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_subd, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_mulh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_muls, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_muld, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_divh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_divs, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_divd, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_maxh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_maxs, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_maxd, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_minh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_mins, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_mind, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_maxnums, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, ptr) -DEF_HELPER_3(vfp_minnumh, f16, f16, f16, ptr) -DEF_HELPER_3(vfp_minnums, f32, f32, f32, ptr) -DEF_HELPER_3(vfp_minnumd, f64, f64, f64, ptr) -DEF_HELPER_1(vfp_negh, f16, f16) -DEF_HELPER_1(vfp_negs, f32, f32) -DEF_HELPER_1(vfp_negd, f64, f64) -DEF_HELPER_1(vfp_absh, f16, f16) -DEF_HELPER_1(vfp_abss, f32, f32) -DEF_HELPER_1(vfp_absd, f64, f64) -DEF_HELPER_2(vfp_sqrth, f16, f16, env) -DEF_HELPER_2(vfp_sqrts, f32, f32, env) -DEF_HELPER_2(vfp_sqrtd, f64, f64, env) -DEF_HELPER_3(vfp_cmph, void, f16, f16, env) -DEF_HELPER_3(vfp_cmps, void, f32, f32, env) -DEF_HELPER_3(vfp_cmpd, void, f64, f64, env) -DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env) -DEF_HELPER_3(vfp_cmpes, void, f32, f32, env) -DEF_HELPER_3(vfp_cmped, void, f64, f64, env) - -DEF_HELPER_2(vfp_fcvtds, f64, f32, env) -DEF_HELPER_2(vfp_fcvtsd, f32, f64, env) -DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, ptr) -DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, ptr) - -DEF_HELPER_2(vfp_uitoh, f16, i32, ptr) -DEF_HELPER_2(vfp_uitos, f32, i32, ptr) -DEF_HELPER_2(vfp_uitod, f64, i32, ptr) -DEF_HELPER_2(vfp_sitoh, f16, i32, ptr) -DEF_HELPER_2(vfp_sitos, f32, i32, ptr) -DEF_HELPER_2(vfp_sitod, f64, i32, ptr) - -DEF_HELPER_2(vfp_touih, i32, f16, ptr) -DEF_HELPER_2(vfp_touis, i32, f32, ptr) -DEF_HELPER_2(vfp_touid, i32, f64, ptr) -DEF_HELPER_2(vfp_touizh, i32, f16, ptr) -DEF_HELPER_2(vfp_touizs, i32, f32, ptr) -DEF_HELPER_2(vfp_touizd, i32, f64, ptr) -DEF_HELPER_2(vfp_tosih, s32, f16, ptr) -DEF_HELPER_2(vfp_tosis, s32, f32, ptr) -DEF_HELPER_2(vfp_tosid, s32, f64, ptr) -DEF_HELPER_2(vfp_tosizh, s32, f16, ptr) -DEF_HELPER_2(vfp_tosizs, s32, f32, ptr) -DEF_HELPER_2(vfp_tosizd, s32, f64, ptr) - -DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr) -DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr) -DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr) -DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr) -DEF_HELPER_3(vfp_touhs, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_touls, i32, f32, i32, ptr) -DEF_HELPER_3(vfp_touqs, i64, f32, i32, ptr) -DEF_HELPER_3(vfp_toshd, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_tosld, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_tosqd, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_touhd, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_tould, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_touqd, i64, f64, i32, ptr) -DEF_HELPER_3(vfp_shtos, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_sltos, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_sqtos, f32, i64, i32, ptr) -DEF_HELPER_3(vfp_uhtos, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_ultos, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_uqtos, f32, i64, i32, ptr) -DEF_HELPER_3(vfp_shtod, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_sltod, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_shtoh, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr) -DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr) - -DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, ptr) -DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, ptr) -DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, ptr) -DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, ptr) - DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) -DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i32) -DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, ptr, i32) -DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, ptr, i32) -DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, ptr, i32) - -DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr) -DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) -DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, ptr) - -DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr) -DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr) -DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr) -DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr) -DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) -DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) -DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) -DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) DEF_HELPER_3(shl_cc, i32, env, i32, i32) @@ -259,13 +112,6 @@ DEF_HELPER_3(shr_cc, i32, env, i32, i32) DEF_HELPER_3(sar_cc, i32, env, i32, i32) DEF_HELPER_3(ror_cc, i32, env, i32, i32) -DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, ptr) -DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, ptr) -DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr) -DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, ptr) -DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr) -DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr) - DEF_HELPER_FLAGS_2(vjcvt, TCG_CALL_NO_RWG, i32, f64, env) DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr) @@ -949,4 +795,5 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-sme.h.inc" #endif +#include "tcg/helper-vfp.h.inc" #include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/helper-vfp.h.inc b/target/arm/tcg/helper-vfp.h.inc new file mode 100644 index 0000000000..31b58568e8 --- /dev/null +++ b/target/arm/tcg/helper-vfp.h.inc @@ -0,0 +1,163 @@ +/* + * ARM VFP helper definitions + * + * Copyright (c) 2007 CodeSourcery. + * Written by Paul Brook + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +DEF_HELPER_1(vfp_get_fpscr, i32, env) +DEF_HELPER_2(vfp_set_fpscr, void, env, i32) + +DEF_HELPER_3(vfp_addh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_adds, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_addd, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_subh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_subs, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_subd, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_mulh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_muls, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_muld, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_divh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_divs, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_divd, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_maxh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_maxs, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_maxd, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_minh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_mins, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_mind, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_maxnumh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_maxnums, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_maxnumd, f64, f64, f64, ptr) +DEF_HELPER_3(vfp_minnumh, f16, f16, f16, ptr) +DEF_HELPER_3(vfp_minnums, f32, f32, f32, ptr) +DEF_HELPER_3(vfp_minnumd, f64, f64, f64, ptr) +DEF_HELPER_1(vfp_negh, f16, f16) +DEF_HELPER_1(vfp_negs, f32, f32) +DEF_HELPER_1(vfp_negd, f64, f64) +DEF_HELPER_1(vfp_absh, f16, f16) +DEF_HELPER_1(vfp_abss, f32, f32) +DEF_HELPER_1(vfp_absd, f64, f64) +DEF_HELPER_2(vfp_sqrth, f16, f16, env) +DEF_HELPER_2(vfp_sqrts, f32, f32, env) +DEF_HELPER_2(vfp_sqrtd, f64, f64, env) +DEF_HELPER_3(vfp_cmph, void, f16, f16, env) +DEF_HELPER_3(vfp_cmps, void, f32, f32, env) +DEF_HELPER_3(vfp_cmpd, void, f64, f64, env) +DEF_HELPER_3(vfp_cmpeh, void, f16, f16, env) +DEF_HELPER_3(vfp_cmpes, void, f32, f32, env) +DEF_HELPER_3(vfp_cmped, void, f64, f64, env) + +DEF_HELPER_2(vfp_fcvtds, f64, f32, env) +DEF_HELPER_2(vfp_fcvtsd, f32, f64, env) +DEF_HELPER_FLAGS_2(bfcvt, TCG_CALL_NO_RWG, i32, f32, ptr) +DEF_HELPER_FLAGS_2(bfcvt_pair, TCG_CALL_NO_RWG, i32, i64, ptr) + +DEF_HELPER_2(vfp_uitoh, f16, i32, ptr) +DEF_HELPER_2(vfp_uitos, f32, i32, ptr) +DEF_HELPER_2(vfp_uitod, f64, i32, ptr) +DEF_HELPER_2(vfp_sitoh, f16, i32, ptr) +DEF_HELPER_2(vfp_sitos, f32, i32, ptr) +DEF_HELPER_2(vfp_sitod, f64, i32, ptr) + +DEF_HELPER_2(vfp_touih, i32, f16, ptr) +DEF_HELPER_2(vfp_touis, i32, f32, ptr) +DEF_HELPER_2(vfp_touid, i32, f64, ptr) +DEF_HELPER_2(vfp_touizh, i32, f16, ptr) +DEF_HELPER_2(vfp_touizs, i32, f32, ptr) +DEF_HELPER_2(vfp_touizd, i32, f64, ptr) +DEF_HELPER_2(vfp_tosih, s32, f16, ptr) +DEF_HELPER_2(vfp_tosis, s32, f32, ptr) +DEF_HELPER_2(vfp_tosid, s32, f64, ptr) +DEF_HELPER_2(vfp_tosizh, s32, f16, ptr) +DEF_HELPER_2(vfp_tosizs, s32, f32, ptr) +DEF_HELPER_2(vfp_tosizd, s32, f64, ptr) + +DEF_HELPER_3(vfp_toshh_round_to_zero, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toslh_round_to_zero, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_touhh_round_to_zero, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toulh_round_to_zero, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toshs_round_to_zero, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_tosls_round_to_zero, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_touhs_round_to_zero, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_touls_round_to_zero, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_toshd_round_to_zero, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_tosld_round_to_zero, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_touhd_round_to_zero, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_tould_round_to_zero, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_touhh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toshh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toulh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_toslh, i32, f16, i32, ptr) +DEF_HELPER_3(vfp_touqh, i64, f16, i32, ptr) +DEF_HELPER_3(vfp_tosqh, i64, f16, i32, ptr) +DEF_HELPER_3(vfp_toshs, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_tosls, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_tosqs, i64, f32, i32, ptr) +DEF_HELPER_3(vfp_touhs, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_touls, i32, f32, i32, ptr) +DEF_HELPER_3(vfp_touqs, i64, f32, i32, ptr) +DEF_HELPER_3(vfp_toshd, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_tosld, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_tosqd, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_touhd, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_tould, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_touqd, i64, f64, i32, ptr) +DEF_HELPER_3(vfp_shtos, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_sltos, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_sqtos, f32, i64, i32, ptr) +DEF_HELPER_3(vfp_uhtos, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_ultos, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_uqtos, f32, i64, i32, ptr) +DEF_HELPER_3(vfp_shtod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_sltod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_sqtod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_uhtod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_ultod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_uqtod, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_shtoh, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_uhtoh, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_sltoh, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_ultoh, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_sqtoh, f16, i64, i32, ptr) +DEF_HELPER_3(vfp_uqtoh, f16, i64, i32, ptr) + +DEF_HELPER_3(vfp_shtos_round_to_nearest, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_sltos_round_to_nearest, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_uhtos_round_to_nearest, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_ultos_round_to_nearest, f32, i32, i32, ptr) +DEF_HELPER_3(vfp_shtod_round_to_nearest, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_sltod_round_to_nearest, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_uhtod_round_to_nearest, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_ultod_round_to_nearest, f64, i64, i32, ptr) +DEF_HELPER_3(vfp_shtoh_round_to_nearest, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_uhtoh_round_to_nearest, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_sltoh_round_to_nearest, f16, i32, i32, ptr) +DEF_HELPER_3(vfp_ultoh_round_to_nearest, f16, i32, i32, ptr) + +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f32, TCG_CALL_NO_RWG, f32, f16, ptr, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f32_to_f16, TCG_CALL_NO_RWG, f16, f32, ptr, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f16_to_f64, TCG_CALL_NO_RWG, f64, f16, ptr, i32) +DEF_HELPER_FLAGS_3(vfp_fcvt_f64_to_f16, TCG_CALL_NO_RWG, f16, f64, ptr, i32) + +DEF_HELPER_4(vfp_muladdd, f64, f64, f64, f64, ptr) +DEF_HELPER_4(vfp_muladds, f32, f32, f32, f32, ptr) +DEF_HELPER_4(vfp_muladdh, f16, f16, f16, f16, ptr) + +DEF_HELPER_FLAGS_2(recpe_f16, TCG_CALL_NO_RWG, f16, f16, ptr) +DEF_HELPER_FLAGS_2(recpe_f32, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(recpe_f64, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_2(rsqrte_f16, TCG_CALL_NO_RWG, f16, f16, ptr) +DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_1(recpe_u32, TCG_CALL_NO_RWG, i32, i32) +DEF_HELPER_FLAGS_1(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32) + +DEF_HELPER_FLAGS_2(rinth_exact, TCG_CALL_NO_RWG, f16, f16, ptr) +DEF_HELPER_FLAGS_2(rints_exact, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(rintd_exact, TCG_CALL_NO_RWG, f64, f64, ptr) +DEF_HELPER_FLAGS_2(rinth, TCG_CALL_NO_RWG, f16, f16, ptr) +DEF_HELPER_FLAGS_2(rints, TCG_CALL_NO_RWG, f32, f32, ptr) +DEF_HELPER_FLAGS_2(rintd, TCG_CALL_NO_RWG, f64, f64, ptr) From patchwork Sun Jun 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id m11-20020a5d6a0b000000b0030b5d203e7esm9086865wru.97.2023.06.11.01.59.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 11/26] target/arm/tcg: Reduce 'helper-vfp.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:31 +0200 Message-Id: <20230611085846.21415-12-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of including helper-vfp.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/helper.h | 1 - target/arm/tcg/mve_helper.c | 4 ++++ target/arm/tcg/sve_helper.c | 3 +++ target/arm/tcg/translate-a64.c | 4 ++++ target/arm/tcg/translate-m-nocp.c | 5 +++++ target/arm/tcg/translate-neon.c | 4 ++++ target/arm/tcg/translate-vfp.c | 6 ++++++ target/arm/tcg/vec_helper.c | 4 ++++ target/arm/vfp_helper.c | 4 ++++ 9 files changed, 34 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index cdc453f040..1041accf71 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -795,5 +795,4 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-sme.h.inc" #endif -#include "tcg/helper-vfp.h.inc" #include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index 403b345ea3..d8ba5a9e60 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -27,6 +27,10 @@ #include "tcg/tcg.h" #include "fpu/softfloat.h" +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + static uint16_t mve_eci_mask(CPUARMState *env) { /* diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 0097522470..8a0d966aae 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -29,6 +29,9 @@ #include "sve_ldst_internal.h" #include "hw/core/tcg-cpu-ops.h" +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H /* Return a value for NZCV as per the ARM PredTest pseudofunction. * diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index aa93f37e21..c0727c900f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -26,6 +26,10 @@ #include "semihosting/semihost.h" #include "cpregs.h" +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; diff --git a/target/arm/tcg/translate-m-nocp.c b/target/arm/tcg/translate-m-nocp.c index 33f6478bb9..7343945b41 100644 --- a/target/arm/tcg/translate-m-nocp.c +++ b/target/arm/tcg/translate-m-nocp.c @@ -21,6 +21,11 @@ #include "translate.h" #include "translate-a32.h" +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +/* Include the generated decoder */ #include "decode-m-nocp.c.inc" /* diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c index 03913de047..497aba2e39 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -24,6 +24,10 @@ #include "translate.h" #include "translate-a32.h" +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + /* Include the generated Neon decoder */ #include "decode-neon-dp.c.inc" #include "decode-neon-ls.c.inc" diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 359b1e3e96..10d4502239 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -24,6 +24,12 @@ #include "translate.h" #include "translate-a32.h" +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + /* Include the generated VFP decoder */ #include "decode-vfp.c.inc" #include "decode-vfp-uncond.c.inc" diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index f59d3b26ea..013ca1b05f 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -25,6 +25,10 @@ #include "qemu/int128.h" #include "vec_internal.h" +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* * Data for expanding active predicate bits to bytes, for byte elements. * diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 36906db8e0..cbd78cc810 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -32,6 +32,10 @@ #ifdef CONFIG_TCG +#define HELPER_H "tcg/helper-vfp.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* Convert host exception flags to vfp form. */ static inline int vfp_exceptbits_from_host(int host_bits) { From patchwork Sun Jun 11 08:58:32 2023 Content-Type: text/plain; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id k10-20020adff5ca000000b003077a19cf75sm9081745wrp.60.2023.06.11.01.59.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 12/26] target/arm/tcg: Move neon_tbl() from op_helper.c to neon_helper.c Date: Sun, 11 Jun 2023 10:58:32 +0200 Message-Id: <20230611085846.21415-13-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=philmd@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org neon_tbl() helper is only called by NEON files. No need to have it in the generic op_helper.c, move it with the rest of the NEON helpers. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/tcg/neon_helper.c | 22 ++++++++++++++++++++++ target/arm/tcg/op_helper.c | 22 ---------------------- 2 files changed, 22 insertions(+), 22 deletions(-) diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c index bc6c4a54e9..0a4ab3e42c 100644 --- a/target/arm/tcg/neon_helper.c +++ b/target/arm/tcg/neon_helper.c @@ -1738,3 +1738,25 @@ void HELPER(neon_zip16)(void *vd, void *vm) rm[0] = m0; rd[0] = d0; } + +uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, + uint64_t ireg, uint64_t def) +{ + uint64_t tmp, val = 0; + uint32_t maxindex = ((desc & 3) + 1) * 8; + uint32_t base_reg = desc >> 2; + uint32_t shift, index, reg; + + for (shift = 0; shift < 64; shift += 8) { + index = (ireg >> shift) & 0xff; + if (index < maxindex) { + reg = base_reg + (index >> 3); + tmp = *aa32_vfp_dreg(env, reg); + tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift; + } else { + tmp = def & (0xffull << shift); + } + val |= tmp; + } + return val; +} diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 3baf8004f6..70a9c37b74 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -82,28 +82,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, raise_exception(env, excp, syndrome, target_el); } -uint64_t HELPER(neon_tbl)(CPUARMState *env, uint32_t desc, - uint64_t ireg, uint64_t def) -{ - uint64_t tmp, val = 0; - uint32_t maxindex = ((desc & 3) + 1) * 8; - uint32_t base_reg = desc >> 2; - uint32_t shift, index, reg; - - for (shift = 0; shift < 64; shift += 8) { - index = (ireg >> shift) & 0xff; - if (index < maxindex) { - reg = base_reg + (index >> 3); - tmp = *aa32_vfp_dreg(env, reg); - tmp = ((tmp >> ((index & 7) << 3)) & 0xff) << shift; - } else { - tmp = def & (0xffull << shift); - } - val |= tmp; - } - return val; -} - void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) { /* From patchwork Sun Jun 11 08:58:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691354 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1572381wru; Sun, 11 Jun 2023 02:05:04 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6/j+OzCt56N5f+FC7PP2CEQXt3dcHZS5aWiiRlNrTulEgWPNZdBwjdYW5AkQJjzWnU8Q/o X-Received: by 2002:a37:6403:0:b0:75b:25a2:c284 with SMTP id y3-20020a376403000000b0075b25a2c284mr4829466qkb.30.1686474304621; Sun, 11 Jun 2023 02:05:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474304; cv=none; d=google.com; s=arc-20160816; b=sKmUiXQMRKcD1eKG+/csnfiNi4Ec6IJ05Wzpv/nUto1iPN4X6lV+XzxVNUrgPOAy2M FZtf98f2769bsgvgveh0coP4yhHHUvWcNmFAp08E+U3FVHDImYM4iWVrRPOhlq1A6TNa XrXzIlEljPpA7vkxfF3eT1HXhgPfDKozhXh5Uj4TbpVyi44+9CxHJAo+kcpFB80v8H3X NMb97F2omC2bR+5DXizcubZcgsUYuMizMW/3U2paRNGF8d2SX7LV2tmfbgtq32dV7+Aj mMO7K1G01gMETmcr4pr8N3szlCBHXzJHVpVNb9wPDWX1EftRe+kflqcDDxSKbyLDaFY6 udjg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QVdVsutRh46jRwa2PoJBROMIYsAkmEcJwwavIyUiJGE=; b=0w33hPuRC1uvdflllCNVnABxRAiqXu+8IHlkWFWCVMfkyXiE00th/vKJg8/iKH8aZp l5CgtIyKKdpsoSqXMxN8nA4dYBeh4e31vOh3oZbixOJHK8nqD5mPr2iuycaDev2FFw8p 70D3MshrTiaiskvxGZsOisVCL0QL8j+Bfg0Kb+ACu2ffFQr3xQyrhOZZ6fWWdedDIzE9 TbrAzK9qTB+oNoiaMuWiDUc6jPhb0E/CmFyHt0MHA//kaAy4mA9SWocCk6vZppC7ka9N +yZCdat0LalZqd/j+yMTCkGZo98wQtFN2hPl4ph6/ttcGh3HWcuiKI+jnun6y/i8zVle 2F2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WViQk21z; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id 16-20020a05600c021000b003f7f6827ab9sm7825038wmi.31.2023.06.11.01.59.44 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:44 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 13/26] target/arm/tcg: Extract NEON definitions to 'helper-neon.h.inc' Date: Sun, 11 Jun 2023 10:58:33 +0200 Message-Id: <20230611085846.21415-14-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org helper.h is used by all units, but not all require the NEON definitions. Move them to a new header; the next commit will remove it from the common helper.h. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/helper.h | 207 +----------------------------- target/arm/tcg/helper-neon.h.inc | 213 +++++++++++++++++++++++++++++++ 2 files changed, 214 insertions(+), 206 deletions(-) create mode 100644 target/arm/tcg/helper-neon.h.inc diff --git a/target/arm/helper.h b/target/arm/helper.h index 1041accf71..97d97dc9d8 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -105,8 +105,6 @@ DEF_HELPER_FLAGS_5(probe_access, TCG_CALL_NO_WG, void, env, tl, i32, i32, i32) DEF_HELPER_FLAGS_2(set_rmode, TCG_CALL_NO_RWG, i32, i32, ptr) -DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) - DEF_HELPER_3(shl_cc, i32, env, i32, i32) DEF_HELPER_3(shr_cc, i32, env, i32, i32) DEF_HELPER_3(sar_cc, i32, env, i32, i32) @@ -117,191 +115,6 @@ DEF_HELPER_FLAGS_2(fjcvtzs, TCG_CALL_NO_RWG, i64, f64, ptr) DEF_HELPER_FLAGS_3(check_hcr_el2_trap, TCG_CALL_NO_WG, void, env, i32, i32) -/* neon_helper.c */ -DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_qadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_qadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_qadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_qadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_uqadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_uqadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_uqadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_uqadd_s64, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_FLAGS_3(neon_sqadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_sqadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_sqadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32) -DEF_HELPER_FLAGS_3(neon_sqadd_u64, TCG_CALL_NO_RWG, i64, env, i64, i64) -DEF_HELPER_3(neon_qsub_u8, i32, env, i32, i32) -DEF_HELPER_3(neon_qsub_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qsub_u16, i32, env, i32, i32) -DEF_HELPER_3(neon_qsub_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qsub_u32, i32, env, i32, i32) -DEF_HELPER_3(neon_qsub_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qadd_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qadd_s64, i64, env, i64, i64) -DEF_HELPER_3(neon_qsub_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qsub_s64, i64, env, i64, i64) - -DEF_HELPER_2(neon_hadd_s8, i32, i32, i32) -DEF_HELPER_2(neon_hadd_u8, i32, i32, i32) -DEF_HELPER_2(neon_hadd_s16, i32, i32, i32) -DEF_HELPER_2(neon_hadd_u16, i32, i32, i32) -DEF_HELPER_2(neon_hadd_s32, s32, s32, s32) -DEF_HELPER_2(neon_hadd_u32, i32, i32, i32) -DEF_HELPER_2(neon_rhadd_s8, i32, i32, i32) -DEF_HELPER_2(neon_rhadd_u8, i32, i32, i32) -DEF_HELPER_2(neon_rhadd_s16, i32, i32, i32) -DEF_HELPER_2(neon_rhadd_u16, i32, i32, i32) -DEF_HELPER_2(neon_rhadd_s32, s32, s32, s32) -DEF_HELPER_2(neon_rhadd_u32, i32, i32, i32) -DEF_HELPER_2(neon_hsub_s8, i32, i32, i32) -DEF_HELPER_2(neon_hsub_u8, i32, i32, i32) -DEF_HELPER_2(neon_hsub_s16, i32, i32, i32) -DEF_HELPER_2(neon_hsub_u16, i32, i32, i32) -DEF_HELPER_2(neon_hsub_s32, s32, s32, s32) -DEF_HELPER_2(neon_hsub_u32, i32, i32, i32) - -DEF_HELPER_2(neon_pmin_u8, i32, i32, i32) -DEF_HELPER_2(neon_pmin_s8, i32, i32, i32) -DEF_HELPER_2(neon_pmin_u16, i32, i32, i32) -DEF_HELPER_2(neon_pmin_s16, i32, i32, i32) -DEF_HELPER_2(neon_pmax_u8, i32, i32, i32) -DEF_HELPER_2(neon_pmax_s8, i32, i32, i32) -DEF_HELPER_2(neon_pmax_u16, i32, i32, i32) -DEF_HELPER_2(neon_pmax_s16, i32, i32, i32) - -DEF_HELPER_2(neon_shl_u16, i32, i32, i32) -DEF_HELPER_2(neon_shl_s16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u8, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s8, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s16, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u32, i32, i32, i32) -DEF_HELPER_2(neon_rshl_s32, i32, i32, i32) -DEF_HELPER_2(neon_rshl_u64, i64, i64, i64) -DEF_HELPER_2(neon_rshl_s64, i64, i64, i64) -DEF_HELPER_3(neon_qshl_u8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshl_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qshl_s64, i64, env, i64, i64) -DEF_HELPER_3(neon_qshlu_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qshlu_s64, i64, env, i64, i64) -DEF_HELPER_3(neon_qrshl_u8, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s8, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64) -DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64) - -DEF_HELPER_2(neon_add_u8, i32, i32, i32) -DEF_HELPER_2(neon_add_u16, i32, i32, i32) -DEF_HELPER_2(neon_padd_u8, i32, i32, i32) -DEF_HELPER_2(neon_padd_u16, i32, i32, i32) -DEF_HELPER_2(neon_sub_u8, i32, i32, i32) -DEF_HELPER_2(neon_sub_u16, i32, i32, i32) -DEF_HELPER_2(neon_mul_u8, i32, i32, i32) -DEF_HELPER_2(neon_mul_u16, i32, i32, i32) - -DEF_HELPER_2(neon_tst_u8, i32, i32, i32) -DEF_HELPER_2(neon_tst_u16, i32, i32, i32) -DEF_HELPER_2(neon_tst_u32, i32, i32, i32) - -DEF_HELPER_1(neon_clz_u8, i32, i32) -DEF_HELPER_1(neon_clz_u16, i32, i32) -DEF_HELPER_1(neon_cls_s8, i32, i32) -DEF_HELPER_1(neon_cls_s16, i32, i32) -DEF_HELPER_1(neon_cls_s32, i32, i32) -DEF_HELPER_1(neon_cnt_u8, i32, i32) -DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32) - -DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) -DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) -DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) -DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) -DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) -DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) -DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) -DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) - -DEF_HELPER_1(neon_narrow_u8, i32, i64) -DEF_HELPER_1(neon_narrow_u16, i32, i64) -DEF_HELPER_2(neon_unarrow_sat8, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_u8, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_s8, i32, env, i64) -DEF_HELPER_2(neon_unarrow_sat16, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_u16, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_s16, i32, env, i64) -DEF_HELPER_2(neon_unarrow_sat32, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_u32, i32, env, i64) -DEF_HELPER_2(neon_narrow_sat_s32, i32, env, i64) -DEF_HELPER_1(neon_narrow_high_u8, i32, i64) -DEF_HELPER_1(neon_narrow_high_u16, i32, i64) -DEF_HELPER_1(neon_narrow_round_high_u8, i32, i64) -DEF_HELPER_1(neon_narrow_round_high_u16, i32, i64) -DEF_HELPER_1(neon_widen_u8, i64, i32) -DEF_HELPER_1(neon_widen_s8, i64, i32) -DEF_HELPER_1(neon_widen_u16, i64, i32) -DEF_HELPER_1(neon_widen_s16, i64, i32) - -DEF_HELPER_2(neon_addl_u16, i64, i64, i64) -DEF_HELPER_2(neon_addl_u32, i64, i64, i64) -DEF_HELPER_2(neon_paddl_u16, i64, i64, i64) -DEF_HELPER_2(neon_paddl_u32, i64, i64, i64) -DEF_HELPER_2(neon_subl_u16, i64, i64, i64) -DEF_HELPER_2(neon_subl_u32, i64, i64, i64) -DEF_HELPER_3(neon_addl_saturate_s32, i64, env, i64, i64) -DEF_HELPER_3(neon_addl_saturate_s64, i64, env, i64, i64) -DEF_HELPER_2(neon_abdl_u16, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s16, i64, i32, i32) -DEF_HELPER_2(neon_abdl_u32, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s32, i64, i32, i32) -DEF_HELPER_2(neon_abdl_u64, i64, i32, i32) -DEF_HELPER_2(neon_abdl_s64, i64, i32, i32) -DEF_HELPER_2(neon_mull_u8, i64, i32, i32) -DEF_HELPER_2(neon_mull_s8, i64, i32, i32) -DEF_HELPER_2(neon_mull_u16, i64, i32, i32) -DEF_HELPER_2(neon_mull_s16, i64, i32, i32) - -DEF_HELPER_1(neon_negl_u16, i64, i64) -DEF_HELPER_1(neon_negl_u32, i64, i64) - -DEF_HELPER_FLAGS_2(neon_qabs_s8, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s16, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s32, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qabs_s64, TCG_CALL_NO_RWG, i64, env, i64) -DEF_HELPER_FLAGS_2(neon_qneg_s8, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32) -DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64) - -DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr) -DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr) -DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr) -DEF_HELPER_3(neon_acge_f32, i32, i32, i32, ptr) -DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, ptr) -DEF_HELPER_3(neon_acge_f64, i64, i64, i64, ptr) -DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, ptr) - -DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qunzip32, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_zip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_zip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr) -DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr) - DEF_HELPER_FLAGS_4(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) @@ -403,13 +216,6 @@ DEF_HELPER_FLAGS_6(gvec_fcmlas_idx, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_6(gvec_fcmlad, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_paddh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_pmaxh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_pminh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_padds, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_pmaxs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_pmins, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) - DEF_HELPER_FLAGS_4(gvec_sstoh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_sitos, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_ustoh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) @@ -630,8 +436,6 @@ DEF_HELPER_FLAGS_4(gvec_ushl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_pmul_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_pmull_q, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(neon_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - DEF_HELPER_FLAGS_3(gvec_ssra_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_ssra_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_ssra_s, TCG_CALL_NO_RWG, void, ptr, ptr, i32) @@ -710,16 +514,6 @@ DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqdmulh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqdmulh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_5(neon_sqrdmulh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - DEF_HELPER_FLAGS_4(sve2_sqdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve2_sqdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve2_sqdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) @@ -795,4 +589,5 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-sme.h.inc" #endif +#include "tcg/helper-neon.h.inc" #include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/helper-neon.h.inc b/target/arm/tcg/helper-neon.h.inc new file mode 100644 index 0000000000..5ea58c058c --- /dev/null +++ b/target/arm/tcg/helper-neon.h.inc @@ -0,0 +1,213 @@ +/* + * ARM NEON helper definitions + * + * Copyright (c) 2007, 2008 CodeSourcery. + * Written by Paul Brook + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i64, env, i32, i64, i64) + +DEF_HELPER_FLAGS_3(neon_qadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_qadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_uqadd_s8, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_uqadd_s16, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_uqadd_s32, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_uqadd_s64, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(neon_sqadd_u8, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_sqadd_u16, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_sqadd_u32, TCG_CALL_NO_RWG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(neon_sqadd_u64, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_3(neon_qsub_u8, i32, env, i32, i32) +DEF_HELPER_3(neon_qsub_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qsub_u16, i32, env, i32, i32) +DEF_HELPER_3(neon_qsub_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qsub_u32, i32, env, i32, i32) +DEF_HELPER_3(neon_qsub_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qadd_u64, i64, env, i64, i64) +DEF_HELPER_3(neon_qadd_s64, i64, env, i64, i64) +DEF_HELPER_3(neon_qsub_u64, i64, env, i64, i64) +DEF_HELPER_3(neon_qsub_s64, i64, env, i64, i64) + +DEF_HELPER_2(neon_hadd_s8, i32, i32, i32) +DEF_HELPER_2(neon_hadd_u8, i32, i32, i32) +DEF_HELPER_2(neon_hadd_s16, i32, i32, i32) +DEF_HELPER_2(neon_hadd_u16, i32, i32, i32) +DEF_HELPER_2(neon_hadd_s32, s32, s32, s32) +DEF_HELPER_2(neon_hadd_u32, i32, i32, i32) +DEF_HELPER_2(neon_rhadd_s8, i32, i32, i32) +DEF_HELPER_2(neon_rhadd_u8, i32, i32, i32) +DEF_HELPER_2(neon_rhadd_s16, i32, i32, i32) +DEF_HELPER_2(neon_rhadd_u16, i32, i32, i32) +DEF_HELPER_2(neon_rhadd_s32, s32, s32, s32) +DEF_HELPER_2(neon_rhadd_u32, i32, i32, i32) +DEF_HELPER_2(neon_hsub_s8, i32, i32, i32) +DEF_HELPER_2(neon_hsub_u8, i32, i32, i32) +DEF_HELPER_2(neon_hsub_s16, i32, i32, i32) +DEF_HELPER_2(neon_hsub_u16, i32, i32, i32) +DEF_HELPER_2(neon_hsub_s32, s32, s32, s32) +DEF_HELPER_2(neon_hsub_u32, i32, i32, i32) + +DEF_HELPER_2(neon_pmin_u8, i32, i32, i32) +DEF_HELPER_2(neon_pmin_s8, i32, i32, i32) +DEF_HELPER_2(neon_pmin_u16, i32, i32, i32) +DEF_HELPER_2(neon_pmin_s16, i32, i32, i32) +DEF_HELPER_2(neon_pmax_u8, i32, i32, i32) +DEF_HELPER_2(neon_pmax_s8, i32, i32, i32) +DEF_HELPER_2(neon_pmax_u16, i32, i32, i32) +DEF_HELPER_2(neon_pmax_s16, i32, i32, i32) + +DEF_HELPER_2(neon_shl_u16, i32, i32, i32) +DEF_HELPER_2(neon_shl_s16, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u8, i32, i32, i32) +DEF_HELPER_2(neon_rshl_s8, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u16, i32, i32, i32) +DEF_HELPER_2(neon_rshl_s16, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u32, i32, i32, i32) +DEF_HELPER_2(neon_rshl_s32, i32, i32, i32) +DEF_HELPER_2(neon_rshl_u64, i64, i64, i64) +DEF_HELPER_2(neon_rshl_s64, i64, i64, i64) +DEF_HELPER_3(neon_qshl_u8, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_u16, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_u32, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qshl_u64, i64, env, i64, i64) +DEF_HELPER_3(neon_qshl_s64, i64, env, i64, i64) +DEF_HELPER_3(neon_qshlu_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qshlu_s64, i64, env, i64, i64) +DEF_HELPER_3(neon_qrshl_u8, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_s8, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_u16, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_u32, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qrshl_u64, i64, env, i64, i64) +DEF_HELPER_3(neon_qrshl_s64, i64, env, i64, i64) + +DEF_HELPER_2(neon_add_u8, i32, i32, i32) +DEF_HELPER_2(neon_add_u16, i32, i32, i32) +DEF_HELPER_2(neon_padd_u8, i32, i32, i32) +DEF_HELPER_2(neon_padd_u16, i32, i32, i32) +DEF_HELPER_2(neon_sub_u8, i32, i32, i32) +DEF_HELPER_2(neon_sub_u16, i32, i32, i32) +DEF_HELPER_2(neon_mul_u8, i32, i32, i32) +DEF_HELPER_2(neon_mul_u16, i32, i32, i32) + +DEF_HELPER_2(neon_tst_u8, i32, i32, i32) +DEF_HELPER_2(neon_tst_u16, i32, i32, i32) +DEF_HELPER_2(neon_tst_u32, i32, i32, i32) + +DEF_HELPER_1(neon_clz_u8, i32, i32) +DEF_HELPER_1(neon_clz_u16, i32, i32) +DEF_HELPER_1(neon_cls_s8, i32, i32) +DEF_HELPER_1(neon_cls_s16, i32, i32) +DEF_HELPER_1(neon_cls_s32, i32, i32) +DEF_HELPER_1(neon_cnt_u8, i32, i32) +DEF_HELPER_FLAGS_1(neon_rbit_u8, TCG_CALL_NO_RWG_SE, i32, i32) + +DEF_HELPER_3(neon_qdmulh_s16, i32, env, i32, i32) +DEF_HELPER_3(neon_qrdmulh_s16, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s16, i32, env, i32, i32, i32) +DEF_HELPER_4(neon_qrdmlsh_s16, i32, env, i32, i32, i32) +DEF_HELPER_3(neon_qdmulh_s32, i32, env, i32, i32) +DEF_HELPER_3(neon_qrdmulh_s32, i32, env, i32, i32) +DEF_HELPER_4(neon_qrdmlah_s32, i32, env, s32, s32, s32) +DEF_HELPER_4(neon_qrdmlsh_s32, i32, env, s32, s32, s32) + +DEF_HELPER_1(neon_narrow_u8, i32, i64) +DEF_HELPER_1(neon_narrow_u16, i32, i64) +DEF_HELPER_2(neon_unarrow_sat8, i32, env, i64) +DEF_HELPER_2(neon_narrow_sat_u8, i32, env, i64) +DEF_HELPER_2(neon_narrow_sat_s8, i32, env, i64) +DEF_HELPER_2(neon_unarrow_sat16, i32, env, i64) +DEF_HELPER_2(neon_narrow_sat_u16, i32, env, i64) +DEF_HELPER_2(neon_narrow_sat_s16, i32, env, i64) +DEF_HELPER_2(neon_unarrow_sat32, i32, env, i64) +DEF_HELPER_2(neon_narrow_sat_u32, i32, env, i64) +DEF_HELPER_2(neon_narrow_sat_s32, i32, env, i64) +DEF_HELPER_1(neon_narrow_high_u8, i32, i64) +DEF_HELPER_1(neon_narrow_high_u16, i32, i64) +DEF_HELPER_1(neon_narrow_round_high_u8, i32, i64) +DEF_HELPER_1(neon_narrow_round_high_u16, i32, i64) +DEF_HELPER_1(neon_widen_u8, i64, i32) +DEF_HELPER_1(neon_widen_s8, i64, i32) +DEF_HELPER_1(neon_widen_u16, i64, i32) +DEF_HELPER_1(neon_widen_s16, i64, i32) + +DEF_HELPER_2(neon_addl_u16, i64, i64, i64) +DEF_HELPER_2(neon_addl_u32, i64, i64, i64) +DEF_HELPER_2(neon_paddl_u16, i64, i64, i64) +DEF_HELPER_2(neon_paddl_u32, i64, i64, i64) +DEF_HELPER_2(neon_subl_u16, i64, i64, i64) +DEF_HELPER_2(neon_subl_u32, i64, i64, i64) +DEF_HELPER_3(neon_addl_saturate_s32, i64, env, i64, i64) +DEF_HELPER_3(neon_addl_saturate_s64, i64, env, i64, i64) +DEF_HELPER_2(neon_abdl_u16, i64, i32, i32) +DEF_HELPER_2(neon_abdl_s16, i64, i32, i32) +DEF_HELPER_2(neon_abdl_u32, i64, i32, i32) +DEF_HELPER_2(neon_abdl_s32, i64, i32, i32) +DEF_HELPER_2(neon_abdl_u64, i64, i32, i32) +DEF_HELPER_2(neon_abdl_s64, i64, i32, i32) +DEF_HELPER_2(neon_mull_u8, i64, i32, i32) +DEF_HELPER_2(neon_mull_s8, i64, i32, i32) +DEF_HELPER_2(neon_mull_u16, i64, i32, i32) +DEF_HELPER_2(neon_mull_s16, i64, i32, i32) + +DEF_HELPER_1(neon_negl_u16, i64, i64) +DEF_HELPER_1(neon_negl_u32, i64, i64) + +DEF_HELPER_FLAGS_2(neon_qabs_s8, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s16, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s32, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qabs_s64, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(neon_qneg_s8, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s16, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s32, TCG_CALL_NO_RWG, i32, env, i32) +DEF_HELPER_FLAGS_2(neon_qneg_s64, TCG_CALL_NO_RWG, i64, env, i64) + +DEF_HELPER_3(neon_ceq_f32, i32, i32, i32, ptr) +DEF_HELPER_3(neon_cge_f32, i32, i32, i32, ptr) +DEF_HELPER_3(neon_cgt_f32, i32, i32, i32, ptr) +DEF_HELPER_3(neon_acge_f32, i32, i32, i32, ptr) +DEF_HELPER_3(neon_acgt_f32, i32, i32, i32, ptr) +DEF_HELPER_3(neon_acge_f64, i64, i64, i64, ptr) +DEF_HELPER_3(neon_acgt_f64, i64, i64, i64, ptr) + +DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip32, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_zip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_zip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr) + +DEF_HELPER_FLAGS_5(neon_paddh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_pmaxh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_pminh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_padds, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_pmaxs, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_pmins, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(neon_pmull_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqdmulh_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqdmulh_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(neon_sqrdmulh_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(neon_sqrdmulh_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) From patchwork Sun Jun 11 08:58:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691347 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1571326wru; Sun, 11 Jun 2023 02:01:42 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4s94LRh62s65AJUVhsIcVU7L74kINvrs1+CmJqoKKNeHtcgsRiPzSCIIF4sdqmO0igqxN3 X-Received: by 2002:a37:6403:0:b0:75b:25a2:c284 with SMTP id y3-20020a376403000000b0075b25a2c284mr4827066qkb.30.1686474102489; Sun, 11 Jun 2023 02:01:42 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474102; cv=none; d=google.com; s=arc-20160816; b=icihrRTSI+UV6kiD+i16sx1cizdbAx9bK+sjcWmvBBwkIm5a/Y1WHU0UWHFNjhwjAp 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id o7-20020adfeac7000000b002fed865c55esm9139039wrn.56.2023.06.11.01.59.48 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:48 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 14/26] target/arm/tcg: Reduce 'helper-neon.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:34 +0200 Message-Id: <20230611085846.21415-15-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of including helper-neon.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/helper.h | 1 - target/arm/tcg/neon_helper.c | 5 ++++- target/arm/tcg/translate-a64.c | 4 ++++ target/arm/tcg/translate-neon.c | 6 ++++++ target/arm/tcg/translate-sme.c | 4 ++++ target/arm/tcg/translate.c | 4 ++++ target/arm/tcg/vec_helper.c | 4 ++++ 7 files changed, 26 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 97d97dc9d8..eb8ac68dc8 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -589,5 +589,4 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-sme.h.inc" #endif -#include "tcg/helper-neon.h.inc" #include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/neon_helper.c b/target/arm/tcg/neon_helper.c index 0a4ab3e42c..0432a6e771 100644 --- a/target/arm/tcg/neon_helper.c +++ b/target/arm/tcg/neon_helper.c @@ -9,10 +9,13 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "vec_internal.h" +#define HELPER_H "tcg/helper-neon.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index c0727c900f..22caf89bb0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -30,6 +30,10 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-neon.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c index 497aba2e39..9a1831f849 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -28,6 +28,12 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-neon.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + /* Include the generated Neon decoder */ #include "decode-neon-dp.c.inc" #include "decode-neon-ls.c.inc" diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index d0054e3f77..24796e5d9e 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -21,6 +21,10 @@ #include "translate.h" #include "translate-a64.h" +#define HELPER_H "tcg/helper-neon.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + /* * Include the generated decoder. */ diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index a352fced6e..2b3951cece 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -29,6 +29,10 @@ #include "cpregs.h" #include "exec/helper-proto.h" +#define HELPER_H "tcg/helper-neon.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" #undef HELPER_H diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 013ca1b05f..af325577f0 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -29,6 +29,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-neon.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* * Data for expanding active predicate bits to bytes, for byte elements. * From patchwork Sun Jun 11 08:58:35 2023 Content-Type: text/plain; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id 8-20020a05600c230800b003f7ed9dae70sm7858539wmo.0.2023.06.11.01.59.52 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 15/26] target/arm/tcg: Extract SVE2 definitions to 'helper-sve.h.inc' Date: Sun, 11 Jun 2023 10:58:35 +0200 Message-Id: <20230611085846.21415-16-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org helper.h is used by all units, but not all require the SVE2 definitions. We already have helper-sve.h.inc for SVE* definitions, move them there. The next commit will remove it from the common helper.h. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/helper.h | 46 --------------------------------- target/arm/tcg/helper-sve.h.inc | 46 +++++++++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 46 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index eb8ac68dc8..444be99c96 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -162,23 +162,6 @@ DEF_HELPER_FLAGS_5(gvec_qrdmlah_s32, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_qrdmlsh_s32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_b, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlah_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, i32) - DEF_HELPER_FLAGS_5(gvec_sdot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_udot_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_sdot_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) @@ -514,35 +497,6 @@ DEF_HELPER_FLAGS_5(gvec_mls_idx_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(gvec_mls_idx_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_h, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_d, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, i32) - -DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, ptr, i32) -DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG, - void, ptr, ptr, ptr, ptr, ptr, i32) - DEF_HELPER_FLAGS_4(gvec_xar_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_smmla_b, TCG_CALL_NO_RWG, diff --git a/target/arm/tcg/helper-sve.h.inc b/target/arm/tcg/helper-sve.h.inc index cc4e1d8948..042a29d76a 100644 --- a/target/arm/tcg/helper-sve.h.inc +++ b/target/arm/tcg/helper-sve.h.inc @@ -2802,3 +2802,49 @@ DEF_HELPER_FLAGS_4(sve2_sqshlu_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve2_sqshlu_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve2_sqshlu_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(sve2_sqshlu_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlah_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve2_sqrdmlsh_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqdmulh_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(sve2_sqrdmulh_idx_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_6(sve2_fmlal_zzzw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_6(sve2_fmlal_zzxw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, i32) From patchwork Sun Jun 11 08:58:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691351 Delivered-To: patch@linaro.org Received: by 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id w25-20020a1cf619000000b003f7f52c9988sm7877641wmc.21.2023.06.11.01.59.57 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 01:59:57 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 16/26] target/arm/tcg: Reduce 'helper-sve.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:36 +0200 Message-Id: <20230611085846.21415-17-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philmd@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of including helper-sve.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/helper.h | 1 - target/arm/tcg/sve_helper.c | 4 ++++ target/arm/tcg/translate-sme.c | 4 ++++ target/arm/tcg/translate-sve.c | 5 +++++ target/arm/tcg/vec_helper.c | 4 ++++ 5 files changed, 17 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 444be99c96..134d428175 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -539,7 +539,6 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #ifdef TARGET_AARCH64 #include "tcg/helper-a64.h.inc" -#include "tcg/helper-sve.h.inc" #include "tcg/helper-sme.h.inc" #endif diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 8a0d966aae..79a42af591 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -33,6 +33,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-sve.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* Return a value for NZCV as per the ARM PredTest pseudofunction. * * The return value has bit 31 set if N is set, bit 1 set if Z is clear, diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index 24796e5d9e..e63b9883a9 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -25,6 +25,10 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-sve.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + /* * Include the generated decoder. */ diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index ff050626e6..45a36760fd 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -22,6 +22,11 @@ #include "translate-a64.h" #include "fpu/softfloat.h" +#define HELPER_H "tcg/helper-sve.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H typedef void GVecGen2sFn(unsigned, uint32_t, uint32_t, TCGv_i64, uint32_t, uint32_t); diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index af325577f0..d93960198f 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -33,6 +33,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-sve.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* * Data for expanding active predicate bits to bytes, for byte elements. * From patchwork Sun Jun 11 08:58:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691365 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1572835wru; Sun, 11 Jun 2023 02:06:57 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7g+uWkQRLbGf2BBu1s2kfQwOZT0mp9oKVBOFJtxNR/Z89gMc6SymkYFCjLK4wzYSveaUG1 X-Received: by 2002:a05:620a:c46:b0:75e:d987:9d36 with SMTP id u6-20020a05620a0c4600b0075ed9879d36mr6428089qki.16.1686474417365; Sun, 11 Jun 2023 02:06:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474417; cv=none; d=google.com; s=arc-20160816; b=l6fhfWOTcdonU/pJUZKa7cYRj/G+KfpLD907fEo2WdU7a2wpsrSPHzvOZ75hQAHxP3 H2NVfCVwEs6AJbSlUTQrHSxBVyAfW/xz9NvJWdSGUBWbBKyhRmLMSA+oE6cdI6h+gYs5 ewhoUdlVGCqP40IM/BAOkHIdfM/M4F9pz4R02MHNn9T64KhPEBOVSnvvqjGjgh/vWZD1 Bt2vaRXQXMdYJlorHDYQiEmnGRRhE9oKFHH2zGo3czY8AyBm4w+KgBzAROcjZKcV20YG rsl8RJYUVcwCpa3zTIY8mkZgTrDcUqmgACQ1Q/DZFE+qx2ybWCKGi3O6VtItUJHTsNUa vvlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=btom/u1hZkX8UjQkUT1e66Oa9l3yd2W6yx3XFKKVFxk=; b=Klwt4+qrsd3mhf93yJRhwUeqe7C8Krkubbeu4w+GDGgTFCW0//B1Icl1hSK+GNLwXT GkZgsRUfpmbHFcHH48QU11H0ODe5WrUe5AITHZVQQO7zSJ0E5yx5GstkZYMIBzDg2DPj IYqpYCWd4KCa3Dqi1SixL/wXC89EwNm0PA595Fo/PMuRjR/jZQNn7ObicG4EYbkkf3bQ //D0L5lRz6RgkUZe92sj2IxGIX1SkR4Tln4WaTRbGN+/Oc8HmVASBWedMLaFdZKYAlJa WyV62yFVD8HUmaE/gPCN4l+5P0u+vI9EXW3jrENXgO/eEUZ0UxJ9ipWmQiHGpR9dw+PM kgOg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WBikaPQO; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id cr5-20020a05600004e500b0030c6751a49dsm9070871wrb.115.2023.06.11.02.00.01 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:01 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 17/26] target/arm/tcg: Reduce 'helper-mve.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:37 +0200 Message-Id: <20230611085846.21415-18-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of including helper-mve.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/helper.h | 2 -- target/arm/tcg/mve_helper.c | 5 ++++- target/arm/tcg/translate-mve.c | 6 ++++++ target/arm/tcg/translate.c | 4 ++++ 4 files changed, 14 insertions(+), 3 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 134d428175..61cd8fd21e 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -541,5 +541,3 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #include "tcg/helper-a64.h.inc" #include "tcg/helper-sme.h.inc" #endif - -#include "tcg/helper-mve.h.inc" diff --git a/target/arm/tcg/mve_helper.c b/target/arm/tcg/mve_helper.c index d8ba5a9e60..a3fca486e0 100644 --- a/target/arm/tcg/mve_helper.c +++ b/target/arm/tcg/mve_helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "internals.h" #include "vec_internal.h" -#include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "tcg/tcg.h" @@ -31,6 +30,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-mve.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + static uint16_t mve_eci_mask(CPUARMState *env) { /* diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c index bbc7b3f4ce..8577dc4377 100644 --- a/target/arm/tcg/translate-mve.c +++ b/target/arm/tcg/translate-mve.c @@ -21,6 +21,12 @@ #include "translate.h" #include "translate-a32.h" +#define HELPER_H "tcg/helper-mve.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + static inline int vidup_imm(DisasContext *s, int x) { return 1 << x; diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 2b3951cece..d88b355230 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -33,6 +33,10 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-mve.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" #undef HELPER_H From patchwork Sun Jun 11 08:58:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691356 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1572472wru; Sun, 11 Jun 2023 02:05:26 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ48ui0T6r4KXvtPTk9KaX5YeTkfNNDzhvwA/EsEg3tVaRKkdIh9OT5Ho4IO5RTVlIZBkfPU X-Received: by 2002:a05:6214:c83:b0:5ef:519:b1a with SMTP id r3-20020a0562140c8300b005ef05190b1amr7623337qvr.24.1686474326459; Sun, 11 Jun 2023 02:05:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474326; cv=none; d=google.com; s=arc-20160816; b=REu9yrebp+ZY+p5wqYXYNqPymhCJfVaN7AP5cXG3FqNTZK1sVdTTm/ULQEINjX71kd EB5QXoKP5gTqAvz7aA7nXGMOky6b4B0n38iNa7JgcOj5B342BkG29jMqyws1mjpMTZYs +5/ncsnuJU9JMBFF4MbrcJwZ6QRQucy7E81tH8k0Bph3Oi7bp5JSwLaeO/JMMYaVx9v4 LdcT4xUcS6dnrS3/iOAQK+cFJnc6z+7VcmAS96zG9JsYM/jH+ECYrto3/ksDZe/Qj+I8 i4l4dFxZ6Cjjzp8YD8r3aChut1IjVY/AWWSUv3jIKLuA4ONVoFEA2Sp8UvLGFcGtH3hB GgoA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=6fgvCMeWGWtzi1ogVNS3n2ceF5EfOYaR43hCpswXEso=; b=gxN92sRYZfge9xtRW8AFJi4Ve6yfEDM2AifDtfZj5ySxkRwWPydyNjaay77l36cB1G EhiKNb4ack/KoDRL9Adr+eKeNJFrIDtYq91qSHd1h9/DinS60aHQ105y17ZWgdYBbXa+ yARUotio6DTCzkF40e4FSX56KY8ojrRcaUJ/I0lPXkkTXmlRVEBvYtvWRRBOoDgJrTdP lASaPtAsRwpSBCXOOAkaQ3lAWVhQTjs/cBC/GDKgfFCd4hnuDmzzoYkurb3vnKhufn4W H5iQHheIaxRhWiSM3HkwUO6VovN0mmAbC0XQlzI7c/jU6X2ugWzYbq/zh+KUJ8C7e5Gz oOfw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="j/qXLV/9"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id d17-20020adffbd1000000b0030fb4b55c13sm3028336wrs.96.2023.06.11.02.00.05 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:05 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 18/26] target/arm/tcg: Reduce 'helper-sme.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:38 +0200 Message-Id: <20230611085846.21415-19-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=philmd@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of including helper-sme.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/helper.h | 1 - target/arm/tcg/sme_helper.c | 5 ++++- target/arm/tcg/translate-a64.c | 4 ++++ target/arm/tcg/translate-sme.c | 6 ++++++ 4 files changed, 14 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 61cd8fd21e..b7201eb89c 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -539,5 +539,4 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, #ifdef TARGET_AARCH64 #include "tcg/helper-a64.h.inc" -#include "tcg/helper-sme.h.inc" #endif diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c index 1e67fcac30..04170ad18d 100644 --- a/target/arm/tcg/sme_helper.c +++ b/target/arm/tcg/sme_helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "internals.h" #include "tcg/tcg-gvec-desc.h" -#include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "qemu/int128.h" @@ -29,6 +28,10 @@ #include "vec_internal.h" #include "sve_ldst_internal.h" +#define HELPER_H "tcg/helper-sme.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + void helper_set_svcr(CPUARMState *env, uint32_t val, uint32_t mask) { aarch64_set_svcr(env, val, mask); diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 22caf89bb0..d1ab1edf6d 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -34,6 +34,10 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-sme.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index e63b9883a9..fa0dc20bf2 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -29,6 +29,12 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-sme.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + /* * Include the generated decoder. */ From patchwork Sun Jun 11 08:58:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691353 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1572385wru; Sun, 11 Jun 2023 02:05:05 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6WKUDJcVRPCvRaLCJ/UtaF6ZMlMK1hnMLEPKv75wNZaM3aPwIf1tSW870rNja4jH3cKS7B X-Received: by 2002:a05:620a:800a:b0:75e:bcef:aa35 with SMTP id ee10-20020a05620a800a00b0075ebcefaa35mr7330226qkb.40.1686474304989; Sun, 11 Jun 2023 02:05:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474304; cv=none; d=google.com; s=arc-20160816; b=GG2NspvNduJRfjp3VZFusDGIGZkj31moDH/TXSs/4f/6S3z9IWnsbkwnlsNlRqrkCq 2r8cbTzUrgHfOHjSKlceFEMcdH9ATIIRxNBRQz6/JefnPJXF8us8gxN5MOPVUNxmKK0H vCVtZ0+dOLOhxKNOfG5ZZ7l61AghUHj9WWe5tlIq8c0uwKpo+ZbmgGHPXrET0xo7R8Ro mW6ch65z37w1nuJlQ4/NQus3YVsj7IJ8y+HXwIZ5IVPdJjmWMTy4MNi8a0aNvOyT1mca 33kR5qGVumOY5PQ7WQRPTYnZRvuXn1Z7T20E+0jCqu7Kc3pw8ZQz1gfUWjrvY7oI+L0C aK8w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JMWaSEeC21286qg08dnBXfstMJP9JJH0vEjQ7Wn/jbk=; b=HLuBNBDJCJZLZ4jxTSWWx2V/n+OZhza3rKUrxZEoOb9o98Vy1ESbTx/zgAVAKLboy0 qTJn0swFZtS71eidSO2WjY0Sd6OR9trLPsOs8vBhjpIeirr4bI/0EN4BbHlvtsgav/la jc/OwzD53N7+Su8Spni1I+p68tgGdA6U6YekDlBx2hqfPN378HqLod/qmkfge1El/zah SekXJFV5+cSmfQ2RZQACRNgQxiLzD9SBDySGd3x06qYolav+yw2ZRn05vefKcqj1stqR wRfE9Mmb5X27lbYMc6Tjyp2Vf5PcPDcZ01BW4ea8HsANV+vT29TAhv3apEfbcILjA7Mj HNcw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=EbpgekJs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id h17-20020a05600c28d100b003f080b2f9f4sm7895759wmd.27.2023.06.11.02.00.10 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 19/26] target/arm/tcg: Reduce 'helper-a64.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:39 +0200 Message-Id: <20230611085846.21415-20-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=philmd@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of including helper-a64.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/helper.h | 4 ---- target/arm/tcg/helper-a64.c | 4 ++++ target/arm/tcg/mte_helper.c | 4 +++- target/arm/tcg/pauth_helper.c | 4 +++- target/arm/tcg/sve_helper.c | 5 ++++- target/arm/tcg/translate-a64.c | 6 ++++++ target/arm/tcg/vec_helper.c | 4 ++++ 7 files changed, 24 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b7201eb89c..71e2cd5580 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -536,7 +536,3 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) - -#ifdef TARGET_AARCH64 -#include "tcg/helper-a64.h.inc" -#endif diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 1c9370f07b..86133c6e0d 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -35,6 +35,10 @@ #include "fpu/softfloat.h" #include /* For crc32 */ +#define HELPER_H "tcg/helper-a64.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* C2.4.7 Multiply and divide */ /* special cases for 0 and LLONG_MIN are mandated by the standard */ uint64_t HELPER(udiv64)(uint64_t num, uint64_t den) diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 9c64def081..f29715869f 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -24,11 +24,13 @@ #include "exec/exec-all.h" #include "exec/ram_addr.h" #include "exec/cpu_ldst.h" -#include "exec/helper-proto.h" #include "hw/core/tcg-cpu-ops.h" #include "qapi/error.h" #include "qemu/guest-random.h" +#define HELPER_H "tcg/helper-a64.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H static int choose_nonexcluded_tag(int tag, int offset, uint16_t exclude) { diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 62af569341..3a8f0d820f 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -22,10 +22,12 @@ #include "internals.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "qemu/xxhash.h" +#define HELPER_H "tcg/helper-a64.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H static uint64_t pac_cell_shuffle(uint64_t i) { diff --git a/target/arm/tcg/sve_helper.c b/target/arm/tcg/sve_helper.c index 79a42af591..64f744bf6a 100644 --- a/target/arm/tcg/sve_helper.c +++ b/target/arm/tcg/sve_helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "tcg/tcg.h" @@ -37,6 +36,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-a64.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* Return a value for NZCV as per the ARM PredTest pseudofunction. * * The return value has bit 31 set if N is set, bit 1 set if Z is clear, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index d1ab1edf6d..6047f07f8c 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -38,6 +38,12 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-a64.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index d93960198f..9dd7e0f5e1 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -37,6 +37,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-a64.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* * Data for expanding active predicate bits to bytes, for byte elements. * From patchwork Sun Jun 11 08:58:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691355 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1572393wru; Sun, 11 Jun 2023 02:05:06 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5/PU+Od4oqpYx0ls2Swh873FLWWewLXJ9Yip2XZXK7MBzl1kDCZFPFV1jJ/ftErlwuhe54 X-Received: by 2002:ac8:5a09:0:b0:3f6:b151:7db1 with SMTP id n9-20020ac85a09000000b003f6b1517db1mr7308974qta.62.1686474306347; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id u5-20020a5d5145000000b0030fa57d8064sm5842041wrt.52.2023.06.11.02.00.14 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:14 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 20/26] target/arm/tcg: Move v8m_stackcheck() from op_helper.c to m_helper.c Date: Sun, 11 Jun 2023 10:58:40 +0200 Message-Id: <20230611085846.21415-21-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=philmd@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org No need to have the v8m_stackcheck() helper in the generic op_helper.c, move it with the rest of the M-profile helpers. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/tcg/m_helper.c | 16 ++++++++++++++++ target/arm/tcg/op_helper.c | 16 ---------------- 2 files changed, 16 insertions(+), 16 deletions(-) diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 0891acc29c..0780bb3dea 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -2893,3 +2893,19 @@ uint32_t *arm_v7m_get_sp_ptr(CPUARMState *env, bool secure, bool threadmode, } } } + +void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) +{ + /* + * Perform the v8M stack limit check for SP updates from translated code, + * raising an exception if the limit is breached. + */ + if (newvalue < v7m_sp_limit(env)) { + /* + * Stack limit exceptions are a rare case, so rather than syncing + * PC/condbits before the call, we use raise_exception_ra() so + * that cpu_restore_state() will sort them out. + */ + raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC()); + } +} diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 70a9c37b74..04a90e3e3a 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -82,22 +82,6 @@ void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, raise_exception(env, excp, syndrome, target_el); } -void HELPER(v8m_stackcheck)(CPUARMState *env, uint32_t newvalue) -{ - /* - * Perform the v8M stack limit check for SP updates from translated code, - * raising an exception if the limit is breached. - */ - if (newvalue < v7m_sp_limit(env)) { - /* - * Stack limit exceptions are a rare case, so rather than syncing - * PC/condbits before the call, we use raise_exception_ra() so - * that cpu_restore_state() will sort them out. - */ - raise_exception_ra(env, EXCP_STKOF, 0, 1, GETPC()); - } -} - uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b) { uint32_t res = a + b; From patchwork Sun Jun 11 08:58:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691350 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1572218wru; Sun, 11 Jun 2023 02:04:25 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4ZEpTC8GNFw807qN9Gqal1I626gRehs3LvpfkjBYA1qmRGB/hnWTvPhjiMwXiX9hHSGOr8 X-Received: by 2002:a05:6214:c67:b0:628:ed0e:a165 with SMTP id t7-20020a0562140c6700b00628ed0ea165mr7639743qvj.58.1686474265554; Sun, 11 Jun 2023 02:04:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474265; cv=none; d=google.com; s=arc-20160816; b=NRRf1gIuwCCfIjyhYrXVZEDEd/UesB59KJZ66w59nJC5sLkOnDWOzbgJ5zv2A63v78 T1s1LgZeUyYUF0EAyKJbB/kXNTOXIc6+biOPltSbsJ/+b/9xZjszJrNra9gpeO2QqYTV DBxYoz2IU/Q+/NZi5DxaJJv3Y9zrHAAW6gV/y3Bz+EmCM1jbh95n7pwAZ7YVCzxw6xc/ ReDQfr1isjCjJflfE+zVJYRNhcM1Lj8UAjEgWLasc1jSDQPdCdtSHdY+kHUyGPXXXVqo bXWxjUBJVYzPWtJ5bV68Y0SQeUi3dG8Bj37+4gvPHyOJ76wR5Jdm3cCdQ/GyRXn01LRW wPfw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=sFrqSxuYHrI3cS6SOens6cMF97H9CMcbIb+bhGC3+VE=; b=K1plmUSumONGSKcI3Nf/uSku4OCQPX6DIVCRkZewvq5Euwbb/LE5ukiqrLv0KoWGHZ SdjsRCcKy2LyCUPOGdLdCB0zNULexWgFBLa9edbfd7D7oyk9DG+xlzWaK+TbfTs9f7hR 8Y8wYPT+75wE3qySTE5TvyVsT/M13CTETi9VuDds5hoAeZLFIZzIXfOva9oKbC8w6SZt ONTLTa93gIjfumsFcHL9S1EnyIpjEX9gJl+y+bYz2EbjD6Dm6w9+L0y1wmN+pzKyykNT s4HPRrpSBPsJy6Mrm7yOtSzSenc4250baIB9tMBZdmZ8JtDTfUKsSESkm5u4KcTLREuf InBA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Amm+rujT; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id m11-20020a5d6a0b000000b0030b5d203e7esm9088473wru.97.2023.06.11.02.00.18 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:18 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 21/26] target/arm/tcg: Extract M-profile definitions to 'helper-m.h.inc' Date: Sun, 11 Jun 2023 10:58:41 +0200 Message-Id: <20230611085846.21415-22-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=philmd@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org helper.h is used by all units, but not all require the M-profile definitions. Move them to a new header; the next commit will remove it from the common helper.h. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/helper.h | 17 ++--------------- target/arm/tcg/helper-m.h.inc | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+), 15 deletions(-) create mode 100644 target/arm/tcg/helper-m.h.inc diff --git a/target/arm/helper.h b/target/arm/helper.h index 71e2cd5580..05117934f3 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -62,21 +62,6 @@ DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_2(cpsr_write_eret, void, env, i32) DEF_HELPER_1(cpsr_read, i32, env) -DEF_HELPER_3(v7m_msr, void, env, i32, i32) -DEF_HELPER_2(v7m_mrs, i32, env, i32) - -DEF_HELPER_2(v7m_bxns, void, env, i32) -DEF_HELPER_2(v7m_blxns, void, env, i32) - -DEF_HELPER_3(v7m_tt, i32, env, i32, i32) - -DEF_HELPER_1(v7m_preserve_fp_state, void, env) - -DEF_HELPER_2(v7m_vlstm, void, env, i32) -DEF_HELPER_2(v7m_vlldm, void, env, i32) - -DEF_HELPER_2(v8m_stackcheck, void, env, i32) - DEF_HELPER_FLAGS_2(check_bxj_trap, TCG_CALL_NO_WG, void, env, i32) DEF_HELPER_4(access_check_cp_reg, cptr, env, i32, i32, i32) @@ -536,3 +521,5 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) + +#include "tcg/helper-m.h.inc" diff --git a/target/arm/tcg/helper-m.h.inc b/target/arm/tcg/helper-m.h.inc new file mode 100644 index 0000000000..122311b6d0 --- /dev/null +++ b/target/arm/tcg/helper-m.h.inc @@ -0,0 +1,23 @@ +/* + * ARM M-profile helper definitions + * + * Copyright (c) 2007 CodeSourcery. + * Written by Paul Brook + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +DEF_HELPER_3(v7m_msr, void, env, i32, i32) +DEF_HELPER_2(v7m_mrs, i32, env, i32) + +DEF_HELPER_2(v7m_bxns, void, env, i32) +DEF_HELPER_2(v7m_blxns, void, env, i32) + +DEF_HELPER_3(v7m_tt, i32, env, i32, i32) + +DEF_HELPER_1(v7m_preserve_fp_state, void, env) + +DEF_HELPER_2(v7m_vlstm, void, env, i32) +DEF_HELPER_2(v7m_vlldm, void, env, i32) + +DEF_HELPER_2(v8m_stackcheck, void, env, i32) From patchwork Sun Jun 11 08:58:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691349 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1571590wru; Sun, 11 Jun 2023 02:02:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7oEOndsgv3ZO9shn1OlbaJojdFwkEQPrU2s6nCPMC5XbPp4SQEKaVuAT9ePYw49d+8LtRE X-Received: by 2002:a05:622a:547:b0:3f6:a400:2c25 with SMTP id m7-20020a05622a054700b003f6a4002c25mr8183746qtx.16.1686474144704; Sun, 11 Jun 2023 02:02:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474144; cv=none; d=google.com; s=arc-20160816; b=sJHcB3bq5779TRZHUlAPwbYxKDlJmdnlqtPO+EygwFbyKm1zMsQdRh+J32yAmwODys WEsxmIU3Kv285xQUd0ASJbumkSxiX//EXLmmAZulbuVAAmg1BeuzcelGpTThPKNSSBFC vEnLngcNbtfHMziX0BjcVwTkxysQeTVllNEZeYpHPmm5kgUysQkXbeHJEW9Yp5UvYu32 YzPv9CzgV/Rmf6X//M6GuoY5hHQ+VXCyzwvR+QKyQ/WhVtBrtPqJO+JKv+QyoZpB5AAf +EvEKh+wxRccIpHry8WjF/V5g6ORjuKBhqpgXEoS/YTEICxZjzVKW7mb3sXrvYqjAWo7 bO6g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Q/kuWTPxcHL3QCO5m7VZbZfFT5tI+SpH0RGLuwEKATs=; b=Mrho9f7cvaHvK7Pv9OImWDaerDhbPEqR89GX2txLP0ju+TL6294v1TH1f/SfozN/uR Ctcz9GsVhkcUbZjAseJp127yI30M2H/BKJUZJ0ZeUHvVG7MX8b3TXnvFwhdd+ilaHSP+ SZAbPKNtq0P8twV3P0oi/rJuPfMqrsGt2HH6DITH77K3DgyEN5rH/P92t63YKgsBWY3E +3kay6ioVgoJveuB7uLcx1LASS8U4IwOvAutqY58KEArvPvjc8nzlmvTqJ62xKnBiGg4 WbLofO+XKM4IuZSrrvuHkdbYybGsA6EsIQbvl1FLIdpJQjRdHY/vb57W5EaxYPQOs7pR ZGlg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=slPZWIsN; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id z10-20020a05600c114a00b003f7e60622f0sm7865177wmz.6.2023.06.11.02.00.22 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:23 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 22/26] target/arm/tcg: Reduce 'helper-m.h.inc' inclusion Date: Sun, 11 Jun 2023 10:58:42 +0200 Message-Id: <20230611085846.21415-23-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=philmd@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Instead of including helper-m.h.inc via helper.h which is included by all TCG files, restrict it to the few files that require it. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/helper.h | 2 -- target/arm/tcg/m_helper.c | 4 ++++ target/arm/tcg/translate-m-nocp.c | 6 ++++++ target/arm/tcg/translate-vfp.c | 4 ++++ target/arm/tcg/translate.c | 5 +++++ 5 files changed, 19 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index 05117934f3..37f9879b95 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -521,5 +521,3 @@ DEF_HELPER_FLAGS_5(gvec_uclamp_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(gvec_uclamp_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) - -#include "tcg/helper-m.h.inc" diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 0780bb3dea..45568d96bb 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -21,6 +21,10 @@ #include "hw/intc/armv7m_nvic.h" #endif +#define HELPER_H "tcg/helper-m.h.inc" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, uint32_t val) { diff --git a/target/arm/tcg/translate-m-nocp.c b/target/arm/tcg/translate-m-nocp.c index 7343945b41..ee9c296a98 100644 --- a/target/arm/tcg/translate-m-nocp.c +++ b/target/arm/tcg/translate-m-nocp.c @@ -25,6 +25,12 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-m.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#include "exec/helper-info.c.inc" +#undef HELPER_H + /* Include the generated decoder */ #include "decode-m-nocp.c.inc" diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 10d4502239..7d36a06726 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -24,6 +24,10 @@ #include "translate.h" #include "translate-a32.h" +#define HELPER_H "tcg/helper-m.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + #define HELPER_H "tcg/helper-vfp.h.inc" #include "exec/helper-proto.h.inc" #include "exec/helper-gen.h.inc" diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index d88b355230..0e692f45f8 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -37,6 +37,11 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H +#define HELPER_H "tcg/helper-m.h.inc" +#include "exec/helper-proto.h.inc" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" #undef HELPER_H From patchwork Sun Jun 11 08:58:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691361 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1572620wru; Sun, 11 Jun 2023 02:05:57 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5fkK0GwsDyb/R8E0ICW8fMlIJDvLWN6IQYX5VqaXjChlgS3UULjC3aPZO82/v7l8lbLPpg X-Received: by 2002:a05:622a:19a9:b0:3f5:2177:eca0 with SMTP id u41-20020a05622a19a900b003f52177eca0mr7283077qtc.5.1686474357035; Sun, 11 Jun 2023 02:05:57 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474357; cv=none; d=google.com; s=arc-20160816; b=ubiiAsPiyK7g6GOuFa+prLMyKJSrebAat/N07pV2DbGUDZFFM4hXd924wZek9PxDq9 4DMnC48VkWUVISBv1RLcF1g0ZiGXPG+/9zkstDVAElQzic1+0ucLYfmCPlk4uRMUC9mx Z3E7NJg93epT+LPtNxQzFIsV3X9nsdSsJCfT6nomiOv6OwNR4BDpwPzZHe/YUpLwc3CF ibB6AtCoWbBN2RP77aVXh2+EF8p/cBna0A/lIOHu+KGlOD3LDSPW7P7dHQ/ksfJW5oC8 JxnQ8N6KfF13Qw7CvNZUlIpxNIBpcqUHGyS5OvCTo2tVsDP/aSF4/IXq1bCGkhm1MDFh h1xQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=7bOi95+MAdYOQf36lFFFxG4Odq562AhoTTqq539rW9I=; b=mWe3x91KXRK12eOirgRQs4645Ba3TGlkyMLICb/vsLSwrr7/5pn5aaGHW0z3EoeFGH lvpSwzkmHlbA34jBk9ddH0BRnnf1IimkQwiWqIplAiPJHTZpDd5koKtZNkxr9onrm43f FVwLy3niMlwOKnUaKJ9PyW0vO9Q9QpKzGYBqfTnpcMI2S6ooMBOUSs+qL7UhHsPrAXTO QNxVmXPeQy2ZPVOpMpXe6jjhoPRcHPxksDud7QZjRdhRyL1qOkEwf9yPbgxqmpXbBS1q 9TR3cLREZnhctihUPJ1/OeDcjz8qkRGcnTb2N+OPmo9k1JDpWSvK0LdRVVV9iSjhUcbb d8sA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pVvQCGkK; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id h4-20020adffa84000000b0030647d1f34bsm9103172wrr.1.2023.06.11.02.00.26 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:27 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 23/26] target/arm/tcg: Inline 'exec/helper-gen.h' Date: Sun, 11 Jun 2023 10:58:43 +0200 Message-Id: <20230611085846.21415-24-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=philmd@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- CHECK: By extracting some inlined (FP) helpers from translate.h, we could reduce 'helper-gen.h.inc' to helper.c. --- target/arm/tcg/translate.h | 4 +++- target/arm/helper.c | 5 +++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 3d7c55d3b6..fc6357eae8 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -6,9 +6,11 @@ #include "tcg/tcg-op-gvec.h" #include "exec/exec-all.h" #include "exec/translator.h" -#include "exec/helper-gen.h" #include "internals.h" +#define HELPER_H "helper.h" +#include "exec/helper-gen.h.inc" +#undef HELPER_H /* internal defines */ diff --git a/target/arm/helper.c b/target/arm/helper.c index d4bee43bd0..89ee68893f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -26,6 +26,11 @@ #include "qapi/error.h" #include "qemu/guest-random.h" #ifdef CONFIG_TCG + +#define HELPER_H "helper.h" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + #include "semihosting/common-semi.h" #endif #include "cpregs.h" From patchwork Sun Jun 11 08:58:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691366 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1572884wru; Sun, 11 Jun 2023 02:07:06 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6zsLbu+ZOCTwm8xvJNVjlxpDDepGI+X1yUxU8ni66eRiFb3OpirGR/Apc0gJv3rZrDhbm1 X-Received: by 2002:a05:622a:487:b0:3f5:3927:79db with SMTP id p7-20020a05622a048700b003f5392779dbmr8090459qtx.41.1686474426332; Sun, 11 Jun 2023 02:07:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1686474426; cv=none; d=google.com; s=arc-20160816; b=BCRoV8tHQiMQA4Bfhw3Rd7b+kc9FDtbJul4k7b4ICIu0NBch000ra0VYySvZzvmhfn NR/5AzWPGlSWvE4HKtzWY0CCATg1N8+qP5BubGGd4M9US1hC9r1smkMFFCfzVkfUzoxF coN4mdLoduUUEvVFoWyyfCdvzknHQxRUIiSzjQRbE89NkzP4q/fUJfQ/asuboVEUlbZE zx/JLIioZ3IdNbiknkc6dissTi1qTsjHJZzfAZvXsrnGn50j8rJPJfqIG/6snqKqew/F XiAvv1dgDmsa1s7j0pjS7mXbFbvHT9xuqt9Hi1E/416sT41/SrEa61yY9eTGf7QfB9qW TVSA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pT+BWdaJs3HaPQ2spxdjE0GeSmYFHB0pF7s+pZ7C19g=; b=viZxYopx+lzjD5QTviOSRZaGSf3U3NfacZ5QLKoYRWvhZsThRqDlVgxBwYBrSy/jRT wpV+ppDk4jwiU+bA3swuTdTGTHsC2iutncpyuM+0RhmyUyUCLgeKelBLHzm/Gz2FaYZU bfCWdRp4V+M5QtNF7BsScLPLVUFbEW6R2pjzpAC4wc3jhp5fKuUSwGXVkR2FISLbMTqQ 45Om7thzZFdTJac0AQ7X/tj93wSkoHD8Wb3dh1+AQqJN7iVDXhx52mEPu7bWAHy3cvtF x2O4PsnB/MtBe0bfp/FXggiD74ivuK7qjLIhbSqRxJgYemCjqE9q0HphSTlm72Lopk4J cSQA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MN1DmNtW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id n5-20020a7bcbc5000000b003f7eafe9d76sm7864732wmi.37.2023.06.11.02.00.31 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:31 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 24/26] target/arm/tcg: Inline 'exec/helper-proto.h' Date: Sun, 11 Jun 2023 10:58:44 +0200 Message-Id: <20230611085846.21415-25-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=philmd@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé --- This mean we can extract more tcg/helper-foo.h.inc, maybe: - gvec / simd / crypto - exception / wfi --- target/arm/debug_helper.c | 6 +++++- target/arm/helper.c | 2 +- target/arm/tcg/crypto_helper.c | 5 ++++- target/arm/tcg/helper-a64.c | 5 ++++- target/arm/tcg/hflags.c | 5 ++++- target/arm/tcg/m_helper.c | 5 ++++- target/arm/tcg/op_helper.c | 5 ++++- target/arm/tcg/psci.c | 5 ++++- target/arm/tcg/tlb_helper.c | 4 +++- target/arm/tcg/translate.c | 2 +- target/arm/tcg/vec_helper.c | 5 ++++- target/arm/vfp_helper.c | 5 ++++- 12 files changed, 42 insertions(+), 12 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 8362462a07..31165b92a5 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -11,10 +11,14 @@ #include "internals.h" #include "cpregs.h" #include "exec/exec-all.h" -#include "exec/helper-proto.h" #include "sysemu/tcg.h" #ifdef CONFIG_TCG + +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + /* Return the Exception Level targeted by debug exceptions. */ static int arm_debug_target_el(CPUARMState *env) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 89ee68893f..523f7b7765 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11,7 +11,6 @@ #include "trace.h" #include "cpu.h" #include "internals.h" -#include "exec/helper-proto.h" #include "qemu/main-loop.h" #include "qemu/timer.h" #include "qemu/bitops.h" @@ -28,6 +27,7 @@ #ifdef CONFIG_TCG #define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" #include "exec/helper-gen.h.inc" #undef HELPER_H diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index d28690321f..1b6b105527 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -12,12 +12,15 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "crypto/aes.h" #include "crypto/sm4.h" #include "vec_internal.h" +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + union CRYPTO_STATE { uint8_t bytes[16]; uint32_t words[4]; diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 86133c6e0d..56c2f01532 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -21,7 +21,6 @@ #include "qemu/units.h" #include "cpu.h" #include "gdbstub/helpers.h" -#include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "qemu/log.h" #include "qemu/main-loop.h" @@ -35,6 +34,10 @@ #include "fpu/softfloat.h" #include /* For crc32 */ +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + #define HELPER_H "tcg/helper-a64.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 616c5fa723..83a1aa08e4 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -8,9 +8,12 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" -#include "exec/helper-proto.h" #include "cpregs.h" +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + static inline bool fgt_svc(CPUARMState *env, int el) { /* diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 45568d96bb..1991eafe05 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -10,7 +10,6 @@ #include "cpu.h" #include "internals.h" #include "gdbstub/helpers.h" -#include "exec/helper-proto.h" #include "qemu/main-loop.h" #include "qemu/bitops.h" #include "qemu/log.h" @@ -25,6 +24,10 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + static void v7m_msr_xpsr(CPUARMState *env, uint32_t mask, uint32_t reg, uint32_t val) { diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 04a90e3e3a..24205074cc 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -19,12 +19,15 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "internals.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" #include "cpregs.h" +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index 6c1239bb96..2822a6b96a 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -18,13 +18,16 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "kvm-consts.h" #include "qemu/main-loop.h" #include "sysemu/runstate.h" #include "internals.h" #include "arm-powerctl.h" +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + bool arm_is_psci_call(ARMCPU *cpu, int excp_type) { /* diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 8df36c2cbf..e663aef2fd 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -9,8 +9,10 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" -#include "exec/helper-proto.h" +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H /* * Returns true if the stage 1 translation regime is using LPAE format page diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 0e692f45f8..fc7a2804f7 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -27,7 +27,6 @@ #include "arm_ldst.h" #include "semihosting/semihost.h" #include "cpregs.h" -#include "exec/helper-proto.h" #define HELPER_H "tcg/helper-neon.h.inc" #include "exec/helper-gen.h.inc" @@ -43,6 +42,7 @@ #undef HELPER_H #define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" #include "exec/helper-info.c.inc" #undef HELPER_H diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 9dd7e0f5e1..325a231de9 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -19,12 +19,15 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "tcg/tcg-gvec-desc.h" #include "fpu/softfloat.h" #include "qemu/int128.h" #include "vec_internal.h" +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + #define HELPER_H "tcg/helper-vfp.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index cbd78cc810..51f8e92ff7 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "exec/helper-proto.h" #include "internals.h" #ifdef CONFIG_TCG #include "qemu/log.h" @@ -32,6 +31,10 @@ #ifdef CONFIG_TCG +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + #define HELPER_H "tcg/helper-vfp.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H From patchwork Sun Jun 11 08:58:45 2023 Content-Type: text/plain; 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id e7-20020a056000120700b0030af8da022dsm9093350wrx.44.2023.06.11.02.00.35 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:35 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= Subject: [PATCH v2 25/26] target/arm/tcg: Rename 'helper.h' -> 'tcg/helper.h.inc' Date: Sun, 11 Jun 2023 10:58:45 +0200 Message-Id: <20230611085846.21415-26-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=philmd@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented as the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename 'helper.h' as 'helper.h.inc'. Since this file is TCG-specific, move it to the tcg/ directory. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- target/arm/tcg/translate.h | 2 +- target/arm/{helper.h => tcg/helper.h.inc} | 0 target/arm/debug_helper.c | 2 +- target/arm/helper.c | 2 +- target/arm/tcg/crypto_helper.c | 2 +- target/arm/tcg/helper-a64.c | 2 +- target/arm/tcg/hflags.c | 2 +- target/arm/tcg/m_helper.c | 2 +- target/arm/tcg/op_helper.c | 2 +- target/arm/tcg/psci.c | 2 +- target/arm/tcg/tlb_helper.c | 2 +- target/arm/tcg/translate.c | 2 +- target/arm/tcg/vec_helper.c | 2 +- target/arm/vfp_helper.c | 2 +- 14 files changed, 13 insertions(+), 13 deletions(-) rename target/arm/{helper.h => tcg/helper.h.inc} (100%) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index fc6357eae8..940347b6bd 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -8,7 +8,7 @@ #include "exec/translator.h" #include "internals.h" -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-gen.h.inc" #undef HELPER_H diff --git a/target/arm/helper.h b/target/arm/tcg/helper.h.inc similarity index 100% rename from target/arm/helper.h rename to target/arm/tcg/helper.h.inc diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 31165b92a5..b32852e947 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -15,7 +15,7 @@ #ifdef CONFIG_TCG -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H diff --git a/target/arm/helper.c b/target/arm/helper.c index 523f7b7765..2bdf7b0d4e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -26,7 +26,7 @@ #include "qemu/guest-random.h" #ifdef CONFIG_TCG -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #include "exec/helper-gen.h.inc" #undef HELPER_H diff --git a/target/arm/tcg/crypto_helper.c b/target/arm/tcg/crypto_helper.c index 1b6b105527..15faa7455e 100644 --- a/target/arm/tcg/crypto_helper.c +++ b/target/arm/tcg/crypto_helper.c @@ -17,7 +17,7 @@ #include "crypto/sm4.h" #include "vec_internal.h" -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 56c2f01532..b8ee45074f 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -34,7 +34,7 @@ #include "fpu/softfloat.h" #include /* For crc32 */ -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 83a1aa08e4..e75cb0100e 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -10,7 +10,7 @@ #include "internals.h" #include "cpregs.h" -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 1991eafe05..4100161775 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -24,7 +24,7 @@ #include "exec/helper-proto.h.inc" #undef HELPER_H -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 24205074cc..e1aadd63f0 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -24,7 +24,7 @@ #include "exec/cpu_ldst.h" #include "cpregs.h" -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H diff --git a/target/arm/tcg/psci.c b/target/arm/tcg/psci.c index 2822a6b96a..e00b9b1493 100644 --- a/target/arm/tcg/psci.c +++ b/target/arm/tcg/psci.c @@ -24,7 +24,7 @@ #include "internals.h" #include "arm-powerctl.h" -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index e663aef2fd..3f8cb358a6 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -10,7 +10,7 @@ #include "internals.h" #include "exec/exec-all.h" -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index fc7a2804f7..f44b9415ec 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -41,7 +41,7 @@ #include "exec/helper-gen.h.inc" #undef HELPER_H -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #include "exec/helper-info.c.inc" #undef HELPER_H diff --git a/target/arm/tcg/vec_helper.c b/target/arm/tcg/vec_helper.c index 325a231de9..46f347a8c3 100644 --- a/target/arm/tcg/vec_helper.c +++ b/target/arm/tcg/vec_helper.c @@ -24,7 +24,7 @@ #include "qemu/int128.h" #include "vec_internal.h" -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H diff --git a/target/arm/vfp_helper.c b/target/arm/vfp_helper.c index 51f8e92ff7..38faf99073 100644 --- a/target/arm/vfp_helper.c +++ b/target/arm/vfp_helper.c @@ -31,7 +31,7 @@ #ifdef CONFIG_TCG -#define HELPER_H "helper.h" +#define HELPER_H "tcg/helper.h.inc" #include "exec/helper-proto.h.inc" #undef HELPER_H From patchwork Sun Jun 11 08:58:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 691360 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1572610wru; Sun, 11 Jun 2023 02:05:56 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5GK/AG7yRE6HkCxerIodyz+CffAZHazFG6m4c2HCX5/GC7+kcjvVqYem6Mx1F7UKeuX5SJ X-Received: by 2002:a05:6214:f6a:b0:62b:6b5b:f763 with SMTP id iy10-20020a0562140f6a00b0062b6b5bf763mr7117327qvb.11.1686474356287; Sun, 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[91.163.26.170]) by smtp.gmail.com with ESMTPSA id v18-20020a5d43d2000000b0030ae93bd196sm9052286wrr.21.2023.06.11.02.00.39 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Sun, 11 Jun 2023 02:00:40 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Peter Maydell , qemu-arm@nongnu.org, =?utf-8?q?Ph?= =?utf-8?q?ilippe_Mathieu-Daud=C3=A9?= , =?utf-8?q?Alex_B?= =?utf-8?q?enn=C3=A9e?= Subject: [PATCH v2 26/26] tests/tcg/aarch64: Rename bti-crt.inc.c -> bti-crt.c.inc Date: Sun, 11 Jun 2023 10:58:46 +0200 Message-Id: <20230611085846.21415-27-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230611085846.21415-1-philmd@linaro.org> References: <20230611085846.21415-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=philmd@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since commit 139c1837db ("meson: rename included C source files to .c.inc"), QEMU standard procedure for included C files is to use *.c.inc. Besides, since commit 6a0057aa22 ("docs/devel: make a statement about includes") this is documented as the Coding Style: If you do use template header files they should be named with the ``.c.inc`` or ``.h.inc`` suffix to make it clear they are being included for expansion. Therefore rename 'bti-crt.inc.c' as 'bti-crt.c.inc'. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson Reviewed-by: Alex Bennée --- tests/tcg/aarch64/bti-1.c | 2 +- tests/tcg/aarch64/bti-3.c | 2 +- tests/tcg/aarch64/{bti-crt.inc.c => bti-crt.c.inc} | 0 3 files changed, 2 insertions(+), 2 deletions(-) rename tests/tcg/aarch64/{bti-crt.inc.c => bti-crt.c.inc} (100%) diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c index 61924f0d7a..99a879af23 100644 --- a/tests/tcg/aarch64/bti-1.c +++ b/tests/tcg/aarch64/bti-1.c @@ -2,7 +2,7 @@ * Branch target identification, basic notskip cases. */ -#include "bti-crt.inc.c" +#include "bti-crt.c.inc" static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) { diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c index a852856d9a..8c534c09d7 100644 --- a/tests/tcg/aarch64/bti-3.c +++ b/tests/tcg/aarch64/bti-3.c @@ -2,7 +2,7 @@ * BTI vs PACIASP */ -#include "bti-crt.inc.c" +#include "bti-crt.c.inc" static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) { diff --git a/tests/tcg/aarch64/bti-crt.inc.c b/tests/tcg/aarch64/bti-crt.c.inc similarity index 100% rename from tests/tcg/aarch64/bti-crt.inc.c rename to tests/tcg/aarch64/bti-crt.c.inc