From patchwork Mon Jun 5 20:14:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689223 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2285152wru; Mon, 5 Jun 2023 13:16:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6+ovniIDWJkBPGj4kmjwe7Mi99i9DAZ8GzI3jD8A2RYHgXlElQbht98Q5x0e5Tha2P9LKC X-Received: by 2002:ac8:5a12:0:b0:3f2:ba:62b3 with SMTP id n18-20020ac85a12000000b003f200ba62b3mr10835391qta.32.1685996199092; Mon, 05 Jun 2023 13:16:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996199; cv=none; d=google.com; s=arc-20160816; b=S7KaUQo2MTXlhD7vxrkUwiM9XWbOYAbHGr54mBf1Zd/pCpnt4fZFraIrM03uwWfQKw l1A4Exebq+TFOudPTuwfkIgZDuPYS6A+x+v+yPe7QaSKqkTcU6Tm1GK5WSidAesh9KzT LFioYwQs4oVhvBycThKxGGEKYo98BPld4Q8PZMJanAo1SksSRSGKwnwDbemzejww7C4Q qk+gwSfLZR+Hipa4NPdiyHSMFlJt47L9DmkDpaincAIavZv7hBKfplUWxoGV7kfoeLTy St/J6NV2KNZFKNwKK9ie0FT2HWFdWEjcfhYwUHeVILvS2ZopmsfwgeBspcTeBL3PyK3i SvGg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nn9Tf0IYWBrZfMOrfRS/Ef1buY3fjYVKvOc76GeHvCA=; b=uEZZcKG34v3Xy3ZO5ClX9TfmQy+jf/juMQqJj8n86ckwGSV8yejtctYwVCOKBdj6pZ YaxFlzlpJ4bsX1VHh+ROcoKZ45Wy7bkJF4CnLOr+vRsmccBLpv/I96A1N6nnMjx5fj+g Ed/6/N6pDgYEm3SK2gfVFY0lx5eMzECEtvVMgJtmtQR+m9/LZ/tV520T8gm19I3m5hT0 +UeTdH6K0BvCfOkciCTiyadGFsxCTqOgVVD1gX/97mln0eOGskAj7ohpfd55R6wOARNt yePU6WaZbHK0rJlyC9n4IrY3tewSullIvI+DGBTuQ5CZObIMfArZZ+2iUzloM10VPj9S sXhA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KCrV7zhJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q18-20020a05622a04d200b003f6b8d11c28si5005201qtx.477.2023.06.05.13.16.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:16:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=KCrV7zhJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GcP-0001ku-Ts; Mon, 05 Jun 2023 16:15:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcN-0001jk-6Z for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:15:55 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcL-0003hV-Di for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:15:54 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-655fce0f354so1323077b3a.0 for ; Mon, 05 Jun 2023 13:15:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996152; x=1688588152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nn9Tf0IYWBrZfMOrfRS/Ef1buY3fjYVKvOc76GeHvCA=; b=KCrV7zhJ+UOYsowtRaEFl85GmaY1xbIKl/A+DaW372OWXJHu9syEE5cws43Uv/EFf/ pScFA+p4+Ns51B0GR98VMgXTDPTN0uPMdEhCncwBgWxJSDp/B+4dWueyPov7NRzLnfRo xi9694V4X1vArQl5/qXOpPXJlnB6SuQzBlHOniAsilNyhC+4xp8EW++1OB8xetLEAjTz Utu8y8QSKnWHG0HUnMwy413UlI/tGiBgfyGeaqYgu1N30IUnZeeI0ud2mBRuO+7f4uOG uqQIGDkyC3dMERDYoEIp3wCOXyZqZMF8SduAvdZUq2B9Z8z/QG5Agj3zVT007knHXmUo 6OgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996152; x=1688588152; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nn9Tf0IYWBrZfMOrfRS/Ef1buY3fjYVKvOc76GeHvCA=; b=dNAQh6OtUFltJS1Npk2q8m0y5mrPoEJyJ2pp00vGJ0dmoBV+kwb2QxDLyoSBy8IFuv ZgGjXO75UElpT+lO2hUqvN3WpHhV5kyzT5moeqQToqdKykMuvIEWwQYQonUM0as9YDXC faY80t6YnAet0m/8PvkukfdnhEQ+/fRUjBXLJDLfy9jYXbZrlym3hpRkhjwy7aw1A0Zx CUMgqAkE9mkVo3YPQlegsOtXgfRXFtZaaCw+zceQVr4itkaKedz9sIijNtElVu2q0/mD +AXJzotsSWJpEHa+ZC/yPgSwGkdosTWNzfQakt/YTrXC3LmrxB5vITiupF2NgGsW6W8D qQxQ== X-Gm-Message-State: AC+VfDzQSdII1TWGRc+BRyodyC/2u/J/i2zogKQ+psr0OfIcZpZRAfc2 KK/5msT7G8mN0bVoJsMcrSIpS9GSSAUN2CMX0Aw= X-Received: by 2002:a05:6a00:850:b0:653:b76d:4d62 with SMTP id q16-20020a056a00085000b00653b76d4d62mr1029119pfk.24.1685996151923; Mon, 05 Jun 2023 13:15:51 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.15.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:15:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PULL 01/52] tcg/ppc: Remove TARGET_LONG_BITS, TCG_TYPE_TL Date: Mon, 5 Jun 2023 13:14:57 -0700 Message-Id: <20230605201548.1596865-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All uses replaced with TCGContext.addr_type. Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index d47a9e3478..11955a6cc2 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2046,6 +2046,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, bool is_ld) { + TCGType addr_type = s->addr_type; TCGLabelQemuLdst *ldst = NULL; MemOp opc = get_memop(oi); MemOp a_bits, s_bits; @@ -2098,17 +2099,18 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); /* Load the (low part) TLB comparator into TMP2. */ - if (cmp_off == 0 && TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { - uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || TARGET_LONG_BITS == 32 + if (cmp_off == 0 + && (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32)) { + uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32 ? LWZUX : LDUX); tcg_out32(s, lxu | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); } else { tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) { tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off + 4 * HOST_BIG_ENDIAN); } else { - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off); + tcg_out_ld(s, addr_type, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off); } } @@ -2116,7 +2118,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, * Load the TLB addend for use on the fast path. * Do this asap to minimize any load use delay. */ - if (TCG_TARGET_REG_BITS >= TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) { tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_REG_TMP1, offsetof(CPUTLBEntry, addend)); } @@ -2151,7 +2153,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, } /* Mask the address for the requested alignment. */ - if (TARGET_LONG_BITS == 32) { + if (addr_type == TCG_TYPE_I32) { tcg_out_rlw(s, RLWINM, TCG_REG_R0, t, 0, (32 - a_bits) & 31, 31 - s->page_bits); } else if (a_bits == 0) { @@ -2163,7 +2165,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, } } - if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) { /* Low part comparison into cr7. */ tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, TCG_TYPE_I32); @@ -2183,8 +2185,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ)); } else { /* Full comparison into cr7. */ - tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, - 0, 7, TCG_TYPE_TL); + tcg_out_cmp(s, TCG_COND_EQ, TCG_REG_R0, TCG_REG_TMP2, 0, 7, addr_type); } /* Load a pointer into the current opcode w/conditional branch-link. */ @@ -2211,7 +2212,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, h->base = guest_base ? TCG_GUEST_BASE_REG : 0; #endif - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS == 64 && addr_type == TCG_TYPE_I32) { /* Zero-extend the guest address for use in the host address. */ tcg_out_ext32u(s, TCG_REG_R0, addrlo); h->index = TCG_REG_R0; From patchwork Mon Jun 5 20:14:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689247 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2287902wru; Mon, 5 Jun 2023 13:25:03 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6FF74Bl5h9Eo2CpLaDMD9aE8VFWHpdBsugjftAWpTEjd8EB7tUN2OgGjzcDgMPw2G6lEFQ X-Received: by 2002:ac8:7f8c:0:b0:3f6:910a:aace with SMTP id z12-20020ac87f8c000000b003f6910aaacemr10808538qtj.23.1685996702986; Mon, 05 Jun 2023 13:25:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996702; cv=none; d=google.com; s=arc-20160816; b=SABSXxV49VAhdjPcqTnzPeMY7AGWv0KOc8HhTmeRvgtOcHdZMS3LfN1f3IoILMP0xn 8gVzlkpOLjL0JNQOX2SdfnlPh/QY4oOMBxyAwZIFZjm73c0E7Zh6KbhJa06dHY32ClMn r8Ga50Ptza9nZWAbMuofsRGFlQBbbIJV2PwkzLwwC3t31M8CIXuu8NjLIDinlkSHiIAc a6KYV514g8hxiTyEDM+bIWVCfO1juzO+qIGPBXy9seTRfWSRzfU5NzTdjjKMdYnTyhC+ AYIO4dvNFIg67vbVMbYCwt4M5pgEcLZQpomV+sahJASHZQQbVvWLd+o55EclDbHMmF6q MnxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Zq0inShA79yUCPfBvlF6JU5DFl9lHhMswh4eTv6SbBc=; b=PfjuIqdA7i/s1luf9UIH3LBmp7oMiSp0FtJXimMEjhSKZj/I9p5eyiKr3d3m63L6Fk WTyjUpsOqpiZwdQKZtKTPoTaClgFnytAdCHcM2W6tZkC99LuuFh9t/CQNYwnoMsVcdGi O/kp3sM2P4E8F2OTgLlZPtbB3gmX8DmJyRyQxTszpe2eDbeeZR/sOlROSo8t12k0TKl5 jDb5EdJFSFA4U/+ZYl2JdrYHnBvMpiWXwD0OSgBexjjY7GcUWGHqCnuG9crJ3olCqE3v dHJQ+bK/mTvQtK21RR4jNiIHk6eomZQc1zpK1Xh8iHvTdAYqevsPBmlO79nVr9s26g93 zlAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MWeAP5Cx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id b14-20020ac87fce000000b003f4f44d9676si5267495qtk.615.2023.06.05.13.25.02 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:25:02 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MWeAP5Cx; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GcY-0001pu-Jm; Mon, 05 Jun 2023 16:16:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcU-0001oD-ND for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:02 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcM-0003i3-3X for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:02 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-65242634690so2955183b3a.0 for ; Mon, 05 Jun 2023 13:15:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996153; x=1688588153; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Zq0inShA79yUCPfBvlF6JU5DFl9lHhMswh4eTv6SbBc=; b=MWeAP5Cxoduu0+5FavthYhr0zcLw7TZ3N6oqn/JWCfC77aGzGR3Ekgcmpk6HLt4MHa yDNb1NWTJAxQU4c6ty7Ly2M/m0CsZDY2Skn32GFT2AElXLiMeaSnoT5Tya5jHVZiHiib TkYZ0cyLnOkSda8U6DErDCmnlzoMXQkqhM0g20UWZ/WI4OIt6NX1zZpG4ESGHA5vFVqL O6m5hSoV/RI8o/ElzymRawQ2KLrDc+9dbq1R7aBpE+KU1D23slDDkukHZDse/f7HXVFQ 1yGtZ0XeOIrbW0HLrfWPdQpxFK+kGV6CHR0qjNi6tcKC80TPa20E+w1DpMQoHUA+wu37 5vUg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996153; x=1688588153; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Zq0inShA79yUCPfBvlF6JU5DFl9lHhMswh4eTv6SbBc=; b=UvlXg2S5IUdlzDG2NOUHUqWOlEPQf2D/7eP3Wju1bUyeLTVHYqpjqWH7kzWjnv+a3p 4t2pC8UNICnlNgdPIEI2Kaj6h7ndYCBEPPYe4Wi25SxysijhJPAA7qtCoSekGN5GfRLE bGGJAtJSPQTWk9XwXwhRNkvdjebpW09bMIV2jL45A8wNJHduKqNuxvHZhAdxu0VlA+pl NNIZRM664/UThCrPESAlmzblk+1hxceMqxSCdv+hwTOBt4aIPDXRIC442as5OS+RrcGb w6cpm30AE174MgVh7tYWjN+KiVFZfA9v76y+Sb0/RoVmOMH+vsZNLIankMCd7nykC6nG 5kxQ== X-Gm-Message-State: AC+VfDwV216IO2r4rkxaoLQJaYtqXy/PVI9FyRUrEuTGc/ewgyZ+QLCE +Zh9Cz4kRoaMBigmckRo3SC60q0wpX3V3UVwnzI= X-Received: by 2002:a05:6a20:8f09:b0:101:1951:d491 with SMTP id b9-20020a056a208f0900b001011951d491mr166183pzk.6.1685996152742; Mon, 05 Jun 2023 13:15:52 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.15.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:15:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 02/52] tcg/riscv: Remove TARGET_LONG_BITS, TCG_TYPE_TL Date: Mon, 5 Jun 2023 13:14:58 -0700 Message-Id: <20230605201548.1596865-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_HELO_TEMPERROR=0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All uses replaced with TCGContext.addr_type. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index c0257124fa..a8f99f7e77 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1195,6 +1195,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, TCGReg addr_reg, MemOpIdx oi, bool is_ld) { + TCGType addr_type = s->addr_type; TCGLabelQemuLdst *ldst = NULL; MemOp opc = get_memop(oi); TCGAtomAlign aa; @@ -1236,19 +1237,19 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, addr_adj = addr_reg; if (a_mask < s_mask) { addr_adj = TCG_REG_TMP0; - tcg_out_opc_imm(s, TARGET_LONG_BITS == 32 ? OPC_ADDIW : OPC_ADDI, + tcg_out_opc_imm(s, addr_type == TCG_TYPE_I32 ? OPC_ADDIW : OPC_ADDI, addr_adj, addr_reg, s_mask - a_mask); } compare_mask = s->page_mask | a_mask; if (compare_mask == sextreg(compare_mask, 0, 12)) { tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addr_adj, compare_mask); } else { - tcg_out_movi(s, TCG_TYPE_TL, TCG_REG_TMP1, compare_mask); + tcg_out_movi(s, addr_type, TCG_REG_TMP1, compare_mask); tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addr_adj); } /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_TMP0, TCG_REG_TMP2, + tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_REG_TMP2, @@ -1259,7 +1260,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); /* TLB Hit - translate address using addend. */ - if (TARGET_LONG_BITS == 64) { + if (addr_type != TCG_TYPE_I32) { tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2); } else if (have_zba) { tcg_out_opc_reg(s, OPC_ADD_UW, TCG_REG_TMP0, addr_reg, TCG_REG_TMP2); @@ -1287,7 +1288,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, if (guest_base != 0) { base = TCG_REG_TMP0; - if (TARGET_LONG_BITS == 64) { + if (addr_type != TCG_TYPE_I32) { tcg_out_opc_reg(s, OPC_ADD, base, addr_reg, TCG_GUEST_BASE_REG); } else if (have_zba) { tcg_out_opc_reg(s, OPC_ADD_UW, base, addr_reg, TCG_GUEST_BASE_REG); @@ -1295,7 +1296,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, tcg_out_ext32u(s, base, addr_reg); tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_GUEST_BASE_REG); } - } else if (TARGET_LONG_BITS == 64) { + } else if (addr_type != TCG_TYPE_I32) { base = addr_reg; } else { base = TCG_REG_TMP0; From patchwork Mon Jun 5 20:14:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689242 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2287391wru; Mon, 5 Jun 2023 13:23:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4iV+czUYeY9OJl+37RzZ7+SmazfNajyaUIp5OsiRGZPOC2SEb9TL3b1fa3lUn7FfF2dh/Y X-Received: by 2002:ac8:5a56:0:b0:3f5:279f:c4dd with SMTP id o22-20020ac85a56000000b003f5279fc4ddmr9773536qta.64.1685996604300; Mon, 05 Jun 2023 13:23:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996604; cv=none; d=google.com; s=arc-20160816; b=cMWT1+haHbDoPP3QhRG3jvQtU13533V0YP3K3A++QPqb6c13KUVlSruFsctr+B8zdr fOlBSKNMsPAcgtI3309zRXd8Mq+TsTTQJKGi9HmiYku0vsKJBLj1RxlR53Dy+iEYnXEG /9WI2cK4+tiZn+DPxSipPMTBhq3kUiPVmO5kmW+ODVdj3W8h0QuOZqo6XKgSsEXIBxms VbJ+LQjNP6KYJPQQN2OTzvYKcg0bXzuUuAzIJ+QVy+kTC0SNSFZzoD7YlwfxkTHw04j3 3KAtz0n2nVT+FpqT0eHAJYiLmXXyu2yS8CRmgPUUTEyzYo4avhv6VxDkHt8OP45pHeE9 Ywxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=kcmNUB/rD8+RMTN7CuMT/6LH8d8g+czDKBZHxrJ+ObQ=; b=LwZmBhvzYLzR8OEWKvMXCp68xlG896wcyKrhl+YJDhyVyk/U1SZCvn7UTKEFFaqWJG YHuI0Xlhq8LSrEe7odBvPfBuOloqlKB4rQiK975fTfoa4dxvloLn4FvaEKfiSVcfNCtR mjs+dlwRKnzRYU6cmB0CNmIWdc5jLasrK+pYZvo8xkEOVdRMLTbgzw/KQtnLxqd9wcEL My9HYo5/6MgwUvHMIXIi3Du0Plasu8OFEH46HtTJLgjql9xF2Xgo4s/GSx3R/6knyuXP +bqnapRxo0uAmQ5hY1PLTJ2vrc1AXaLGdRWOoH/un6yRL6sPLiWym04b9X8yVZvCOaIF dXDw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m+Wq5v2S; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id k6-20020ac85fc6000000b003f365244139si5310577qta.70.2023.06.05.13.23.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:23:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m+Wq5v2S; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GcP-0001kr-MT; Mon, 05 Jun 2023 16:15:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcO-0001k7-O4 for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:15:56 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcM-0003jW-Us for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:15:56 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-655fce0f354so1323097b3a.0 for ; Mon, 05 Jun 2023 13:15:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996153; x=1688588153; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=kcmNUB/rD8+RMTN7CuMT/6LH8d8g+czDKBZHxrJ+ObQ=; b=m+Wq5v2SkSBrJOLUngK/AWCHuYUBdfeQdJu2ZWYKY7nxNrIAtdsek5XQtHwIa0ZrDW 0Icmm7gv7DfrpnFES7pu6taHWDWCzWUdR0JfT0+A3uPa5e8n52uS69Ys0agP8XSKx45N dCkdzlRWwQjkjNLNkJcVRrjeuChgxE8fYT9aN1enyS5NMpzu70ozDqGbwYn93SLJ1sfv rSrZKxFtiAWZQQcm2TkK+N/prBqvgEf1h2Mz5vFTBgm2gc3aA+rAX7Pij0eCTpINCtqi Xw6XOI17vhdGAkogv8Bnpj++7xNf58yEkZZdggV+EN2o5HScxRj8Vl9n1SBlvUg9abi1 z5Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996153; x=1688588153; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=kcmNUB/rD8+RMTN7CuMT/6LH8d8g+czDKBZHxrJ+ObQ=; b=YD/2XkPUcrYVRFKXdkKf8v22bfFVC3Pua22cRsJzHQRZ/zKpEakqVjXC6/MeMZ+JqK InF1pW21wwQHmTYFRw1oisdB7tWSO24htZmengt8qaPRR4NJoKjMkaSGTlIFsoUeY5bt 8WL8VntAnIIya9Ka+bTR4uOdP8lF3194SE5j10sqPDJOI45gSdWiyLmtbjh70aW6lIEk 8WTldRIzn9uss9D8KVuH2WlEOd3ODulGA22wTR1NoNfMDvA9v+DSqYga+uTJCdX16is7 e1J8fIY6ZlZrmkzz6JY+9i2RuMNT8uRcz3io0Jc2/vhBHMwV8wVwQ45Qf335qC6wR7+k omBQ== X-Gm-Message-State: AC+VfDyS02h3t9Q8fSwvN5HZ6DtHsE/qTSsx9FrJh+XA/satCcTv9Gju wsiGgsQvsTPI76C1i77QE5OUKNkC8bVMABw7rCM= X-Received: by 2002:a05:6a00:22cd:b0:656:6d18:3d83 with SMTP id f13-20020a056a0022cd00b006566d183d83mr952836pfj.7.1685996153521; Mon, 05 Jun 2023 13:15:53 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.15.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:15:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 03/52] tcg/s390x: Remove TARGET_LONG_BITS, TCG_TYPE_TL Date: Mon, 5 Jun 2023 13:14:59 -0700 Message-Id: <20230605201548.1596865-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All uses replaced with TCGContext.addr_type. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 503126cd66..2795242b60 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1745,6 +1745,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, TCGReg addr_reg, MemOpIdx oi, bool is_ld) { + TCGType addr_type = s->addr_type; TCGLabelQemuLdst *ldst = NULL; MemOp opc = get_memop(oi); MemOp s_bits = opc & MO_SIZE; @@ -1786,7 +1787,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, tgen_andi_risbg(s, TCG_REG_R0, addr_reg, tlb_mask); } else { tcg_out_insn(s, RX, LA, TCG_REG_R0, addr_reg, TCG_REG_NONE, a_off); - tgen_andi(s, TCG_TYPE_TL, TCG_REG_R0, tlb_mask); + tgen_andi(s, addr_type, TCG_REG_R0, tlb_mask); } if (is_ld) { @@ -1794,7 +1795,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, } else { ofs = offsetof(CPUTLBEntry, addr_write); } - if (TARGET_LONG_BITS == 32) { + if (addr_type == TCG_TYPE_I32) { tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } else { tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); @@ -1807,7 +1808,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, tcg_out_insn(s, RXY, LG, h->index, TCG_TMP0, TCG_REG_NONE, offsetof(CPUTLBEntry, addend)); - if (TARGET_LONG_BITS == 32) { + if (addr_type == TCG_TYPE_I32) { tcg_out_insn(s, RRE, ALGFR, h->index, addr_reg); h->base = TCG_REG_NONE; } else { @@ -1830,7 +1831,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, } h->base = addr_reg; - if (TARGET_LONG_BITS == 32) { + if (addr_type == TCG_TYPE_I32) { tcg_out_ext32u(s, TCG_TMP0, addr_reg); h->base = TCG_TMP0; } From patchwork Mon Jun 5 20:15:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689275 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2289208wru; Mon, 5 Jun 2023 13:28:52 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5hNdmZE2yN+ALc8URoaWKqh9YcgsF5V5oMIHxOVSEpw4YUglygJxuhN/TrvhapGKLW1I9K X-Received: by 2002:a05:6214:c68:b0:626:2047:c845 with SMTP id t8-20020a0562140c6800b006262047c845mr8630332qvj.55.1685996932449; Mon, 05 Jun 2023 13:28:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996932; cv=none; d=google.com; s=arc-20160816; b=Dfadq4EJHQ7BRpfc+ae6FB/AZYtpxmJ3m0ECbt9uaJCZZ6T8csTJr8C1fbMn0f7Dvz niCdt9+WY9qkjPQiNV+QYUQ/5WEI1PXfogQ6i+g5Qc3/jWjJ/5YHWjhBwKLQQ5Hw+XeY CEOnc6DozlwaWt5whHfrqrR8K4xt334oC+8wR0QH4Aolj9662gPWjKdZqqZ8NrWFs5JE +aPT+NtGtd95epWFaupBKTK40O2om1S+wH9vBipahkThvzXLM10v7HxuJocJrU1Ilxzh AirNu1PR0wKdIZepTxNfKUHqgzu1lf7llu1rDWsCka2xTFp2CsfvcuSWt7drgvXpJTp0 XOjQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=HIYhvEBe+5na9q7sHii4+3BzV/97aBHrhxLYvL4RaKA=; b=fNI3FdMjUgnsJvRETfTHGBp8KMTRB8KzLCtcGDJHQN9YCgKVxwMVQ2jV7LBIwn+ezy FYdOrItsv5lFCp44tFbAvVwJD+S1AxchqvxiDn9KOlqjIk2PG7k/ArRmlFLUlk40snX3 oC7joVnTSo/ST6SYzpizbIlqya/KYKh8o/nh7h32kZhcxY2XaOSdEiTcJcyxxPZDEOud ifw5gMWLEGX2c4IWgnBSzuoIqf0jgf0PpmiRX2ssKnozPodzwsuBqEfO9uOPs7yS6ITc Uoly/t7fh11wt1K8WJwG77gENmw4BIOAvQMFLgLFbPEyDQIbTDNBC5cZiZTxDCA5bCKU NsgA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x1m7aCsS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id if7-20020a0562141c4700b006258f40e7fbsi5324529qvb.454.2023.06.05.13.28.52 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:28:52 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=x1m7aCsS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GcR-0001lO-CO; Mon, 05 Jun 2023 16:15:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcP-0001kj-8i for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:15:57 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcN-0003ju-Nb for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:15:57 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6537d2a8c20so2336828b3a.2 for ; Mon, 05 Jun 2023 13:15:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996154; x=1688588154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HIYhvEBe+5na9q7sHii4+3BzV/97aBHrhxLYvL4RaKA=; b=x1m7aCsS/nkatNWFv0ZemDFOeRejzgwuKIgZCpTSmAvJ62iHyt5wyQ0I6Kt10AlinX 9IAhctQCgDVboP183ZT5mRDi8roef29FD4BAPMeFOBiELFoaiiOCNjpkJkg05EwP4bRK x9+kDVH0fteulBwDVOPEo3rvzQyf+eMkgmrtmypNHPngVkhM7myay2ghQZZOJPlBlV3/ Nw8swO/2zABK1jJItOct+uj7Ld1vB9ivsVTAM8MJaCC4v17g2jAFGKT/74lWm4ttI2H+ mjAZXQe1GGN4+sPTf6GNLElvhX+kx3SeOlO1HaRzr8mvN2MyDEZU6WmMHLPzBtxSofK8 GWRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996154; x=1688588154; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HIYhvEBe+5na9q7sHii4+3BzV/97aBHrhxLYvL4RaKA=; b=HIMfdN9lQZ+BZg+JzkzXjOJgiWsWBbz2G0dLZerLNCzGQ2XeVB2Gs3htr7hAySS8Kx jvITByKKErS+e1VMZ/5ZI+wicJcDfEldaAvCLeu9YHJaGanAhPSgWOhj0lfx7NXjwpOM W6uvJ/r/IWaahl5+3QD0j3TrWGJXIg3HCnR46JvpoY6Q0iB+TMgyaRh0DWlr5e4DpZ/J CFOd45IaTb/dB3aI0H+h7le/Rf2aAia93ksn/np9fBZhdeXnVg1A1058FWD8b4BER3gP 6Eit8ILwANNITo0YaPohbv22G5QWyRtxfd36iKxy41hFitLrl+jUAhYIbujlimrFAfYN ILvg== X-Gm-Message-State: AC+VfDwmil4a7v/bTRqkjraDzrDZ/qeZ2HhdMcXEoxxMAIWPKT97XLs+ 6z8jbJ75V1wYxH62HAEDOM/npKPj3uhV4mMWwus= X-Received: by 2002:a05:6a00:1a12:b0:64f:aea5:7b49 with SMTP id g18-20020a056a001a1200b0064faea57b49mr776628pfv.17.1685996154261; Mon, 05 Jun 2023 13:15:54 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.15.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:15:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 04/52] tcg/sparc64: Remove TARGET_LONG_BITS, TCG_TYPE_TL Date: Mon, 5 Jun 2023 13:15:00 -0700 Message-Id: <20230605201548.1596865-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org All uses replaced with TCGContext.addr_type. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index d2d0f604c2..48efd83817 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1027,6 +1027,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, TCGReg addr_reg, MemOpIdx oi, bool is_ld) { + TCGType addr_type = s->addr_type; TCGLabelQemuLdst *ldst = NULL; MemOp opc = get_memop(oi); MemOp s_bits = opc & MO_SIZE; @@ -1063,7 +1064,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T3, ARITH_ADD); /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, TCG_TYPE_TL, TCG_REG_T2, TCG_REG_T1, cmp_off); + tcg_out_ld(s, addr_type, TCG_REG_T2, TCG_REG_T1, cmp_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T1, TCG_REG_T1, add_off); h->base = TCG_REG_T1; @@ -1084,7 +1085,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, ldst->label_ptr[0] = s->code_ptr; /* bne,pn %[xi]cc, label0 */ - cc = TARGET_LONG_BITS == 64 ? BPCC_XCC : BPCC_ICC; + cc = addr_type == TCG_TYPE_I32 ? BPCC_ICC : BPCC_XCC; tcg_out_bpcc0(s, COND_NE, BPCC_PN | cc, 0); #else /* @@ -1110,7 +1111,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, #endif /* If the guest address must be zero-extended, do in the delay slot. */ - if (TARGET_LONG_BITS == 32) { + if (addr_type == TCG_TYPE_I32) { tcg_out_ext32u(s, TCG_REG_T2, addr_reg); h->index = TCG_REG_T2; } else { From patchwork Mon Jun 5 20:15:01 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689225 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2285285wru; Mon, 5 Jun 2023 13:17:04 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4y0aCJdSiLjpuK9x5OiehbB4BC/O5wWfvOlv1nMUA+WiY/KnglneQORdU/nyN33sqD0m6u X-Received: by 2002:a05:620a:8084:b0:75b:23a0:d9d8 with SMTP id ef4-20020a05620a808400b0075b23a0d9d8mr792317qkb.46.1685996224389; Mon, 05 Jun 2023 13:17:04 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996224; cv=none; d=google.com; s=arc-20160816; b=nCs7iWU/OZyIazoCKO3qBxPBG+lrMw+hkkE66Mw2X6SYIenWzLz1SeMtkHfUqiQGTF 5KR3mjLssr2sw4NYCzHj0dA0pX/hry8uW8K5hTXN5nRks3QLHsWVUebxqzr52jYKPOmF /5rbLKn6UeGwzQFZExfiNPC06op5XkChjfYdPyRDlwNm6Fw2ntUSCrzj7q5SFrBHauUK fCoENJBszIslNrrtY0tz+YoST9tzdh9vBMwjVWDw4eQxOAg5EmIgaxqHp+97FYkjGTU+ 6pLOceh+aBMFkJ/4I13PJPBFk8Mbu5u2GDmvh9oQksAtubDcKIKIegS1bDwWkvpMg3Ra Wpow== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=AXcfOIJ9N4qoMjKYaO213RdnJ56sDPXoAOZMWVB9Z+s=; b=tUPY7z1U4kYk/l1fsFRTy1U1pKNlqLNg2WVJEf4GyxppB6jk/qGhS4VAeVS+qx7LgH sbua8eRoBFr3ccR3PS7xRW4RfyuCoi6wNU5ktibmNj/Bz4PGmDHstcbdtOLYMMEtwX9F kWf+6bqmNqeYn5WzyAmYYwh2/rKo8d+xG005ykfXg+Bj905QgWsj1w0Loz+O3S9a+M+2 7Xr+kHdPR7RdrhDN5em3iSheEeZSsutfq6cbIGPwmH7Hv3XEtlcbT6Sg4TUVqm9D3ZRA Sep9YCHS1HOWzHVDHGqeDs90a6M3E0rDHisVAlIYxf6NIQZXDctSI6PjEwqwqCJpUd1N H5TQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pUk7ZZIQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f5-20020ae9ea05000000b0074fc53cbdfcsi4824380qkg.667.2023.06.05.13.17.04 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:17:04 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=pUk7ZZIQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GcS-0001lh-4C; Mon, 05 Jun 2023 16:16:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcQ-0001kw-4P for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:15:58 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcO-0003kp-DP for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:15:57 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-655d1fc8ad8so1363102b3a.1 for ; Mon, 05 Jun 2023 13:15:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996155; x=1688588155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AXcfOIJ9N4qoMjKYaO213RdnJ56sDPXoAOZMWVB9Z+s=; b=pUk7ZZIQXVqrsl2oi3JFyTBEpIcZIGbkP8uyiUrHbxe62lk9gDQ6SYHVR3W3/uWOkS CCyDIhFTtK6l8RVUbdOh+3szyNqhXT0ki3b63VSYiQ4s8//XGGzTUVL6Uhjqb089A4CZ 5NIeidKpZLCyttMJzRPg4YQ+v+wL9RGAZbY32p/vFMR0/hPsF67wJ/h4cKq2iOnRG2I7 M95yNbkMyCCAsJhBGzCiVD2wv5Un7NYvhF/oaS5QHsi4d/TbVaS999Hfitssgwo7AXZY hsjHTtfHKDAClOUq7aA/UgWmZEupWp/9he8238pflISHGRKzWnzRSZxoyU+x5rWqPDAV Iz5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996155; x=1688588155; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AXcfOIJ9N4qoMjKYaO213RdnJ56sDPXoAOZMWVB9Z+s=; b=kvyqxpe6cq/XR4JnxJvKt4qdcAMfvlW9C4Z/nR0xV449iglSZf+BUIviUbqFxAJLb8 AdSgjh7HfAyCXT9QWRN/9jXy7rKIJr2yECGqn3gDtJqNqC6qHa1LUEKhIzb7NPgmXMOG 9iv79WkuH4ND98ZF2OLSvPXOF62FlcT5VXZNmMyBKQYtlyz3E9U7ifpFZq0MzhAN9/JT dJZpqMY7xR0xv5sjaJl6N5cggncJ+5ruLgJq890FIrMZMgFe9MoQksqrlJj092JPu+Wc sRPuk/YfqDZDuQO108qgtocUZwWsHww2lLU8c28bohT4CMBUEiqB4ryDrV+T9mx8xCPU Nuag== X-Gm-Message-State: AC+VfDy8l/HyrADIRu2W1U/LH2JfYsm8MhxTS2z47Le3WWIkB7Ak6HI8 r0mk3mUfh35Hfjrfm9pKh6OlExhQMSJNaLb+zUA= X-Received: by 2002:a05:6a00:248b:b0:64d:1215:a0f5 with SMTP id c11-20020a056a00248b00b0064d1215a0f5mr731061pfv.34.1685996155086; Mon, 05 Jun 2023 13:15:55 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:15:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 05/52] tcg: Move TCG_TYPE_TL from tcg.h to tcg-op.h Date: Mon, 5 Jun 2023 13:15:01 -0700 Message-Id: <20230605201548.1596865-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Removes the only use of TARGET_LONG_BITS from tcg.h, which is to be target independent. Move the symbol to a define in tcg-op.h, which will continue to be target dependent. Rather than complicate matters for the use in tb_gen_code(), expand the definition there. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 8 ++++++++ include/tcg/tcg.h | 7 ------- accel/tcg/translate-all.c | 2 +- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 35c5700183..844c666374 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -722,6 +722,14 @@ static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) #error must include QEMU headers #endif +#if TARGET_LONG_BITS == 32 +# define TCG_TYPE_TL TCG_TYPE_I32 +#elif TARGET_LONG_BITS == 64 +# define TCG_TYPE_TL TCG_TYPE_I64 +#else +# error +#endif + #if TARGET_INSN_START_WORDS == 1 static inline void tcg_gen_insn_start(target_ulong pc) { diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 072c35f7f5..0da17f1b4f 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -292,13 +292,6 @@ typedef enum TCGType { #else TCG_TYPE_PTR = TCG_TYPE_I64, #endif - - /* An alias for the size of the target "long", aka register. */ -#if TARGET_LONG_BITS == 64 - TCG_TYPE_TL = TCG_TYPE_I64, -#else - TCG_TYPE_TL = TCG_TYPE_I32, -#endif } TCGType; /** diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index bf814b9e81..d7c93e3b57 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -350,7 +350,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tb_set_page_addr0(tb, phys_pc); tb_set_page_addr1(tb, -1); tcg_ctx->gen_tb = tb; - tcg_ctx->addr_type = TCG_TYPE_TL; + tcg_ctx->addr_type = TARGET_LONG_BITS == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64; #ifdef CONFIG_SOFTMMU tcg_ctx->page_bits = TARGET_PAGE_BITS; tcg_ctx->page_mask = TARGET_PAGE_MASK; From patchwork Mon Jun 5 20:15:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689249 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2287994wru; Mon, 5 Jun 2023 13:25:21 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ42ANh8kDUpTSOw+t9G6nOrI5Ea8pJ8vl3WfctnRiDvdGAeApKgXejZk61exwzq+mBM2Zrk X-Received: by 2002:a05:622a:291:b0:3f8:698b:34a3 with SMTP id z17-20020a05622a029100b003f8698b34a3mr8579823qtw.67.1685996721160; Mon, 05 Jun 2023 13:25:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996721; cv=none; d=google.com; s=arc-20160816; b=blMptFWAHFOpod2SGX/r7TEkgc4m+Tx4eRsM0OW6CGKikd0wFrJQ85V3P15zLQ5fx9 MTUwF7n4Qu4d6k+N+td9pyEsXyf8vg5cPALIImJjsgYR6TMJdugvaeeVLF+R8hHaPn22 qMq6/uxaU7yyr+0eQaqOpMaSDndXZNyXJhAPDH2cfSWx+uVzlWgkwmm2FEL3YohCryfG EN0STngnYXH2ZQuNXcQffx8S+XbTRw9PQ1s2uys3uPkCgUFg1yqqqqBJZUhDksQfzp0k GqgCha8lO3iAnj3WDeZL5jujQyM78RT1Z1MXRaDcDzJeRDiWiP93ohoyoVP6T6dd5rZj vLeg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=9Q4L5Xu0HMQdUE9v27UYwFFrBy92qJzPKsISG2RoSJg=; b=gO5R6IvL1yZf2szaWMh4lx8z32LD3SWl83Cnz46NzrGt9Wns9N/1ZmdAAu9Xp10BQm qARYQqhZeYLBsCLP+/FrTe1EeUSXiSQOHYfiZLPZisy5JcbagmBEE5GBbLYAcjWn8Ubc p26obVqTZMz/ILute3wOPiHvEmjJ/DppgABXNWBhcDdcs3Vuam76aI0U7+wPrbRu6Ejg TatlxHDY4+5iPD1etHC/C+hAABPwxO89uIj6+Odo1KeSeF9DQuYcPq6GzC0fhYjaF6dp 7dvXQcvjvXUKd5MnwFsC0piWzZ28mwtxpmkiBj20RVm0wPEfN4w137DoSilBKfHN0m9r Sn0Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y19hKIdY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t6-20020ac85886000000b003f6b1049714si5164385qta.806.2023.06.05.13.25.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:25:21 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=y19hKIdY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GcU-0001o0-Of; Mon, 05 Jun 2023 16:16:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcS-0001nZ-PP for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:00 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcQ-0003la-EM for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:00 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-652426346bbso2709355b3a.3 for ; Mon, 05 Jun 2023 13:15:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996156; x=1688588156; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9Q4L5Xu0HMQdUE9v27UYwFFrBy92qJzPKsISG2RoSJg=; b=y19hKIdYfvNt8Zx/BN1WBHKC63wRxPSDt87KasaUPenqxn4GWpKa+YnBB7KPa5WA99 mrOmDVHxMH2ddzatQU7HnfZ0KwyvXliNs59uF5SsljKIiMHyWSW2oiJpHb9EKRzW87kF PadrE7XUSQppk1XQ4DpYVvYV3laPeaXyE/ogxB3WQee0Q1aQ/FwrvnLdbI+7SkssB7cU z8HqrrBqJNktN3WfWwTRurRtG3/CCMcSy/538B2c/tWU/DQDA7iU6qNLdFSSICYQZQFZ 90TlZa8n7uoNXLnUrbTkt1fUZ8RHN/BN4l4f/VpdcoLAPLt+icZBrG1sWrwaYThTZNG+ Mkng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996156; x=1688588156; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9Q4L5Xu0HMQdUE9v27UYwFFrBy92qJzPKsISG2RoSJg=; b=NezHPZ1DptGFbA9Ior9Cp0O+g2lI32KGIXsH2svbs7xNgMecUARz9OPB4MaJK4ICUq y1xg/EUh7jiTjWVATD+fwRz5sdtTWhmM2vaGdUahNPZzjfiWXdCQNpata/eSjTcxq2WA Z2C4Cg5B1Xrfa6KHKzWYcAJ+YEZ6zf6AN85JTjRp4VZCKUhIFeb4kMM6dkeelbbuxKz0 yRyBmt9F6YnHynZSzJYy3GlPdmeQBR62ekCM4Kp4X7fNMK7n1SWNFtKOEWCz9i6oYrO0 Nsu+7a7gQWaeyYXf3OK8eNvbHWWv4F9fDIszQe4MrEnzJ0J0H0uPYo//DwPQRCJy1DaK d7qA== X-Gm-Message-State: AC+VfDyEbwNiFk65kign7Qr9YZTQe1IxNGzPH2+RXpBfRANp9NQgWA1/ ZcTGulH8ZqkmxRe9+JWTNpJzaKkKLCBOAUdpvm8= X-Received: by 2002:a05:6a00:234b:b0:647:d698:56d2 with SMTP id j11-20020a056a00234b00b00647d69856d2mr797988pfj.27.1685996156026; Mon, 05 Jun 2023 13:15:56 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.15.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:15:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PULL 06/52] tcg: Widen CPUTLBEntry comparators to 64-bits Date: Mon, 5 Jun 2023 13:15:02 -0700 Message-Id: <20230605201548.1596865-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This makes CPUTLBEntry agnostic to the address size of the guest. When 32-bit addresses are in effect, we can simply read the low 32 bits of the 64-bit field. Similarly when we need to update the field for setting TLB_NOTDIRTY. For TCG backends that could in theory be big-endian, but in practice are not (arm, loongarch, riscv), use QEMU_BUILD_BUG_ON to document and ensure this is not accidentally missed. For s390x, which is always big-endian, use HOST_BIG_ENDIAN anyway, to document the reason for the adjustment. For sparc64 and ppc64, always perform a 64-bit load, and rely on the following 32-bit comparison to ignore the high bits. Rearrange mips and ppc if ladders for clarity. Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 37 +++++++++++--------------------- include/exec/cpu_ldst.h | 19 ++++++++++------ accel/tcg/cputlb.c | 8 +++++-- tcg/aarch64/tcg-target.c.inc | 1 + tcg/arm/tcg-target.c.inc | 1 + tcg/loongarch64/tcg-target.c.inc | 1 + tcg/mips/tcg-target.c.inc | 13 ++++++----- tcg/ppc/tcg-target.c.inc | 28 +++++++++++++----------- tcg/riscv/tcg-target.c.inc | 1 + tcg/s390x/tcg-target.c.inc | 1 + tcg/sparc64/tcg-target.c.inc | 8 +++++-- 11 files changed, 67 insertions(+), 51 deletions(-) diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index a6e0cf1812..b757d37966 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -65,11 +65,7 @@ /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 -#if HOST_LONG_BITS == 32 && TARGET_LONG_BITS == 32 -#define CPU_TLB_ENTRY_BITS 4 -#else #define CPU_TLB_ENTRY_BITS 5 -#endif #define CPU_TLB_DYN_MIN_BITS 6 #define CPU_TLB_DYN_DEFAULT_BITS 8 @@ -95,33 +91,26 @@ # endif /* Minimalized TLB entry for use by TCG fast path. */ -typedef struct CPUTLBEntry { - /* bit TARGET_LONG_BITS to TARGET_PAGE_BITS : virtual address - bit TARGET_PAGE_BITS-1..4 : Nonzero for accesses that should not - go directly to ram. - bit 3 : indicates that the entry is invalid - bit 2..0 : zero - */ - union { - struct { - target_ulong addr_read; - target_ulong addr_write; - target_ulong addr_code; - /* Addend to virtual address to get host address. IO accesses - use the corresponding iotlb value. */ - uintptr_t addend; - }; +typedef union CPUTLBEntry { + struct { + uint64_t addr_read; + uint64_t addr_write; + uint64_t addr_code; /* - * Padding to get a power of two size, as well as index - * access to addr_{read,write,code}. + * Addend to virtual address to get host address. IO accesses + * use the corresponding iotlb value. */ - target_ulong addr_idx[(1 << CPU_TLB_ENTRY_BITS) / TARGET_LONG_SIZE]; + uintptr_t addend; }; + /* + * Padding to get a power of two size, as well as index + * access to addr_{read,write,code}. + */ + uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)]; } CPUTLBEntry; QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); - #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ #if !defined(CONFIG_USER_ONLY) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index 5939688f69..a43b34e46b 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -334,18 +334,25 @@ static inline target_ulong tlb_read_idx(const CPUTLBEntry *entry, { /* Do not rearrange the CPUTLBEntry structure members. */ QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_read) != - MMU_DATA_LOAD * TARGET_LONG_SIZE); + MMU_DATA_LOAD * sizeof(uint64_t)); QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_write) != - MMU_DATA_STORE * TARGET_LONG_SIZE); + MMU_DATA_STORE * sizeof(uint64_t)); QEMU_BUILD_BUG_ON(offsetof(CPUTLBEntry, addr_code) != - MMU_INST_FETCH * TARGET_LONG_SIZE); + MMU_INST_FETCH * sizeof(uint64_t)); - const target_ulong *ptr = &entry->addr_idx[access_type]; -#if TCG_OVERSIZED_GUEST - return *ptr; +#if TARGET_LONG_BITS == 32 + /* Use qatomic_read, in case of addr_write; only care about low bits. */ + const uint32_t *ptr = (uint32_t *)&entry->addr_idx[access_type]; + ptr += HOST_BIG_ENDIAN; + return qatomic_read(ptr); #else + const uint64_t *ptr = &entry->addr_idx[access_type]; +# if TCG_OVERSIZED_GUEST + return *ptr; +# else /* ofs might correspond to .addr_write, so use qatomic_read */ return qatomic_read(ptr); +# endif #endif } diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 90c72c9940..6beaeb0a81 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1000,11 +1000,15 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *tlb_entry, addr &= TARGET_PAGE_MASK; addr += tlb_entry->addend; if ((addr - start) < length) { -#if TCG_OVERSIZED_GUEST +#if TARGET_LONG_BITS == 32 + uint32_t *ptr_write = (uint32_t *)&tlb_entry->addr_write; + ptr_write += HOST_BIG_ENDIAN; + qatomic_set(ptr_write, *ptr_write | TLB_NOTDIRTY); +#elif TCG_OVERSIZED_GUEST tlb_entry->addr_write |= TLB_NOTDIRTY; #else qatomic_set(&tlb_entry->addr_write, - tlb_entry->addr_write | TLB_NOTDIRTY); + tlb_entry->addr_write | TLB_NOTDIRTY); #endif } } diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 261ad25210..e23c57e2cd 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1690,6 +1690,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, tcg_out_insn(s, 3502, ADD, 1, TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP0); /* Load the tlb comparator into TMP0, and the fast path addend into TMP1. */ + QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP1, is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 20cc1cc477..64eb0cb5dc 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1430,6 +1430,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, * Add the tlb_table pointer, creating the CPUTLBEntry address in R1. * Load the tlb comparator into R2/R3 and the fast path addend into R1. */ + QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); if (cmp_off == 0) { if (s->addr_type == TCG_TYPE_I32) { tcg_out_ld32_rwb(s, COND_AL, TCG_REG_R2, TCG_REG_R1, TCG_REG_R0); diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 0bae922982..e89f3b848b 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -875,6 +875,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, tcg_out_opc_add_d(s, TCG_REG_TMP2, TCG_REG_TMP2, TCG_REG_TMP1); /* Load the tlb comparator and the addend. */ + QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 3274d9aace..4c0de0a380 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1311,14 +1311,17 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, /* Add the tlb_table pointer, creating the CPUTLBEntry address in TMP3. */ tcg_out_opc_reg(s, ALIAS_PADD, TCG_TMP3, TCG_TMP3, TCG_TMP1); + if (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32) { + /* Load the (low half) tlb comparator. */ + tcg_out_ld(s, TCG_TYPE_I32, TCG_TMP0, TCG_TMP3, + cmp_off + HOST_BIG_ENDIAN * 4); + } else { + tcg_out_ld(s, TCG_TYPE_I64, TCG_TMP0, TCG_TMP3, cmp_off); + } + if (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32) { - /* Load the tlb comparator. */ - tcg_out_ld(s, addr_type, TCG_TMP0, TCG_TMP3, cmp_off); /* Load the tlb addend for the fast path. */ tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP3, TCG_TMP3, add_off); - } else { - /* Load the low half of the tlb comparator. */ - tcg_out_ldst(s, OPC_LW, TCG_TMP0, TCG_TMP3, cmp_off + LO_OFF); } /* diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 11955a6cc2..73f6ea0393 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2098,20 +2098,24 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, } tcg_out32(s, AND | SAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_R0)); - /* Load the (low part) TLB comparator into TMP2. */ - if (cmp_off == 0 - && (TCG_TARGET_REG_BITS == 64 || addr_type == TCG_TYPE_I32)) { - uint32_t lxu = (TCG_TARGET_REG_BITS == 32 || addr_type == TCG_TYPE_I32 - ? LWZUX : LDUX); - tcg_out32(s, lxu | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); + /* + * Load the (low part) TLB comparator into TMP2. + * For 64-bit host, always load the entire 64-bit slot for simplicity. + * We will ignore the high bits with tcg_out_cmp(..., addr_type). + */ + if (TCG_TARGET_REG_BITS == 64) { + if (cmp_off == 0) { + tcg_out32(s, LDUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); + } else { + tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); + tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off); + } + } else if (cmp_off == 0 && !HOST_BIG_ENDIAN) { + tcg_out32(s, LWZUX | TAB(TCG_REG_TMP2, TCG_REG_TMP1, TCG_REG_TMP2)); } else { tcg_out32(s, ADD | TAB(TCG_REG_TMP1, TCG_REG_TMP1, TCG_REG_TMP2)); - if (TCG_TARGET_REG_BITS == 32 && addr_type != TCG_TYPE_I32) { - tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, - TCG_REG_TMP1, cmp_off + 4 * HOST_BIG_ENDIAN); - } else { - tcg_out_ld(s, addr_type, TCG_REG_TMP2, TCG_REG_TMP1, cmp_off); - } + tcg_out_ld(s, TCG_TYPE_I32, TCG_REG_TMP2, TCG_REG_TMP1, + cmp_off + 4 * HOST_BIG_ENDIAN); } /* diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index a8f99f7e77..a6d56e2d0e 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1249,6 +1249,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, } /* Load the tlb comparator and the addend. */ + QEMU_BUILD_BUG_ON(HOST_BIG_ENDIAN); tcg_out_ld(s, addr_type, TCG_REG_TMP0, TCG_REG_TMP2, is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write)); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 2795242b60..03be800c3b 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1796,6 +1796,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, ofs = offsetof(CPUTLBEntry, addr_write); } if (addr_type == TCG_TYPE_I32) { + ofs += HOST_BIG_ENDIAN * 4; tcg_out_insn(s, RX, C, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); } else { tcg_out_insn(s, RXY, CG, TCG_REG_R0, TCG_TMP0, TCG_REG_NONE, ofs); diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 48efd83817..6c60657c36 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1063,8 +1063,12 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, /* Add the tlb_table pointer, creating the CPUTLBEntry address into R2. */ tcg_out_arith(s, TCG_REG_T1, TCG_REG_T1, TCG_REG_T3, ARITH_ADD); - /* Load the tlb comparator and the addend. */ - tcg_out_ld(s, addr_type, TCG_REG_T2, TCG_REG_T1, cmp_off); + /* + * Load the tlb comparator and the addend. + * Always load the entire 64-bit comparator for simplicity. + * We will ignore the high bits via BPCC_ICC below. + */ + tcg_out_ld(s, TCG_TYPE_I64, TCG_REG_T2, TCG_REG_T1, cmp_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T1, TCG_REG_T1, add_off); h->base = TCG_REG_T1; From patchwork Mon Jun 5 20:15:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689257 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288292wru; Mon, 5 Jun 2023 13:26:11 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6WFJDbbnSozKR6Wzv5krOT82w15w5zpsLOnrUB89YcGchIE0zZg8IvzMYW2STHifh7ufxC X-Received: by 2002:a37:6c2:0:b0:75e:c960:920a with SMTP id 185-20020a3706c2000000b0075ec960920amr299110qkg.4.1685996770842; Mon, 05 Jun 2023 13:26:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996770; cv=none; d=google.com; s=arc-20160816; b=GknPl0m4UmOzxccotSbgHGJ5fbQBCC1bEwNvSdN8x4rnwAXPftAzG80ylU30cMUW/q nLXbKUXmJzNhNBGdu2s7yMInFI1eBSiYQVS9wouIITJ/y/hOM7EILSLXVZeWFArnvxKX XsvTrgAp41pwLTqA5HPG7MlsOK39DLV0/6BKS5pO+WUNAxTLPQRpLRG/y4c9bLhQC/rS YXX7bImGUJhQgI/H6UQE801W4FoSoelo9e0cOH1f+pgQHMJfQiTaZVcfijZLmxvV0aMw 2cm8t85ULJpIS5QKCnaArVU00FqdAu03uucoRCFNlKvmV7iTG68PbTDvtmoyZslyjsi/ muKg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MbH2uafo/Bq5KipVVfwAbK/Qn2ilFDN5deNKLGvFCm8=; b=LYkDRgM1hNqK+gG31rLJ0jC67N+TiqwmrIe600XtJUPcXXwgiRENu9EXmeHtSDn26D xt09CPx2QikMZ9hsydJICJpXeJErgnz4dms7d8y34RWXSMuwOOOFIpMuXOkeLe3ehEi4 6kYBDnhapJlzsaC4XbkdOyd5HrtfsOzke0LtfWepoXAWFjPYbLMx55DTD9gnyPWbiDeh 7aexzRXxwxg7VPyGO5ssbGmWLIfp4Ha/IJLvNGatXqDxTJFeFyA4zC3dSj0iKjssiNeL AZGiRVu1nYfzNiXzsmeLstdxHLCUC6LPH2Qn/8AA5ZsD8H84llUu5e4bmmM32RUGtwRg 95dw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AWcAjUTv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id e19-20020a05620a12d300b0075dabfdefb4si2092942qkl.331.2023.06.05.13.26.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:26:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AWcAjUTv; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GcX-0001pn-PS; Mon, 05 Jun 2023 16:16:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcU-0001nq-AU for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:02 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcQ-0003mj-Rx for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:02 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-65540715b4bso1364507b3a.0 for ; Mon, 05 Jun 2023 13:15:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996157; x=1688588157; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=MbH2uafo/Bq5KipVVfwAbK/Qn2ilFDN5deNKLGvFCm8=; b=AWcAjUTvjbK5raKib/NZTacUhcg8olJFg8Oz/6m9/jVqw3l0UdI39aXrcRtXtiNvQU lZ7vjJR9khuk8mJ8ps3jHI/MlG33qwLxcqPExGo3z5Gtx0cJeDT+d0geBmEb//6rQ0pu mnT5zKvhINvd98j/fmLmDIArCRNbFR0s/0WBBQxibNxX6cK0y23g4WAo9TM9AfcWollQ BStElDw329IXlI5sH14gg+nqZFq8CSWr9pDin4cbcvM9syGxpd7wn6K/4T7VmuiGv0Uz BUWpCZNUMjXNmjuIVB2DgbCBcnriQc6PTNxFWN/E8R9ZamwdNp09GrO9R4UnLNjE6x+U /3pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996157; x=1688588157; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MbH2uafo/Bq5KipVVfwAbK/Qn2ilFDN5deNKLGvFCm8=; b=WWAVa15ppaosgkOHKZu/wGbhSQlur8daZaH5o03hr+fYM7uKumWPE15sV6sg1soDDd HQXRz9XNshemE1IStetpiz33w3/H2h205OA7cv85dVEb1M4SSCnIlVXPVltVvZFK/H0r QMxfFX2zp6Lrz9B3XtGStnjib7BMwHREUO3R47TaQy9mjiqx4oeHjsKLjKBgqVcJlf+j txRROKBkT6jEG53U05cUt70BvBKeUMB9UULNIHqkPKJamWVpB34yQnSjBWIdclzvlP2p OMfauZ4Xzx87VbMg5ggTSpcXKB96bLZKvkAfrw0fK8El+T56Dt5f5LTr6k9NSOGciAKs p2rQ== X-Gm-Message-State: AC+VfDzIEM8QA1OcdIh0eG8I/3B3FQ3zJxB6cogFZShKaoR//NOyHtie mrMtt0DZQNUBUPrgNDWSpyWklEc2osT1ogK6LXM= X-Received: by 2002:a05:6a00:14cf:b0:64d:2ea4:9377 with SMTP id w15-20020a056a0014cf00b0064d2ea49377mr803684pfu.14.1685996156851; Mon, 05 Jun 2023 13:15:56 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:15:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 07/52] tcg: Add tlb_fast_offset to TCGContext Date: Mon, 5 Jun 2023 13:15:03 -0700 Message-Id: <20230605201548.1596865-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Disconnect the layout of ArchCPU from TCG compilation. Pass the relative offset of 'env' and 'neg.tlb.f' as a parameter. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 39 +--------------------- include/exec/tlb-common.h | 56 ++++++++++++++++++++++++++++++++ include/tcg/tcg.h | 1 + accel/tcg/translate-all.c | 2 ++ tcg/tcg.c | 13 ++++++++ tcg/aarch64/tcg-target.c.inc | 7 ++-- tcg/arm/tcg-target.c.inc | 7 ++-- tcg/i386/tcg-target.c.inc | 9 ++--- tcg/loongarch64/tcg-target.c.inc | 7 ++-- tcg/mips/tcg-target.c.inc | 7 ++-- tcg/ppc/tcg-target.c.inc | 7 ++-- tcg/riscv/tcg-target.c.inc | 7 ++-- tcg/s390x/tcg-target.c.inc | 7 ++-- tcg/sparc64/tcg-target.c.inc | 7 ++-- 14 files changed, 110 insertions(+), 66 deletions(-) create mode 100644 include/exec/tlb-common.h diff --git a/include/exec/cpu-defs.h b/include/exec/cpu-defs.h index b757d37966..0d418a0384 100644 --- a/include/exec/cpu-defs.h +++ b/include/exec/cpu-defs.h @@ -61,12 +61,11 @@ #define NB_MMU_MODES 16 #if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +#include "exec/tlb-common.h" /* use a fully associative victim tlb of 8 entries */ #define CPU_VTLB_SIZE 8 -#define CPU_TLB_ENTRY_BITS 5 - #define CPU_TLB_DYN_MIN_BITS 6 #define CPU_TLB_DYN_DEFAULT_BITS 8 @@ -90,27 +89,6 @@ # endif # endif -/* Minimalized TLB entry for use by TCG fast path. */ -typedef union CPUTLBEntry { - struct { - uint64_t addr_read; - uint64_t addr_write; - uint64_t addr_code; - /* - * Addend to virtual address to get host address. IO accesses - * use the corresponding iotlb value. - */ - uintptr_t addend; - }; - /* - * Padding to get a power of two size, as well as index - * access to addr_{read,write,code}. - */ - uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)]; -} CPUTLBEntry; - -QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); - #endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ #if !defined(CONFIG_USER_ONLY) @@ -184,17 +162,6 @@ typedef struct CPUTLBDesc { CPUTLBEntryFull *fulltlb; } CPUTLBDesc; -/* - * Data elements that are per MMU mode, accessed by the fast path. - * The structure is aligned to aid loading the pair with one insn. - */ -typedef struct CPUTLBDescFast { - /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ - uintptr_t mask; - /* The array of tlb entries itself. */ - CPUTLBEntry *table; -} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); - /* * Data elements that are shared between all MMU modes. */ @@ -230,10 +197,6 @@ typedef struct CPUTLB { CPUTLBDescFast f[NB_MMU_MODES]; } CPUTLB; -/* This will be used by TCG backends to compute offsets. */ -#define TLB_MASK_TABLE_OFS(IDX) \ - ((int)offsetof(ArchCPU, neg.tlb.f[IDX]) - (int)offsetof(ArchCPU, env)) - #else typedef struct CPUTLB { } CPUTLB; diff --git a/include/exec/tlb-common.h b/include/exec/tlb-common.h new file mode 100644 index 0000000000..dc5a5faa0b --- /dev/null +++ b/include/exec/tlb-common.h @@ -0,0 +1,56 @@ +/* + * Common definitions for the softmmu tlb + * + * Copyright (c) 2003 Fabrice Bellard + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see . + */ +#ifndef EXEC_TLB_COMMON_H +#define EXEC_TLB_COMMON_H 1 + +#define CPU_TLB_ENTRY_BITS 5 + +/* Minimalized TLB entry for use by TCG fast path. */ +typedef union CPUTLBEntry { + struct { + uint64_t addr_read; + uint64_t addr_write; + uint64_t addr_code; + /* + * Addend to virtual address to get host address. IO accesses + * use the corresponding iotlb value. + */ + uintptr_t addend; + }; + /* + * Padding to get a power of two size, as well as index + * access to addr_{read,write,code}. + */ + uint64_t addr_idx[(1 << CPU_TLB_ENTRY_BITS) / sizeof(uint64_t)]; +} CPUTLBEntry; + +QEMU_BUILD_BUG_ON(sizeof(CPUTLBEntry) != (1 << CPU_TLB_ENTRY_BITS)); + +/* + * Data elements that are per MMU mode, accessed by the fast path. + * The structure is aligned to aid loading the pair with one insn. + */ +typedef struct CPUTLBDescFast { + /* Contains (n_entries - 1) << CPU_TLB_ENTRY_BITS */ + uintptr_t mask; + /* The array of tlb entries itself. */ + CPUTLBEntry *table; +} CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); + +#endif /* EXEC_TLB_COMMON_H */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 0da17f1b4f..54f260a66b 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -547,6 +547,7 @@ struct TCGContext { TCGType addr_type; /* TCG_TYPE_I32 or TCG_TYPE_I64 */ #ifdef CONFIG_SOFTMMU + int tlb_fast_offset; int page_mask; uint8_t page_bits; uint8_t tlb_dyn_max_bits; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index d7c93e3b57..5cea9acd5a 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -355,6 +355,8 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->page_bits = TARGET_PAGE_BITS; tcg_ctx->page_mask = TARGET_PAGE_MASK; tcg_ctx->tlb_dyn_max_bits = CPU_TLB_DYN_MAX_BITS; + tcg_ctx->tlb_fast_offset = + (int)offsetof(ArchCPU, neg.tlb.f) - (int)offsetof(ArchCPU, env); #endif tb_overflow: diff --git a/tcg/tcg.c b/tcg/tcg.c index 2352ca4ade..2d17c09aea 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -41,6 +41,7 @@ #define NO_CPU_IO_DEFS #include "exec/exec-all.h" +#include "exec/tlb-common.h" #include "tcg/tcg-op.h" #if UINTPTR_MAX == UINT32_MAX @@ -407,6 +408,13 @@ static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGContext *s, int which) return (uintptr_t)tcg_splitwx_to_rx(&s->gen_tb->jmp_target_addr[which]); } +#if defined(CONFIG_SOFTMMU) && !defined(CONFIG_TCG_INTERPRETER) +static int tlb_mask_table_ofs(TCGContext *s, int which) +{ + return s->tlb_fast_offset + which * sizeof(CPUTLBDescFast); +} +#endif + /* Signal overflow, starting over with fewer guest insns. */ static G_NORETURN void tcg_raise_tb_overflow(TCGContext *s) @@ -1521,6 +1529,11 @@ void tcg_func_start(TCGContext *s) tcg_debug_assert(s->addr_type == TCG_TYPE_I32 || s->addr_type == TCG_TYPE_I64); + +#if defined(CONFIG_SOFTMMU) && !defined(CONFIG_TCG_INTERPRETER) + tcg_debug_assert(s->tlb_fast_offset < 0); + tcg_debug_assert(s->tlb_fast_offset >= MIN_TLB_MASK_TABLE_OFS); +#endif } static TCGTemp *tcg_temp_alloc(TCGContext *s) diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index e23c57e2cd..35ca80cd56 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1636,6 +1636,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) return true; } +/* We expect to use a 7-bit scaled negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -512 + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -1674,12 +1677,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, ? TCG_TYPE_I64 : TCG_TYPE_I32); /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {tmp0,tmp1}. */ - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -512); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 8); tcg_out_insn(s, 3314, LDP, TCG_REG_TMP0, TCG_REG_TMP1, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index), 1, 0); + tlb_mask_table_ofs(s, mem_index), 1, 0); /* Extract the TLB index from the address into X0. */ tcg_out_insn(s, 3502S, AND_LSR, mask_type == TCG_TYPE_I64, diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 64eb0cb5dc..83e286088f 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1374,6 +1374,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) return true; } +/* We expect to use an 9-bit sign-magnitude negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -256 + static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, TCGReg addrlo, TCGReg addrhi, MemOpIdx oi, bool is_ld) @@ -1405,7 +1408,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, int mem_index = get_mmuidx(oi); int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write); - int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int fast_off = tlb_mask_table_ofs(s, mem_index); unsigned s_mask = (1 << (opc & MO_SIZE)) - 1; TCGReg t_addr; @@ -1416,8 +1419,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, ldst->addrhi_reg = addrhi; /* Load env_tlb(env)->f[mmu_idx].{mask,table} into {r0,r1}. */ - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -256); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) != 0); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) != 4); tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index ae54e5fbf3..ab997b5fb3 100644 --- a/tcg/i386/tcg-target.c.inc +++ b/tcg/i386/tcg-target.c.inc @@ -1900,6 +1900,8 @@ static inline int setup_guest_base_seg(void) #endif /* setup_guest_base_seg */ #endif /* !SOFTMMU */ +#define MIN_TLB_MASK_TABLE_OFS INT_MIN + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -1934,6 +1936,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, int trexw = 0, hrexw = 0, tlbrexw = 0; unsigned mem_index = get_mmuidx(oi); unsigned s_mask = (1 << s_bits) - 1; + int fast_ofs = tlb_mask_table_ofs(s, mem_index); int tlb_mask; ldst = new_ldst_label(s); @@ -1959,12 +1962,10 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, s->page_bits - CPU_TLB_ENTRY_BITS); tcg_out_modrm_offset(s, OPC_AND_GvEv + trexw, TCG_REG_L0, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index) + - offsetof(CPUTLBDescFast, mask)); + fast_ofs + offsetof(CPUTLBDescFast, mask)); tcg_out_modrm_offset(s, OPC_ADD_GvEv + hrexw, TCG_REG_L0, TCG_AREG0, - TLB_MASK_TABLE_OFS(mem_index) + - offsetof(CPUTLBDescFast, table)); + fast_ofs + offsetof(CPUTLBDescFast, table)); /* * If the required alignment is at least as large as the access, simply diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index e89f3b848b..baf5fc3819 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -834,6 +834,9 @@ bool tcg_target_has_memory_bswap(MemOp memop) return false; } +/* We expect to use a 12-bit negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -855,7 +858,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, #ifdef CONFIG_SOFTMMU unsigned s_bits = opc & MO_SIZE; int mem_index = get_mmuidx(oi); - int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); + int fast_ofs = tlb_mask_table_ofs(s, mem_index); int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); @@ -864,8 +867,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, ldst->oi = oi; ldst->addrlo_reg = addr_reg; - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 4c0de0a380..9faa8bdf0b 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1254,6 +1254,9 @@ bool tcg_target_has_memory_bswap(MemOp memop) return false; } +/* We expect to use a 16-bit negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -32768 + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -1279,7 +1282,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, #ifdef CONFIG_SOFTMMU unsigned s_mask = (1 << s_bits) - 1; int mem_index = get_mmuidx(oi); - int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int fast_off = tlb_mask_table_ofs(s, mem_index); int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); int table_off = fast_off + offsetof(CPUTLBDescFast, table); int add_off = offsetof(CPUTLBEntry, addend); @@ -1293,8 +1296,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, ldst->addrhi_reg = addrhi; /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP0, TCG_AREG0, mask_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_TMP1, TCG_AREG0, table_off); diff --git a/tcg/ppc/tcg-target.c.inc b/tcg/ppc/tcg-target.c.inc index 73f6ea0393..507fe6cda8 100644 --- a/tcg/ppc/tcg-target.c.inc +++ b/tcg/ppc/tcg-target.c.inc @@ -2036,6 +2036,9 @@ bool tcg_target_has_memory_bswap(MemOp memop) return aa.atom <= MO_64; } +/* We expect to use a 16-bit negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -32768 + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -2072,7 +2075,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, int mem_index = get_mmuidx(oi); int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) : offsetof(CPUTLBEntry, addr_write); - int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int fast_off = tlb_mask_table_ofs(s, mem_index); int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); int table_off = fast_off + offsetof(CPUTLBDescFast, table); @@ -2083,8 +2086,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, ldst->addrhi_reg = addrhi; /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -32768); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, mask_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP2, TCG_AREG0, table_off); diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index a6d56e2d0e..eeaeb6b6e3 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -1185,6 +1185,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) return true; } +/* We expect to use a 12-bit negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -(1 << 11) + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -1208,7 +1211,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, unsigned s_bits = opc & MO_SIZE; unsigned s_mask = (1u << s_bits) - 1; int mem_index = get_mmuidx(oi); - int fast_ofs = TLB_MASK_TABLE_OFS(mem_index); + int fast_ofs = tlb_mask_table_ofs(s, mem_index); int mask_ofs = fast_ofs + offsetof(CPUTLBDescFast, mask); int table_ofs = fast_ofs + offsetof(CPUTLBDescFast, table); int compare_mask; @@ -1219,8 +1222,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, TCGReg *pbase, ldst->oi = oi; ldst->addrlo_reg = addr_reg; - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 11)); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_AREG0, mask_ofs); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP1, TCG_AREG0, table_ofs); diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index 03be800c3b..aeddebbb5c 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -1735,6 +1735,9 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *lb) return true; } +/* We're expecting to use a 20-bit negative offset on the tlb memory ops. */ +#define MIN_TLB_MASK_TABLE_OFS -(1 << 19) + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -1757,7 +1760,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, #ifdef CONFIG_SOFTMMU unsigned s_mask = (1 << s_bits) - 1; int mem_index = get_mmuidx(oi); - int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int fast_off = tlb_mask_table_ofs(s, mem_index); int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); int table_off = fast_off + offsetof(CPUTLBDescFast, table); int ofs, a_off; @@ -1771,8 +1774,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, tcg_out_sh64(s, RSY_SRLG, TCG_TMP0, addr_reg, TCG_REG_NONE, s->page_bits - CPU_TLB_ENTRY_BITS); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 19)); tcg_out_insn(s, RXY, NG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, mask_off); tcg_out_insn(s, RXY, AG, TCG_TMP0, TCG_AREG0, TCG_REG_NONE, table_off); diff --git a/tcg/sparc64/tcg-target.c.inc b/tcg/sparc64/tcg-target.c.inc index 6c60657c36..ffcb879211 100644 --- a/tcg/sparc64/tcg-target.c.inc +++ b/tcg/sparc64/tcg-target.c.inc @@ -1017,6 +1017,9 @@ bool tcg_target_has_memory_bswap(MemOp memop) return true; } +/* We expect to use a 13-bit negative offset from ENV. */ +#define MIN_TLB_MASK_TABLE_OFS -(1 << 12) + /* * For softmmu, perform the TLB load and compare. * For useronly, perform any required alignment tests. @@ -1040,7 +1043,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, #ifdef CONFIG_SOFTMMU int mem_index = get_mmuidx(oi); - int fast_off = TLB_MASK_TABLE_OFS(mem_index); + int fast_off = tlb_mask_table_ofs(s, mem_index); int mask_off = fast_off + offsetof(CPUTLBDescFast, mask); int table_off = fast_off + offsetof(CPUTLBDescFast, table); int cmp_off = is_ld ? offsetof(CPUTLBEntry, addr_read) @@ -1050,8 +1053,6 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext *s, HostAddress *h, int cc; /* Load tlb_mask[mmu_idx] and tlb_table[mmu_idx]. */ - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) > 0); - QEMU_BUILD_BUG_ON(TLB_MASK_TABLE_OFS(0) < -(1 << 12)); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T2, TCG_AREG0, mask_off); tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_T3, TCG_AREG0, table_off); From patchwork Mon Jun 5 20:15:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689233 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2286443wru; Mon, 5 Jun 2023 13:20:28 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7jPaU3OeYgcE618KseyOQstjCCLVTP1MPiZRa2Xi/yk1SFoqeEfLUfvH/QZpS0qtqlLyH0 X-Received: by 2002:a05:620a:cf3:b0:75d:4699:7570 with SMTP id c19-20020a05620a0cf300b0075d46997570mr808090qkj.15.1685996428164; Mon, 05 Jun 2023 13:20:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996428; cv=none; d=google.com; s=arc-20160816; b=PhfXxU/uCjXomN8u7xyEGDnbtFiVrTWKh5LLJrEWdWNoUZeXlSiLAbOns6DFABc+ZN jos8elJ3H1MbY3Akf+PpXVXVuU1LLFx8K/4m3zLEjDf4b1D/QzL5nzppRo8GY8v4ASwq CqRnVBK+3pIPgwGkSQowydjwcoY0NJlhQO8tfge/N0ZsIXNMAB9K48J/OHOed7MMptlI wC6R7OAX/ZXLTNqjWGwotpijchpiyXrmBQcwKKu5WoPiWlFMu2ilipf4JaK/R9L6dD9Q VLid+LIxgeMxp00SGujWYiK8Muir21SFfdXFdOFHcgmB10jm/zXUtszg/ExYksvSR1Aw IjYQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=YqDV+jm8g9evb7GNVfVDtXxCAOldVWaEESSAIjdOu2o=; b=V/Q3DS1KfC4SzZ/4wHu6S2uTqdepSVFfygKQkjSzIYvxScrQcz75zLhbf4c/iL9c/A y1PoQY1bwydM9cE8w7y2CWPV1MPNjobtHoh4uDStumxBQ0uCHs9oAktiTvqwpyaBbc/y UrAMQ2GUIgBBjco7yEdwN/jLvkpgHiw+6WNQvPl8uETRZz/B/PHBTpV8TjYwm6klqWgZ W4DPV4RX+JB8TcG53i5Uz0wrr0Wjg7EnnqCWNkuksx284IPelih2AxD29F/vihxXYBIU coskgMPiuLj0QQs1ZxHNCgLJ9MCTivImpttKKzxcIkNOPq/WFdNa9bsfG+H0bRqYi30J pPHg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aQpwa3qu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q25-20020ae9e419000000b007594108539esi4948540qkc.125.2023.06.05.13.20.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:20:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=aQpwa3qu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GcV-0001of-MB; Mon, 05 Jun 2023 16:16:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcT-0001nh-O2 for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:01 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcQ-0003mw-SI for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:01 -0400 Received: by mail-pf1-x429.google.com with SMTP id d2e1a72fcca58-651f2f38634so4813644b3a.0 for ; Mon, 05 Jun 2023 13:15:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996157; x=1688588157; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=YqDV+jm8g9evb7GNVfVDtXxCAOldVWaEESSAIjdOu2o=; b=aQpwa3qufmzPaeZT+NA9CUG1yplHoISB0eqzU3StOQssT0/Uxb4Nb4PZ/DumDCcDDk uxkVgt4wWfza0Qy33Q7fP8+kMOmst0rUOUzGHZyeOTuSLdbsYZuZHWDYkE1oArf/NZIV UYvSNa15uxckDPmgnlp+cRN+M0QNboBVUI1bxMyP5aA5OyW1WZ0LWcu2uvX37DmLfdCg YNTBilnqLzPwQc+A0kjtiFSFLedL6JB7rK+ahlPoOdk9Pdv/PEYszHKvZKgTt7eYa2Xj 3TbVDL1Dyb0HILXCrwNF8zec3tROTnEbom+14Y9j9o3RfxjrFz5ythGsYKlAQ+xMZLZe GkYQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996157; x=1688588157; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YqDV+jm8g9evb7GNVfVDtXxCAOldVWaEESSAIjdOu2o=; b=G9yint8l7tinExfHkoyX/iNBXKZOtPInzDIm3rFNowRQH7z0Kle1nGvuu1E3+nMe7w qe7xjP1wQ1jewyePguZ4xo2HgstOVev7s5Bc2qsJxRa5kYG409MWPzc0D6FNBFALkWlo J7EHdVhJyad8V41+t50NvD5PYCujhBc8Ns8L4zAhUKAGc2+BVyhrpw1cwh3MiOOQ9QaC FsaI06pr+SB3KZV8VMsK4OLUt7Vx6SmC5YYvDJoXpdnLAFILYPZLMhGo1mEWj5nv2CPa anogLnjCLlpVYHyeQPOoWeLQZ18f9xjoLQd6osX6fW0lp4haRCdtwak3I/7be5LIVSpy fMKg== X-Gm-Message-State: AC+VfDxh2xYd1pg31j5sDHgoCTDS2eiNlsmoqCt2/64M72NIxQQTpuoZ OW5xIzrmfkBYEnttJDAnm8Y2tOjqdF7yPGJ7Sl4= X-Received: by 2002:a05:6a00:2292:b0:652:542c:ad8d with SMTP id f18-20020a056a00229200b00652542cad8dmr996404pfe.9.1685996157655; Mon, 05 Jun 2023 13:15:57 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.15.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:15:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 08/52] target/avr: Add missing includes of qemu/error-report.h Date: Mon, 5 Jun 2023 13:15:04 -0700 Message-Id: <20230605201548.1596865-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This had been pulled in from tcg/tcg.h, via exec/cpu_ldst.h, via exec/exec-all.h, but the include of tcg.h will be removed. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/avr/helper.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/avr/helper.c b/target/avr/helper.c index 156dde4e92..2bad242a66 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/error-report.h" #include "cpu.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" From patchwork Mon Jun 5 20:15:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689250 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288098wru; Mon, 5 Jun 2023 13:25:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7xZ6LOxfqW9A9ikYr+JM/8ldg/3USH4zlKwgRXf2h6ExIqGnBrD0q645lAX4NHGED78zeH X-Received: by 2002:a05:6214:400f:b0:5cd:1adc:30e2 with SMTP id kd15-20020a056214400f00b005cd1adc30e2mr7965660qvb.11.1685996738863; Mon, 05 Jun 2023 13:25:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996738; cv=none; d=google.com; s=arc-20160816; b=w4BrZE0V2bTZt6bU3L4K4X22c/oKV5EkiLaJqdXxwQI/TEq2jf+DDOE7VjkWOwFNZo +/4C8n+1zOPuU6uExqXXOLfIRNn8N+o3lI8cmBUn4mhSRhRM2n4RrOBR3BamrWaoDIWU HW4xPGQK0//9VbumShuiwKRq/LWpkSnY7elX5QcJG/fZQl/ebxgpTx4b7/gKhnCgHBgX KIv8gMw3MP0B+xq9n/fudZVKK+PjWswd77EowlGUx+XSPZEVRmopepNbWTSUI64T3VZJ svY+/GRygjeEbnCO++yNSw9n66xTycTQhWL/MNaa0qsaz13JhmO0Box8o7yrzFmY2mqA Fv9A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BNL16VFJ/JVKBYmioxTJxOZayJwkRUPqGfQWbKcHjhI=; b=arjQ70i+MdqbAP8mC4O3x6a5eYM53RZHfMT6zxyjHtkHTLCg6XMMtK35eKy3Y5xz1P eSaiayJs7nNYTtmvbnS2m+2s5qXkRpci1wbHHTiRyLmfh1n2E7vLFqsdZDAuvUrQgFhT a0/rB7ZZxZBTy/OQrGyI5DPDgRiQMc0mAv5dWIAd3XLRU8yrbBj2xBbHym8/qkpid5WU qHEX8HNQ75kDE5qX7HRf2Uzd0ju4/aUDMbCQt+p2iD7Mfis86jnb4BPSdIE0TFZunXDG +Z86aCC8LCNIYeZlVPq3xA5DUaHAQtlinDIItcMxQxHXjyQq2i1LgbfDmOq53mYDztAS INMA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MlJpHsfY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o15-20020a05622a044f00b003f68e9b05basi5305405qtx.334.2023.06.05.13.25.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:25:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MlJpHsfY; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GcW-0001pF-RS; Mon, 05 Jun 2023 16:16:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcU-0001o5-LN for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:02 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcS-0003nm-0A for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:02 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-650c8cb68aeso3084081b3a.3 for ; Mon, 05 Jun 2023 13:15:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996158; x=1688588158; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BNL16VFJ/JVKBYmioxTJxOZayJwkRUPqGfQWbKcHjhI=; b=MlJpHsfYfgxjVmgCYc8l1kVmR3TWflq7344LHL/KBgLsFrpNUijwPwSwehWfjr5BvR drbkr/MlchiPjiKZND+JTwB1t4Un6WkjjDJIE0K0oujFZdgdv/rhPZ7K9GLtD5qiPH7H 1J80Ge1iQJYOpqrAq11M+bYtTjv845z4ADrGoYHhJ1PZPj9/znGv8jT16bg4LS+SwhHA V0SnXYf34k3HMaELZdaY1il526cMDxuj+Vw3CapTLFTll1SemmYJrFAYnszP+iJ4WlXV bJMPBeEJMJcJYUlthIthlH7VnIquZI8NOQOLvCzVSplflPEKmQOJdqava266YisKGdTX pl3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996158; x=1688588158; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BNL16VFJ/JVKBYmioxTJxOZayJwkRUPqGfQWbKcHjhI=; b=GGhXDAc+QxDL4ha+eiGsa7zo+T0v4l4WmieQLk5X4pq5f17qCOpokeynAY5LWzQKph D+MGpM/WxBJEJ8qD+78vuBDzrs7wIa1pvcTGGX42Q0yLbS0lcswlth8zYz39FCTKRbGe ryGQSihLDur/QYL29Vlo8RobnQIzTOB2vmFqjQ8hg5Vi39i/mAmFMwUzEIrF8Sr8Kbbo 4okcvTunSbaKyk7O4haMIs878fMJ5QWfxb/QUeVlLW/XoMu2fhkMZk3xVHwhtnInuftA b08VRlHkxhuIHHMwP1K3QS47hWWe1pqLf2hj9tRq33ok6gJ34M2/n/2YAKF+BW1CExIc dscA== X-Gm-Message-State: AC+VfDxI8MrCkf+sWTdNmroIYOQ+FghTj/XLPgrFAhihk+jTqy/Wttlj a+QX7YrxyHH/HtqtblB4M4J3mxqZst+Kjfaq5u4= X-Received: by 2002:a05:6a00:198c:b0:64d:6a78:1575 with SMTP id d12-20020a056a00198c00b0064d6a781575mr591535pfl.30.1685996158481; Mon, 05 Jun 2023 13:15:58 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.15.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:15:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 09/52] target/*: Add missing includes of tcg/debug-assert.h Date: Mon, 5 Jun 2023 13:15:05 -0700 Message-Id: <20230605201548.1596865-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This had been pulled in from tcg/tcg.h, via exec/cpu_ldst.h, via exec/exec-all.h, but the include of tcg.h will be removed. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/avr/cpu.c | 1 + target/rx/cpu.c | 1 + target/rx/op_helper.c | 1 + target/tricore/cpu.c | 1 + 4 files changed, 4 insertions(+) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index a24c23c247..8f741f258c 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "cpu.h" #include "disas/dis-asm.h" +#include "tcg/debug-assert.h" static void avr_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 67452e310c..157e57da0f 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -24,6 +24,7 @@ #include "exec/exec-all.h" #include "hw/loader.h" #include "fpu/softfloat.h" +#include "tcg/debug-assert.h" static void rx_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c index acce650185..dc0092ca99 100644 --- a/target/rx/op_helper.c +++ b/target/rx/op_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "fpu/softfloat.h" +#include "tcg/debug-assert.h" static inline G_NORETURN void raise_exception(CPURXState *env, int index, diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index d0a9272961..7fa113fed2 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "qemu/error-report.h" +#include "tcg/debug-assert.h" static inline void set_feature(CPUTriCoreState *env, int feature) { From patchwork Mon Jun 5 20:15:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689238 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2286952wru; Mon, 5 Jun 2023 13:21:59 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7DNnvoxU8AxrvTwTZkON3WHKmmCCwxwvkjRdRxq9z2D6IJMvlW9V0VLDm+fILNF6j5GVmq X-Received: by 2002:a05:620a:47b1:b0:75d:872c:6d4 with SMTP id dt49-20020a05620a47b100b0075d872c06d4mr736833qkb.37.1685996518921; Mon, 05 Jun 2023 13:21:58 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996518; cv=none; d=google.com; s=arc-20160816; b=gkPoKsOGQAbAo3JInLn0fCwPiU8Dn/PJsphRqCOZqXlEGmyCdVAtNRhu0cGTEHNRHi I+dNGoaJqLCYAotRUTmZ6MFAS3SV6DaIb/qj1pt4IXuKsi8cCGaOi/N1pOCBvj35op9U wz4FmXIT8QKM5Ack4+mTkmKJ8GF1S8n+3L51wsmglk1/3f3rlnCDC2hQd9VvPc/C+fvp 26rd3+mSNAh3FZ8I/t1dCr80PpNk27AbbfKb6WYohMbdSOQR7n3OPSIutxRKjLKlDTA/ S0f+EIioO8+0W1zxMVP2stgBolWrhDUAjF46S7Fybgn98nQ3+NTpU5GJBQVX/LHnP/cH gAtw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=u/ikHj+R8q+414Kg3TRPRaaz9VV3CP4E0627qsrQV5k=; b=THxXmGqGFp7UySdKyNPnLgTFxHxl8jbHaECuC5sJhpbi45P/zmGqGPn/zw0ri2LWNz WcHeA4BID3noF6g9r9wsXId8Zz4Jm2KCXdy4AwV8P4jDQusqJkvO+PBh8R+TiHYhEft1 SwkCjCx/cHnMNMozOLmqb1fPRyv0RENfZuhvrAGK+f6NkwuBoen6Z2oEd18oDxJuUzvv GfjxWABfny6o6BaLPbKIIHriFmsRs3G/3soTDAqMnqUBymiiQpcj2pZqQlpdXl9G4X2a M9yjRSYcVLGHPBwovlu25wLT0OwKuT+lJYsmjNjPRRWSs6aUCUvW5pT4jb/qpbKWIruy z2Ag== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Gh2kk1x8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p8-20020a05620a132800b0075ebaf61ce1si1245349qkj.696.2023.06.05.13.21.58 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:21:58 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Gh2kk1x8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GcY-0001py-NJ; Mon, 05 Jun 2023 16:16:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcV-0001oU-Dr for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:03 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcT-0003oF-Nj for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:03 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-65540715b4bso1364647b3a.0 for ; Mon, 05 Jun 2023 13:16:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996159; x=1688588159; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=u/ikHj+R8q+414Kg3TRPRaaz9VV3CP4E0627qsrQV5k=; b=Gh2kk1x84/s4C334U/p2pidxHfGy9/FfIt1A0vOWQIWOXar0RGgaMe8uQ9dr/j+FzF okDmgEtbYmtvJdu9vt7d0U+IkWgDW4fht8hkCjeGGVK12k6jYt4r7XhWKyc7pLlCAqXP VpxOIpFQspe9RVEGDLf6wC2ylZ6reBsoB+E5c/hcN7ePIsFFqPE3pSStJuAdXTy/8HrS qgvNNQQ8jrdVFKXxU2zdlSyLVpzEeiGRz5VbJ7G5XZzt6Nf9EqVRfbe7rFbqPAiBHg2o 50GbnUyGinB3bJcGXN7BWqzwgm03vMVtZH/tY42L50EfXQj9KMZSN8+654NP9iBgZkOL gH0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996159; x=1688588159; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=u/ikHj+R8q+414Kg3TRPRaaz9VV3CP4E0627qsrQV5k=; b=S5A1+PPTOrap1nwaFPV7r2wA0MxEkkOBkZOCW8eQ/ufQim6Ee8YRWymba4WhAt1ZTx PZdbs4RPYFOIpQgf++KHBJisSO6V5FxHxBVGgSIqGsijhnuygl6hucBHfXBI2OB9s+7r j4QLboj8zQeNaUzhHp4wsW+WxGkmVZRnvKFEMlIcg7ZJtuNb9THrAxz9K3Shr3KmfgUs yJsJ4fhoazZw0hYvOm6uvWVknbt+EGFCxKbvZOzoyVkGoavYaMsg5dmHvvct6+lvLdCz FTeMzjPRc61/CoIm3wpedXc1ysc0Tubwij9AzIBpmOXHLSYVMLfFoBoyj3hlf6QEGOLs L7tA== X-Gm-Message-State: AC+VfDy1/D4A6EKqXyk5ZoYcdYgZaNiJMbrohj7D3TpMqUqq5R2i5dNb TAzslM9Zw3tJxKIteqLXKDYMy0H2bm9qODe0fR8= X-Received: by 2002:a05:6a00:194f:b0:658:e95b:256a with SMTP id s15-20020a056a00194f00b00658e95b256amr1020877pfk.1.1685996159410; Mon, 05 Jun 2023 13:15:59 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.15.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:15:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 10/52] *: Add missing includes of tcg/tcg.h Date: Mon, 5 Jun 2023 13:15:06 -0700 Message-Id: <20230605201548.1596865-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This had been pulled in from exec/cpu_ldst.h, via exec/exec-all.h, but the include of tcg.h will be removed. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- accel/tcg/monitor.c | 1 + accel/tcg/tcg-accel-ops-mttcg.c | 2 +- accel/tcg/tcg-accel-ops-rr.c | 2 +- target/i386/helper.c | 3 +++ target/openrisc/sys_helper.c | 1 + 5 files changed, 7 insertions(+), 2 deletions(-) diff --git a/accel/tcg/monitor.c b/accel/tcg/monitor.c index 92fce580f1..f171bc6f5e 100644 --- a/accel/tcg/monitor.c +++ b/accel/tcg/monitor.c @@ -15,6 +15,7 @@ #include "sysemu/cpus.h" #include "sysemu/cpu-timers.h" #include "sysemu/tcg.h" +#include "tcg/tcg.h" #include "internal.h" diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttcg.c index d50239e0e2..5d72c9b1bd 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -32,7 +32,7 @@ #include "qemu/guest-random.h" #include "exec/exec-all.h" #include "hw/boards.h" - +#include "tcg/tcg.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index b6d10fa9a2..70b9b89073 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -32,7 +32,7 @@ #include "qemu/notify.h" #include "qemu/guest-random.h" #include "exec/exec-all.h" - +#include "tcg/tcg.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-rr.h" #include "tcg-accel-ops-icount.h" diff --git a/target/i386/helper.c b/target/i386/helper.c index 8857444819..682d10d98a 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -28,6 +28,9 @@ #include "monitor/monitor.h" #endif #include "qemu/log.h" +#ifdef CONFIG_TCG +#include "tcg/tcg.h" +#endif void cpu_sync_avx_hflag(CPUX86State *env) { diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index ccdee3b8be..110f157601 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -26,6 +26,7 @@ #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #endif +#include "tcg/tcg.h" #define TO_SPR(group, number) (((group) << 11) + (number)) From patchwork Mon Jun 5 20:15:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689248 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2287973wru; Mon, 5 Jun 2023 13:25:18 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6pQgLShSPCoqAkwqZsc7NvtBsgNa3cJdQXp9rSYGpIJHr0+ifvpA1HP9NHPFhNVAOTOBoi X-Received: by 2002:a05:620a:2202:b0:75e:bf97:677 with SMTP id m2-20020a05620a220200b0075ebf970677mr866518qkh.43.1685996717824; Mon, 05 Jun 2023 13:25:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996717; cv=none; d=google.com; s=arc-20160816; b=Uf5gqBIg5+QIvrH6DoB09HaeVSgQydckmQ3i7orlToW3f04uu/n30Cog7NxSZRqUe7 lQrgbBtPcC+4YCfCjSWWdodbg9z7RiivqOJNWTAZOqTPFy1BBJp4bF9X2qDjS/U1ldFh ZFDnh34qqyeAaXHFnXTOzXiriYzZbdMrX2l6KZ+PlQhTsIWHuYJJjC4HH4QPiYQMHUrH Z9MNpn9sp9l+srT8llYzOhhpNLdXw6u/rSyTkx5+vNqCAYRRlHMGuSnX4KiCbcTiWMZf ndP7mqpPBbqEndWMrIQ4thgIlnrtxQNG4xLX4VOgHxgmQnTzpadvNXs84BoEaZJDq1SV KEQA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Nm3vurP4nrIBPcuYZqIJNG8548lhbs4a/90KI8HFUTo=; b=lm7/mqmZg2AMrJQZKoWdRRXm7TWedbDIWX0HpYs8EWlPkldq0CD4476BtY1NOqOzk5 szum1Xm23TXlmHxRQB49dkf77tHIP4DV+XzHu+qxea2yZ3GQvW8jTXg9aMDeY5Cl1X6k +QfjgoYpn2Odj86QHHyrLl90kjjv8zCkcjT3NzKE6ZQ8J9YRBJJhp6GagFJewmRw5kgH 9NqqLxicscFXm69x7QgQDqd2oMbfbnwzlNAGV/SPqszD+juteq0sryon3phz/ROzN3EM Dvcpsqy80dSDc+O0WLQwOTehqL3Nhq2cbVfeq5cak9BedFu2krIE78ajuL+V18XYAn6E GJbg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lrgphcoy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m10-20020ae9f20a000000b0075b284b9c79si4876666qkg.642.2023.06.05.13.25.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:25:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Lrgphcoy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GcY-0001pv-Jq; Mon, 05 Jun 2023 16:16:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcW-0001ov-Eq for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:04 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcT-0003qB-Rs for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:03 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-652328c18d5so2567579b3a.1 for ; Mon, 05 Jun 2023 13:16:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996160; x=1688588160; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Nm3vurP4nrIBPcuYZqIJNG8548lhbs4a/90KI8HFUTo=; b=LrgphcoyA2y7vmQjPdbTgLkGDbL3wW5P3wNGMQFoysy5VI2d/BvubXsXtMagDVTeEd mbfmryQp1hJ6QYJ1jRDDBVeVlUMyEWF06/fG8rdhIFLraQqzgyPQZYmUeybnI1leir8v uC+1pujg9/GrrTHa1BcGIYdE3ngCftt9o6uFU2doFuUXy1vtBsBKssJwRDqf1JuseqhI QrAH485F12/1F0esA0a+pVj6Gt195FMMq1Je2l+04k3VHnZ3fyKklwsdkPOiIu8HW/f+ HAUeOMseIGAF5YsCn7jwuvQJOhPzfXZcDudTTuie3AV+cpAzL7j0TmbsQDdDXXXpaY6Y 5Ujw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996160; x=1688588160; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nm3vurP4nrIBPcuYZqIJNG8548lhbs4a/90KI8HFUTo=; b=Mu4Y/jZjsWBJxDMwDmhmXnCeZj9nfMnOYF+vTk96RxUWrugEvrTCuEDls6ND5SXnFb 9K0Qf9/Erbcxu1wgvPAxAcBLVufPuLbWWzCdrCKFLbO4BuHRRnS6U1RAL4zunanhB2BY XXcAlg2LL2RQtlpjU5iOQQJ2cGHwlMqlKv1XNbDjXMfMW267F1DH66YFZF9k9I3RYROF iYrYkCM0t3PNAqRIM87bbBfL9Jq1m20M3CMYwxsZeuoUoMdHtYk3TY5n2bUWgJ4A1uGH yY+tPjO4gYmyxb3AFg472keLjGcAelYaEvmssL57RlKKMy54ZCwHIL2Q4ovAc9siINvU q9wA== X-Gm-Message-State: AC+VfDxaNV6X7ZuhijUDwnR/Na1Nm7sjp3s82vj5cXwnYeHeYPvGpEtL kVEJQEm3FPphlTDHhk1XRRBGgISRqlPx69TYVj0= X-Received: by 2002:a05:6a00:1346:b0:659:ab2d:71e7 with SMTP id k6-20020a056a00134600b00659ab2d71e7mr910801pfu.3.1685996160328; Mon, 05 Jun 2023 13:16:00 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.15.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:15:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 11/52] tcg: Split out tcg-target-reg-bits.h Date: Mon, 5 Jun 2023 13:15:07 -0700 Message-Id: <20230605201548.1596865-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Often, the only thing we need to know about the TCG host is the register size. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 12 +----------- tcg/aarch64/tcg-target-reg-bits.h | 12 ++++++++++++ tcg/arm/tcg-target-reg-bits.h | 12 ++++++++++++ tcg/i386/tcg-target-reg-bits.h | 16 ++++++++++++++++ tcg/i386/tcg-target.h | 2 -- tcg/loongarch64/tcg-target-reg-bits.h | 21 +++++++++++++++++++++ tcg/loongarch64/tcg-target.h | 11 ----------- tcg/mips/tcg-target-reg-bits.h | 18 ++++++++++++++++++ tcg/mips/tcg-target.h | 8 -------- tcg/ppc/tcg-target-reg-bits.h | 16 ++++++++++++++++ tcg/ppc/tcg-target.h | 5 ----- tcg/riscv/tcg-target-reg-bits.h | 19 +++++++++++++++++++ tcg/riscv/tcg-target.h | 9 --------- tcg/s390x/tcg-target-reg-bits.h | 17 +++++++++++++++++ tcg/sparc64/tcg-target-reg-bits.h | 12 ++++++++++++ tcg/tci/tcg-target-reg-bits.h | 18 ++++++++++++++++++ tcg/tci/tcg-target.h | 8 -------- tcg/s390x/tcg-target.c.inc | 5 ----- 18 files changed, 162 insertions(+), 59 deletions(-) create mode 100644 tcg/aarch64/tcg-target-reg-bits.h create mode 100644 tcg/arm/tcg-target-reg-bits.h create mode 100644 tcg/i386/tcg-target-reg-bits.h create mode 100644 tcg/loongarch64/tcg-target-reg-bits.h create mode 100644 tcg/mips/tcg-target-reg-bits.h create mode 100644 tcg/ppc/tcg-target-reg-bits.h create mode 100644 tcg/riscv/tcg-target-reg-bits.h create mode 100644 tcg/s390x/tcg-target-reg-bits.h create mode 100644 tcg/sparc64/tcg-target-reg-bits.h create mode 100644 tcg/tci/tcg-target-reg-bits.h diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 54f260a66b..5fe90cbb42 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -32,6 +32,7 @@ #include "qemu/plugin.h" #include "qemu/queue.h" #include "tcg/tcg-mo.h" +#include "tcg-target-reg-bits.h" #include "tcg-target.h" #include "tcg/tcg-cond.h" #include "tcg/debug-assert.h" @@ -44,17 +45,6 @@ #define CPU_TEMP_BUF_NLONGS 128 #define TCG_STATIC_FRAME_SIZE (CPU_TEMP_BUF_NLONGS * sizeof(long)) -/* Default target word size to pointer size. */ -#ifndef TCG_TARGET_REG_BITS -# if UINTPTR_MAX == UINT32_MAX -# define TCG_TARGET_REG_BITS 32 -# elif UINTPTR_MAX == UINT64_MAX -# define TCG_TARGET_REG_BITS 64 -# else -# error Unknown pointer size for tcg target -# endif -#endif - #if TCG_TARGET_REG_BITS == 32 typedef int32_t tcg_target_long; typedef uint32_t tcg_target_ulong; diff --git a/tcg/aarch64/tcg-target-reg-bits.h b/tcg/aarch64/tcg-target-reg-bits.h new file mode 100644 index 0000000000..3b57a1aafb --- /dev/null +++ b/tcg/aarch64/tcg-target-reg-bits.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Define target-specific register size + * Copyright (c) 2023 Linaro + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#define TCG_TARGET_REG_BITS 64 + +#endif diff --git a/tcg/arm/tcg-target-reg-bits.h b/tcg/arm/tcg-target-reg-bits.h new file mode 100644 index 0000000000..23b7730a8d --- /dev/null +++ b/tcg/arm/tcg-target-reg-bits.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2023 Linaro + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#define TCG_TARGET_REG_BITS 32 + +#endif diff --git a/tcg/i386/tcg-target-reg-bits.h b/tcg/i386/tcg-target-reg-bits.h new file mode 100644 index 0000000000..aa386050eb --- /dev/null +++ b/tcg/i386/tcg-target-reg-bits.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2008 Fabrice Bellard + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#ifdef __x86_64__ +# define TCG_TARGET_REG_BITS 64 +#else +# define TCG_TARGET_REG_BITS 32 +#endif + +#endif diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 1468f8ef25..2a2e3fffa8 100644 --- a/tcg/i386/tcg-target.h +++ b/tcg/i386/tcg-target.h @@ -30,11 +30,9 @@ #define TCG_TARGET_INSN_UNIT_SIZE 1 #ifdef __x86_64__ -# define TCG_TARGET_REG_BITS 64 # define TCG_TARGET_NB_REGS 32 # define MAX_CODE_GEN_BUFFER_SIZE (2 * GiB) #else -# define TCG_TARGET_REG_BITS 32 # define TCG_TARGET_NB_REGS 24 # define MAX_CODE_GEN_BUFFER_SIZE UINT32_MAX #endif diff --git a/tcg/loongarch64/tcg-target-reg-bits.h b/tcg/loongarch64/tcg-target-reg-bits.h new file mode 100644 index 0000000000..51373ad70a --- /dev/null +++ b/tcg/loongarch64/tcg-target-reg-bits.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2021 WANG Xuerui + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +/* + * Loongson removed the (incomplete) 32-bit support from kernel and toolchain + * for the initial upstreaming of this architecture, so don't bother and just + * support the LP64* ABI for now. + */ +#if defined(__loongarch64) +# define TCG_TARGET_REG_BITS 64 +#else +# error unsupported LoongArch register size +#endif + +#endif diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h index 482901ac15..26f1aab780 100644 --- a/tcg/loongarch64/tcg-target.h +++ b/tcg/loongarch64/tcg-target.h @@ -29,17 +29,6 @@ #ifndef LOONGARCH_TCG_TARGET_H #define LOONGARCH_TCG_TARGET_H -/* - * Loongson removed the (incomplete) 32-bit support from kernel and toolchain - * for the initial upstreaming of this architecture, so don't bother and just - * support the LP64* ABI for now. - */ -#if defined(__loongarch64) -# define TCG_TARGET_REG_BITS 64 -#else -# error unsupported LoongArch register size -#endif - #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_NB_REGS 32 diff --git a/tcg/mips/tcg-target-reg-bits.h b/tcg/mips/tcg-target-reg-bits.h new file mode 100644 index 0000000000..56fe0a725e --- /dev/null +++ b/tcg/mips/tcg-target-reg-bits.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2008-2009 Arnaud Patard + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#if _MIPS_SIM == _ABIO32 +# define TCG_TARGET_REG_BITS 32 +#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 +# define TCG_TARGET_REG_BITS 64 +#else +# error "Unknown ABI" +#endif + +#endif diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h index e4806f6ff5..dd2efa795c 100644 --- a/tcg/mips/tcg-target.h +++ b/tcg/mips/tcg-target.h @@ -27,14 +27,6 @@ #ifndef MIPS_TCG_TARGET_H #define MIPS_TCG_TARGET_H -#if _MIPS_SIM == _ABIO32 -# define TCG_TARGET_REG_BITS 32 -#elif _MIPS_SIM == _ABIN32 || _MIPS_SIM == _ABI64 -# define TCG_TARGET_REG_BITS 64 -#else -# error "Unknown ABI" -#endif - #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_NB_REGS 32 diff --git a/tcg/ppc/tcg-target-reg-bits.h b/tcg/ppc/tcg-target-reg-bits.h new file mode 100644 index 0000000000..0efa80e7e0 --- /dev/null +++ b/tcg/ppc/tcg-target-reg-bits.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2008 Fabrice Bellard + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#ifdef _ARCH_PPC64 +# define TCG_TARGET_REG_BITS 64 +#else +# define TCG_TARGET_REG_BITS 32 +#endif + +#endif diff --git a/tcg/ppc/tcg-target.h b/tcg/ppc/tcg-target.h index 40f20b0c1a..c7552b6391 100644 --- a/tcg/ppc/tcg-target.h +++ b/tcg/ppc/tcg-target.h @@ -25,11 +25,6 @@ #ifndef PPC_TCG_TARGET_H #define PPC_TCG_TARGET_H -#ifdef _ARCH_PPC64 -# define TCG_TARGET_REG_BITS 64 -#else -# define TCG_TARGET_REG_BITS 32 -#endif #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) #define TCG_TARGET_NB_REGS 64 diff --git a/tcg/riscv/tcg-target-reg-bits.h b/tcg/riscv/tcg-target-reg-bits.h new file mode 100644 index 0000000000..761ca0d774 --- /dev/null +++ b/tcg/riscv/tcg-target-reg-bits.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2018 SiFive, Inc + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +/* + * We don't support oversize guests. + * Since we will only build tcg once, this in turn requires a 64-bit host. + */ +#if __riscv_xlen != 64 +#error "unsupported code generation mode" +#endif +#define TCG_TARGET_REG_BITS 64 + +#endif diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h index 54fdff0caa..e1d8110ee4 100644 --- a/tcg/riscv/tcg-target.h +++ b/tcg/riscv/tcg-target.h @@ -25,15 +25,6 @@ #ifndef RISCV_TCG_TARGET_H #define RISCV_TCG_TARGET_H -/* - * We don't support oversize guests. - * Since we will only build tcg once, this in turn requires a 64-bit host. - */ -#if __riscv_xlen != 64 -#error "unsupported code generation mode" -#endif -#define TCG_TARGET_REG_BITS 64 - #define TCG_TARGET_INSN_UNIT_SIZE 4 #define TCG_TARGET_NB_REGS 32 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) diff --git a/tcg/s390x/tcg-target-reg-bits.h b/tcg/s390x/tcg-target-reg-bits.h new file mode 100644 index 0000000000..b01414e09d --- /dev/null +++ b/tcg/s390x/tcg-target-reg-bits.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2009 Ulrich Hecht + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +/* We only support generating code for 64-bit mode. */ +#if UINTPTR_MAX == UINT64_MAX +# define TCG_TARGET_REG_BITS 64 +#else +# error "unsupported code generation mode" +#endif + +#endif diff --git a/tcg/sparc64/tcg-target-reg-bits.h b/tcg/sparc64/tcg-target-reg-bits.h new file mode 100644 index 0000000000..34a6711013 --- /dev/null +++ b/tcg/sparc64/tcg-target-reg-bits.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2023 Linaro + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#define TCG_TARGET_REG_BITS 64 + +#endif diff --git a/tcg/tci/tcg-target-reg-bits.h b/tcg/tci/tcg-target-reg-bits.h new file mode 100644 index 0000000000..dcb1a203f8 --- /dev/null +++ b/tcg/tci/tcg-target-reg-bits.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define target-specific register size + * Copyright (c) 2009, 2011 Stefan Weil + */ + +#ifndef TCG_TARGET_REG_BITS_H +#define TCG_TARGET_REG_BITS_H + +#if UINTPTR_MAX == UINT32_MAX +# define TCG_TARGET_REG_BITS 32 +#elif UINTPTR_MAX == UINT64_MAX +# define TCG_TARGET_REG_BITS 64 +#else +# error Unknown pointer size for tci target +#endif + +#endif diff --git a/tcg/tci/tcg-target.h b/tcg/tci/tcg-target.h index 60a6ed65ce..37ee10c959 100644 --- a/tcg/tci/tcg-target.h +++ b/tcg/tci/tcg-target.h @@ -44,14 +44,6 @@ #define TCG_TARGET_INSN_UNIT_SIZE 4 #define MAX_CODE_GEN_BUFFER_SIZE ((size_t)-1) -#if UINTPTR_MAX == UINT32_MAX -# define TCG_TARGET_REG_BITS 32 -#elif UINTPTR_MAX == UINT64_MAX -# define TCG_TARGET_REG_BITS 64 -#else -# error Unknown pointer size for tci target -#endif - /* Optional instructions. */ #define TCG_TARGET_HAS_bswap16_i32 1 diff --git a/tcg/s390x/tcg-target.c.inc b/tcg/s390x/tcg-target.c.inc index aeddebbb5c..a878acd8ca 100644 --- a/tcg/s390x/tcg-target.c.inc +++ b/tcg/s390x/tcg-target.c.inc @@ -24,11 +24,6 @@ * THE SOFTWARE. */ -/* We only support generating code for 64-bit mode. */ -#if TCG_TARGET_REG_BITS != 64 -#error "unsupported code generation mode" -#endif - #include "../tcg-ldst.c.inc" #include "../tcg-pool.c.inc" #include "elf.h" From patchwork Mon Jun 5 20:15:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689252 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288221wru; Mon, 5 Jun 2023 13:26:00 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ68lBVZjaAAwEoLrWsjVeUEmiHMbqn3J9yVJ+QmcFzac3JC9o6jTXMpB9dJ3ky77IsRBAUP X-Received: by 2002:a05:620a:2201:b0:75d:a13:ae74 with SMTP id m1-20020a05620a220100b0075d0a13ae74mr688642qkh.36.1685996760689; Mon, 05 Jun 2023 13:26:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996760; cv=none; d=google.com; s=arc-20160816; b=AlX/K8TdSoGeED7thVlHTTmm4wm5OCAQ+X8ZCY4ZYJWqCOMLoH4P66hlIKNH4BEHpe Jn6opxDcExYzr1VrKYUvB7Ppn+E9XE+S1ZFws3Azi849d7Y9U25f6InjZLvUCVJ3U1b0 6ftwqPKjz1xaj0DeNV3+q5XmuIVYTAtnaYGKwCoEWUy0Empv/Uk2A62shyiBvqpq/N/+ IcJSCd1Yu/d5Or2okQF2SAcfzjy0orsxCTtPeq99XSQXawO77STLLik1StiE6ZPQNPkS 3PiaM3l1Mw9mYYbQhmCCrp6r2XFdWDhk69Vw/0CKoETQ9IpHxFw9tv79Fki5Xl0Zs+eA 7CIw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=vLSnH2FNmWoBPe6jdA7O8wsGiKQZYAPPgH74uYmHViE=; b=nnqNhzXTSM103FC71DODNruH/pDJ4xVlUAhCK0mFOD5MDBvcM78L2icNuTU1qv4cyv 3StXLuIHUUhRG0a5aC5sJNmXwoqm/GMf5gQ5LqWz0BcZvTih3q+efatw9aSghEEGrXJn kh4ExU5F6pTuKlb2d1Vck1OJDkWndu6DMewSKY8ggfAsJmHvUWiPD1XOlQoeuTpggkcE L+HNpnH8s30AGpmemqXmwgmEkgDSU5LyNQ+mA3Av2AIFgd2hT07SMXwZEkL6qVPcIkO3 EtDsUNkrlajyRZrM+nOu1TwzDNgYQAFVpzG62m0Um562a6ueziHXGiya6idPcD1lmvdI i79Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E5V9CD4D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p15-20020ae9f30f000000b0075b39115540si5050360qkg.502.2023.06.05.13.26.00 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:26:00 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=E5V9CD4D; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GcZ-0001r2-Bi; Mon, 05 Jun 2023 16:16:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcW-0001ow-Ev for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:04 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcU-0003qn-MF for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:04 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-65242634690so2955330b3a.0 for ; Mon, 05 Jun 2023 13:16:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996161; x=1688588161; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=vLSnH2FNmWoBPe6jdA7O8wsGiKQZYAPPgH74uYmHViE=; b=E5V9CD4D03iGQukTZwCsLGw1uJlAaQh4hd+eZIJn9TIBaDGcoEtv219H7I29YNU8yv ZFAI9xsZ/tkZugGu+3uvfTOOCciZfhupn0zEmiwcjvZJuDjXqFCQ4glPfHi4LFffWmo6 MQbLb+eiMWisEmDFrnOrTczwQCNkJn2ShAYHEa55Fg+NK9+sl0iMDIRh0SAdLaZo96qB uAWR1lZaQn/IHSKL/1eD8aAUKY/mHZtR6dbNlse0flu/C76KNMMGz3rnLDZRkQ7G4zkj gOV3cjQ0XuyvzYRjS+VE2FAwbjsFAezrvU2/bPV4gSvVvZUlgn6Q6Jpdi2x/CXz6jIAB pQew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996161; x=1688588161; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vLSnH2FNmWoBPe6jdA7O8wsGiKQZYAPPgH74uYmHViE=; b=XH7H77MjBHXT4kGkgY2gjSvzdkyTTApPwkiUqCszEnnQzMJsRfoBFm1bexFfsnp2K2 S1RmskpBegetKQg8ACzurGReciVzN36vkfi8Ef8dCX6fIZeSbvwAYgtonAx7k/FxzROd hsyNbe83MjVBqVlmJX4mLwi/L0zEctvwePF4A2UBQdXWN1W3syWhhXSsQFIHSyPkiLeA JRiUfCfL46VjTfwWNdDhFfEJWaRKEGo4CBoNUHg9erS3epAcXBk4o1vmZfXuvSEmuq7R vQHBNp+iBQVerolSGPIzcfIbN+OtXcQgx8o2Y9kd6hTGMQ33Ecy+Hh08pBJYk7MweK23 jj2Q== X-Gm-Message-State: AC+VfDxMN1TIQQjq6VftAQMLA6p67xynDh0C49DoTGf21nQTAkAc1wfV e+ZJggM0aSilYZS3ajjMdNZRLWjIZ/VBS+c/64U= X-Received: by 2002:a05:6a20:244b:b0:112:cf5:d5fb with SMTP id t11-20020a056a20244b00b001120cf5d5fbmr51194pzc.50.1685996161130; Mon, 05 Jun 2023 13:16:01 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 12/52] target/arm: Fix test of TCG_OVERSIZED_GUEST Date: Mon, 5 Jun 2023 13:15:08 -0700 Message-Id: <20230605201548.1596865-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The symbol is always defined, even if to 0. We wanted to test for TCG_OVERSIZED_GUEST == 0. This fixed, the #error is reached while building arm-softmmu, because TCG_OVERSIZED_GUEST is not true (nor supposed to be true) for arm32 guest on a 32-bit host. But that's ok, because this feature doesn't apply to arm32. Add an #ifdef for TARGET_AARCH64. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/ptw.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 69c05cd9da..b0d2a05403 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -418,6 +418,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, uint64_t new_val, S1Translate *ptw, ARMMMUFaultInfo *fi) { +#ifdef TARGET_AARCH64 uint64_t cur_val; void *host = ptw->out_host; @@ -473,7 +474,7 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, * we know that TCG_OVERSIZED_GUEST is set, which means that we are * running in round-robin mode and could only race with dma i/o. */ -#ifndef TCG_OVERSIZED_GUEST +#if !TCG_OVERSIZED_GUEST # error "Unexpected configuration" #endif bool locked = qemu_mutex_iothread_locked(); @@ -497,6 +498,10 @@ static uint64_t arm_casq_ptw(CPUARMState *env, uint64_t old_val, #endif return cur_val; +#else + /* AArch32 does not have FEAT_HADFS. */ + g_assert_not_reached(); +#endif } static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, From patchwork Mon Jun 5 20:15:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689232 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2285765wru; Mon, 5 Jun 2023 13:18:25 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ531SYP4877PPGAgHmGd8S96AlRp/9bzU9E3JZPAkOXcR/l9pUagWVjdfL9sdg5yplvcb2D X-Received: by 2002:a05:620a:19a1:b0:75d:4a80:68a1 with SMTP id bm33-20020a05620a19a100b0075d4a8068a1mr1023014qkb.22.1685996305255; Mon, 05 Jun 2023 13:18:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996305; cv=none; d=google.com; s=arc-20160816; b=ClZiteaYHx4xMNR78yt4t2sQUtm32N9JmVfP+w10NphMsgqotx36yC2VSTIdPQFEfM EZnu9Ebs3td+hXdAMxeSkWidx3ER0iOPDmgPTCUeEvkfGkP1zIFrpbR/cTciGheNCyZA 9qv4pwDWnWftlCBjt5ul0bIliM4cKS145QvQEiQxIwTZ2F546X+hMTU6wF0Jnc4PC+JF 1ULWhgDVBPhiyT/Nknvs+OplZBuYaBoIN796DPLdmT/t/we+g3eUK1AP2Z7t2saOZv2Q piXsKIS9MbqWKA1sqiCIRB09jJBKihqv/myaHFswBoKnt836MELYrpbR7shdFCS0zlkk S9Lg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ebG/JBGVQUzhkBt/ZqcczxWo6SU1DNkNqSEwarGUTCU=; b=RkCtEWbpTKKm4r56ZDma5HyvkdOrZz+0sQ1Hw9whPpSmJQfxsPXOnph/AnIHXPgI8C /R+ktAXkmSnXF/ksDoVXfgp0v9mnT/hJlSzeEgf6MqmzkB70WzAtEs5f/aceBBpNAwev Hzmu5wsNoLDy/IOJcA6UCH7f3P0Yn+ifMTchOF8GlWwd7i8jerEWY+5dPe7bf1M4tui0 7f8WGx1pbL+McDmlI+ECFOIFEMYqiyp0KJR+oQwvVUOOsS3HzxE1b8vSvpj/rmGrIIuj nZPgavMsoHjh+T6Q0YgkwsZH7UkRiXRnvkP9eMpMPITLSmJ7LzarAk6wG1PS4Fp0WQpR Iciw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VUcR2ytQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id u24-20020a05620a121800b0075eba0ba2ecsi1365705qkj.765.2023.06.05.13.18.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:18:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VUcR2ytQ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gcb-0001rB-0A; Mon, 05 Jun 2023 16:16:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcX-0001pg-It for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:05 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcV-0003ri-Hc for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:05 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-650c89c7e4fso5357362b3a.0 for ; Mon, 05 Jun 2023 13:16:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996162; x=1688588162; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ebG/JBGVQUzhkBt/ZqcczxWo6SU1DNkNqSEwarGUTCU=; b=VUcR2ytQlFmX9xl9zbseIZXL9gskOt6wYo4EcqPyKesph+tmkR5EYKqiai7hvbqUJV ekC0RQ2HzKvBIGK+dRySezM8r7wRhlh9q6v/dNfaMJRVGVmpWBcaSkl41xBtbiSorHZm m+jJTvIozLyL706b37s6PvRYqBgknmdiHbBwfQ2x1wazoilUxfBMUXlDP15F57sjG53q 6c3aKtZPUdJcI/T/y+/uJjW7tKnTjyOmSzIP4o4BfWtsJ1YN9qDGYmnuXbxUJ4LJB9no ovul8fn+tVMqQYIqHNH7107LOvmw+/2Wj/f21uUzlwDmG0mEcAoea8AAwVeL5W8aPgwq Ig1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996162; x=1688588162; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ebG/JBGVQUzhkBt/ZqcczxWo6SU1DNkNqSEwarGUTCU=; b=FUqp+IuSPX5FnLeolKMXCx6FyAeh3nF7bHNKLyutgSOdlUS3gTFwRF0vBuMR3hnZZ0 NopTNW+sTXp4Leq4mGczLFi+ATkqLcvrgkBexWaH4wdW22sdIB8x8nTCA8M2Q86id0m9 rr7pVU5Fysb7qi/1c3FKZUq5BA34YCto/BXaUTIQSwMHMNXVDPRdBsChlZQ5GibQ7VyI 3CGb3IJVIWwvYLGqLJ4wQTwdK9VJfUFzgS/ErsAxTSCanRy6rjOQiLYvBFEa2+HKFrsr zMoCUOgk5kfiXWlzxUCk/sJCwUlx9mffUhfIGzIwq7M5PmutSCQT04USYt/UATy600U+ iW6g== X-Gm-Message-State: AC+VfDwusSbxYpkm7ZnPKFjmcFiGnHPSKEuEJ53Ey8KfNY38HKuHwUOW SYLhSowNsF0jANxoc0Sq/8VWHKuLY+vgWYMBQIU= X-Received: by 2002:aa7:8884:0:b0:64c:4f2f:a235 with SMTP id z4-20020aa78884000000b0064c4f2fa235mr910102pfe.30.1685996161899; Mon, 05 Jun 2023 13:16:01 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 13/52] tcg: Split out tcg/oversized-guest.h Date: Mon, 5 Jun 2023 13:15:09 -0700 Message-Id: <20230605201548.1596865-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move a use of TARGET_LONG_BITS out of tcg/tcg.h. Include the new file only where required. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/cpu_ldst.h | 3 +-- include/tcg/oversized-guest.h | 23 +++++++++++++++++++++++ include/tcg/tcg.h | 9 --------- accel/tcg/cputlb.c | 1 + accel/tcg/tcg-all.c | 1 + target/arm/ptw.c | 1 + target/riscv/cpu_helper.c | 1 + 7 files changed, 28 insertions(+), 11 deletions(-) create mode 100644 include/tcg/oversized-guest.h diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index a43b34e46b..896f305ff3 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -326,8 +326,7 @@ static inline void clear_helper_retaddr(void) #else -/* Needed for TCG_OVERSIZED_GUEST */ -#include "tcg/tcg.h" +#include "tcg/oversized-guest.h" static inline target_ulong tlb_read_idx(const CPUTLBEntry *entry, MMUAccessType access_type) diff --git a/include/tcg/oversized-guest.h b/include/tcg/oversized-guest.h new file mode 100644 index 0000000000..641b9749ff --- /dev/null +++ b/include/tcg/oversized-guest.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define TCG_OVERSIZED_GUEST + * Copyright (c) 2008 Fabrice Bellard + */ + +#ifndef EXEC_TCG_OVERSIZED_GUEST_H +#define EXEC_TCG_OVERSIZED_GUEST_H + +#include "tcg-target-reg-bits.h" +#include "cpu-param.h" + +/* + * Oversized TCG guests make things like MTTCG hard + * as we can't use atomics for cputlb updates. + */ +#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS +#define TCG_OVERSIZED_GUEST 1 +#else +#define TCG_OVERSIZED_GUEST 0 +#endif + +#endif diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 5fe90cbb42..021fc903ad 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -59,15 +59,6 @@ typedef uint64_t tcg_target_ulong; #error unsupported #endif -/* Oversized TCG guests make things like MTTCG hard - * as we can't use atomics for cputlb updates. - */ -#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS -#define TCG_OVERSIZED_GUEST 1 -#else -#define TCG_OVERSIZED_GUEST 0 -#endif - #if TCG_TARGET_NB_REGS <= 32 typedef uint32_t TCGRegSet; #elif TCG_TARGET_NB_REGS <= 64 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 6beaeb0a81..32a4817139 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -40,6 +40,7 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" +#include "tcg/oversized-guest.h" #include "exec/helper-proto.h" /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ diff --git a/accel/tcg/tcg-all.c b/accel/tcg/tcg-all.c index a831f8d7c3..02af6a2891 100644 --- a/accel/tcg/tcg-all.c +++ b/accel/tcg/tcg-all.c @@ -28,6 +28,7 @@ #include "exec/replay-core.h" #include "sysemu/cpu-timers.h" #include "tcg/tcg.h" +#include "tcg/oversized-guest.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/accel.h" diff --git a/target/arm/ptw.c b/target/arm/ptw.c index b0d2a05403..b2dc223525 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -14,6 +14,7 @@ #include "cpu.h" #include "internals.h" #include "idau.h" +#include "tcg/oversized-guest.h" typedef struct S1Translate { diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 57d04385f1..56381aaf26 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -31,6 +31,7 @@ #include "sysemu/cpu-timers.h" #include "cpu_bits.h" #include "debug.h" +#include "tcg/oversized-guest.h" int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) { From patchwork Mon Jun 5 20:15:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689240 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2287081wru; Mon, 5 Jun 2023 13:22:25 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7JBCd+OlTofLRV+ToopLAeyrCwLTCDjrp3p2Ft4XW5Er/HR49Te7aCy3gU40rQO1p7+mNw X-Received: by 2002:a05:620a:22b4:b0:75d:4d78:e130 with SMTP id p20-20020a05620a22b400b0075d4d78e130mr741898qkh.36.1685996545148; Mon, 05 Jun 2023 13:22:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996545; cv=none; d=google.com; s=arc-20160816; b=VK0nWaIKl0jCruamNUBYs9okmUYtydliH1k09Jyw33KFcNlQLJnbEr5eg5lDXt7SLy YdVwJ7XTGSLsveswUWDy7NzugS/faaJoHLDiH/U02gZUSe/7Po3xTjTJ39FA0ynX6gZW 34YwKc8oXxEgpLqWDoyQ5SfGjyd7EYOH/lzaVdXD09WkaxajTOkkY+BjMrvB3lXAk7dC Ss/yIw3eTzQO2NAdC5F2IVsesIcCmuN4sSfDw13anxerVBMvVyMYDJ9SuaYnvD15quhH tKbnGkTV7DDnh3sCLC3F7jRBsDgfo0C4HoiFIK4DcBoQCd3OOSjI0S4jRcEb69/NHKJ0 xaug== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DtX1Xou+g8BHGzx+Q/lku+gaQZV4Vw8c6hAcrxfkg1o=; b=OustvveDIMRTYkkydHl9wo6WVpBIqJKfhgnSymVGMiMUeQfLTdV41iS7PHle1mTsS9 pZ4To9QtJqwNm3bbRvUoGKSl6oHmCzN2LpQzKp+i8ISoRgNwQUxkUQh2YbtSM4a7Hsxx 1h6xVYnFfh+9lVddWcsk3S4TQXA6FVp0daHaRudEyoMXNIyrslgMpRKZXp3WOolB7gj5 M+3kGqJTTOoEIk726fwb9l4EJKchQGWtW0ouZKmm+yAsTbyPwRmVzjta9g3Xvk4oZL0U 1YYlhG7uObWRsLH+t/S2/dMFwIzj/13W7Ac6vU6gz77KW2lS5MWQzREx9mf5rWXTDTB/ qXQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=izjz76ll; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id t27-20020a05620a005b00b007577c68be3dsi477224qkt.246.2023.06.05.13.22.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:22:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=izjz76ll; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gca-0001rA-0A; Mon, 05 Jun 2023 16:16:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6GcZ-0001qc-3b for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:07 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcW-0003sa-9b for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:06 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-65311774e52so1935107b3a.3 for ; Mon, 05 Jun 2023 13:16:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996163; x=1688588163; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DtX1Xou+g8BHGzx+Q/lku+gaQZV4Vw8c6hAcrxfkg1o=; b=izjz76llhWMubddICX+pREPbwqivkgBpvwzb9J3kBAYX183S4u8jbK8GcOQ2cvo+hK h3BKWeYSwGFDHX/0x1Au4HajpXLv07PGNnthUFj2pg/NqKBs+Zeuoy8qPMPu4SWloPoR yeL+Vb+w9d5brXc7+5H+DLrBVOug4pP8WZ+5DW55f4slK7RzNXD0UkMPJvj0BNvIJfDN 067+ZDMMe6cHE7h686wCfOGdKdUo9ouHDznfmS/yOeQ7fRvXzWUBLpiL3zu7kT1bkY6q B7umvrnruUq6Mn6C9NplKTsutr/Je3zzNDfd4Hi60CEmULGGAOuH+xCOAqWJts+Brx86 EFIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996163; x=1688588163; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DtX1Xou+g8BHGzx+Q/lku+gaQZV4Vw8c6hAcrxfkg1o=; b=UNMcMzyB9c+GYRYUPAk1un7M0LdgsrtpvfOZ9FIG6PAjp6PJ9afj5dO3chKI+4EvwO 0wUb+FKB4eJnqsWtNCc7Q6qeUl877cV8blNFrlAVlAfR564IMdffs44KX+L+T+2qBGwF bEAdME9fLjm2hUHpgMqX1P+S5wsj3+XVqn+LYqnt9YfFicYJNTgk/MZAmNLFHNMU0s3u 1PYQVxZAv8a8km/XPwWCAuNm9GQwHswboOWJxvyrUdt5sZjWKTIuzZxvdyBYYAQsas25 fP0+mEV3uPACb7fJxknkemL/irsZj+JL01w8e/G0oISR8O/vhFAbUX/zxyz5tgJWwU4C O3lg== X-Gm-Message-State: AC+VfDzWFD8cwmMIm0eHLfIXpIxCjhsIR6l4DCkhunUPFM3R9VEYK8Yb RpGiRkTk3PrY5DeIjE/od6lk4LxM2gBTiXX9+qI= X-Received: by 2002:a05:6a20:12d6:b0:10b:9dc1:c5e5 with SMTP id v22-20020a056a2012d600b0010b9dc1c5e5mr93114pzg.34.1685996162942; Mon, 05 Jun 2023 13:16:02 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 14/52] tcg: Move TCGv, dup_const_tl definitions to tcg-op.h Date: Mon, 5 Jun 2023 13:15:10 -0700 Message-Id: <20230605201548.1596865-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org These two items are the last uses of TARGET_LONG_BITS within tcg.h, and are more in common with the other "_tl" definitions within that file. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-op.h | 15 ++++++++++++++- include/tcg/tcg.h | 19 ------------------- target/mips/tcg/translate.h | 1 + 3 files changed, 15 insertions(+), 20 deletions(-) diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 844c666374..b8f0599f3c 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -808,19 +808,23 @@ static inline void tcg_gen_plugin_cb_end(void) } #if TARGET_LONG_BITS == 32 +typedef TCGv_i32 TCGv; #define tcg_temp_new() tcg_temp_new_i32() #define tcg_global_mem_new tcg_global_mem_new_i32 #define tcg_temp_free tcg_temp_free_i32 #define tcgv_tl_temp tcgv_i32_temp #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i32 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i32 -#else +#elif TARGET_LONG_BITS == 64 +typedef TCGv_i64 TCGv; #define tcg_temp_new() tcg_temp_new_i64() #define tcg_global_mem_new tcg_global_mem_new_i64 #define tcg_temp_free tcg_temp_free_i64 #define tcgv_tl_temp tcgv_i64_temp #define tcg_gen_qemu_ld_tl tcg_gen_qemu_ld_i64 #define tcg_gen_qemu_st_tl tcg_gen_qemu_st_i64 +#else +#error Unhandled TARGET_LONG_BITS value #endif void tcg_gen_qemu_ld_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); @@ -1182,6 +1186,7 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i64 #define tcg_gen_dup_tl_vec tcg_gen_dup_i64_vec #define tcg_gen_dup_tl tcg_gen_dup_i64 +#define dup_const_tl dup_const #else #define tcg_gen_movi_tl tcg_gen_movi_i32 #define tcg_gen_mov_tl tcg_gen_mov_i32 @@ -1296,6 +1301,14 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); #define tcg_gen_atomic_umax_fetch_tl tcg_gen_atomic_umax_fetch_i32 #define tcg_gen_dup_tl_vec tcg_gen_dup_i32_vec #define tcg_gen_dup_tl tcg_gen_dup_i32 + +#define dup_const_tl(VECE, C) \ + (__builtin_constant_p(VECE) \ + ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ + : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ + : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ + : (qemu_build_not_reached_always(), 0)) \ + : (target_long)dup_const(VECE, C)) #endif #if UINTPTR_MAX == UINT32_MAX diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 021fc903ad..9b2833b31d 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -357,13 +357,6 @@ typedef struct TCGv_i128_d *TCGv_i128; typedef struct TCGv_ptr_d *TCGv_ptr; typedef struct TCGv_vec_d *TCGv_vec; typedef TCGv_ptr TCGv_env; -#if TARGET_LONG_BITS == 32 -#define TCGv TCGv_i32 -#elif TARGET_LONG_BITS == 64 -#define TCGv TCGv_i64 -#else -#error Unhandled TARGET_LONG_BITS value -#endif /* call flags */ /* Helper does not read globals (either directly or through an exception). It @@ -1163,18 +1156,6 @@ uint64_t dup_const(unsigned vece, uint64_t c); : (qemu_build_not_reached_always(), 0)) \ : dup_const(VECE, C)) -#if TARGET_LONG_BITS == 64 -# define dup_const_tl dup_const -#else -# define dup_const_tl(VECE, C) \ - (__builtin_constant_p(VECE) \ - ? ( (VECE) == MO_8 ? 0x01010101ul * (uint8_t)(C) \ - : (VECE) == MO_16 ? 0x00010001ul * (uint16_t)(C) \ - : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ - : (qemu_build_not_reached_always(), 0)) \ - : (target_long)dup_const(VECE, C)) -#endif - #ifdef CONFIG_DEBUG_TCG void tcg_assert_listed_vecop(TCGOpcode); #else diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index 69f85841d2..fa8bf55209 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -10,6 +10,7 @@ #include "qemu/log.h" #include "exec/translator.h" +#include "tcg/tcg-op.h" #define MIPS_DEBUG_DISAS 0 From patchwork Mon Jun 5 20:15:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689265 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288700wru; Mon, 5 Jun 2023 13:27:20 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6K/qwFKWrGc220Wa4X7jQPXbO/uTVyNO49n9D5unYEnRUCTU+1OMUPbStvxAv/L25LJLIz X-Received: by 2002:a05:620a:2225:b0:75e:c716:93c4 with SMTP id n5-20020a05620a222500b0075ec71693c4mr711764qkh.30.1685996840270; Mon, 05 Jun 2023 13:27:20 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996840; cv=none; d=google.com; s=arc-20160816; b=lh2W+jbrEsrxfLja2uAyejAhTP4nC76S+8Inlc1RzkRloAY1TlKyxhrf+9XXShFomA iadE4AAAYDvM7cRNywydfqmvNJMKclvp1Qo+6dN9KrOmmAV3zAsupR3n3+1/9gRxjSeA eYmhI5WH5PAiBI6tCPucdW+xJmG78yCRZCB47U+jJPgP3Nwr4vkOgEGRxyA2JhJQP/8X qMPP4hbg4mY0QIBtsKC3l68hCBBDLMxjv9985VB+k8f58LVjYZNwqHvKCOX+tUw8iJEs Ul6WhBfj9rOSX+pF5fRvxQ/EQV8HH/aiTVyHQgSSMXi0AKebThSJGrfjbCzOnXLISvMW wmdA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nIPRQb9RDkuci2hni4sRI4JG+1cfECrQne7p/39R7JA=; b=ZTwlclJxrdqgCZ8q4FyX3NrStd62Wv6epYSqsMSE6ATzxp8Dr/RC3sb6DvdOyNI+qG I55Wn+6lo5z4yFtFRecm5dDkKUcuo6qGR6me6o0FWwTjYSxb1FVQ1zEoqkPMMV7tN3+8 K3joglpHl21zHpMqdHX42BpHFgNEHnt4fsrOMt/3ADToD91Gn8Qr8AvFhr0UjArNG9ec RlkBGCCZRZOxVfUZaIC/Nvcn5kPsWFTyzBZDnJKELq19Ub19UQuANe+ypaR3TgZpqwK8 wVwe19/6xZ6YyMJLvgNKKE65JESa0+SmRYQ8rLrdptqAPqAJAzu9apTNxuZkf7Vo+9Vi LryQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GOE352v+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id f4-20020a05620a068400b0074ada06c1a8si4855134qkh.202.2023.06.05.13.27.20 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:27:20 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GOE352v+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gd5-00022H-Dt; Mon, 05 Jun 2023 16:16:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcm-0001wC-P1 for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:21 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcX-0003kp-Ch for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:20 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-655d1fc8ad8so1363500b3a.1 for ; Mon, 05 Jun 2023 13:16:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996164; x=1688588164; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nIPRQb9RDkuci2hni4sRI4JG+1cfECrQne7p/39R7JA=; b=GOE352v+q0lTZp7eh8hSGCcTT84vJ705YLU51tJ1FQyRBkH4U5T7rr1pxOUZUt4Pcx v/l/Gmz5hYN23ElwI4sNjfMbafAe76Uzmf6qm46yu3rkR7VkJlb4/iPDiSbN+OSXwRdh Fv0sKhnPRY/lh/lyoYDNENCh3dTGnrLjm4Acd2amPkWCs+S39+lBpNGFfsXaegHOs3Gc KTH6Opm8GxPpvXqOfF/15iAFXBjksSq4oehrwCxQxb3Hx/2OhMHoxbvxX02kbiXkWngW AmO0DfLZLY2nDnpTLZ8SbQuv8UyekRTFUDBq7ZG6Y1POCntboDB9CzOqXJobDcsrk+1s 0OjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996164; x=1688588164; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nIPRQb9RDkuci2hni4sRI4JG+1cfECrQne7p/39R7JA=; b=icl2w684Pkq7XcsDz9/1fMcEllCk/GdCHT0OnA3LV9t4f4pUfW6LS3+mgOTLZ0kA0O /uatQeYoED7iu4zEbLU1hg2xl+odZzKAUy4E/TqjWHftRgUNsLU0UzGFMorCWkgG1Pom P1hg7KcK3VporcVh57Q+tu+9CyGtOv87SSGjTRc6WegxpEbLRzjL4YRzAtEtaerC+g84 0wfjb1n0mvbpayDJ57APHGpaypaeDFLNcUgDUgnTbY+WeMAwredNYfrmFvq+vyqLh0Kp 3QByFLDoiMysTRAmjIJ28MZZc/jX3ComKUdl3ybGIR93zgt/0lfpN066gaDLDMAU4Xm/ 3MuA== X-Gm-Message-State: AC+VfDzfoUKfyqIB+W07fY26iqiAi1EP6ApoVxy36l9NNXBWLP3/M7q4 LvsN/XAfSCJC3BxDujHD6zg+4Y8tAsfOTRijUns= X-Received: by 2002:aa7:888b:0:b0:64d:1451:8224 with SMTP id z11-20020aa7888b000000b0064d14518224mr753329pfe.22.1685996163859; Mon, 05 Jun 2023 13:16:03 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 15/52] tcg: Split tcg/tcg-op-common.h from tcg/tcg-op.h Date: Mon, 5 Jun 2023 13:15:11 -0700 Message-Id: <20230605201548.1596865-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Create tcg/tcg-op-common.h, moving everything that does not concern TARGET_LONG_BITS or TCGv. Adjust tcg/*.c to use the new header instead of tcg-op.h, in preparation for compiling tcg/ only once. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-op-common.h | 996 ++++++++++++++++++++++++++++++++++ include/tcg/tcg-op.h | 1004 +---------------------------------- tcg/optimize.c | 2 +- tcg/tcg-op-gvec.c | 2 +- tcg/tcg-op-ldst.c | 2 +- tcg/tcg-op-vec.c | 2 +- tcg/tcg-op.c | 2 +- tcg/tcg.c | 2 +- tcg/tci.c | 3 +- 9 files changed, 1007 insertions(+), 1008 deletions(-) create mode 100644 include/tcg/tcg-op-common.h diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h new file mode 100644 index 0000000000..04a9ca1fc6 --- /dev/null +++ b/include/tcg/tcg-op-common.h @@ -0,0 +1,996 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Target independent opcode generation functions. + * + * Copyright (c) 2008 Fabrice Bellard + */ + +#ifndef TCG_TCG_OP_COMMON_H +#define TCG_TCG_OP_COMMON_H + +#include "tcg/tcg.h" +#include "exec/helper-proto.h" +#include "exec/helper-gen.h" + +/* Basic output routines. Not for general consumption. */ + +void tcg_gen_op1(TCGOpcode, TCGArg); +void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg); +void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg); +void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); +void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); +void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); + +void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg); +void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg); +void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg); + +static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) +{ + tcg_gen_op1(opc, tcgv_i32_arg(a1)); +} + +static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) +{ + tcg_gen_op1(opc, tcgv_i64_arg(a1)); +} + +static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) +{ + tcg_gen_op1(opc, a1); +} + +static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) +{ + tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2)); +} + +static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) +{ + tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); +} + +static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) +{ + tcg_gen_op2(opc, tcgv_i32_arg(a1), a2); +} + +static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) +{ + tcg_gen_op2(opc, tcgv_i64_arg(a1), a2); +} + +static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) +{ + tcg_gen_op2(opc, a1, a2); +} + +static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, + TCGv_i32 a2, TCGv_i32 a3) +{ + tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3)); +} + +static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, + TCGv_i64 a2, TCGv_i64 a3) +{ + tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3)); +} + +static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, + TCGv_i32 a2, TCGArg a3) +{ + tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3); +} + +static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, + TCGv_i64 a2, TCGArg a3) +{ + tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3); +} + +static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, + TCGv_ptr base, TCGArg offset) +{ + tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset); +} + +static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, + TCGv_ptr base, TCGArg offset) +{ + tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset); +} + +static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4) +{ + tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4)); +} + +static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4) +{ + tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4)); +} + +static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGArg a4) +{ + tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), a4); +} + +static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGArg a4) +{ + tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), a4); +} + +static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGArg a3, TCGArg a4) +{ + tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4); +} + +static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGArg a3, TCGArg a4) +{ + tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); +} + +static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) +{ + tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); +} + +static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) +{ + tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); +} + +static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) +{ + tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5); +} + +static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) +{ + tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5); +} + +static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGArg a4, TCGArg a5) +{ + tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), a4, a5); +} + +static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGArg a4, TCGArg a5) +{ + tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), a4, a5); +} + +static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4, + TCGv_i32 a5, TCGv_i32 a6) +{ + tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), + tcgv_i32_arg(a6)); +} + +static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4, + TCGv_i64 a5, TCGv_i64 a6) +{ + tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), + tcgv_i64_arg(a6)); +} + +static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4, + TCGv_i32 a5, TCGArg a6) +{ + tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); +} + +static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4, + TCGv_i64 a5, TCGArg a6) +{ + tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); +} + +static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, + TCGv_i32 a3, TCGv_i32 a4, + TCGArg a5, TCGArg a6) +{ + tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), + tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); +} + +static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, + TCGv_i64 a3, TCGv_i64 a4, + TCGArg a5, TCGArg a6) +{ + tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), + tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6); +} + + +/* Generic ops. */ + +static inline void gen_set_label(TCGLabel *l) +{ + l->present = 1; + tcg_gen_op1(INDEX_op_set_label, label_arg(l)); +} + +void tcg_gen_br(TCGLabel *l); +void tcg_gen_mb(TCGBar); + +/** + * tcg_gen_exit_tb() - output exit_tb TCG operation + * @tb: The TranslationBlock from which we are exiting + * @idx: Direct jump slot index, or exit request + * + * See tcg/README for more info about this TCG operation. + * See also tcg.h and the block comment above TB_EXIT_MASK. + * + * For a normal exit from the TB, back to the main loop, @tb should + * be NULL and @idx should be 0. Otherwise, @tb should be valid and + * @idx should be one of the TB_EXIT_ values. + */ +void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx); + +/** + * tcg_gen_goto_tb() - output goto_tb TCG operation + * @idx: Direct jump slot index (0 or 1) + * + * See tcg/README for more info about this TCG operation. + * + * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within + * the pages this TB resides in because we don't take care of direct jumps when + * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a + * static address translation, so the destination address is always valid, TBs + * are always invalidated properly, and direct jumps are reset when mapping + * changes. + */ +void tcg_gen_goto_tb(unsigned idx); + +/** + * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid + * @addr: Guest address of the target TB + * + * If the TB is not valid, jump to the epilogue. + * + * This operation is optional. If the TCG backend does not implement goto_ptr, + * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument. + */ +void tcg_gen_lookup_and_goto_ptr(void); + +static inline void tcg_gen_plugin_cb_start(unsigned from, unsigned type, + unsigned wr) +{ + tcg_gen_op3(INDEX_op_plugin_cb_start, from, type, wr); +} + +static inline void tcg_gen_plugin_cb_end(void) +{ + tcg_emit_op(INDEX_op_plugin_cb_end, 0); +} + +/* 32 bit ops */ + +void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg); +void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); +void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); +void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); +void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); +void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); +void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, + unsigned int ofs, unsigned int len); +void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, + unsigned int ofs, unsigned int len); +void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, + unsigned int ofs, unsigned int len); +void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, + unsigned int ofs, unsigned int len); +void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, + unsigned int ofs); +void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *); +void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *); +void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, + TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, + TCGv_i32 arg1, int32_t arg2); +void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, + TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); +void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, + TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); +void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, + TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); +void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); +void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); +void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); +void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); + +/* Replicate a value of size @vece from @in to all the lanes in @out */ +void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); + +static inline void tcg_gen_discard_i32(TCGv_i32 arg) +{ + tcg_gen_op1_i32(INDEX_op_discard, arg); +} + +static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) +{ + if (ret != arg) { + tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); + } +} + +static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); +} + +static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); +} + +static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); +} + +static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); +} + +static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); +} + +static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); +} + +static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); +} + +static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); +} + +static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) +{ + tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); +} + +static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) +{ + if (TCG_TARGET_HAS_neg_i32) { + tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); + } else { + tcg_gen_subfi_i32(ret, 0, arg); + } +} + +static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) +{ + if (TCG_TARGET_HAS_not_i32) { + tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); + } else { + tcg_gen_xori_i32(ret, arg, -1); + } +} + +/* 64 bit ops */ + +void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); +void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); +void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); +void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); +void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); +void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); +void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, + unsigned int ofs, unsigned int len); +void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, + unsigned int ofs, unsigned int len); +void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, + unsigned int ofs, unsigned int len); +void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, + unsigned int ofs, unsigned int len); +void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, + unsigned int ofs); +void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *); +void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *); +void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, + TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, + TCGv_i64 arg1, int64_t arg2); +void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, + TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); +void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); +void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, + TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); +void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); +void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); +void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); + +/* Replicate a value of size @vece from @in to all the lanes in @out */ +void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in); + +#if TCG_TARGET_REG_BITS == 64 +static inline void tcg_gen_discard_i64(TCGv_i64 arg) +{ + tcg_gen_op1_i64(INDEX_op_discard, arg); +} + +static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) +{ + if (ret != arg) { + tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); + } +} + +static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); +} + +static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); +} + +static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); +} + +static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); +} + +static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); +} + +static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); +} + +static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); +} + +static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); +} + +static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); +} + +static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); +} + +static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, + tcg_target_long offset) +{ + tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); +} + +static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); +} + +static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) +{ + tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); +} +#else /* TCG_TARGET_REG_BITS == 32 */ +void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); + +void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); + +void tcg_gen_discard_i64(TCGv_i64 arg); +void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); +void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); +void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); +#endif /* TCG_TARGET_REG_BITS */ + +static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) +{ + if (TCG_TARGET_HAS_neg_i64) { + tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); + } else { + tcg_gen_subfi_i64(ret, 0, arg); + } +} + +/* Size changing operations. */ + +void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg); +void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg); +void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high); +void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg); +void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); +void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); +void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); + +void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src); +void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg); +void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi); + +static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) +{ + tcg_gen_deposit_i64(ret, lo, hi, 32, 32); +} + +/* Local load/store bit ops */ + +void tcg_gen_qemu_ld_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_st_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_ld_i64_chk(TCGv_i64, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_st_i64_chk(TCGv_i64, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_ld_i128_chk(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType); +void tcg_gen_qemu_st_i128_chk(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType); + +/* Atomic ops */ + +void tcg_gen_atomic_cmpxchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_cmpxchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_cmpxchg_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, + TCGv_i128, TCGArg, MemOp, TCGType); + +void tcg_gen_nonatomic_cmpxchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_nonatomic_cmpxchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_nonatomic_cmpxchg_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, + TCGv_i128, TCGArg, MemOp, TCGType); + +void tcg_gen_atomic_xchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_xchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); + +void tcg_gen_atomic_fetch_add_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_add_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_and_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_and_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_or_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_or_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_xor_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_xor_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_smin_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_smin_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_umin_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_umin_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_smax_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_smax_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_umax_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_fetch_umax_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); + +void tcg_gen_atomic_add_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_add_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_and_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_and_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_or_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_or_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_xor_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_xor_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_smin_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_smin_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_umin_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_umin_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_smax_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_smax_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_umax_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, + TCGArg, MemOp, TCGType); +void tcg_gen_atomic_umax_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, + TCGArg, MemOp, TCGType); + +/* Vector ops */ + +void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); +void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); +void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); +void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long); +void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); +void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); +void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); +void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a); +void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); +void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); + +void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); + +void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); + +void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); + +void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, + TCGv_vec a, TCGv_vec b); + +void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, + TCGv_vec b, TCGv_vec c); +void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r, + TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d); + +void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); +void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); +void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); + +/* Host pointer ops */ + +#if UINTPTR_MAX == UINT32_MAX +# define PTR i32 +# define NAT TCGv_i32 +#else +# define PTR i64 +# define NAT TCGv_i64 +#endif + +static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) +{ + glue(tcg_gen_ld_,PTR)((NAT)r, a, o); +} + +static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) +{ + glue(tcg_gen_st_, PTR)((NAT)r, a, o); +} + +static inline void tcg_gen_discard_ptr(TCGv_ptr a) +{ + glue(tcg_gen_discard_,PTR)((NAT)a); +} + +static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b) +{ + glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b); +} + +static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b) +{ + glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b); +} + +static inline void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s) +{ + glue(tcg_gen_mov_,PTR)((NAT)d, (NAT)s); +} + +static inline void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s) +{ + glue(tcg_gen_movi_,PTR)((NAT)d, s); +} + +static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, + intptr_t b, TCGLabel *label) +{ + glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label); +} + +static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a) +{ +#if UINTPTR_MAX == UINT32_MAX + tcg_gen_mov_i32((NAT)r, a); +#else + tcg_gen_ext_i32_i64((NAT)r, a); +#endif +} + +static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a) +{ +#if UINTPTR_MAX == UINT32_MAX + tcg_gen_extrl_i64_i32((NAT)r, a); +#else + tcg_gen_mov_i64((NAT)r, a); +#endif +} + +static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a) +{ +#if UINTPTR_MAX == UINT32_MAX + tcg_gen_extu_i32_i64(r, (NAT)a); +#else + tcg_gen_mov_i64(r, (NAT)a); +#endif +} + +static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a) +{ +#if UINTPTR_MAX == UINT32_MAX + tcg_gen_mov_i32(r, (NAT)a); +#else + tcg_gen_extrl_i64_i32(r, (NAT)a); +#endif +} + +#undef PTR +#undef NAT + +#endif /* TCG_TCG_OP_COMMON_H */ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index b8f0599f3c..47f1dce816 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -1,722 +1,14 @@ +/* SPDX-License-Identifier: MIT */ /* - * Tiny Code Generator for QEMU + * Target dependent opcode generation functions. * * Copyright (c) 2008 Fabrice Bellard - * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. */ #ifndef TCG_TCG_OP_H #define TCG_TCG_OP_H -#include "tcg/tcg.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" - -/* Basic output routines. Not for general consumption. */ - -void tcg_gen_op1(TCGOpcode, TCGArg); -void tcg_gen_op2(TCGOpcode, TCGArg, TCGArg); -void tcg_gen_op3(TCGOpcode, TCGArg, TCGArg, TCGArg); -void tcg_gen_op4(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg); -void tcg_gen_op5(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); -void tcg_gen_op6(TCGOpcode, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg, TCGArg); - -void vec_gen_2(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg); -void vec_gen_3(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg); -void vec_gen_4(TCGOpcode, TCGType, unsigned, TCGArg, TCGArg, TCGArg, TCGArg); - -static inline void tcg_gen_op1_i32(TCGOpcode opc, TCGv_i32 a1) -{ - tcg_gen_op1(opc, tcgv_i32_arg(a1)); -} - -static inline void tcg_gen_op1_i64(TCGOpcode opc, TCGv_i64 a1) -{ - tcg_gen_op1(opc, tcgv_i64_arg(a1)); -} - -static inline void tcg_gen_op1i(TCGOpcode opc, TCGArg a1) -{ - tcg_gen_op1(opc, a1); -} - -static inline void tcg_gen_op2_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2) -{ - tcg_gen_op2(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2)); -} - -static inline void tcg_gen_op2_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2) -{ - tcg_gen_op2(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2)); -} - -static inline void tcg_gen_op2i_i32(TCGOpcode opc, TCGv_i32 a1, TCGArg a2) -{ - tcg_gen_op2(opc, tcgv_i32_arg(a1), a2); -} - -static inline void tcg_gen_op2i_i64(TCGOpcode opc, TCGv_i64 a1, TCGArg a2) -{ - tcg_gen_op2(opc, tcgv_i64_arg(a1), a2); -} - -static inline void tcg_gen_op2ii(TCGOpcode opc, TCGArg a1, TCGArg a2) -{ - tcg_gen_op2(opc, a1, a2); -} - -static inline void tcg_gen_op3_i32(TCGOpcode opc, TCGv_i32 a1, - TCGv_i32 a2, TCGv_i32 a3) -{ - tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), tcgv_i32_arg(a3)); -} - -static inline void tcg_gen_op3_i64(TCGOpcode opc, TCGv_i64 a1, - TCGv_i64 a2, TCGv_i64 a3) -{ - tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), tcgv_i64_arg(a3)); -} - -static inline void tcg_gen_op3i_i32(TCGOpcode opc, TCGv_i32 a1, - TCGv_i32 a2, TCGArg a3) -{ - tcg_gen_op3(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3); -} - -static inline void tcg_gen_op3i_i64(TCGOpcode opc, TCGv_i64 a1, - TCGv_i64 a2, TCGArg a3) -{ - tcg_gen_op3(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3); -} - -static inline void tcg_gen_ldst_op_i32(TCGOpcode opc, TCGv_i32 val, - TCGv_ptr base, TCGArg offset) -{ - tcg_gen_op3(opc, tcgv_i32_arg(val), tcgv_ptr_arg(base), offset); -} - -static inline void tcg_gen_ldst_op_i64(TCGOpcode opc, TCGv_i64 val, - TCGv_ptr base, TCGArg offset) -{ - tcg_gen_op3(opc, tcgv_i64_arg(val), tcgv_ptr_arg(base), offset); -} - -static inline void tcg_gen_op4_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4) -{ - tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4)); -} - -static inline void tcg_gen_op4_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4) -{ - tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4)); -} - -static inline void tcg_gen_op4i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGArg a4) -{ - tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), a4); -} - -static inline void tcg_gen_op4i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGArg a4) -{ - tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), a4); -} - -static inline void tcg_gen_op4ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGArg a3, TCGArg a4) -{ - tcg_gen_op4(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), a3, a4); -} - -static inline void tcg_gen_op4ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGArg a3, TCGArg a4) -{ - tcg_gen_op4(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), a3, a4); -} - -static inline void tcg_gen_op5_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, TCGv_i32 a5) -{ - tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5)); -} - -static inline void tcg_gen_op5_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, TCGv_i64 a5) -{ - tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5)); -} - -static inline void tcg_gen_op5i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, TCGArg a5) -{ - tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5); -} - -static inline void tcg_gen_op5i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, TCGArg a5) -{ - tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5); -} - -static inline void tcg_gen_op5ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGArg a4, TCGArg a5) -{ - tcg_gen_op5(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), a4, a5); -} - -static inline void tcg_gen_op5ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGArg a4, TCGArg a5) -{ - tcg_gen_op5(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), a4, a5); -} - -static inline void tcg_gen_op6_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, - TCGv_i32 a5, TCGv_i32 a6) -{ - tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), - tcgv_i32_arg(a6)); -} - -static inline void tcg_gen_op6_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, - TCGv_i64 a5, TCGv_i64 a6) -{ - tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), - tcgv_i64_arg(a6)); -} - -static inline void tcg_gen_op6i_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, - TCGv_i32 a5, TCGArg a6) -{ - tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), tcgv_i32_arg(a5), a6); -} - -static inline void tcg_gen_op6i_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, - TCGv_i64 a5, TCGArg a6) -{ - tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), tcgv_i64_arg(a5), a6); -} - -static inline void tcg_gen_op6ii_i32(TCGOpcode opc, TCGv_i32 a1, TCGv_i32 a2, - TCGv_i32 a3, TCGv_i32 a4, - TCGArg a5, TCGArg a6) -{ - tcg_gen_op6(opc, tcgv_i32_arg(a1), tcgv_i32_arg(a2), - tcgv_i32_arg(a3), tcgv_i32_arg(a4), a5, a6); -} - -static inline void tcg_gen_op6ii_i64(TCGOpcode opc, TCGv_i64 a1, TCGv_i64 a2, - TCGv_i64 a3, TCGv_i64 a4, - TCGArg a5, TCGArg a6) -{ - tcg_gen_op6(opc, tcgv_i64_arg(a1), tcgv_i64_arg(a2), - tcgv_i64_arg(a3), tcgv_i64_arg(a4), a5, a6); -} - - -/* Generic ops. */ - -static inline void gen_set_label(TCGLabel *l) -{ - l->present = 1; - tcg_gen_op1(INDEX_op_set_label, label_arg(l)); -} - -void tcg_gen_br(TCGLabel *l); -void tcg_gen_mb(TCGBar); - -/* Helper calls. */ - -/* 32 bit ops */ - -void tcg_gen_movi_i32(TCGv_i32 ret, int32_t arg); -void tcg_gen_addi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_subfi_i32(TCGv_i32 ret, int32_t arg1, TCGv_i32 arg2); -void tcg_gen_subi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_andi_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_ori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_xori_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_shli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_shri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_sari_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_muli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_div_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_eqv_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_nand_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_nor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_orc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_clz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_ctz_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_clzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); -void tcg_gen_ctzi_i32(TCGv_i32 ret, TCGv_i32 arg1, uint32_t arg2); -void tcg_gen_clrsb_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_ctpop_i32(TCGv_i32 a1, TCGv_i32 a2); -void tcg_gen_rotl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_rotli_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_rotr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_rotri_i32(TCGv_i32 ret, TCGv_i32 arg1, int32_t arg2); -void tcg_gen_deposit_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2, - unsigned int ofs, unsigned int len); -void tcg_gen_deposit_z_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_extract_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_sextract_i32(TCGv_i32 ret, TCGv_i32 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_extract2_i32(TCGv_i32 ret, TCGv_i32 al, TCGv_i32 ah, - unsigned int ofs); -void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *); -void tcg_gen_brcondi_i32(TCGCond cond, TCGv_i32 arg1, int32_t arg2, TCGLabel *); -void tcg_gen_setcond_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_setcondi_i32(TCGCond cond, TCGv_i32 ret, - TCGv_i32 arg1, int32_t arg2); -void tcg_gen_movcond_i32(TCGCond cond, TCGv_i32 ret, TCGv_i32 c1, - TCGv_i32 c2, TCGv_i32 v1, TCGv_i32 v2); -void tcg_gen_add2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); -void tcg_gen_sub2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 al, - TCGv_i32 ah, TCGv_i32 bl, TCGv_i32 bh); -void tcg_gen_mulu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_muls2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_mulsu2_i32(TCGv_i32 rl, TCGv_i32 rh, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_ext8s_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_ext16s_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_ext8u_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_ext16u_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_bswap16_i32(TCGv_i32 ret, TCGv_i32 arg, int flags); -void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg); -void tcg_gen_smin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_smax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_umin_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_umax_i32(TCGv_i32, TCGv_i32 arg1, TCGv_i32 arg2); -void tcg_gen_abs_i32(TCGv_i32, TCGv_i32); - -/* Replicate a value of size @vece from @in to all the lanes in @out */ -void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in); - -static inline void tcg_gen_discard_i32(TCGv_i32 arg) -{ - tcg_gen_op1_i32(INDEX_op_discard, arg); -} - -static inline void tcg_gen_mov_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - if (ret != arg) { - tcg_gen_op2_i32(INDEX_op_mov_i32, ret, arg); - } -} - -static inline void tcg_gen_ld8u_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld8u_i32, ret, arg2, offset); -} - -static inline void tcg_gen_ld8s_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld8s_i32, ret, arg2, offset); -} - -static inline void tcg_gen_ld16u_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld16u_i32, ret, arg2, offset); -} - -static inline void tcg_gen_ld16s_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld16s_i32, ret, arg2, offset); -} - -static inline void tcg_gen_ld_i32(TCGv_i32 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_ld_i32, ret, arg2, offset); -} - -static inline void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_st8_i32, arg1, arg2, offset); -} - -static inline void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_st16_i32, arg1, arg2, offset); -} - -static inline void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i32(INDEX_op_st_i32, arg1, arg2, offset); -} - -static inline void tcg_gen_add_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_add_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_sub_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_sub_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_and_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_and_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_or_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_or_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_xor_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_xor_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_shl_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_shl_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_shr_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_shr_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_sar_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_sar_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_mul_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2) -{ - tcg_gen_op3_i32(INDEX_op_mul_i32, ret, arg1, arg2); -} - -static inline void tcg_gen_neg_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - if (TCG_TARGET_HAS_neg_i32) { - tcg_gen_op2_i32(INDEX_op_neg_i32, ret, arg); - } else { - tcg_gen_subfi_i32(ret, 0, arg); - } -} - -static inline void tcg_gen_not_i32(TCGv_i32 ret, TCGv_i32 arg) -{ - if (TCG_TARGET_HAS_not_i32) { - tcg_gen_op2_i32(INDEX_op_not_i32, ret, arg); - } else { - tcg_gen_xori_i32(ret, arg, -1); - } -} - -/* 64 bit ops */ - -void tcg_gen_movi_i64(TCGv_i64 ret, int64_t arg); -void tcg_gen_addi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_subfi_i64(TCGv_i64 ret, int64_t arg1, TCGv_i64 arg2); -void tcg_gen_subi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_andi_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_ori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_xori_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_shli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_shri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_sari_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_muli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_div_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_eqv_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_nand_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_nor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_orc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_clz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_ctz_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_clzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); -void tcg_gen_ctzi_i64(TCGv_i64 ret, TCGv_i64 arg1, uint64_t arg2); -void tcg_gen_clrsb_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ctpop_i64(TCGv_i64 a1, TCGv_i64 a2); -void tcg_gen_rotl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_rotli_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_rotr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_rotri_i64(TCGv_i64 ret, TCGv_i64 arg1, int64_t arg2); -void tcg_gen_deposit_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2, - unsigned int ofs, unsigned int len); -void tcg_gen_deposit_z_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_extract_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_sextract_i64(TCGv_i64 ret, TCGv_i64 arg, - unsigned int ofs, unsigned int len); -void tcg_gen_extract2_i64(TCGv_i64 ret, TCGv_i64 al, TCGv_i64 ah, - unsigned int ofs); -void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *); -void tcg_gen_brcondi_i64(TCGCond cond, TCGv_i64 arg1, int64_t arg2, TCGLabel *); -void tcg_gen_setcond_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_setcondi_i64(TCGCond cond, TCGv_i64 ret, - TCGv_i64 arg1, int64_t arg2); -void tcg_gen_movcond_i64(TCGCond cond, TCGv_i64 ret, TCGv_i64 c1, - TCGv_i64 c2, TCGv_i64 v1, TCGv_i64 v2); -void tcg_gen_add2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); -void tcg_gen_sub2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 al, - TCGv_i64 ah, TCGv_i64 bl, TCGv_i64 bh); -void tcg_gen_mulu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_muls2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_mulsu2_i64(TCGv_i64 rl, TCGv_i64 rh, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_not_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext8s_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext16s_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext8u_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext16u_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ext32u_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_bswap16_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); -void tcg_gen_bswap32_i64(TCGv_i64 ret, TCGv_i64 arg, int flags); -void tcg_gen_bswap64_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_hswap_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_smin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_smax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_umin_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_umax_i64(TCGv_i64, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_abs_i64(TCGv_i64, TCGv_i64); - -/* Replicate a value of size @vece from @in to all the lanes in @out */ -void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in); - -#if TCG_TARGET_REG_BITS == 64 -static inline void tcg_gen_discard_i64(TCGv_i64 arg) -{ - tcg_gen_op1_i64(INDEX_op_discard, arg); -} - -static inline void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg) -{ - if (ret != arg) { - tcg_gen_op2_i64(INDEX_op_mov_i64, ret, arg); - } -} - -static inline void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld8u_i64, ret, arg2, offset); -} - -static inline void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld8s_i64, ret, arg2, offset); -} - -static inline void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld16u_i64, ret, arg2, offset); -} - -static inline void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld16s_i64, ret, arg2, offset); -} - -static inline void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld32u_i64, ret, arg2, offset); -} - -static inline void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld32s_i64, ret, arg2, offset); -} - -static inline void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_ld_i64, ret, arg2, offset); -} - -static inline void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_st8_i64, arg1, arg2, offset); -} - -static inline void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_st16_i64, arg1, arg2, offset); -} - -static inline void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_st32_i64, arg1, arg2, offset); -} - -static inline void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, - tcg_target_long offset) -{ - tcg_gen_ldst_op_i64(INDEX_op_st_i64, arg1, arg2, offset); -} - -static inline void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_add_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_sub_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_and_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_or_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_xor_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_shl_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_shr_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_sar_i64, ret, arg1, arg2); -} - -static inline void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2) -{ - tcg_gen_op3_i64(INDEX_op_mul_i64, ret, arg1, arg2); -} -#else /* TCG_TARGET_REG_BITS == 32 */ -void tcg_gen_st8_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_st16_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); - -void tcg_gen_add_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_sub_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); - -void tcg_gen_discard_i64(TCGv_i64 arg); -void tcg_gen_mov_i64(TCGv_i64 ret, TCGv_i64 arg); -void tcg_gen_ld8u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_ld8s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_ld16u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_ld16s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_ld_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset); -void tcg_gen_and_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_or_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_xor_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_shl_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_shr_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_sar_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -void tcg_gen_mul_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2); -#endif /* TCG_TARGET_REG_BITS */ - -static inline void tcg_gen_neg_i64(TCGv_i64 ret, TCGv_i64 arg) -{ - if (TCG_TARGET_HAS_neg_i64) { - tcg_gen_op2_i64(INDEX_op_neg_i64, ret, arg); - } else { - tcg_gen_subfi_i64(ret, 0, arg); - } -} - -/* Size changing operations. */ - -void tcg_gen_extu_i32_i64(TCGv_i64 ret, TCGv_i32 arg); -void tcg_gen_ext_i32_i64(TCGv_i64 ret, TCGv_i32 arg); -void tcg_gen_concat_i32_i64(TCGv_i64 dest, TCGv_i32 low, TCGv_i32 high); -void tcg_gen_extrl_i64_i32(TCGv_i32 ret, TCGv_i64 arg); -void tcg_gen_extrh_i64_i32(TCGv_i32 ret, TCGv_i64 arg); -void tcg_gen_extr_i64_i32(TCGv_i32 lo, TCGv_i32 hi, TCGv_i64 arg); -void tcg_gen_extr32_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i64 arg); - -void tcg_gen_mov_i128(TCGv_i128 dst, TCGv_i128 src); -void tcg_gen_extr_i128_i64(TCGv_i64 lo, TCGv_i64 hi, TCGv_i128 arg); -void tcg_gen_concat_i64_i128(TCGv_i128 ret, TCGv_i64 lo, TCGv_i64 hi); - -static inline void tcg_gen_concat32_i64(TCGv_i64 ret, TCGv_i64 lo, TCGv_i64 hi) -{ - tcg_gen_deposit_i64(ret, lo, hi, 32, 32); -} - -/* QEMU specific operations. */ +#include "tcg/tcg-op-common.h" #ifndef TARGET_LONG_BITS #error must include QEMU headers @@ -756,57 +48,6 @@ static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, # error "Unhandled number of operands to insn_start" #endif -/** - * tcg_gen_exit_tb() - output exit_tb TCG operation - * @tb: The TranslationBlock from which we are exiting - * @idx: Direct jump slot index, or exit request - * - * See tcg/README for more info about this TCG operation. - * See also tcg.h and the block comment above TB_EXIT_MASK. - * - * For a normal exit from the TB, back to the main loop, @tb should - * be NULL and @idx should be 0. Otherwise, @tb should be valid and - * @idx should be one of the TB_EXIT_ values. - */ -void tcg_gen_exit_tb(const TranslationBlock *tb, unsigned idx); - -/** - * tcg_gen_goto_tb() - output goto_tb TCG operation - * @idx: Direct jump slot index (0 or 1) - * - * See tcg/README for more info about this TCG operation. - * - * NOTE: In softmmu emulation, direct jumps with goto_tb are only safe within - * the pages this TB resides in because we don't take care of direct jumps when - * address mapping changes, e.g. in tlb_flush(). In user mode, there's only a - * static address translation, so the destination address is always valid, TBs - * are always invalidated properly, and direct jumps are reset when mapping - * changes. - */ -void tcg_gen_goto_tb(unsigned idx); - -/** - * tcg_gen_lookup_and_goto_ptr() - look up the current TB, jump to it if valid - * @addr: Guest address of the target TB - * - * If the TB is not valid, jump to the epilogue. - * - * This operation is optional. If the TCG backend does not implement goto_ptr, - * this op is equivalent to calling tcg_gen_exit_tb() with 0 as the argument. - */ -void tcg_gen_lookup_and_goto_ptr(void); - -static inline void tcg_gen_plugin_cb_start(unsigned from, unsigned type, - unsigned wr) -{ - tcg_gen_op3(INDEX_op_plugin_cb_start, from, type, wr); -} - -static inline void tcg_gen_plugin_cb_end(void) -{ - tcg_emit_op(INDEX_op_plugin_cb_end, 0); -} - #if TARGET_LONG_BITS == 32 typedef TCGv_i32 TCGv; #define tcg_temp_new() tcg_temp_new_i32() @@ -827,13 +68,6 @@ typedef TCGv_i64 TCGv; #error Unhandled TARGET_LONG_BITS value #endif -void tcg_gen_qemu_ld_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); -void tcg_gen_qemu_st_i32_chk(TCGv_i32, TCGTemp *, TCGArg, MemOp, TCGType); -void tcg_gen_qemu_ld_i64_chk(TCGv_i64, TCGTemp *, TCGArg, MemOp, TCGType); -void tcg_gen_qemu_st_i64_chk(TCGv_i64, TCGTemp *, TCGArg, MemOp, TCGType); -void tcg_gen_qemu_ld_i128_chk(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType); -void tcg_gen_qemu_st_i128_chk(TCGv_i128, TCGTemp *, TCGArg, MemOp, TCGType); - static inline void tcg_gen_qemu_ld_i32(TCGv_i32 v, TCGv a, TCGArg i, MemOp m) { @@ -870,91 +104,6 @@ tcg_gen_qemu_st_i128(TCGv_i128 v, TCGv a, TCGArg i, MemOp m) tcg_gen_qemu_st_i128_chk(v, tcgv_tl_temp(a), i, m, TCG_TYPE_TL); } -void tcg_gen_atomic_cmpxchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_cmpxchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_cmpxchg_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, - TCGv_i128, TCGArg, MemOp, TCGType); - -void tcg_gen_nonatomic_cmpxchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_nonatomic_cmpxchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_nonatomic_cmpxchg_i128_chk(TCGv_i128, TCGTemp *, TCGv_i128, - TCGv_i128, TCGArg, MemOp, TCGType); - -void tcg_gen_atomic_xchg_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_xchg_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); - -void tcg_gen_atomic_fetch_add_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_add_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_and_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_and_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_or_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_or_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_xor_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_xor_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_smin_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_smin_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_umin_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_umin_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_smax_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_smax_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_umax_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_fetch_umax_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); - -void tcg_gen_atomic_add_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_add_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_and_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_and_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_or_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_or_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_xor_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_xor_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_smin_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_smin_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_umin_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_umin_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_smax_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_smax_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_umax_fetch_i32_chk(TCGv_i32, TCGTemp *, TCGv_i32, - TCGArg, MemOp, TCGType); -void tcg_gen_atomic_umax_fetch_i64_chk(TCGv_i64, TCGTemp *, TCGv_i64, - TCGArg, MemOp, TCGType); - #define DEF_ATOMIC2(N, S) \ static inline void N##_##S(TCGv_##S r, TCGv a, TCGv_##S v, \ TCGArg i, MemOp m) \ @@ -1013,63 +162,6 @@ DEF_ATOMIC2(tcg_gen_atomic_umax_fetch, i64) #undef DEF_ATOMIC2 #undef DEF_ATOMIC3 -void tcg_gen_mov_vec(TCGv_vec, TCGv_vec); -void tcg_gen_dup_i32_vec(unsigned vece, TCGv_vec, TCGv_i32); -void tcg_gen_dup_i64_vec(unsigned vece, TCGv_vec, TCGv_i64); -void tcg_gen_dup_mem_vec(unsigned vece, TCGv_vec, TCGv_ptr, tcg_target_long); -void tcg_gen_dupi_vec(unsigned vece, TCGv_vec, uint64_t); -void tcg_gen_add_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_sub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_mul_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_and_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_or_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_xor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_andc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_orc_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_nand_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_nor_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_eqv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_not_vec(unsigned vece, TCGv_vec r, TCGv_vec a); -void tcg_gen_neg_vec(unsigned vece, TCGv_vec r, TCGv_vec a); -void tcg_gen_abs_vec(unsigned vece, TCGv_vec r, TCGv_vec a); -void tcg_gen_ssadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_usadd_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_sssub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_ussub_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_smin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_umin_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_smax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); -void tcg_gen_umax_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); - -void tcg_gen_shli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); -void tcg_gen_shri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); -void tcg_gen_sari_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); -void tcg_gen_rotli_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); -void tcg_gen_rotri_vec(unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); - -void tcg_gen_shls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); -void tcg_gen_shrs_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); -void tcg_gen_sars_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); -void tcg_gen_rotls_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); - -void tcg_gen_shlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); -void tcg_gen_shrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); -void tcg_gen_sarv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); -void tcg_gen_rotlv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); -void tcg_gen_rotrv_vec(unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); - -void tcg_gen_cmp_vec(TCGCond cond, unsigned vece, TCGv_vec r, - TCGv_vec a, TCGv_vec b); - -void tcg_gen_bitsel_vec(unsigned vece, TCGv_vec r, TCGv_vec a, - TCGv_vec b, TCGv_vec c); -void tcg_gen_cmpsel_vec(TCGCond cond, unsigned vece, TCGv_vec r, - TCGv_vec a, TCGv_vec b, TCGv_vec c, TCGv_vec d); - -void tcg_gen_ld_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); -void tcg_gen_st_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset); -void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); - #if TARGET_LONG_BITS == 64 #define tcg_gen_movi_tl tcg_gen_movi_i64 #define tcg_gen_mov_tl tcg_gen_mov_i64 @@ -1309,94 +401,6 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t); : (VECE) == MO_32 ? 0x00000001ul * (uint32_t)(C) \ : (qemu_build_not_reached_always(), 0)) \ : (target_long)dup_const(VECE, C)) -#endif - -#if UINTPTR_MAX == UINT32_MAX -# define PTR i32 -# define NAT TCGv_i32 -#else -# define PTR i64 -# define NAT TCGv_i64 -#endif - -static inline void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) -{ - glue(tcg_gen_ld_,PTR)((NAT)r, a, o); -} - -static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o) -{ - glue(tcg_gen_st_, PTR)((NAT)r, a, o); -} - -static inline void tcg_gen_discard_ptr(TCGv_ptr a) -{ - glue(tcg_gen_discard_,PTR)((NAT)a); -} - -static inline void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b) -{ - glue(tcg_gen_add_,PTR)((NAT)r, (NAT)a, (NAT)b); -} - -static inline void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b) -{ - glue(tcg_gen_addi_,PTR)((NAT)r, (NAT)a, b); -} - -static inline void tcg_gen_mov_ptr(TCGv_ptr d, TCGv_ptr s) -{ - glue(tcg_gen_mov_,PTR)((NAT)d, (NAT)s); -} - -static inline void tcg_gen_movi_ptr(TCGv_ptr d, intptr_t s) -{ - glue(tcg_gen_movi_,PTR)((NAT)d, s); -} - -static inline void tcg_gen_brcondi_ptr(TCGCond cond, TCGv_ptr a, - intptr_t b, TCGLabel *label) -{ - glue(tcg_gen_brcondi_,PTR)(cond, (NAT)a, b, label); -} - -static inline void tcg_gen_ext_i32_ptr(TCGv_ptr r, TCGv_i32 a) -{ -#if UINTPTR_MAX == UINT32_MAX - tcg_gen_mov_i32((NAT)r, a); -#else - tcg_gen_ext_i32_i64((NAT)r, a); -#endif -} - -static inline void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a) -{ -#if UINTPTR_MAX == UINT32_MAX - tcg_gen_extrl_i64_i32((NAT)r, a); -#else - tcg_gen_mov_i64((NAT)r, a); -#endif -} - -static inline void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a) -{ -#if UINTPTR_MAX == UINT32_MAX - tcg_gen_extu_i32_i64(r, (NAT)a); -#else - tcg_gen_mov_i64(r, (NAT)a); -#endif -} - -static inline void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a) -{ -#if UINTPTR_MAX == UINT32_MAX - tcg_gen_mov_i32(r, (NAT)a); -#else - tcg_gen_extrl_i64_i32(r, (NAT)a); -#endif -} - -#undef PTR -#undef NAT +#endif /* TARGET_LONG_BITS == 64 */ #endif /* TCG_TCG_OP_H */ diff --git a/tcg/optimize.c b/tcg/optimize.c index bf975a3a6c..d2156367a3 100644 --- a/tcg/optimize.c +++ b/tcg/optimize.c @@ -25,7 +25,7 @@ #include "qemu/osdep.h" #include "qemu/int128.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" #include "tcg-internal.h" #define CASE_OP_32_64(x) \ diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index f51bcaa87b..7a9599e49e 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" #include "tcg/tcg-op-gvec.h" #include "tcg/tcg-gvec-desc.h" diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 3d27c347d7..3c00bf0c95 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -26,7 +26,7 @@ #include "exec/exec-all.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" #include "tcg/tcg-mo.h" #include "exec/plugin-gen.h" #include "tcg-internal.h" diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index aeeb2435cb..35d67eeda0 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" #include "tcg/tcg-mo.h" #include "tcg-internal.h" diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index edbd1c61d7..8c1ad49c4e 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -26,7 +26,7 @@ #include "exec/exec-all.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" #include "exec/plugin-gen.h" #include "tcg-internal.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 2d17c09aea..e13d0a6f09 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -42,7 +42,7 @@ #include "exec/exec-all.h" #include "exec/tlb-common.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg-op-common.h" #if UINTPTR_MAX == UINT32_MAX # define ELF_CLASS ELFCLASS32 diff --git a/tcg/tci.c b/tcg/tci.c index bab4397bc5..813572ff39 100644 --- a/tcg/tci.c +++ b/tcg/tci.c @@ -18,8 +18,7 @@ */ #include "qemu/osdep.h" -#include "exec/cpu_ldst.h" -#include "tcg/tcg-op.h" +#include "tcg/tcg.h" #include "tcg/tcg-ldst.h" #include From patchwork Mon Jun 5 20:15:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689258 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288296wru; Mon, 5 Jun 2023 13:26:12 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4d5y4zLuxggpSVnR4f6H3VceUmY69LSrNKrnv+R+1kDGudjLXCX82iaD9rUdJtDwJAq+RN X-Received: by 2002:a05:620a:20d2:b0:75b:23a1:365e with SMTP id f18-20020a05620a20d200b0075b23a1365emr882346qka.31.1685996772613; Mon, 05 Jun 2023 13:26:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996772; cv=none; d=google.com; s=arc-20160816; b=tZgS10o/bY4if+WqZ+AJhyNrC94cPwUo8wJ8revqjbIdGc22Yhy79MQxC1/L7uBxen rA2VSuU5OiCYcGEC02GYmyza2hXAVN9S3k8cN7n/1s6GRjnWpebgeSqK3BmhK5LSiY8X KCWEqHPLyU2zUeHwuAt3UdheaBT6C71j84NARNP3AvIq1+c+9LxLVQ0lwnD/6cVIOPW0 ikYX3F51WtyJUSw2PqqOc+EgvbyYJ9oKSnoK3gOMFLjk6KjPi9yIyJuNgKcDVawRGboY W6qNlgPOuKdfA3KcVGyKWlkwp74IcLRCXbOVKkn5aHMvSXXYweI159iOvXsRQGKJYbvH n5eQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RsSQnoabB8P2vFjJIJJqaM8+MtwtaRqODWT37hxDvOk=; b=qePzbstYrYhJ0gaf2ZXvW1sGHjboqka0Kjeq9Sk7JrqWqEZe2vxhCpXwEXqEX7jBon dnZpG49q50iSGpggfyQLhTjBUxOhLB63IN8nDPY5iE/XRWAhek1D2L48MGS2qNfKIX3K EL8OmLiPc6E//jGhtV76AHmsnLnAF9UFjfsxLVC5rRUqmrmmCr2ZPwwVRdE6A/Q6ciwe xBxfXfqHFd3Wv+EmkmEuaV0+6enilbntD3N1V13dM0xQ7dzLIUeJv8KvBi0cqwya0ozm p19WcAb+GRbRqF/uS00kVjmLsqa/lD3hgSGh5pzHm2GYT0IMrV01rrvHObSHxgYvVcja bbuw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BxvpNATc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id p21-20020a05620a15f500b0074e3db3adc6si4935063qkm.186.2023.06.05.13.26.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:26:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=BxvpNATc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gce-0001tK-3b; Mon, 05 Jun 2023 16:16:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcc-0001s2-3h for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:10 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcX-0003qB-F2 for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:09 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-652328c18d5so2567672b3a.1 for ; Mon, 05 Jun 2023 13:16:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996164; x=1688588164; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RsSQnoabB8P2vFjJIJJqaM8+MtwtaRqODWT37hxDvOk=; b=BxvpNATc2Uga40umd7ZZRKUSLa0+8FOeWTcNrqpq2IO7pjRmICT3xxU84Ch66Ram5Q SduQQ4pmvuwxqn0CMCMxUgxLQRa5dKQ+5XrhEnCrhOWzRFFnNGoa409eABo7y6YSeEa/ xZjCsueifYcTqTckmJcYYBXQRRglXSypgJmCEOzdahT0zEGZkxQjOVfe3HmEi1evY/vE zOs5BeKQu1CZ+UxWPXhxjYkpP0bkqaN/5A28/t6Vt9FtHeboF8qH+X/0EIUFOazZOJx4 LgOHhZ8jRcbqeuzhaW6cHBSiXW+4yRqOsGuugsREFtfjeW957J/5Y74eXTerfwis1+pC J8/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996164; x=1688588164; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RsSQnoabB8P2vFjJIJJqaM8+MtwtaRqODWT37hxDvOk=; b=QsyHk9MmjxEYfT1G5QBSgfAcMN8pIltBZs3Yogxe2gtEpF3XzA73zxE8QYE2eWZkCy fZQ2ZLuzz0fq7qo9AY5PVDj0QDKaTAVvO38zAq89owGwhq2oWEV8erejBZh31zTqfNs/ o0CKzBlbqcW/I/6ZAEl+kXCbZ7aett4IKwV/HHODK2AGukki813REIMlgj3ZlgSgSOGo mOg5g734zFvLp9DbDrqgrrbkIIXrpNVqxZ34BXvW/S+Jusi5/sjdZ4kPOcxDv0Hzpr8R BUeYhQRY9g5FWNIBN8oSCT3dJJsZF5eTs/PEmJFJIgk4rNQp2kjpUdpngsDMGnPbz+P7 WkbQ== X-Gm-Message-State: AC+VfDwmgvK4n73abjSs4aubaCrDCOrIHmHD5AHvtTpNIciPFHNrtWjC Nke7cNY7EC4tmeRFEqccCLZcDeskG1yn/Zl+fNU= X-Received: by 2002:a05:6a00:2d04:b0:64d:b0d8:a396 with SMTP id fa4-20020a056a002d0400b0064db0d8a396mr1013185pfb.7.1685996164678; Mon, 05 Jun 2023 13:16:04 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 16/52] target/arm: Include helper-gen.h in translator.h Date: Mon, 5 Jun 2023 13:15:12 -0700 Message-Id: <20230605201548.1596865-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This had been included via tcg-op-common.h via tcg-op.h, but that is going away. It is needed for inlines within translator.h, so we might as well do it there and not individually in each translator c file. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 1 + target/arm/tcg/translate-a64.c | 2 -- target/arm/tcg/translate-sme.c | 1 - target/arm/tcg/translate-sve.c | 2 -- target/arm/tcg/translate.c | 2 -- 5 files changed, 1 insertion(+), 7 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index a9d1f4adc2..868a3abd0d 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -2,6 +2,7 @@ #define TARGET_ARM_TRANSLATE_H #include "exec/translator.h" +#include "exec/helper-gen.h" #include "internals.h" diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 741a608739..bc0cb98955 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -29,8 +29,6 @@ #include "qemu/host-utils.h" #include "semihosting/semihost.h" #include "exec/gen-icount.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" #include "exec/log.h" #include "cpregs.h" #include "translate-a64.h" diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index e3adba314e..b0812d9dd6 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -23,7 +23,6 @@ #include "tcg/tcg-op-gvec.h" #include "tcg/tcg-gvec-desc.h" #include "translate.h" -#include "exec/helper-gen.h" #include "translate-a64.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 92ab290106..106baf311f 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -27,8 +27,6 @@ #include "arm_ldst.h" #include "translate.h" #include "internals.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" #include "exec/log.h" #include "translate-a64.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 7468476724..c89825ad6a 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -30,8 +30,6 @@ #include "qemu/bitops.h" #include "arm_ldst.h" #include "semihosting/semihost.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" #include "exec/log.h" #include "cpregs.h" From patchwork Mon Jun 5 20:15:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689262 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288397wru; Mon, 5 Jun 2023 13:26:29 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6rHzOf+w9A+mxB6exhrEBLrfYcxBvJgE0uc0Go0xf7d1woRumSqLKAXUVQApugOXRIKGJz X-Received: by 2002:a05:6214:212e:b0:626:1adb:e10b with SMTP id r14-20020a056214212e00b006261adbe10bmr10051265qvc.13.1685996789240; Mon, 05 Jun 2023 13:26:29 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996789; cv=none; d=google.com; s=arc-20160816; b=JHRPU5mC62NBxJ8QTmN3aKE8SWtyLKQI8hExV+ME5mx/0lSjGW8cBfPzcRwLeTnYWT anUi+nG7pzHMZehhBuxFewAIUPpGv2pDMGs3lNRgBQm92ndQgXNBYVRBZtakW3iiwm4Z xbpd/MqaaWuEydv9qy/jLN10JnHLesaRfr6SZPF0vXJPohRlLkX5ji4th5vD21aDKR74 +DmNiAdS+uAd2cvh07gx7rXDsL7421GgGLYM9UbXmiHjpMiWvUAiiK2S/rp/t5tnmDi6 5mPCmCvZIel0bG1/FvrH7NTT2eFxTDClil7VHe3JlmSPPKIo4gwOLpK1al/YoSshHJ1X vqVg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=iT3NE5JjFQ/pg6k9nejAED1CUNCtrcw54M2DdXwyNbY=; b=m3I4T5IpLed9u9LgXWX6pv0qvSQiPt3GuoR+bsqjjtn9qseJ/QMzuQXEQef0/bMGL7 7LAvVyVKYZm/FuCp+ZBx8ERQzpPssODAXTGumZGEOHz98Xa6ujWM6/HLLRFIXbQ63tgg T6WcfwyEkLeK+q4FNwkcbSn/JVAnGym0S/PwmNhuIvQ9rT83qiGiQ9CwGjw0oTlnBZv0 eNsnb7P41mnjWNmTB88vqceNUI5NMtOr3Ry8axt2y5yUxaMuIKTb+nM7WViyuI5oWya8 o050oxo4Y2CVXPHqvyAbQJ/bGeGvqlG8uWlkbOmiYTIPEjO0mTxBP3LXwMBlPNczozE7 xbmg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dVl+zL3i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id y7-20020a05622a120700b003f6b218debbsi5230545qtx.372.2023.06.05.13.26.29 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:26:29 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=dVl+zL3i; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gce-0001tS-EF; Mon, 05 Jun 2023 16:16:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gca-0001rC-Ne for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:08 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcY-0003mj-F9 for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:08 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-65540715b4bso1364825b3a.0 for ; Mon, 05 Jun 2023 13:16:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996165; x=1688588165; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=iT3NE5JjFQ/pg6k9nejAED1CUNCtrcw54M2DdXwyNbY=; b=dVl+zL3i/ygkfezarAt0Yz9MV/ft7oW7SQ4fqJ6D4Ve6+DVsIPHLEFj73TJ9zhFi74 OlOTelCI6MspFb4iiyJ+PcN+0fzbQN4aMdkcf2LFohgBH40be0gDZffWLs45LZcfwVMd 0kQKIsfRBuHw/bYk5F2xbN6BzH/f4TzWieM4pOQMYTh/Odn2osQPWREFIhtoyaeZjOkg 89gpqY4MTO2EIw8pR0GA9l+fJQ8U5SlGxH7L8y5TmEpPN6rLtiVw+gLtYb0A4AixTo6i GfLgXOICGYaCQP/7i/kY+rRoYm1m9mJYjL7WI+mpz3Ebu8cIDDNdJ2cpo2NH+YffmjSE kFZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996165; x=1688588165; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iT3NE5JjFQ/pg6k9nejAED1CUNCtrcw54M2DdXwyNbY=; b=Nyhr9MCkEu5XB23uT0yMTQnrzxcDAVUbLBz60obFljPTP/2cGlfqG7opx3PH3+MPwo T1XynXuNe6+Rx/GS20VA2+04Vn2PBqyTHqKyc8W27RDY5iApe0z+bTls5OnAca59Vp9n af0JA9ekbuHSCjPyoDDmD+OxJchFi8Xo+fs1BZsnOGjMU7i0HlfIdV41uBmaKl5+QzVO K0vccqG9YQ8h9yd43UDKbQ8f/z5cbP5q485q3Sdl9GfkoGMJiAgIJmLOMd69/x8Gis3i DPqNyxpZM3xX1xUY+5bX1590JEqaqlLnnM/3H2jVwTbRftdnNJyP3fY1mLfGaiuZ+DJC 2K2g== X-Gm-Message-State: AC+VfDzORxc99Au/QcVaC87llIBD/o1l2Kaa27GdAYRiTeC+m2t4JKjI NJKt2/afSdByt0S8B3MzkUedsYaII46M+PdafMk= X-Received: by 2002:a05:6a00:21cb:b0:65e:691a:460f with SMTP id t11-20020a056a0021cb00b0065e691a460fmr908011pfj.8.1685996165389; Mon, 05 Jun 2023 13:16:05 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 17/52] target/hexagon: Include helper-gen.h where needed Date: Mon, 5 Jun 2023 13:15:13 -0700 Message-Id: <20230605201548.1596865-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This had been included via tcg-op-common.h via tcg-op.h, but that is going away. In idef-parser.y, shuffle some tcg related includes into a more logical order. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hexagon/genptr.c | 1 + target/hexagon/translate.c | 1 + target/hexagon/idef-parser/idef-parser.y | 3 ++- 3 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index bcb287dd8b..217bc7bb5a 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -20,6 +20,7 @@ #include "internal.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" +#include "exec/helper-gen.h" #include "insn.h" #include "opcodes.h" #include "translate.h" diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 8838ab2364..42a7697fc9 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -20,6 +20,7 @@ #include "cpu.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" +#include "exec/helper-gen.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "internal.h" diff --git a/target/hexagon/idef-parser/idef-parser.y b/target/hexagon/idef-parser/idef-parser.y index 5c983954ed..cd2612eb8c 100644 --- a/target/hexagon/idef-parser/idef-parser.y +++ b/target/hexagon/idef-parser/idef-parser.y @@ -843,13 +843,14 @@ int main(int argc, char **argv) fputs("#include \"qemu/log.h\"\n", output_file); fputs("#include \"cpu.h\"\n", output_file); fputs("#include \"internal.h\"\n", output_file); + fputs("#include \"tcg/tcg.h\"\n", output_file); fputs("#include \"tcg/tcg-op.h\"\n", output_file); + fputs("#include \"exec/helper-gen.h\"\n", output_file); fputs("#include \"insn.h\"\n", output_file); fputs("#include \"opcodes.h\"\n", output_file); fputs("#include \"translate.h\"\n", output_file); fputs("#define QEMU_GENERATE\n", output_file); fputs("#include \"genptr.h\"\n", output_file); - fputs("#include \"tcg/tcg.h\"\n", output_file); fputs("#include \"macros.h\"\n", output_file); fprintf(output_file, "#include \"%s\"\n", argv[ARG_INDEX_EMITTER_H]); From patchwork Mon Jun 5 20:15:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689239 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2287082wru; Mon, 5 Jun 2023 13:22:25 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5C1FVLE9xCWYz89qTFTChTPFvVA9DpjjmZlTzbq6P2P31X9yzke9JpgXuXepO7mkSDuKx0 X-Received: by 2002:a05:620a:985:b0:75c:cc95:66d with SMTP id x5-20020a05620a098500b0075ccc95066dmr913913qkx.29.1685996545137; Mon, 05 Jun 2023 13:22:25 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996545; cv=none; d=google.com; s=arc-20160816; b=xDETgsHGjOo9mkAUpfcPJbpb+CAG+CZQeomDfb3uI+9fLPJ+M8hTtnR5pf6tKMa5Fh /0OgKvat9IYIijZTaHlW7lAo1xkfsq5AlJOhtdQTvWdeVG+DAlMHYWWmT0HepAyuNr/q NQDl+HgklENHInZK79z6fFnVdTC1Ro5aV+1AEpXr242pbwBKvvtr4eM/AkxqDzsvAchc gfJwnGW07JCtp5r/yT0IbU7LbNtTjUUHyJZdU8mvzB4KPHk6JlJUniDwyqStYac2OkNc ec3LGjJ50SHTQSyBxL03FDQKu0AAtWsjjHGFU7cl2AbgIOeKofqJZAt4qeSeHtMQwoKm QtLw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=d7/adIaPH4ntgaFSk3M/76lh+noxDuixny/KD9oUAVM=; b=i8hQ7A+O7LpDbpOQ9i2M9vKvoLHa40cciqXk7ipc/6fuTBn6fsLxxyLq2sjpOfTml3 0zzjOrDuuAEulexspErWp0tnqz8n/bT3eaNe87vpN1Q3gvJGrW3mBnPcrXd+KzQ47ZXA rHMPm7j5axup4/LwYLeGy/H23ldZ4+C4GLu1dp1XGF+BY0J6j5WRZJf52FOazPpIKD3L Tjwzg1qs7IyKNV+l9WUGytinELelkEAPwVjt+mb5u6fiPeQGAELENqnTam0DVk9ld9pd Or1vWOMjlUkgtpqVOxjEAGMVHVM6hzCTxZA1yhfSaUAPbRW+Nq0Q9MnU+Aqm3JRwiYrv BYSA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iTt2xUxI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c10-20020ae9e20a000000b007577bd16a23si3138946qkc.434.2023.06.05.13.22.25 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:22:25 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=iTt2xUxI; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gcd-0001t4-0G; Mon, 05 Jun 2023 16:16:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gca-0001rE-OL for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:08 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6GcY-0003hV-TR for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:08 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-655fce0f354so1323314b3a.0 for ; Mon, 05 Jun 2023 13:16:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996166; x=1688588166; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d7/adIaPH4ntgaFSk3M/76lh+noxDuixny/KD9oUAVM=; b=iTt2xUxIGQITA9UY4i9tFBj6E1zuuEtNXuPY0WpZk/HyLb0+7xBJ07KRrzoUoYCPrA 8CjhBWYjZx0wXBgUuB71KDatFCotEhypIxl4HFCLnT7oMofHoikt/gWDiPW9eyg1RI0d Xv3KWYvoibi4ccA1iraDlH5/uSNSo5NRx1lmgJeNTB2GVOq739LRRiyKZfvqnie5uLmv H6i5vFf+e4vccwWH1yMqpYdW/i5nYlQS4W+TDC4SinQl2f41vGmMXSPhkq0UL+ffQe+P qEPAFTtbaYQHTWIeZ3dzgG4+Q+WE8GCzEZGVuTurN7iGSs0srPtZZ4jVAsEzJRaxBGHZ BYpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996166; x=1688588166; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d7/adIaPH4ntgaFSk3M/76lh+noxDuixny/KD9oUAVM=; b=dRhWa79zV0vgXRSgzg8hcF+eGAWZUhi2rgoTc0C65D53Mk7iDlWyZzlQ/8UIdR/4pr BZzBqOz369w068vO98ODTbkalB8E8XbyzCK8xDT/TA3CCjGFj2CE8MV7AheN98/FPMGP XQVs6qvGqMEz2eJ0h0OA8La1JIYySLYmsylN71mmescErJVdz1Glsj0zGhd5XMkzqkA1 jHL7NGUE5NC0wt4EBRPJEdgmLIvG+0fKLbTyI+2CSUgtYJum7xGfevanRAnSz/YDdeXk erdk943zqf7hkYbjAfs94Lb9XwMuQOcLVZesXXefAFztfx03ojSy+VtlQvLWeu5BCl0Y e7qA== X-Gm-Message-State: AC+VfDw+aczkGQ0tNth67w7kKYZZBvlwmF+jOVm9WURvowMMgPrZXcFS e+ilJS+gp/uPbq9lsr7JC+sktLr5vJE+KEKImYo= X-Received: by 2002:a05:6a21:150b:b0:117:a86:6c7a with SMTP id nq11-20020a056a21150b00b001170a866c7amr138134pzb.12.1685996166141; Mon, 05 Jun 2023 13:16:06 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 18/52] tcg: Remove outdated comments in helper-head.h Date: Mon, 5 Jun 2023 13:15:14 -0700 Message-Id: <20230605201548.1596865-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/helper-head.h | 18 +++--------------- 1 file changed, 3 insertions(+), 15 deletions(-) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index f863a6ef5d..a355ef8ebe 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -1,18 +1,6 @@ -/* Helper file for declaring TCG helper functions. - Used by other helper files. - - Targets should use DEF_HELPER_N and DEF_HELPER_FLAGS_N to declare helper - functions. Names should be specified without the helper_ prefix, and - the return and argument types specified. 3 basic types are understood - (i32, i64 and ptr). Additional aliases are provided for convenience and - to match the types used by the C helper implementation. - - The target helper.h should be included in all files that use/define - helper functions. THis will ensure that function prototypes are - consistent. In addition it should be included an extra two times for - helper.c, defining: - GEN_HELPER 1 to produce op generation functions (gen_helper_*) - GEN_HELPER 2 to do runtime registration helper functions. +/* + * Helper file for declaring TCG helper functions. + * Used by other helper files. */ #ifndef EXEC_HELPER_HEAD_H From patchwork Mon Jun 5 20:15:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689261 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288356wru; Mon, 5 Jun 2023 13:26:22 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ48oBsesD6bNguOa0Bb4iLv4hcFnZFSuhnbZ8pR5egs/fmKnkSCQs3nXT23KfCvfJqZ9WO7 X-Received: by 2002:a05:620a:1b8f:b0:75d:59f0:faf with SMTP id dv15-20020a05620a1b8f00b0075d59f00fafmr978015qkb.63.1685996782584; Mon, 05 Jun 2023 13:26:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996782; cv=none; d=google.com; s=arc-20160816; b=wd3LxiEsE5pY1/Kn+wlcM4w0q44dV1zHaS4bVPHUG3aeA/KYU3DqNTJo6Y8EQXzxAY mn7dSZW9QMEaG5hGbtcpNaib2pMPiv1H4p38tK/EC5jf8TNQfDDrlq6mZzBc4nvmeQzl jBczesDfzsL/6sdXREWtZ4wvp4Y1P7lOqSqAh02BQ3kGq7K7GtMZOKjd/RFg7cqF2jWI ZEXU/CkSLPjyHVAooxr8WR/eGMwZ8gvyAm4G4MDukSGPykihhDaO7cEgs92GbJQZCzK3 FmNqOQf66LO08g51bsIH4OsrKybSlI43R/NCiFwwKa5z6fvz9qHK69gO4ynXzMCt3b3u s8Qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=mywdJxLuV7PbxTU1NspN1+FQdPIaeeESk+yMp9Ce2bA=; b=tF886zd/P7Uktr/KCFuzYBn4l1z3nT96KnfIQTjewl2G+LOZBEqF8M9G/GOrQA5uhP MuLFLkllCK9KWBAJ3n0D7TXwVCuibZPeUn2YqVRD0tIOc3GQzhHtLM58kEHpgcDstmwm T8P0EVsitkEomV3FDP0pnLVIoBfOD6rx3VrQxYH37XeAzcpVYnTeVuGdMCuik5mQXbEE OBsKQSEljWM6Qn/WJgL+G1WkLYD52z7hOMewBpSaAOA//mzUwgDGFLwWqgLY38OXaRS/ p87wfxjzi/T0OhThSwKk2QtWw5rf4bRWtPf+9hBeEtBx5Ak2gw91mpqppT3dwW9/8m3Q agKQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ne2EJgQJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id r16-20020a05620a03d000b0075eb9d6a047si1349528qkm.270.2023.06.05.13.26.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:26:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ne2EJgQJ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gcf-0001u6-Ru; Mon, 05 Jun 2023 16:16:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcc-0001s3-3T for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:10 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gca-0003wa-6B for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:09 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-651e298be3fso5056734b3a.2 for ; Mon, 05 Jun 2023 13:16:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996167; x=1688588167; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mywdJxLuV7PbxTU1NspN1+FQdPIaeeESk+yMp9Ce2bA=; b=Ne2EJgQJc91woigRXHaEw6Hn1TEkPlABz93ZqqsimW7irJ1rFWXslUXDpxQf0EY/du /4T7rDbI6HhNjuA9ADtrzrj2P7ArgRpdZfOB8jfCeBQSaZbWB+cZ/L15a/xNAtAhNPgx bgaLqMbRxrf+CK6G6CvoW6yjOzrfx1jRQ49z8FIuJumPQUM2Yh8VubToD+6YQFvEy85t Lg5VW/Ul1M76LUW+1iPTZHRsmo+xPOxABMjf7GmB5R1o9hrO9VIWIXe8nigfqvPWuAUS 8/I3C8CXwqhy5vMbDYxyZm2mWeskf7PT5r+P3c57CiCIWhxLD/RmeGl7Yr12yQCtpDJ9 0LoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996167; x=1688588167; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mywdJxLuV7PbxTU1NspN1+FQdPIaeeESk+yMp9Ce2bA=; b=UNBLoEMeCrfq0hlpteCWEN4knoa9NHL9coIjCqcg61iJlIlrgOdVOWe8CO5fuOAoeg eheRA9ISZWeTYUMDELmctTWaJBUPjL2yZrT71vYFxBspvKZ4fTBGAL4MTSpQkavhCuyx hmXoAjGERS3KNqleKTac79XObymlFdmKORxCUuzE2wmVokv6MkR7OTWr9XrjuCXZGolt hCnj1R2CJfARm1gaDjEHt9162smcGTPUY+QZDcvCwhMLHsEN3o/onxFZONBWXIocTJ94 5qzkVMur7WtW/ZoIvUr/NubXWoqNiUEaRq6zsnioDx9bJkvYWgBgqh6rhyX1/ZwcgV6/ J7wA== X-Gm-Message-State: AC+VfDx3Dl9vk39eskrVMYem0dykUKSAZgFJtjulIP7QznvYNlOcwZq7 gzQ3cL9+s+RWjpGJ4PyZROK5B9aqr5xAucZj0sM= X-Received: by 2002:a05:6a00:24c9:b0:64d:277c:77c3 with SMTP id d9-20020a056a0024c900b0064d277c77c3mr855607pfv.23.1685996166902; Mon, 05 Jun 2023 13:16:06 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 19/52] tcg: Move TCGHelperInfo and dependencies to tcg/helper-info.h Date: Mon, 5 Jun 2023 13:15:15 -0700 Message-Id: <20230605201548.1596865-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This will be required outside of tcg-internal.h soon. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/helper-info.h | 59 +++++++++++++++++++++++++++++++++++++++ tcg/tcg-internal.h | 47 +------------------------------ 2 files changed, 60 insertions(+), 46 deletions(-) create mode 100644 include/tcg/helper-info.h diff --git a/include/tcg/helper-info.h b/include/tcg/helper-info.h new file mode 100644 index 0000000000..f65f81c2e7 --- /dev/null +++ b/include/tcg/helper-info.h @@ -0,0 +1,59 @@ +/* + * TCG Helper Infomation Structure + * + * Copyright (c) 2023 Linaro Ltd + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TCG_HELPER_INFO_H +#define TCG_HELPER_INFO_H + +#ifdef CONFIG_TCG_INTERPRETER +#include +#endif + +/* + * Describe the calling convention of a given argument type. + */ +typedef enum { + TCG_CALL_RET_NORMAL, /* by registers */ + TCG_CALL_RET_BY_REF, /* for i128, by reference */ + TCG_CALL_RET_BY_VEC, /* for i128, by vector register */ +} TCGCallReturnKind; + +typedef enum { + TCG_CALL_ARG_NORMAL, /* by registers (continuing onto stack) */ + TCG_CALL_ARG_EVEN, /* like normal, but skipping odd slots */ + TCG_CALL_ARG_EXTEND, /* for i32, as a sign/zero-extended i64 */ + TCG_CALL_ARG_EXTEND_U, /* ... as a zero-extended i64 */ + TCG_CALL_ARG_EXTEND_S, /* ... as a sign-extended i64 */ + TCG_CALL_ARG_BY_REF, /* for i128, by reference, first */ + TCG_CALL_ARG_BY_REF_N, /* ... by reference, subsequent */ +} TCGCallArgumentKind; + +typedef struct TCGCallArgumentLoc { + TCGCallArgumentKind kind : 8; + unsigned arg_slot : 8; + unsigned ref_slot : 8; + unsigned arg_idx : 4; + unsigned tmp_subindex : 2; +} TCGCallArgumentLoc; + +typedef struct TCGHelperInfo { + void *func; + const char *name; +#ifdef CONFIG_TCG_INTERPRETER + ffi_cif *cif; +#endif + unsigned typemask : 32; + unsigned flags : 8; + unsigned nr_in : 8; + unsigned nr_out : 8; + TCGCallReturnKind out_kind : 8; + + /* Maximum physical arguments are constrained by TCG_TYPE_I128. */ + TCGCallArgumentLoc in[MAX_CALL_IARGS * (128 / TCG_TARGET_REG_BITS)]; +} TCGHelperInfo; + +#endif /* TCG_HELPER_INFO_H */ diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index 67b698bd5c..fbe62b31b8 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -25,55 +25,10 @@ #ifndef TCG_INTERNAL_H #define TCG_INTERNAL_H -#ifdef CONFIG_TCG_INTERPRETER -#include -#endif +#include "tcg/helper-info.h" #define TCG_HIGHWATER 1024 -/* - * Describe the calling convention of a given argument type. - */ -typedef enum { - TCG_CALL_RET_NORMAL, /* by registers */ - TCG_CALL_RET_BY_REF, /* for i128, by reference */ - TCG_CALL_RET_BY_VEC, /* for i128, by vector register */ -} TCGCallReturnKind; - -typedef enum { - TCG_CALL_ARG_NORMAL, /* by registers (continuing onto stack) */ - TCG_CALL_ARG_EVEN, /* like normal, but skipping odd slots */ - TCG_CALL_ARG_EXTEND, /* for i32, as a sign/zero-extended i64 */ - TCG_CALL_ARG_EXTEND_U, /* ... as a zero-extended i64 */ - TCG_CALL_ARG_EXTEND_S, /* ... as a sign-extended i64 */ - TCG_CALL_ARG_BY_REF, /* for i128, by reference, first */ - TCG_CALL_ARG_BY_REF_N, /* ... by reference, subsequent */ -} TCGCallArgumentKind; - -typedef struct TCGCallArgumentLoc { - TCGCallArgumentKind kind : 8; - unsigned arg_slot : 8; - unsigned ref_slot : 8; - unsigned arg_idx : 4; - unsigned tmp_subindex : 2; -} TCGCallArgumentLoc; - -typedef struct TCGHelperInfo { - void *func; - const char *name; -#ifdef CONFIG_TCG_INTERPRETER - ffi_cif *cif; -#endif - unsigned typemask : 32; - unsigned flags : 8; - unsigned nr_in : 8; - unsigned nr_out : 8; - TCGCallReturnKind out_kind : 8; - - /* Maximum physical arguments are constrained by TCG_TYPE_I128. */ - TCGCallArgumentLoc in[MAX_CALL_IARGS * (128 / TCG_TARGET_REG_BITS)]; -} TCGHelperInfo; - extern TCGContext tcg_init_ctx; extern TCGContext **tcg_ctxs; extern unsigned int tcg_cur_ctxs; From patchwork Mon Jun 5 20:15:16 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689260 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288332wru; Mon, 5 Jun 2023 13:26:18 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4ZSIem/7GcXvBJ1vjtgNYmfI6JY+tBqr3BTr0IQdG8VjqnoL9gHpp0gphdgcIEhyOdg782 X-Received: by 2002:a05:6214:b66:b0:61b:3557:a699 with SMTP id ey6-20020a0562140b6600b0061b3557a699mr12962923qvb.9.1685996778263; Mon, 05 Jun 2023 13:26:18 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996778; cv=none; d=google.com; s=arc-20160816; b=Hrzkq76kOj3Ke1NqjBdrcqo5DqvP2TJQcvvo5xjXkbdfeN5hWgQZ0GSzz5Q0aAJYzB mJNCiDQHe2D1BuptxuH/B/qdedDfoqOXiO9Qj0ayuqj8i/0vBlyxBxCzkU5vcv1NdKL0 I6h6Ye4La4seMd1fNRs+JgbNa78bpcvBi481Ncr5rIe9Ti41ZbOFX0N+f5mHj8pdJXxl 6XlZ1rs9WuS1angtmW7N4yRrETVT9/UEgum03y/Az3ZCXBZbgyUHo2WQ45XUTOJJuBLq bv85EytI7ka9lx4U8HNp5Tfa15GzdbG+o8Q+LDItTS5zbjYvjDVKgu+Yr2CJsIH/SJ1/ ++lQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=C5zXRH6RMydm6C993KqsKbt4XIAg5Irw8g60niqjjOI=; b=YJMQhgwI0tJrNzsog4qg+pAZTMxL078vDrWx2KA+1aB0DSdmK1MRu8Tw/UsLOSseO2 pF8l1Ui0GfoWFw4bShvHtf4V5inWerebHNJ9UdMlm88/zZc3pe1x4Xn/QwPtlX0ercVI o4exD6ZTDD8qR3AilUOcV+RIR2YwB4eagjt2ZxfEywjrvAqhjXahFO9vjTXSOtGqU9wn n5jXBY/26plGiFu+36e+dMPF5LblD0zQLou8XrDmjCrSEWMgQKHe9wlqii/oVosiCzjf JPyBS8CqzAeN8ae5cojIyFp+xGPxatP4NWoCkuHlvzNySgtogWBL4uoX5/G1iX+TgBDC kNRg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vsT5lUdw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q4-20020a056214194400b00626376bc967si5589826qvk.523.2023.06.05.13.26.18 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:26:18 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=vsT5lUdw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gd8-000292-SI; Mon, 05 Jun 2023 16:16:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcr-0001xa-7p for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:26 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcb-0003xV-Gh for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:24 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-652a6bf4e6aso2459292b3a.2 for ; Mon, 05 Jun 2023 13:16:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996168; x=1688588168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=C5zXRH6RMydm6C993KqsKbt4XIAg5Irw8g60niqjjOI=; b=vsT5lUdwNH6faZhHiC50WaFJ4mI0jjfqimwbgoY1Oakc1J/KYYFa+ZEzPR72B6cGQt H0+d10XF0loF2YbmyNzBeU5MglvQaVbf1hYly5dBqU11ex9axEqce4PHuoolSirCi/Yh 1MfE+ZsXd8DN/CN6XEfZuCH/OoTqM8y1wZKbzpaiD5N/hyH5dGowwfvCepW6z6CDdejO 0dBud9xXGrVSDPn4Ldqfx6iRZyn6hKYRGzypeU9bjdljaOIaRwbmCFhwsco48Tx/SPIc vstwdMuYeGgyqyERD8ZUVtE06XGYFMMb7h5QmJP20tVrF9/DskD4kub+QGHZjyssxShB +CJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996168; x=1688588168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=C5zXRH6RMydm6C993KqsKbt4XIAg5Irw8g60niqjjOI=; b=AOk9qhOqgYAUSeFboTcddyjtIE9y0V4E0aD0NmvHZbEE3CcpsRalEN0EWtBpJOec7V hEr7e5mrPniPdaG0DaJu1cgnzgW9EGDQ4ms6mnJmkieFsHO+IfHf85X8Dzx0Ra8GaKCE HetsYpIIwf0Je3bv7jyj8bMYxQJQzNI+A2wy/GGm6LB49crdnHTStEJokyJofklDk9O8 ham7ObHC9hi8cgvxNcSNQpYfe8WbEMz3CRMsGdTde4yFjDr2I63vyJAFGsq+rG2TA7Ss qsvzprRM+QrXFWLV/bMddrUy///wpykJ4bWsaG1dpTdWx8Q9xkrYDT5oQSKb+kWb+TTe BUoA== X-Gm-Message-State: AC+VfDwORVRwCvP5UvWJ+zD4xQ5uh1LOhb7u3NLY+ULRcjp8q+v89BxY 9aFxTC4ONhXMnDkmg5fH/UBU8ELsZDf84sUERpc= X-Received: by 2002:a05:6a20:6a0a:b0:10f:7abd:fe5e with SMTP id p10-20020a056a206a0a00b0010f7abdfe5emr94620pzk.40.1685996167752; Mon, 05 Jun 2023 13:16:07 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PULL 20/52] tcg: Pass TCGHelperInfo to tcg_gen_callN Date: Mon, 5 Jun 2023 13:15:16 -0700 Message-Id: <20230605201548.1596865-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org In preparation for compiling tcg/ only once, eliminate the all_helpers array. Instantiate the info structs for the generic helpers in accel/tcg/, and the structs for the target-specific helpers in each translate.c. Since we don't see all of the info structs at startup, initialize at first use, using g_once_init_* to make sure we don't race while doing so. Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson --- MAINTAINERS | 1 + include/exec/helper-gen.h | 66 ++++++++++++-------- include/exec/helper-tcg.h | 75 ----------------------- include/qemu/typedefs.h | 1 + include/tcg/helper-info.h | 9 ++- include/tcg/tcg.h | 2 +- accel/tcg/plugin-gen.c | 5 ++ accel/tcg/tcg-runtime.c | 4 ++ target/alpha/translate.c | 3 + target/arm/tcg/translate.c | 3 + target/avr/translate.c | 5 ++ target/cris/translate.c | 6 +- target/hexagon/translate.c | 4 ++ target/hppa/translate.c | 5 ++ target/i386/tcg/translate.c | 5 ++ target/loongarch/translate.c | 4 ++ target/m68k/translate.c | 3 + target/microblaze/translate.c | 4 ++ target/mips/tcg/translate.c | 5 ++ target/nios2/translate.c | 5 ++ target/openrisc/translate.c | 5 ++ target/ppc/translate.c | 4 ++ target/riscv/translate.c | 4 ++ target/rx/translate.c | 5 ++ target/s390x/tcg/translate.c | 4 ++ target/sh4/translate.c | 4 ++ target/sparc/translate.c | 3 + target/tricore/translate.c | 5 ++ target/xtensa/translate.c | 4 ++ tcg/tcg.c | 108 ++++++++++++--------------------- include/exec/helper-info.c.inc | 96 +++++++++++++++++++++++++++++ 31 files changed, 282 insertions(+), 175 deletions(-) delete mode 100644 include/exec/helper-tcg.h create mode 100644 include/exec/helper-info.c.inc diff --git a/MAINTAINERS b/MAINTAINERS index 89f274f85e..a1b8376f4c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -154,6 +154,7 @@ F: include/exec/exec-all.h F: include/exec/tb-flush.h F: include/exec/target_long.h F: include/exec/helper*.h +F: include/exec/helper-info.c.inc F: include/sysemu/cpus.h F: include/sysemu/tcg.h F: include/hw/core/tcg-cpu-ops.h diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h index 7b6ca975ef..248cff3351 100644 --- a/include/exec/helper-gen.h +++ b/include/exec/helper-gen.h @@ -1,81 +1,96 @@ -/* Helper file for declaring TCG helper functions. - This one expands generation functions for tcg opcodes. */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Helper file for declaring TCG helper functions. + * This one expands generation functions for tcg opcodes. + * Define HELPER_H for the header file to be expanded, + * and static inline to change from global file scope. + */ #ifndef HELPER_GEN_H #define HELPER_GEN_H +#include "tcg/tcg.h" +#include "tcg/helper-info.h" #include "exec/helper-head.h" #define DEF_HELPER_FLAGS_0(name, flags, ret) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ { \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 0, NULL); \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 0, NULL); \ } #define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1)) \ { \ - TCGTemp *args[1] = { dh_arg(t1, 1) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 1, args); \ + TCGTemp *args[1] = { dh_arg(t1, 1) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 1, args); \ } #define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ { \ - TCGTemp *args[2] = { dh_arg(t1, 1), dh_arg(t2, 2) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 2, args); \ + TCGTemp *args[2] = { dh_arg(t1, 1), dh_arg(t2, 2) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 2, args); \ } #define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ { \ - TCGTemp *args[3] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 3, args); \ + TCGTemp *args[3] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 3, args); \ } #define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \ { \ - TCGTemp *args[4] = { dh_arg(t1, 1), dh_arg(t2, 2), \ - dh_arg(t3, 3), dh_arg(t4, 4) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 4, args); \ + TCGTemp *args[4] = { dh_arg(t1, 1), dh_arg(t2, 2), \ + dh_arg(t3, 3), dh_arg(t4, 4) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 4, args); \ } #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \ { \ - TCGTemp *args[5] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 5, args); \ + TCGTemp *args[5] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 5, args); \ } #define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \ { \ - TCGTemp *args[6] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 6, args); \ + TCGTemp *args[6] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 6, args); \ } #define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\ +extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \ dh_arg_decl(t7, 7)) \ { \ - TCGTemp *args[7] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \ - dh_arg(t7, 7) }; \ - tcg_gen_callN(HELPER(name), dh_retvar(ret), 7, args); \ + TCGTemp *args[7] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \ + dh_arg(t7, 7) }; \ + tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 7, args); \ } #include "helper.h" @@ -90,6 +105,5 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ #undef DEF_HELPER_FLAGS_5 #undef DEF_HELPER_FLAGS_6 #undef DEF_HELPER_FLAGS_7 -#undef GEN_HELPER #endif /* HELPER_GEN_H */ diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h deleted file mode 100644 index 3933258f1a..0000000000 --- a/include/exec/helper-tcg.h +++ /dev/null @@ -1,75 +0,0 @@ -/* Helper file for declaring TCG helper functions. - This one defines data structures private to tcg.c. */ - -#ifndef HELPER_TCG_H -#define HELPER_TCG_H - -#include "exec/helper-head.h" - -/* Need one more level of indirection before stringification - to get all the macros expanded first. */ -#define str(s) #s - -#define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .typemask = dh_typemask(ret, 0) }, - -#define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) }, - -#define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \ - | dh_typemask(t2, 2) }, - -#define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \ - | dh_typemask(t2, 2) | dh_typemask(t3, 3) }, - -#define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \ - | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) }, - -#define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \ - | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \ - | dh_typemask(t5, 5) }, - -#define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ - { .func = HELPER(NAME), .name = str(NAME), \ - .flags = FLAGS | dh_callflag(ret), \ - .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \ - | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \ - | dh_typemask(t5, 5) | dh_typemask(t6, 6) }, - -#define DEF_HELPER_FLAGS_7(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6, t7) \ - { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \ - .typemask = dh_typemask(ret, 0) | dh_typemask(t1, 1) \ - | dh_typemask(t2, 2) | dh_typemask(t3, 3) | dh_typemask(t4, 4) \ - | dh_typemask(t5, 5) | dh_typemask(t6, 6) | dh_typemask(t7, 7) }, - -#include "helper.h" -#include "accel/tcg/tcg-runtime.h" -#include "accel/tcg/plugin-helpers.h" - -#undef str -#undef DEF_HELPER_FLAGS_0 -#undef DEF_HELPER_FLAGS_1 -#undef DEF_HELPER_FLAGS_2 -#undef DEF_HELPER_FLAGS_3 -#undef DEF_HELPER_FLAGS_4 -#undef DEF_HELPER_FLAGS_5 -#undef DEF_HELPER_FLAGS_6 -#undef DEF_HELPER_FLAGS_7 - -#endif /* HELPER_TCG_H */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index 8e9ef252f5..8c1840bfc1 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -131,6 +131,7 @@ typedef struct ReservedRegion ReservedRegion; typedef struct SavedIOTLB SavedIOTLB; typedef struct SHPCDevice SHPCDevice; typedef struct SSIBus SSIBus; +typedef struct TCGHelperInfo TCGHelperInfo; typedef struct TranslationBlock TranslationBlock; typedef struct VirtIODevice VirtIODevice; typedef struct Visitor Visitor; diff --git a/include/tcg/helper-info.h b/include/tcg/helper-info.h index f65f81c2e7..4b6c9b43e8 100644 --- a/include/tcg/helper-info.h +++ b/include/tcg/helper-info.h @@ -40,12 +40,17 @@ typedef struct TCGCallArgumentLoc { unsigned tmp_subindex : 2; } TCGCallArgumentLoc; -typedef struct TCGHelperInfo { +struct TCGHelperInfo { void *func; const char *name; + + /* Used with g_once_init_enter. */ #ifdef CONFIG_TCG_INTERPRETER ffi_cif *cif; +#else + uintptr_t init; #endif + unsigned typemask : 32; unsigned flags : 8; unsigned nr_in : 8; @@ -54,6 +59,6 @@ typedef struct TCGHelperInfo { /* Maximum physical arguments are constrained by TCG_TYPE_I128. */ TCGCallArgumentLoc in[MAX_CALL_IARGS * (128 / TCG_TARGET_REG_BITS)]; -} TCGHelperInfo; +}; #endif /* TCG_HELPER_INFO_H */ diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 9b2833b31d..34035dab81 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -937,7 +937,7 @@ typedef struct TCGTargetOpDef { bool tcg_op_supported(TCGOpcode op); -void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args); +void tcg_gen_callN(TCGHelperInfo *, TCGTemp *ret, int nargs, TCGTemp **args); TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); void tcg_op_remove(TCGContext *s, TCGOp *op); diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 5b73a39ce5..40b34a0403 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -49,6 +49,11 @@ #include "exec/exec-all.h" #include "exec/plugin-gen.h" #include "exec/translator.h" +#include "exec/helper-proto.h" + +#define HELPER_H "accel/tcg/plugin-helpers.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H #ifdef CONFIG_SOFTMMU # define CONFIG_SOFTMMU_GATE 1 diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index e4e030043f..14b59a36e5 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -31,6 +31,10 @@ #include "exec/log.h" #include "tcg/tcg.h" +#define HELPER_H "accel/tcg/tcg-runtime.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + /* 32-bit helpers */ int32_t HELPER(div_i32)(int32_t arg1, int32_t arg2) diff --git a/target/alpha/translate.c b/target/alpha/translate.c index be8adb2526..545e5743c3 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -30,6 +30,9 @@ #include "exec/translator.h" #include "exec/log.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H #undef ALPHA_DEBUG_DISAS #define CONFIG_SOFTFLOAT_INLINE diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index c89825ad6a..4d84850d74 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -33,6 +33,9 @@ #include "exec/log.h" #include "cpregs.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T) #define ENABLE_ARCH_5 arm_dc_feature(s, ARM_FEATURE_V5) diff --git a/target/avr/translate.c b/target/avr/translate.c index cd82f5d591..4fa40b568a 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -31,6 +31,11 @@ #include "exec/translator.h" #include "exec/gen-icount.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + /* * Define if you want a BREAK instruction translated to a breakpoint * Active debugging connection is assumed diff --git a/target/cris/translate.c b/target/cris/translate.c index b2beb9964d..3c21826cc2 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -34,11 +34,13 @@ #include "exec/translator.h" #include "crisv32-decode.h" #include "qemu/qemu-print.h" - #include "exec/helper-gen.h" - #include "exec/log.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + #define DISAS_CRIS 0 #if DISAS_CRIS diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 42a7697fc9..00e25035ce 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -31,6 +31,10 @@ #include "genptr.h" #include "printinsn.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + #include "analyze_funcs_generated.c.inc" typedef void (*AnalyzeInsn)(DisasContext *ctx); diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 59e4688bfa..2c50fa72c3 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -29,6 +29,11 @@ #include "exec/translator.h" #include "exec/log.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + /* Since we have a distinction between register size and address size, we need to redefine all of these. */ diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index 91c9c0c478..d509105505 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -34,6 +34,11 @@ #include "exec/log.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + #define PREFIX_REPZ 0x01 #define PREFIX_REPNZ 0x02 #define PREFIX_LOCK 0x04 diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index ae53f5ee9d..67140ada56 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -26,6 +26,10 @@ static TCGv cpu_lladdr, cpu_llval; #include "exec/gen-icount.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 #define DISAS_EXIT_UPDATE DISAS_TARGET_2 diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 44d852b106..90ca51fb9e 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -34,6 +34,9 @@ #include "exec/log.h" #include "fpu/softfloat.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H //#define DEBUG_DISPATCH 1 diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index ee0d7b81ad..7a5d1066da 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -31,6 +31,10 @@ #include "exec/log.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + #define EXTRACT_FIELD(src, start, end) \ (((src) >> start) & ((1 << (end - start + 1)) - 1)) diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index a6ca2e5a3b..bff1859b86 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -37,6 +37,11 @@ #include "fpu_helper.h" #include "translate.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + /* * Many sysemu-only helpers are not reachable for user-only. * Define stub generators here, so that we need not either sprinkle diff --git a/target/nios2/translate.c b/target/nios2/translate.c index a548e16ed5..28c1d700e1 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -35,6 +35,11 @@ #include "exec/gen-icount.h" #include "semihosting/semihost.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + /* is_jmp field values */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */ diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 43ba0cc1ad..06e6eae952 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -35,6 +35,11 @@ #include "exec/log.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + /* is_jmp field values */ #define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */ #define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */ diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 9b7884586c..67d7ee0a70 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -41,6 +41,10 @@ #include "qemu/qemu-print.h" #include "qapi/error.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + #define CPU_SINGLE_STEP 0x1 #define CPU_BRANCH_STEP 0x2 diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 928da0d3f0..ed968162da 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -33,6 +33,10 @@ #include "instmap.h" #include "internals.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + /* global register indices */ static TCGv cpu_gpr[32], cpu_gprh[32], cpu_pc, cpu_vl, cpu_vstart; static TCGv_i64 cpu_fpr[32]; /* assume F and D extensions */ diff --git a/target/rx/translate.c b/target/rx/translate.c index 70fad98e93..89dbec26f9 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -28,6 +28,11 @@ #include "exec/translator.h" #include "exec/log.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + typedef struct DisasContext { DisasContextBase base; CPURXState *env; diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 3eb3708d55..60b17585a7 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -46,6 +46,10 @@ #include "exec/log.h" #include "qemu/atomic128.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + /* Information that (most) every instruction needs to manipulate. */ typedef struct DisasContext DisasContext; diff --git a/target/sh4/translate.c b/target/sh4/translate.c index d9accfa1e7..9d2c7a3337 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -29,6 +29,10 @@ #include "exec/log.h" #include "qemu/qemu-print.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + typedef struct DisasContext { DisasContextBase base; diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 9377798490..ebaf376500 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -33,6 +33,9 @@ #include "exec/log.h" #include "asi.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H #define DYNAMIC_PC 1 /* dynamic pc value */ #define JUMP_PC 2 /* dynamic pc value which takes only two values diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 2646cb3eb5..eee935bbaf 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -33,6 +33,11 @@ #include "exec/translator.h" #include "exec/log.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + + /* * TCG registers */ diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 728aeebebf..11bb8c079b 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -45,6 +45,10 @@ #include "exec/log.h" +#define HELPER_H "helper.h" +#include "exec/helper-info.c.inc" +#undef HELPER_H + struct DisasContext { DisasContextBase base; diff --git a/tcg/tcg.c b/tcg/tcg.c index e13d0a6f09..ffd3ccaff7 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -848,13 +848,6 @@ void tcg_pool_reset(TCGContext *s) s->pool_current = NULL; } -#include "exec/helper-proto.h" - -static TCGHelperInfo all_helpers[] = { -#include "exec/helper-tcg.h" -}; -static GHashTable *helper_table; - /* * Create TCGHelperInfo structures for "tcg/tcg-ldst.h" functions, * akin to what "exec/helper-tcg.h" does with DEF_HELPER_FLAGS_N. @@ -964,57 +957,45 @@ static ffi_type *typecode_to_ffi(int argmask) g_assert_not_reached(); } -static void init_ffi_layouts(void) +static ffi_cif *init_ffi_layout(TCGHelperInfo *info) { - /* g_direct_hash/equal for direct comparisons on uint32_t. */ - GHashTable *ffi_table = g_hash_table_new(NULL, NULL); + unsigned typemask = info->typemask; + struct { + ffi_cif cif; + ffi_type *args[]; + } *ca; + ffi_status status; + int nargs; - for (int i = 0; i < ARRAY_SIZE(all_helpers); ++i) { - TCGHelperInfo *info = &all_helpers[i]; - unsigned typemask = info->typemask; - gpointer hash = (gpointer)(uintptr_t)typemask; - struct { - ffi_cif cif; - ffi_type *args[]; - } *ca; - ffi_status status; - int nargs; - ffi_cif *cif; + /* Ignoring the return type, find the last non-zero field. */ + nargs = 32 - clz32(typemask >> 3); + nargs = DIV_ROUND_UP(nargs, 3); + assert(nargs <= MAX_CALL_IARGS); - cif = g_hash_table_lookup(ffi_table, hash); - if (cif) { - info->cif = cif; - continue; + ca = g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); + ca->cif.rtype = typecode_to_ffi(typemask & 7); + ca->cif.nargs = nargs; + + if (nargs != 0) { + ca->cif.arg_types = ca->args; + for (int j = 0; j < nargs; ++j) { + int typecode = extract32(typemask, (j + 1) * 3, 3); + ca->args[j] = typecode_to_ffi(typecode); } - - /* Ignoring the return type, find the last non-zero field. */ - nargs = 32 - clz32(typemask >> 3); - nargs = DIV_ROUND_UP(nargs, 3); - assert(nargs <= MAX_CALL_IARGS); - - ca = g_malloc0(sizeof(*ca) + nargs * sizeof(ffi_type *)); - ca->cif.rtype = typecode_to_ffi(typemask & 7); - ca->cif.nargs = nargs; - - if (nargs != 0) { - ca->cif.arg_types = ca->args; - for (int j = 0; j < nargs; ++j) { - int typecode = extract32(typemask, (j + 1) * 3, 3); - ca->args[j] = typecode_to_ffi(typecode); - } - } - - status = ffi_prep_cif(&ca->cif, FFI_DEFAULT_ABI, nargs, - ca->cif.rtype, ca->cif.arg_types); - assert(status == FFI_OK); - - cif = &ca->cif; - info->cif = cif; - g_hash_table_insert(ffi_table, hash, (gpointer)cif); } - g_hash_table_destroy(ffi_table); + status = ffi_prep_cif(&ca->cif, FFI_DEFAULT_ABI, nargs, + ca->cif.rtype, ca->cif.arg_types); + assert(status == FFI_OK); + + return &ca->cif; } + +#define HELPER_INFO_INIT(I) (&(I)->cif) +#define HELPER_INFO_INIT_VAL(I) init_ffi_layout(I) +#else +#define HELPER_INFO_INIT(I) (&(I)->init) +#define HELPER_INFO_INIT_VAL(I) 1 #endif /* CONFIG_TCG_INTERPRETER */ static inline bool arg_slot_reg_p(unsigned arg_slot) @@ -1327,16 +1308,6 @@ static void tcg_context_init(unsigned max_cpus) args_ct += n; } - /* Register helpers. */ - /* Use g_direct_hash/equal for direct pointer comparisons on func. */ - helper_table = g_hash_table_new(NULL, NULL); - - for (i = 0; i < ARRAY_SIZE(all_helpers); ++i) { - init_call_layout(&all_helpers[i]); - g_hash_table_insert(helper_table, (gpointer)all_helpers[i].func, - (gpointer)&all_helpers[i]); - } - init_call_layout(&info_helper_ld32_mmu); init_call_layout(&info_helper_ld64_mmu); init_call_layout(&info_helper_ld128_mmu); @@ -1344,10 +1315,6 @@ static void tcg_context_init(unsigned max_cpus) init_call_layout(&info_helper_st64_mmu); init_call_layout(&info_helper_st128_mmu); -#ifdef CONFIG_TCG_INTERPRETER - init_ffi_layouts(); -#endif - tcg_target_init(s); process_op_defs(s); @@ -2141,15 +2108,18 @@ bool tcg_op_supported(TCGOpcode op) static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs); -void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) +void tcg_gen_callN(TCGHelperInfo *info, TCGTemp *ret, int nargs, TCGTemp **args) { - const TCGHelperInfo *info; TCGv_i64 extend_free[MAX_CALL_IARGS]; int n_extend = 0; TCGOp *op; int i, n, pi = 0, total_args; - info = g_hash_table_lookup(helper_table, (gpointer)func); + if (unlikely(g_once_init_enter(HELPER_INFO_INIT(info)))) { + init_call_layout(info); + g_once_init_leave(HELPER_INFO_INIT(info), HELPER_INFO_INIT_VAL(info)); + } + total_args = info->nr_out + info->nr_in + 2; op = tcg_op_alloc(INDEX_op_call, total_args); @@ -2216,7 +2186,7 @@ void tcg_gen_callN(void *func, TCGTemp *ret, int nargs, TCGTemp **args) g_assert_not_reached(); } } - op->args[pi++] = (uintptr_t)func; + op->args[pi++] = (uintptr_t)info->func; op->args[pi++] = (uintptr_t)info; tcg_debug_assert(pi == total_args); diff --git a/include/exec/helper-info.c.inc b/include/exec/helper-info.c.inc new file mode 100644 index 0000000000..530d2e6d35 --- /dev/null +++ b/include/exec/helper-info.c.inc @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Helper file for declaring TCG helper functions. + * This one expands info structures for tcg helpers. + * Define HELPER_H for the header file to be expanded. + */ + +#include "tcg/tcg.h" +#include "tcg/helper-info.h" +#include "exec/helper-head.h" + +/* + * Need one more level of indirection before stringification + * to get all the macros expanded first. + */ +#define str(s) #s + +#define DEF_HELPER_FLAGS_0(NAME, FLAGS, RET) \ + TCGHelperInfo glue(helper_info_, NAME) = { \ + .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(RET), \ + .typemask = dh_typemask(RET, 0) \ + }; + +#define DEF_HELPER_FLAGS_1(NAME, FLAGS, RET, T1) \ + TCGHelperInfo glue(helper_info_, NAME) = { \ + .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(RET), \ + .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + }; + +#define DEF_HELPER_FLAGS_2(NAME, FLAGS, RET, T1, T2) \ + TCGHelperInfo glue(helper_info_, NAME) = { \ + .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(RET), \ + .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + | dh_typemask(T2, 2) \ + }; + +#define DEF_HELPER_FLAGS_3(NAME, FLAGS, RET, T1, T2, T3) \ + TCGHelperInfo glue(helper_info_, NAME) = { \ + .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(RET), \ + .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + | dh_typemask(T2, 2) | dh_typemask(T3, 3) \ + }; + +#define DEF_HELPER_FLAGS_4(NAME, FLAGS, RET, T1, T2, T3, T4) \ + TCGHelperInfo glue(helper_info_, NAME) = { \ + .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(RET), \ + .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + | dh_typemask(T2, 2) | dh_typemask(T3, 3) \ + | dh_typemask(T4, 4) \ + }; + +#define DEF_HELPER_FLAGS_5(NAME, FLAGS, RET, T1, T2, T3, T4, T5) \ + TCGHelperInfo glue(helper_info_, NAME) = { \ + .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(RET), \ + .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + | dh_typemask(T2, 2) | dh_typemask(T3, 3) \ + | dh_typemask(T4, 4) | dh_typemask(T5, 5) \ + }; + +#define DEF_HELPER_FLAGS_6(NAME, FLAGS, RET, T1, T2, T3, T4, T5, T6) \ + TCGHelperInfo glue(helper_info_, NAME) = { \ + .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(RET), \ + .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + | dh_typemask(T2, 2) | dh_typemask(T3, 3) \ + | dh_typemask(T4, 4) | dh_typemask(T5, 5) \ + | dh_typemask(T6, 6) \ + }; + +#define DEF_HELPER_FLAGS_7(NAME, FLAGS, RET, T1, T2, T3, T4, T5, T6, T7) \ + TCGHelperInfo glue(helper_info_, NAME) = { \ + .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(RET), \ + .typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \ + | dh_typemask(T2, 2) | dh_typemask(T3, 3) \ + | dh_typemask(T4, 4) | dh_typemask(T5, 5) \ + | dh_typemask(T6, 6) | dh_typemask(T7, 7) \ + }; + +#include HELPER_H + +#undef str +#undef DEF_HELPER_FLAGS_0 +#undef DEF_HELPER_FLAGS_1 +#undef DEF_HELPER_FLAGS_2 +#undef DEF_HELPER_FLAGS_3 +#undef DEF_HELPER_FLAGS_4 +#undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 +#undef DEF_HELPER_FLAGS_7 From patchwork Mon Jun 5 20:15:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689224 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2285154wru; Mon, 5 Jun 2023 13:16:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ57RptL0/0VagVvBXzQDc1a0/TJWWkEg43U3iGq99jUcj9g5vf+OxADwwym3EOy9qF9jAFJ X-Received: by 2002:a05:6214:230f:b0:62b:3812:46bd with SMTP id gc15-20020a056214230f00b0062b381246bdmr8413996qvb.26.1685996199374; Mon, 05 Jun 2023 13:16:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996199; cv=none; d=google.com; s=arc-20160816; b=NjX0/IiNZnDdrVx8Lzfanymr+Y37ldbYyQwJ+QaJV50ywJhLQLb+G71uZM78s8hkfl 6DB3FQXsSXt3yIOy3ZACfAWxY0UXq3Y0qPYpMtFtvul1F/PKPqqDZke5kl8xLtF4dox8 uVfcS9B6Eom+eeMgQkADEDqmKOY+3Cg67IIho+WY0DjpdgMnn5Xr/jn5HPRzq6iJt23y t1P/bEoWCrtYmLL7FKH7JgqAWkV6EwJ/I/4kY9Sd+2hk63cn0gTm43dPZjz5X+nCmbrz pQx2JhJHC8akhhFrvs7CSiAV71584uFsYncp3SxCFIafiSVUqotCVaRnveuFk1PunqwJ iOsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+RwbeHiXrnAwWu35QTng9LeorJuoL8zzpp/ed/KIDaE=; b=n0axb9+JwflGrzI52TbhlteJAPzrchmCdFFq2+QOEi6+6g05vdBek3VC1gMoAJLt1Q XmKVz9fvVgo6jAuhkOVzwVmcHPZKo5UE8W9Mo3/iK0ui+4yLlVe1tDlImUePaaRfj1FJ FykcRWuslNPPPPtK3dwYRqBWmVgqgwJ82pI6VrNnt0FcNQ7MqCefwH+80ErTQTaqx4Vh JWWFeN2z+lZc+9ZAlwEWhZfDVPNOptshV+HAzPkbF5kU5eyJJ8IGSgNWfJ2xWv9i8hjF fNBU4WGm92bz4nxfiv/u36Ic7uTVk376j2WvtIWHW3iVqcmyii9CFtAybzvPhWJxgAbc oZQg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GeqpQYS7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id q8-20020ad45ca8000000b005a3906055f8si5413286qvh.169.2023.06.05.13.16.39 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:16:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=GeqpQYS7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gch-0001uU-Ov; Mon, 05 Jun 2023 16:16:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcf-0001u7-RT for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:13 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcc-0003xz-Ck for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:12 -0400 Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-53482b44007so2781208a12.2 for ; Mon, 05 Jun 2023 13:16:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996168; x=1688588168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+RwbeHiXrnAwWu35QTng9LeorJuoL8zzpp/ed/KIDaE=; b=GeqpQYS77kmofs43PQ3ezkiRbxIvKgZ5vsvR3SIH70LrWHJGjShj8seZnR6DMO2s55 AHTpBCVLgIdhwFDyoEhliOLdOZNo810jmT48WcPTtY04whuQhxl17u9Zp/wvsTv9yIwi ozQ/TAtN+qxKf1a6tVxG2L973Wfh+IRiRKMzfdkufbzcGu9YCXi/I3qw2hblVNVxNDxW SWXhdae1YIs8KwoHF8aGPmgpwAouuS1X4MWMlx6MzjisdPMaEBOhKQ1tYNNW2Cuzuehg Y9ehgpmCXZdlgMd9OBWCGIPUsw00FEMNLq5K0cnDEq/Jzk5m3I38l0jyqg3JwNmhzPsR Yl+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996168; x=1688588168; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+RwbeHiXrnAwWu35QTng9LeorJuoL8zzpp/ed/KIDaE=; b=Thex/7EsoAePIcRimj/bgnk3TGrJOfCElH3d8g79eizHLayDxG+gxyaBRs1S001Krj VZIjyOfkHQJkUHD2UPm3SXAgawfCXJKYOENqbCRunNdSyTgk5rekooHVSD4Ycx/BF3vl 2XldW571Ay1topvUT69/h/w3NotNn2/AqxRvVdJHCJ03uuCe98b43uB19IfPKV+E3tz3 kCc0d8Ssg9/iRGEePcLF3otyh1PYwqh46TGekNbSlAUHoym4Src8Be8JPkdDbRZvaYPo wuxbbofH0G+rnD0ro6MvGq43PyQMgsDDvyiRICzImRAG4/6efI80q2+wPvMOiKpDp6/g Ml1g== X-Gm-Message-State: AC+VfDy4OwbJAC4x+s8x8yb72tXNApsUzZmWsQPTIH5sDNNocId2MdUD 7OU7Y+v3XTcoZX14kl1M3AbgIv4GcnbuTiw/CIA= X-Received: by 2002:a05:6a21:338b:b0:10e:43e:e223 with SMTP id yy11-20020a056a21338b00b0010e043ee223mr225847pzb.1.1685996168518; Mon, 05 Jun 2023 13:16:08 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 21/52] tcg: Move temp_idx and tcgv_i32_temp debug out of line Date: Mon, 5 Jun 2023 13:15:17 -0700 Message-Id: <20230605201548.1596865-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Removes a multiplicity of calls to __assert_fail, saving up to 360kiB of .text space as measured on an x86_64 host. Old New Less %Change 9257272 8888680 368592 3.98% qemu-system-aarch64 6100968 5911832 189136 3.10% qemu-system-riscv64 5839112 5707032 132080 2.26% qemu-system-mips 4447608 4341752 105856 2.38% qemu-system-s390x Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 30 ++++++++++++++++-------------- tcg/tcg.c | 19 +++++++++++++++++++ 2 files changed, 35 insertions(+), 14 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 34035dab81..64c10a63f3 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -630,13 +630,6 @@ static inline void *tcg_splitwx_to_rw(const void *rx) } #endif -static inline size_t temp_idx(TCGTemp *ts) -{ - ptrdiff_t n = ts - tcg_ctx->temps; - tcg_debug_assert(n >= 0 && n < tcg_ctx->nb_temps); - return n; -} - static inline TCGArg temp_arg(TCGTemp *ts) { return (uintptr_t)ts; @@ -647,16 +640,25 @@ static inline TCGTemp *arg_temp(TCGArg a) return (TCGTemp *)(uintptr_t)a; } -/* Using the offset of a temporary, relative to TCGContext, rather than - its index means that we don't use 0. That leaves offset 0 free for - a NULL representation without having to leave index 0 unused. */ +#ifdef CONFIG_DEBUG_TCG +size_t temp_idx(TCGTemp *ts); +TCGTemp *tcgv_i32_temp(TCGv_i32 v); +#else +static inline size_t temp_idx(TCGTemp *ts) +{ + return ts - tcg_ctx->temps; +} + +/* + * Using the offset of a temporary, relative to TCGContext, rather than + * its index means that we don't use 0. That leaves offset 0 free for + * a NULL representation without having to leave index 0 unused. + */ static inline TCGTemp *tcgv_i32_temp(TCGv_i32 v) { - uintptr_t o = (uintptr_t)v; - TCGTemp *t = (void *)tcg_ctx + o; - tcg_debug_assert(offsetof(TCGContext, temps[temp_idx(t)]) == o); - return t; + return (void *)tcg_ctx + (uintptr_t)v; } +#endif static inline TCGTemp *tcgv_i64_temp(TCGv_i64 v) { diff --git a/tcg/tcg.c b/tcg/tcg.c index ffd3ccaff7..59624fceec 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1800,6 +1800,25 @@ TCGv_vec tcg_constant_vec_matching(TCGv_vec match, unsigned vece, int64_t val) return tcg_constant_vec(t->base_type, vece, val); } +#ifdef CONFIG_DEBUG_TCG +size_t temp_idx(TCGTemp *ts) +{ + ptrdiff_t n = ts - tcg_ctx->temps; + assert(n >= 0 && n < tcg_ctx->nb_temps); + return n; +} + +TCGTemp *tcgv_i32_temp(TCGv_i32 v) +{ + uintptr_t o = (uintptr_t)v - offsetof(TCGContext, temps); + + assert(o < sizeof(TCGTemp) * tcg_ctx->nb_temps); + assert(o % sizeof(TCGTemp) == 0); + + return (void *)tcg_ctx + (uintptr_t)v; +} +#endif /* CONFIG_DEBUG_TCG */ + /* Return true if OP may appear in the opcode stream. Test the runtime variable that controls each opcode. */ bool tcg_op_supported(TCGOpcode op) From patchwork Mon Jun 5 20:15:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689270 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288961wru; Mon, 5 Jun 2023 13:28:07 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5UolhDzDxMTbgNC8HuIdv8yfu7WfIaNEJo+wPVYWn7lcbvSKzfLaI2cHKLPdUb3hj7Rhq+ X-Received: by 2002:a05:620a:8e12:b0:75e:b914:3659 with SMTP id re18-20020a05620a8e1200b0075eb9143659mr700062qkn.32.1685996886783; Mon, 05 Jun 2023 13:28:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996886; cv=none; d=google.com; s=arc-20160816; b=CIWDVIYcD1/+6VMXn10cDih3c+7mjFPOwHUYy60pqmJSxHxIDVPDROmM+IjySjssfw WL5akwiXFoJIU0OyCTbwq5ubhN/D+M/Jj//NAdInHfQu5dKbZu1eTF6LVB1Etd2pvnIc jWTrYQF8uyVpNkGvQedDlSXQ9alpY/NgZYH+p70OgI2w3Y3JuwBcfbD86ulI7zxgtElj wYSi7L1Kn6IJKxHfBQjiITjDE0evut/RWucdB04OsDyqqjQc/9ffdt8Jk+LYjnmm31D3 amyQj/VSdA+RBP/3eggNnLJR7DCAe78X+1blzcb6gq/fyHtpN7kwgFMxHx1Q36nIdrie 7OqA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QuKcmQB095cKvyXtd0GqYuNL/df36qhJFKRlq23RlvQ=; b=mVYNZGHkgRewXJWVF/rBnTqOZIDtE+kOU40Yha4qALJgYfpUzgPHaI3SLpAQRDfL9y C4uCwCpNxo3NvK8fk2rruWsrB+Tiurel3iMEUm7mXPlo3p1arTpMdlu2/yq0bzYUOLVO mMVzos5JdDiYNfxAD7syDrAgLG2GmI4PDpKAbgxWtBJ1h06DZEuBI1qy/XXPs5Yy99wP m1Ewgf7naUn58WvK6SV0zZrTbBlMaCjhPKe7WUY6SyIjUbCsabTwKKKVtAbhAU4YgKrh gG283YyOSKK7dm42WlezeWd62SVjqx6/rKfBcSPDGgfG/DstHsJlJfBlQQbq+Yfnmqzu J5rg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N6s0qx+6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id m25-20020ae9e019000000b0075b367f2c98si4974141qkk.85.2023.06.05.13.28.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:28:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N6s0qx+6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GdD-0002Ew-FG; Mon, 05 Jun 2023 16:16:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcr-0001xh-OA for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:26 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcc-0003yp-SF for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:25 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-656923b7c81so1295831b3a.1 for ; Mon, 05 Jun 2023 13:16:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996169; x=1688588169; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QuKcmQB095cKvyXtd0GqYuNL/df36qhJFKRlq23RlvQ=; b=N6s0qx+69bskQl5XHFaaST/irApA9tsTpheaEOCuF4MQuidnwbJVcK3ZGqQyAbpxyW bKmz6a8u5JjVYjrTXdKftXXC0H0IlSTrI5HXxFStJrDh3lKIrrTqf6f5SDpdAB6bTQwX UG6PJ6wYxXvbuq8tlEstRbVw2eLhjpxwthUowCB9CWrXjyKy4pYijppfM2AIMdCbgRLI 0an5vFN4KZtv7M/uPzvoubHHQP8CdunqWfk3v1LtZ3waXS8NDbRHXeKbFDPesajC/KNJ FKiR6Qht+VSwdDGo+RQXWQixZux59lat9DhxNNaTRNY2cNUJHRpaiH9rY82dyor/q3rN g3Qw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996169; x=1688588169; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QuKcmQB095cKvyXtd0GqYuNL/df36qhJFKRlq23RlvQ=; b=E8YZCRrNJqFYDNk11CeA/EfE17BO3sM3hEq3UCPNaz+S7r9iJNucksRbVU7wSDRuCR ElkOhfQW4D9lpgTIMBdj7CYVkDNXDxI+DtLI+CyFRvs5lfCU7XRqlHHfKh83rXqSgNFF 6L7N1DvFUxTuz5tOIuh9CHQM92oCsxI3RoS9h+Kd9cYDpnwwAhOVrAVxolp6MDgZfL0g ehAjzlQGHtHOz1SPEn5JhMjYbxZB840PTu9Zi4uzvQ3ZW0xuwbc9Wp1WKAu6oe1+8LVh XYlP5pWWTH6SYeQ9TXWJqQLV8B/GBZ/m8TsGyfdm1RK0rnKBtUB1wGq2LlnmSyvrxe7c GcbQ== X-Gm-Message-State: AC+VfDzjxWhk/jBknIPmKUemRL44S1mX0Dqjtv2B5JP9V6+xRZ9S7W/t 63behOCz7eMbIN7g3LTJSOSff8JKVCwRf03OtdY= X-Received: by 2002:aa7:8884:0:b0:63b:6149:7ad6 with SMTP id z4-20020aa78884000000b0063b61497ad6mr743227pfe.34.1685996169298; Mon, 05 Jun 2023 13:16:09 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 22/52] tcg: Split tcg_gen_callN Date: Mon, 5 Jun 2023 13:15:18 -0700 Message-Id: <20230605201548.1596865-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Make tcg_gen_callN a static function. Create tcg_gen_call[0-7] functions for use by helper-gen.h.inc. Removes a multiplicty of calls to __stack_chk_fail, saving up to 143kiB of .text space as measured on an x86_64 host. Old New Less %Change 8888680 8741816 146864 1.65% qemu-system-aarch64 5911832 5856152 55680 0.94% qemu-system-riscv64 5816728 5767512 49216 0.85% qemu-system-mips64 6707832 6659144 48688 0.73% qemu-system-ppc64 Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/helper-gen.h | 40 ++++++++++++++--------------- include/tcg/tcg.h | 14 +++++++++- tcg/tcg.c | 54 ++++++++++++++++++++++++++++++++++++++- 3 files changed, 86 insertions(+), 22 deletions(-) diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h index 248cff3351..784dd24ae2 100644 --- a/include/exec/helper-gen.h +++ b/include/exec/helper-gen.h @@ -17,7 +17,7 @@ extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ { \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 0, NULL); \ + tcg_gen_call0(&glue(helper_info_, name), dh_retvar(ret)); \ } #define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ @@ -25,8 +25,8 @@ extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1)) \ { \ - TCGTemp *args[1] = { dh_arg(t1, 1) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 1, args); \ + tcg_gen_call1(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1)); \ } #define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ @@ -34,8 +34,8 @@ extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ { \ - TCGTemp *args[2] = { dh_arg(t1, 1), dh_arg(t2, 2) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 2, args); \ + tcg_gen_call2(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2)); \ } #define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ @@ -43,8 +43,8 @@ extern TCGHelperInfo glue(helper_info_, name); \ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ { \ - TCGTemp *args[3] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 3, args); \ + tcg_gen_call3(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3)); \ } #define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ @@ -53,9 +53,9 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \ { \ - TCGTemp *args[4] = { dh_arg(t1, 1), dh_arg(t2, 2), \ - dh_arg(t3, 3), dh_arg(t4, 4) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 4, args); \ + tcg_gen_call4(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), \ + dh_arg(t3, 3), dh_arg(t4, 4)); \ } #define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ @@ -64,9 +64,9 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \ { \ - TCGTemp *args[5] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 5, args); \ + tcg_gen_call5(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5)); \ } #define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ @@ -75,9 +75,9 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \ { \ - TCGTemp *args[6] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 6, args); \ + tcg_gen_call6(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6)); \ } #define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\ @@ -87,10 +87,10 @@ static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \ dh_arg_decl(t7, 7)) \ { \ - TCGTemp *args[7] = { dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \ - dh_arg(t7, 7) }; \ - tcg_gen_callN(&glue(helper_info_, name), dh_retvar(ret), 7, args); \ + tcg_gen_call7(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \ + dh_arg(t7, 7)); \ } #include "helper.h" diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 64c10a63f3..7c1bbba673 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -939,7 +939,19 @@ typedef struct TCGTargetOpDef { bool tcg_op_supported(TCGOpcode op); -void tcg_gen_callN(TCGHelperInfo *, TCGTemp *ret, int nargs, TCGTemp **args); +void tcg_gen_call0(TCGHelperInfo *, TCGTemp *ret); +void tcg_gen_call1(TCGHelperInfo *, TCGTemp *ret, TCGTemp *); +void tcg_gen_call2(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *); +void tcg_gen_call3(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, + TCGTemp *, TCGTemp *); +void tcg_gen_call4(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, + TCGTemp *, TCGTemp *); +void tcg_gen_call5(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, + TCGTemp *, TCGTemp *, TCGTemp *); +void tcg_gen_call6(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, + TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *); +void tcg_gen_call7(TCGHelperInfo *, TCGTemp *ret, TCGTemp *, TCGTemp *, + TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *, TCGTemp *); TCGOp *tcg_emit_op(TCGOpcode opc, unsigned nargs); void tcg_op_remove(TCGContext *s, TCGOp *op); diff --git a/tcg/tcg.c b/tcg/tcg.c index 59624fceec..d369367c5a 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -2127,7 +2127,7 @@ bool tcg_op_supported(TCGOpcode op) static TCGOp *tcg_op_alloc(TCGOpcode opc, unsigned nargs); -void tcg_gen_callN(TCGHelperInfo *info, TCGTemp *ret, int nargs, TCGTemp **args) +static void tcg_gen_callN(TCGHelperInfo *info, TCGTemp *ret, TCGTemp **args) { TCGv_i64 extend_free[MAX_CALL_IARGS]; int n_extend = 0; @@ -2217,6 +2217,58 @@ void tcg_gen_callN(TCGHelperInfo *info, TCGTemp *ret, int nargs, TCGTemp **args) } } +void tcg_gen_call0(TCGHelperInfo *info, TCGTemp *ret) +{ + tcg_gen_callN(info, ret, NULL); +} + +void tcg_gen_call1(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1) +{ + tcg_gen_callN(info, ret, &t1); +} + +void tcg_gen_call2(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, TCGTemp *t2) +{ + TCGTemp *args[2] = { t1, t2 }; + tcg_gen_callN(info, ret, args); +} + +void tcg_gen_call3(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, + TCGTemp *t2, TCGTemp *t3) +{ + TCGTemp *args[3] = { t1, t2, t3 }; + tcg_gen_callN(info, ret, args); +} + +void tcg_gen_call4(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, + TCGTemp *t2, TCGTemp *t3, TCGTemp *t4) +{ + TCGTemp *args[4] = { t1, t2, t3, t4 }; + tcg_gen_callN(info, ret, args); +} + +void tcg_gen_call5(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, + TCGTemp *t2, TCGTemp *t3, TCGTemp *t4, TCGTemp *t5) +{ + TCGTemp *args[5] = { t1, t2, t3, t4, t5 }; + tcg_gen_callN(info, ret, args); +} + +void tcg_gen_call6(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, TCGTemp *t2, + TCGTemp *t3, TCGTemp *t4, TCGTemp *t5, TCGTemp *t6) +{ + TCGTemp *args[6] = { t1, t2, t3, t4, t5, t6 }; + tcg_gen_callN(info, ret, args); +} + +void tcg_gen_call7(TCGHelperInfo *info, TCGTemp *ret, TCGTemp *t1, + TCGTemp *t2, TCGTemp *t3, TCGTemp *t4, + TCGTemp *t5, TCGTemp *t6, TCGTemp *t7) +{ + TCGTemp *args[7] = { t1, t2, t3, t4, t5, t6, t7 }; + tcg_gen_callN(info, ret, args); +} + static void tcg_reg_alloc_start(TCGContext *s) { int i, n; From patchwork Mon Jun 5 20:15:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689272 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2289061wru; Mon, 5 Jun 2023 13:28:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7T7YHmH1qNa0Doe01sXmMTAZwvNiUtr5wzyt2a83vNLqjyZWLXDmjvvGCpHeRQ4dnjK/kp X-Received: by 2002:a05:622a:348:b0:3f8:465:23a9 with SMTP id r8-20020a05622a034800b003f8046523a9mr10663473qtw.23.1685996904620; Mon, 05 Jun 2023 13:28:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996904; cv=none; d=google.com; s=arc-20160816; b=gcfYdtGnhzBZPdye65h/jGLizL0V/+G8JZyQYgDWqj0cKT7rHDzIYx1LqHXCj1fIYD p4rsnnl8uXSvYyvdvhW8ChkDii+IGxKKDbXASQIgDHpfv1dFrIXE2Xi7utAyDDn9XVv0 cUbAaQJmm+eDgBrOqlILHdT/jcpb/xreUQtxh+UDQDwn+18MQSs6QhDRrgJoFsDDSk9s 4j9IVNvrTQ/yinKctnPJD19yNOT2BW8zV4kPT4ckpigRwuc0qLIrigQb8DZhRXhhgjDK kd0ugTK96bmSVm4vr/eOh0cgCtoSHM5UtCTW/xy8n6D9wWht/T6JaB/WucwP09qfFzqa hZPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cFkKfVOLs8ujZZUFJZuyQlWbxSGBsennZlNe4u6SMrM=; b=yf+BZyE/4QnWAQSJzB+IhkP0/1PwFMFBz7kZyMPP3rnx70fQlPV+uVG/j6E3NZ2lTh uHz0PtF34/5BXuC0KyTunT7b5yWCUxUA9yUhse5bHn/xxoFUiSNoSICwu01ZBM6z66hZ 0rrDYJBnRvrawVVSJfwqBbhURT6xevWZ2KfEgBC5B8joCRdzcnpo2wMsuFgzNydyUE8r apMcGhM8YGD/FvMfEpqchH9dIBh7eQ2NML/X0Hz0HUAvKpJKOo7RGiXXBX66qi1iKOqT HuVVj497jjNdT/r7fpL2ApZ/ylErIeXfxSWnTKOYBFXFBoaaaETDoc2WcREVyLrlAH2M 1Mlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PidV1JRy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c1-20020ac87d81000000b003f6a701ae03si5031929qtd.630.2023.06.05.13.28.24 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:28:24 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=PidV1JRy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gd7-00027L-JI; Mon, 05 Jun 2023 16:16:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gch-0001uJ-1r for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:15 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcd-0003ju-02 for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:14 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-6537d2a8c20so2337147b3a.2 for ; Mon, 05 Jun 2023 13:16:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996170; x=1688588170; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cFkKfVOLs8ujZZUFJZuyQlWbxSGBsennZlNe4u6SMrM=; b=PidV1JRyzUdL+ifKqE0YxkKlOaMl3JeqJ/53q8pexq3Hi/xBLYU/W3TSJExZq62Jcq xsKma6B++41mSdo6IKaA+fFD/aA/4Q21Ei9diwCpFF9dNbNOW/99Mk+WfIBMubyjGf4q uSx7XnA7So4xl9YfvVQrHBDdFeGenfOI2IU8duXKku7oGXmM23MVdsbMCVbHdeitc/pj uRiX7zZuW+w+PauYIJ1V8t6bC9HHmjPm20+MTGSFioFChcgc7s8cqQIYKqgJd6sz9gO5 yYVQoIQexl6EXmXZDQTUtjXOuBPEatltLJeDAviByIBy2j9VMNxI99KFaklWgKj9UiE/ xrew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996170; x=1688588170; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cFkKfVOLs8ujZZUFJZuyQlWbxSGBsennZlNe4u6SMrM=; b=TwgzPwtuJhqIDr9qz0/SNfElO3/qxaYN12vHoKcL1PUC+I+JjBhE7X50p6Fu9lkKJM HVK0pwg63xDwvjCVTruSbaOG8+2k/MsCRSqq/23zfulDrLC/Ppnr7eS3XMAKvgWs+mX8 mnf8k/AHq8lX2FmbKpUJAH21CGtYbaEXzxk1tVezQnbJ4E89OfEFgVzGgjdolCdAnMQc crjOnz4cmrbCss3jVuXt7edUsDbxApOSkxKGxGEYQjBBO45jQfmohVS9ovcyjydE70Lb 7phwqJTiSz0WffTZu2hw0iPM2PNhrej4SNVwz7qhMRPHFrgmCcoINGybpHygLYzK4ZkV yuKQ== X-Gm-Message-State: AC+VfDyl+tyrygTg+3l5QAjqovm+/WOcQNME/e0/KT77efOkfQpzg5rk TRp6SIBIR1u4GIJmJqdSJlZRJkyj2SD7bZVa5H0= X-Received: by 2002:a05:6a00:178c:b0:65a:6870:3ae6 with SMTP id s12-20020a056a00178c00b0065a68703ae6mr774957pfg.22.1685996170146; Mon, 05 Jun 2023 13:16:10 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 23/52] tcg: Split helper-gen.h Date: Mon, 5 Jun 2023 13:15:19 -0700 Message-Id: <20230605201548.1596865-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Create helper-gen-common.h without the target specific portion. Use that in tcg-op-common.h. Reorg headers in target/arm to ensure that helper-gen.h is included before helper-info.c.inc. All other targets are already correct in this regard. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- MAINTAINERS | 1 + include/exec/helper-gen-common.h | 18 ++++++ include/exec/helper-gen.h | 101 ++---------------------------- include/tcg/tcg-op-common.h | 2 +- include/exec/helper-gen.h.inc | 102 +++++++++++++++++++++++++++++++ target/arm/tcg/translate.c | 8 +-- 6 files changed, 129 insertions(+), 103 deletions(-) create mode 100644 include/exec/helper-gen-common.h create mode 100644 include/exec/helper-gen.h.inc diff --git a/MAINTAINERS b/MAINTAINERS index a1b8376f4c..2366f64d3d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -154,6 +154,7 @@ F: include/exec/exec-all.h F: include/exec/tb-flush.h F: include/exec/target_long.h F: include/exec/helper*.h +F: include/exec/helper*.h.inc F: include/exec/helper-info.c.inc F: include/sysemu/cpus.h F: include/sysemu/tcg.h diff --git a/include/exec/helper-gen-common.h b/include/exec/helper-gen-common.h new file mode 100644 index 0000000000..5d6d78a625 --- /dev/null +++ b/include/exec/helper-gen-common.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Helper file for declaring TCG helper functions. + * This one expands generation functions for tcg opcodes. + */ + +#ifndef HELPER_GEN_COMMON_H +#define HELPER_GEN_COMMON_H + +#define HELPER_H "accel/tcg/tcg-runtime.h" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#define HELPER_H "accel/tcg/plugin-helpers.h" +#include "exec/helper-gen.h.inc" +#undef HELPER_H + +#endif /* HELPER_GEN_COMMON_H */ diff --git a/include/exec/helper-gen.h b/include/exec/helper-gen.h index 784dd24ae2..f7ec155699 100644 --- a/include/exec/helper-gen.h +++ b/include/exec/helper-gen.h @@ -2,108 +2,15 @@ /* * Helper file for declaring TCG helper functions. * This one expands generation functions for tcg opcodes. - * Define HELPER_H for the header file to be expanded, - * and static inline to change from global file scope. */ #ifndef HELPER_GEN_H #define HELPER_GEN_H -#include "tcg/tcg.h" -#include "tcg/helper-info.h" -#include "exec/helper-head.h" +#include "exec/helper-gen-common.h" -#define DEF_HELPER_FLAGS_0(name, flags, ret) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ -{ \ - tcg_gen_call0(&glue(helper_info_, name), dh_retvar(ret)); \ -} - -#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1)) \ -{ \ - tcg_gen_call1(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1)); \ -} - -#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ -{ \ - tcg_gen_call2(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1), dh_arg(t2, 2)); \ -} - -#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ -{ \ - tcg_gen_call3(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3)); \ -} - -#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ - dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \ -{ \ - tcg_gen_call4(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1), dh_arg(t2, 2), \ - dh_arg(t3, 3), dh_arg(t4, 4)); \ -} - -#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ - dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \ -{ \ - tcg_gen_call5(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5)); \ -} - -#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ - dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \ -{ \ - tcg_gen_call6(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6)); \ -} - -#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\ -extern TCGHelperInfo glue(helper_info_, name); \ -static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ - dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ - dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \ - dh_arg_decl(t7, 7)) \ -{ \ - tcg_gen_call7(&glue(helper_info_, name), dh_retvar(ret), \ - dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ - dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \ - dh_arg(t7, 7)); \ -} - -#include "helper.h" -#include "accel/tcg/tcg-runtime.h" -#include "accel/tcg/plugin-helpers.h" - -#undef DEF_HELPER_FLAGS_0 -#undef DEF_HELPER_FLAGS_1 -#undef DEF_HELPER_FLAGS_2 -#undef DEF_HELPER_FLAGS_3 -#undef DEF_HELPER_FLAGS_4 -#undef DEF_HELPER_FLAGS_5 -#undef DEF_HELPER_FLAGS_6 -#undef DEF_HELPER_FLAGS_7 +#define HELPER_H "helper.h" +#include "exec/helper-gen.h.inc" +#undef HELPER_H #endif /* HELPER_GEN_H */ diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index 04a9ca1fc6..f6f05469c5 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -10,7 +10,7 @@ #include "tcg/tcg.h" #include "exec/helper-proto.h" -#include "exec/helper-gen.h" +#include "exec/helper-gen-common.h" /* Basic output routines. Not for general consumption. */ diff --git a/include/exec/helper-gen.h.inc b/include/exec/helper-gen.h.inc new file mode 100644 index 0000000000..c009641517 --- /dev/null +++ b/include/exec/helper-gen.h.inc @@ -0,0 +1,102 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Helper file for declaring TCG helper functions. + * This one expands generation functions for tcg opcodes. + * Define HELPER_H for the header file to be expanded, + * and static inline to change from global file scope. + */ + +#include "tcg/tcg.h" +#include "tcg/helper-info.h" +#include "exec/helper-head.h" + +#define DEF_HELPER_FLAGS_0(name, flags, ret) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \ +{ \ + tcg_gen_call0(&glue(helper_info_, name), dh_retvar(ret)); \ +} + +#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1)) \ +{ \ + tcg_gen_call1(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1)); \ +} + +#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \ +{ \ + tcg_gen_call2(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2)); \ +} + +#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \ +{ \ + tcg_gen_call3(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3)); \ +} + +#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \ + dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \ +{ \ + tcg_gen_call4(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), \ + dh_arg(t3, 3), dh_arg(t4, 4)); \ +} + +#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \ +{ \ + tcg_gen_call5(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5)); \ +} + +#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \ +{ \ + tcg_gen_call6(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6)); \ +} + +#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\ +extern TCGHelperInfo glue(helper_info_, name); \ +static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \ + dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \ + dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \ + dh_arg_decl(t7, 7)) \ +{ \ + tcg_gen_call7(&glue(helper_info_, name), dh_retvar(ret), \ + dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \ + dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \ + dh_arg(t7, 7)); \ +} + +#include HELPER_H + +#undef DEF_HELPER_FLAGS_0 +#undef DEF_HELPER_FLAGS_1 +#undef DEF_HELPER_FLAGS_2 +#undef DEF_HELPER_FLAGS_3 +#undef DEF_HELPER_FLAGS_4 +#undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 +#undef DEF_HELPER_FLAGS_7 diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 4d84850d74..ce50531dff 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -32,6 +32,9 @@ #include "semihosting/semihost.h" #include "exec/log.h" #include "cpregs.h" +#include "translate.h" +#include "translate-a32.h" +#include "exec/gen-icount.h" #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" @@ -48,9 +51,6 @@ #define ENABLE_ARCH_7 arm_dc_feature(s, ARM_FEATURE_V7) #define ENABLE_ARCH_8 arm_dc_feature(s, ARM_FEATURE_V8) -#include "translate.h" -#include "translate-a32.h" - /* These are TCG temporaries used only by the legacy iwMMXt decoder */ static TCGv_i64 cpu_V0, cpu_V1, cpu_M0; /* These are TCG globals which alias CPUARMState fields */ @@ -59,8 +59,6 @@ TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; TCGv_i64 cpu_exclusive_addr; TCGv_i64 cpu_exclusive_val; -#include "exec/gen-icount.h" - static const char * const regnames[] = { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", "r12", "r13", "r14", "pc" }; From patchwork Mon Jun 5 20:15:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689229 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2285531wru; Mon, 5 Jun 2023 13:17:46 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6PtLFSn7ynn2gB9w6EKn9vmwSuKDwD/INCHGsNexRb27n5muKZ6Ymgm8a6Ph7/ErNH8r2k X-Received: by 2002:ac8:7fce:0:b0:3f6:b218:deac with SMTP id b14-20020ac87fce000000b003f6b218deacmr8046793qtk.45.1685996266777; Mon, 05 Jun 2023 13:17:46 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996266; cv=none; d=google.com; s=arc-20160816; b=SubME+QeUB/3neUW8VeFvhWr3/IKhx8qlrL1ntNU5m16/t9vnrS7YWGFbSqvLYKRJP W5ZqI3t3hdXhsw/bMLoNkElYZiKEmH1PTjxTwlKwm6C/od74JIyTtpjp6xjFwkwpo19Y mGeEx5L8lfmcBJV15V5JuGgLdxDOd2ag9iBBD9io29RC6ly79j4wUl15E9JwtehkHQwu qK2p9ME8Yd2SkcVgdyMo983B5xyKt0TasgRCnbTJwDLQ/cP6DZWz4En+I/iaCznyX/gT kXamC3j+fbTP9O58VzPP9pHfFn3xIKR/JxKHIPKcs8k9M4J5k3IP+xQHl6ufPmgHIuGs t+0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BdBdv+EshRKxwfl8jPqTp56oD+23gjpgogLGEpAp1cY=; b=f8WRkdArz0PDC/+2lQYf2Vzqapb6IxbTZatyf6w0rmYAgTjqnwd0C6zNkwCnHgwDbR TVrvh3N7E3NqIvMy2r8J3Sx2m6skryenkL0frRc3dLVTH/nRA/jVM1+Um9IomMuJT/va sWIlv3eUQzA2J8ji0V7o8CPggiUk5b1weV9KZtpQYg+k0VHZvIn8Z0mZXp+vnUv+vFQE n2A+MBRzU7GdbbJF4Dmu1iTk9omsm/eMkYSpkCjV5iC9zYcP3cjudg0k6OwS1uPcwFPw bDAMWA5nV/vSZvcSJRrgP0wQ7uI/fRSu49CRw8vejr7kMOEIYuFzMvW4KDguioO2iYzr 92ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QBYXKOHR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w18-20020ac87e92000000b003ef38288cd6si1667618qtj.101.2023.06.05.13.17.46 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:17:46 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QBYXKOHR; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gcs-0001xZ-PM; Mon, 05 Jun 2023 16:16:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcj-0001ul-CE for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:17 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcf-0003zu-Jd for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:17 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-653fcd58880so1751904b3a.0 for ; Mon, 05 Jun 2023 13:16:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996171; x=1688588171; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BdBdv+EshRKxwfl8jPqTp56oD+23gjpgogLGEpAp1cY=; b=QBYXKOHRC3/H9GCoiZ5WoVxEIi1kqTDYhvcSdj+c6RgQltF25w5vbwUnGZ2AUYJZph UkygHSsGlf/zJW+ymRbixz3e+c8x0VgC70Q41iuXke8Cfm8NUYL22OYPXNz6M6fzJk3R Yql6Q1Vsi++zLwIJkJLhBFSYgcmpTQ1LzEzpvEzJcqHUEZYoEjUTV0Rwcub1UgbaBUVQ b6Gz7Xhljw7qMefFAUPOw/qrlHS7xFQq4Sx8nc3xEAC/Tk3gL+HZUL6uIeyglcEvZdTP zv7RwfIQxqE6ts9Fss4p7NIYn6ICKh9YDJjAQI99vtWCOLC2to1M2g2qoHL9JkurUJK6 KNNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996171; x=1688588171; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BdBdv+EshRKxwfl8jPqTp56oD+23gjpgogLGEpAp1cY=; b=hQxvfFRODVvnwHEKVPhRQiVinxU67PjNbm+YKX6n0PhQGA9YsqBxdVtjYtOqazirMp 8Kn8x7vaTV2vgR8qm7kR+OKUxDEHDQX8uPWuCrxXqNDCNMhC6Fnp3GSP9wfNa0+xwe7n vAyazyHduYmDLkSp2fOyQkeJQpFwv+AwwNdx5DDnmnz1HMpN6htdyxWfkFO7vMTaLpsQ FwvcJFsKZxrpHZvJ4HhJ8kdAoH+eazBzF4rCTg4rH29O93dn48cbUUESWQOQZH6iO3VV A5Bi2hnX/NpqeAF49rKljMpI5wL7sPb1IAgm1AkPS/wjgBZaAtjZGSbhcKEh5IZhgFO7 OU1w== X-Gm-Message-State: AC+VfDx3rj6no7fW9IpqbD4SBTmaUuf+W3OPBqO9qtE+U7v5Aoa/ui2a 6UmbFjw9odwFgHB11BStUXUZWuFfnNSA8c7tWYQ= X-Received: by 2002:a05:6a00:2303:b0:638:7e00:3737 with SMTP id h3-20020a056a00230300b006387e003737mr948573pfh.23.1685996170967; Mon, 05 Jun 2023 13:16:10 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 24/52] tcg: Split helper-proto.h Date: Mon, 5 Jun 2023 13:15:20 -0700 Message-Id: <20230605201548.1596865-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Create helper-proto-common.h without the target specific portion. Use that in tcg-op-common.h. Include helper-proto.h in target/arm and target/hexagon before helper-info.c.inc; all other targets are already correct in this regard. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/helper-proto-common.h | 18 ++++++++ include/exec/helper-proto.h | 73 ++++-------------------------- include/tcg/tcg-op-common.h | 2 +- include/exec/helper-proto.h.inc | 68 ++++++++++++++++++++++++++++ accel/tcg/cputlb.c | 3 +- accel/tcg/plugin-gen.c | 2 +- accel/tcg/tcg-runtime-gvec.c | 2 +- accel/tcg/tcg-runtime.c | 2 +- target/arm/tcg/translate.c | 1 + target/hexagon/translate.c | 1 + 10 files changed, 102 insertions(+), 70 deletions(-) create mode 100644 include/exec/helper-proto-common.h create mode 100644 include/exec/helper-proto.h.inc diff --git a/include/exec/helper-proto-common.h b/include/exec/helper-proto-common.h new file mode 100644 index 0000000000..4d4b022668 --- /dev/null +++ b/include/exec/helper-proto-common.h @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Helper file for declaring TCG helper functions. + * This one expands prototypes for the helper functions. + */ + +#ifndef HELPER_PROTO_COMMON_H +#define HELPER_PROTO_COMMON_H + +#define HELPER_H "accel/tcg/tcg-runtime.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + +#define HELPER_H "accel/tcg/plugin-helpers.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H + +#endif /* HELPER_PROTO_COMMON_H */ diff --git a/include/exec/helper-proto.h b/include/exec/helper-proto.h index 7a3f04b58c..6935cb4f16 100644 --- a/include/exec/helper-proto.h +++ b/include/exec/helper-proto.h @@ -1,71 +1,16 @@ -/* Helper file for declaring TCG helper functions. - This one expands prototypes for the helper functions. */ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Helper file for declaring TCG helper functions. + * This one expands prototypes for the helper functions. + */ #ifndef HELPER_PROTO_H #define HELPER_PROTO_H -#include "exec/helper-head.h" +#include "exec/helper-proto-common.h" -/* - * Work around an issue with --enable-lto, in which GCC's ipa-split pass - * decides to split out the noreturn code paths that raise an exception, - * taking the __builtin_return_address() along into the new function, - * where it no longer computes a value that returns to TCG generated code. - * Despite the name, the noinline attribute affects splitter, so this - * prevents the optimization in question. Given that helpers should not - * otherwise be called directly, this should have any other visible effect. - * - * See https://gitlab.com/qemu-project/qemu/-/issues/1454 - */ -#define DEF_HELPER_ATTR __attribute__((noinline)) - -#define DEF_HELPER_FLAGS_0(name, flags, ret) \ -dh_ctype(ret) HELPER(name) (void) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), \ - dh_ctype(t3)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ - dh_ctype(t4)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ - dh_ctype(t4), dh_ctype(t5)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ - dh_ctype(t4), dh_ctype(t5), \ - dh_ctype(t6)) DEF_HELPER_ATTR; - -#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \ -dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ - dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \ - dh_ctype(t7)) DEF_HELPER_ATTR; - -#define IN_HELPER_PROTO - -#include "helper.h" -#include "accel/tcg/tcg-runtime.h" -#include "accel/tcg/plugin-helpers.h" - -#undef IN_HELPER_PROTO - -#undef DEF_HELPER_FLAGS_0 -#undef DEF_HELPER_FLAGS_1 -#undef DEF_HELPER_FLAGS_2 -#undef DEF_HELPER_FLAGS_3 -#undef DEF_HELPER_FLAGS_4 -#undef DEF_HELPER_FLAGS_5 -#undef DEF_HELPER_FLAGS_6 -#undef DEF_HELPER_FLAGS_7 -#undef DEF_HELPER_ATTR +#define HELPER_H "helper.h" +#include "exec/helper-proto.h.inc" +#undef HELPER_H #endif /* HELPER_PROTO_H */ diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h index f6f05469c5..be382bbf77 100644 --- a/include/tcg/tcg-op-common.h +++ b/include/tcg/tcg-op-common.h @@ -9,7 +9,7 @@ #define TCG_TCG_OP_COMMON_H #include "tcg/tcg.h" -#include "exec/helper-proto.h" +#include "exec/helper-proto-common.h" #include "exec/helper-gen-common.h" /* Basic output routines. Not for general consumption. */ diff --git a/include/exec/helper-proto.h.inc b/include/exec/helper-proto.h.inc new file mode 100644 index 0000000000..c3aa666929 --- /dev/null +++ b/include/exec/helper-proto.h.inc @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Helper file for declaring TCG helper functions. + * This one expands prototypes for the helper functions. + * Define HELPER_H for the header file to be expanded. + */ + +#include "exec/helper-head.h" + +/* + * Work around an issue with --enable-lto, in which GCC's ipa-split pass + * decides to split out the noreturn code paths that raise an exception, + * taking the __builtin_return_address() along into the new function, + * where it no longer computes a value that returns to TCG generated code. + * Despite the name, the noinline attribute affects splitter, so this + * prevents the optimization in question. Given that helpers should not + * otherwise be called directly, this should not have any other visible effect. + * + * See https://gitlab.com/qemu-project/qemu/-/issues/1454 + */ +#define DEF_HELPER_ATTR __attribute__((noinline)) + +#define DEF_HELPER_FLAGS_0(name, flags, ret) \ +dh_ctype(ret) HELPER(name) (void) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1)) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2)) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), \ + dh_ctype(t3)) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ + dh_ctype(t4)) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ + dh_ctype(t4), dh_ctype(t5)) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ + dh_ctype(t4), dh_ctype(t5), \ + dh_ctype(t6)) DEF_HELPER_ATTR; + +#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7) \ +dh_ctype(ret) HELPER(name) (dh_ctype(t1), dh_ctype(t2), dh_ctype(t3), \ + dh_ctype(t4), dh_ctype(t5), dh_ctype(t6), \ + dh_ctype(t7)) DEF_HELPER_ATTR; + +#define IN_HELPER_PROTO + +#include HELPER_H + +#undef IN_HELPER_PROTO + +#undef DEF_HELPER_FLAGS_0 +#undef DEF_HELPER_FLAGS_1 +#undef DEF_HELPER_FLAGS_2 +#undef DEF_HELPER_FLAGS_3 +#undef DEF_HELPER_FLAGS_4 +#undef DEF_HELPER_FLAGS_5 +#undef DEF_HELPER_FLAGS_6 +#undef DEF_HELPER_FLAGS_7 +#undef DEF_HELPER_ATTR diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 32a4817139..5e2ca47243 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -29,7 +29,7 @@ #include "tcg/tcg.h" #include "qemu/error-report.h" #include "exec/log.h" -#include "exec/helper-proto.h" +#include "exec/helper-proto-common.h" #include "qemu/atomic.h" #include "qemu/atomic128.h" #include "exec/translate-all.h" @@ -41,7 +41,6 @@ #endif #include "tcg/tcg-ldst.h" #include "tcg/oversized-guest.h" -#include "exec/helper-proto.h" /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 40b34a0403..3e528f191d 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -49,7 +49,7 @@ #include "exec/exec-all.h" #include "exec/plugin-gen.h" #include "exec/translator.h" -#include "exec/helper-proto.h" +#include "exec/helper-proto-common.h" #define HELPER_H "accel/tcg/plugin-helpers.h" #include "exec/helper-info.c.inc" diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index 97399493d5..6c99f952ca 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" #include "cpu.h" -#include "exec/helper-proto.h" +#include "exec/helper-proto-common.h" #include "tcg/tcg-gvec-desc.h" diff --git a/accel/tcg/tcg-runtime.c b/accel/tcg/tcg-runtime.c index 14b59a36e5..9fa539ad3d 100644 --- a/accel/tcg/tcg-runtime.c +++ b/accel/tcg/tcg-runtime.c @@ -24,7 +24,7 @@ #include "qemu/osdep.h" #include "qemu/host-utils.h" #include "cpu.h" -#include "exec/helper-proto.h" +#include "exec/helper-proto-common.h" #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "disas/disas.h" diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index ce50531dff..379f266256 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -35,6 +35,7 @@ #include "translate.h" #include "translate-a32.h" #include "exec/gen-icount.h" +#include "exec/helper-proto.h" #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 00e25035ce..770de58647 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -21,6 +21,7 @@ #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/helper-gen.h" +#include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "internal.h" From patchwork Mon Jun 5 20:15:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689243 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2287469wru; Mon, 5 Jun 2023 13:23:38 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4UXn05Wl5s9sRtFzziKAQgzPLns2ROmzfeMcoIk6/dnQZLhV8NG8k0UGVxTgK6LJ40RJb2 X-Received: by 2002:a05:6214:c6d:b0:621:7241:df33 with SMTP id t13-20020a0562140c6d00b006217241df33mr1622qvj.0.1685996618661; Mon, 05 Jun 2023 13:23:38 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996618; cv=none; d=google.com; s=arc-20160816; b=qLpM00fT0WkIsLDbW5hCsaUwuY3eOdeZ6MSQLijQUyAJnhcopGVJ9et5uX+GQaoSpE u5tgxNK4SLLSVWGWXoJSkQfB13YtoV13t9w12d89fkT2zUINKe3RvL+0gnyZPPezRGVk vHzhK2bp/BztkZUHfR4xH74kQ8Kw9RFM/CGzSEUM/N00VXjhitus4xT+c/1A4Y1/7q+v mw+7x6f+B4bNasTiRakv3XzNxMQ6GQXYPZX+cC+pe/QsaqPEGn2fS+5VjGSM4rzwoiAd aNee4v4HidyO3rLD13Sm75RlXydHtliPdNjB+JJo5PQ4tGpLY4ez+qV8hLLwAq9KhMAt ac6Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=t25Lwror6gMHE9REWAtcEk6T/FuH34tcWxvUnV0Sx38=; b=S0/AjvDZln18M6niy7yFhM3JK9CPPchn7CBq3ATvQAtpcAoSSCklenjOV3I7KUDhrz JXvDI0JK61hkFkpG2fmKlBpL1SEhTTFJz3guX+a7MXmV4Q6BSx8ktx6/yvuQwNw+F6Qu Bp+z/o5yvQfH020DVSos+hhMB+vL4czlhyCsPdCrJotreeyAj/g3tt/mYq5k4hZni5as OBb3oUhYBHurbx3ggOqo41T8599VSvzR97pJvWEDm5nYg5++3TpSdkStkqAxzKBItwQM x94bRNWbpzFgXCNovQ6IuqXwY0fFo1cMlHNKe3O5Zz39gKnpnRqoQp8tJcEXd0vWxg6g Z1pA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wzkd9mb6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o4-20020a0562140e4400b006257cf747fasi5409451qvc.549.2023.06.05.13.23.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:23:38 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=wzkd9mb6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gcn-0001vr-AQ; Mon, 05 Jun 2023 16:16:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gch-0001uL-AE for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:15 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcf-0003qB-J2 for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:15 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-652328c18d5so2567814b3a.1 for ; Mon, 05 Jun 2023 13:16:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996172; x=1688588172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=t25Lwror6gMHE9REWAtcEk6T/FuH34tcWxvUnV0Sx38=; b=wzkd9mb6C6/ynyjnTtFU9lrOyQ53RV0UbyMYVYPbPQHGZIdFzklw/h9ehBaqLEjKFc jZ0VQUG/zEDS8/FZ3MCHT76XVKNUISX2MhY5w8eeGMBzWeAdZKKwN537vO74CwYbxFUt AsrNn1ya/DMfxDwAZ7C6naTFf5pNpf9RSlHKXVciFvPjC4ANnljlajmU3/nM7MLsEC3p RGqJmCpOEtEv1yvjcRhV89ZJLVjbCAcgie4XVHT9WZYP79Y9AwKtpS82Z1B1ZeimNOvK gMveJ767FrEBu/z59Jj1lCCJvPsowYxyEX4U6JBjCdJOvY1Zd+FhnKKT4c3F2sj8NUs4 qMYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996172; x=1688588172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=t25Lwror6gMHE9REWAtcEk6T/FuH34tcWxvUnV0Sx38=; b=SuZMl3rD53WBGetiubifjAeuglnn59QdPnmc9O7suxpEh/LQ1mmkeQ4bF0I7Y1N3eG fgXJtDOTpjHnbgeQTc5SUnbXltOpNq1xZRIQCe/obDT/FwcdnHKwkjEoH5Kft/tyqlX2 YDRtwnp99+lXvj/OypItAUnM3n84uarrOYWR8v3YdlCjHbQ1Crdxq++eR9AOM+uvbbTG j6kq+2k6OkKYWXpisiOc6nOzGumKoUkCz5umK9Fq187gAi6nA1G7aSOatJr0xwAfV4rr /NClBbWFPZV1Rrnq5BhueUtEmYzOzYRh77oD0A3QAcKFKjVTpRHSK9iNI4DIQkI8DiS+ 9I4Q== X-Gm-Message-State: AC+VfDxktVDmWKWkL9ss71GvowqBN1sMeTqR76NaZvWDpwpDGlTxRdrm 9TBKKgFAo1nf0Rw1eC3cemlRtsNod5vIMJVC1L8= X-Received: by 2002:a05:6a20:12d6:b0:10b:9dc1:c5e5 with SMTP id v22-20020a056a2012d600b0010b9dc1c5e5mr93465pzg.34.1685996171742; Mon, 05 Jun 2023 13:16:11 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 25/52] target/sh4: Emit insn_start for each insn in gUSA region Date: Mon, 5 Jun 2023 13:15:21 -0700 Message-Id: <20230605201548.1596865-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Fixes an assert in tcg_gen_code that we don't accidentally eliminate an insn_start during optimization. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/sh4/translate.c | 15 ++++++++++++--- 1 file changed, 12 insertions(+), 3 deletions(-) diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 9d2c7a3337..76f46d268b 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -2146,9 +2146,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env) /* The entire region has been translated. */ ctx->envflags &= ~TB_FLAG_GUSA_MASK; - ctx->base.pc_next = pc_end; - ctx->base.num_insns += max_insns - 1; - return; + goto done; fail: qemu_log_mask(LOG_UNIMP, "Unrecognized gUSA sequence %08x-%08x\n", @@ -2165,8 +2163,19 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env) purposes of accounting within the TB. We might as well report the entire region consumed via ctx->base.pc_next so that it's immediately available in the disassembly dump. */ + + done: ctx->base.pc_next = pc_end; ctx->base.num_insns += max_insns - 1; + + /* + * Emit insn_start to cover each of the insns in the region. + * This matches an assert in tcg.c making sure that we have + * tb->icount * insn_start. + */ + for (i = 1; i < max_insns; ++i) { + tcg_gen_insn_start(pc + i * 2, ctx->envflags); + } } #endif From patchwork Mon Jun 5 20:15:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689245 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2287624wru; Mon, 5 Jun 2023 13:24:11 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ58tFQT2aAwfHdbQLyzkmIAEDUy4zKeHqzmP2qbdbC+GpiwiZXO/honLE1y/333xlxyE+9m X-Received: by 2002:ad4:5aae:0:b0:623:8d60:da60 with SMTP id u14-20020ad45aae000000b006238d60da60mr10638026qvg.34.1685996651506; Mon, 05 Jun 2023 13:24:11 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996651; cv=none; d=google.com; s=arc-20160816; b=grRqw9OxlaT8wXoIoDTJumBHarOwCZfVSdjGgchv4YHS4NZK3rI7TFvNtPyi8A5iMV XXwTVW/HkFl7Vy7CCzE6mEDAcWIOrJegVmB9tJoUMkUApaqFWXPWRZm5IKLL+j4O+WW+ NFM2VVHiqZxC+1aBrb002BALkBGe5npZHfRCrg2UizYpMDsZ0/xNp5AiK1R4xUCH7DAO +eHnKDTKURnTBcMRQIADIpMZ2jwEGtw/POC8QG8U0f1sFjVzKcfCth2FjdJSKVz592tY qMb8SoeT2jI5qUFaXUsanXS1rNg9srsrygW48I6nlJHLTQihzTfN4AuGLCyhsQIMDAY3 wq6A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=BiNBFteZnKnv2DFn9PJfwp5Vpck7RigEqXHrl2bvYfo=; b=DYEXf16R31V/8VkwOmlNBgybgDlOikpcqi7eMOOBLlJsozLeG8JED+K/qlSoRLtQtI Oe1uannI0tPdeiv34jofvdlQE6JQyM69tbDX9mqIjqHv3YuGK0YJm7l7I0OzZj+t6pIH uWP0xo+LIQ3N0VUSAt+u5hOCLpNtTtt8xfgEuU4kYgrqzCIWBurQNxvyPukw09C4c8jd GkCVjNZa9MwpJ7dLHrrbiQYiG3necTt6eSoxwb3unKtdil4ZzN8ARSNg5UVmZarbEMki uchMlFK5hsTJesvPtFOhrAGVINgc45AObaGAL3K2whU6mQBtynWqsLmAPeJ92u+n9tCB ZgDA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WSK3lTP5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id im12-20020a056214246c00b00621138c67fasi5207225qvb.318.2023.06.05.13.24.11 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:24:11 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WSK3lTP5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gcn-0001we-Sa; Mon, 05 Jun 2023 16:16:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gci-0001uj-RX for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:17 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcf-0003ri-JD for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:16 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-650c89c7e4fso5357538b3a.0 for ; Mon, 05 Jun 2023 13:16:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996172; x=1688588172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=BiNBFteZnKnv2DFn9PJfwp5Vpck7RigEqXHrl2bvYfo=; b=WSK3lTP5c6TE9Q9OqIEA5EGgIp99g6z4SN2Pqb3qeSlTK3Dt93X4eNkjbTTZO/ZLXh 2koFGb9d5eoigmb3ZsXDVVt5xpWvsE+rXJ9Vu676pKXwkE2I7RqjmksOxPGRc9SBTdva UGk6xccIIaE8CMC36sJHgxYbqNL4ROygtd9SjqO+RinnGx4TQvnhGOpF5Tror11MYkIO kKaRWAmnYDdnZ+FXVO5G7nvzKV6QDF96fRn613OTG/vbFaK0ueS8Sv4EkgOfkOy4d6Nf paIu099A2c06MOkAWipcNwZQtSa8MYZV5u70LppmPXCHNeKKm4APqaL/YgmnFzZa0zDB EdEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996172; x=1688588172; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=BiNBFteZnKnv2DFn9PJfwp5Vpck7RigEqXHrl2bvYfo=; b=fov9oLmniCmN0tbYTE+y+XBSQ/pdaBaFTFgjl+C0apQrlwOMdJgsj7kxW6D9DpF0oM nlsmG2NZwbtZHAOKbIBnugaPMu8Y173L+b7OYhbCstFBQs3XXn4+ci2Q1jnKor1R6m6g ZAQivTyF2nRnS7Afm766jeQNf31AxAXCWpojvwfNBPL1B4O08NdvQ/gQw5QoY6AQdrhr aZjJE/2lQcLTSsuLn7nPxHfa4FZpv4o+95q1+Do1vyPLKYYxQL7u885V5CWxkC0qYz45 bq3Y1OdNTwzM+SY2s7boPtQrao77ISAtNIwE1mAleazWkyyzBEgH8jqjA1fojpmTCKho jZOA== X-Gm-Message-State: AC+VfDyDzmrlbYEdEqTN354YtRFG7W2evTyztbI6rWSz+1LI9YryjuO1 keneuJLlv0l5qv2j7VEEepdydEYSQ3rg4sxRojk= X-Received: by 2002:a05:6a00:2d83:b0:65b:a187:d433 with SMTP id fb3-20020a056a002d8300b0065ba187d433mr757043pfb.6.1685996172604; Mon, 05 Jun 2023 13:16:12 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PULL 26/52] tcg: Add insn_start_words to TCGContext Date: Mon, 5 Jun 2023 13:15:22 -0700 Message-Id: <20230605201548.1596865-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This will enable replacement of TARGET_INSN_START_WORDS in tcg.c. Split out "tcg/insn-start-words.h" and use it in target/. Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson --- include/tcg/insn-start-words.h | 17 +++++++++++++++++ include/tcg/tcg-op.h | 8 ++++---- include/tcg/tcg-opc.h | 6 +++--- include/tcg/tcg.h | 9 ++------- accel/tcg/perf.c | 8 ++++++-- accel/tcg/translate-all.c | 20 +++++++++++++------- target/i386/helper.c | 2 +- target/openrisc/sys_helper.c | 2 +- tcg/tcg.c | 16 +++++++++++----- 9 files changed, 58 insertions(+), 30 deletions(-) create mode 100644 include/tcg/insn-start-words.h diff --git a/include/tcg/insn-start-words.h b/include/tcg/insn-start-words.h new file mode 100644 index 0000000000..50c18bd326 --- /dev/null +++ b/include/tcg/insn-start-words.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Define TARGET_INSN_START_WORDS + * Copyright (c) 2008 Fabrice Bellard + */ + +#ifndef TARGET_INSN_START_WORDS + +#include "cpu.h" + +#ifndef TARGET_INSN_START_EXTRA_WORDS +# define TARGET_INSN_START_WORDS 1 +#else +# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) +#endif + +#endif /* TARGET_INSN_START_WORDS */ diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h index 47f1dce816..d63683c47b 100644 --- a/include/tcg/tcg-op.h +++ b/include/tcg/tcg-op.h @@ -22,20 +22,20 @@ # error #endif -#if TARGET_INSN_START_WORDS == 1 +#ifndef TARGET_INSN_START_EXTRA_WORDS static inline void tcg_gen_insn_start(target_ulong pc) { TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 64 / TCG_TARGET_REG_BITS); tcg_set_insn_start_param(op, 0, pc); } -#elif TARGET_INSN_START_WORDS == 2 +#elif TARGET_INSN_START_EXTRA_WORDS == 1 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1) { TCGOp *op = tcg_emit_op(INDEX_op_insn_start, 2 * 64 / TCG_TARGET_REG_BITS); tcg_set_insn_start_param(op, 0, pc); tcg_set_insn_start_param(op, 1, a1); } -#elif TARGET_INSN_START_WORDS == 3 +#elif TARGET_INSN_START_EXTRA_WORDS == 2 static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, target_ulong a2) { @@ -45,7 +45,7 @@ static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1, tcg_set_insn_start_param(op, 2, a2); } #else -# error "Unhandled number of operands to insn_start" +#error Unhandled TARGET_INSN_START_EXTRA_WORDS value #endif #if TARGET_LONG_BITS == 32 diff --git a/include/tcg/tcg-opc.h b/include/tcg/tcg-opc.h index 21594c1590..acfa5ba753 100644 --- a/include/tcg/tcg-opc.h +++ b/include/tcg/tcg-opc.h @@ -188,9 +188,9 @@ DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64)) #define DATA64_ARGS (TCG_TARGET_REG_BITS == 64 ? 1 : 2) -/* QEMU specific */ -DEF(insn_start, 0, 0, DATA64_ARGS * TARGET_INSN_START_WORDS, - TCG_OPF_NOT_PRESENT) +/* There are tcg_ctx->insn_start_words here, not just one. */ +DEF(insn_start, 0, 0, DATA64_ARGS, TCG_OPF_NOT_PRESENT) + DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 7c1bbba673..813c733910 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -173,12 +173,6 @@ typedef uint64_t TCGRegSet; #define TCG_TARGET_HAS_v256 0 #endif -#ifndef TARGET_INSN_START_EXTRA_WORDS -# define TARGET_INSN_START_WORDS 1 -#else -# define TARGET_INSN_START_WORDS (1 + TARGET_INSN_START_EXTRA_WORDS) -#endif - typedef enum TCGOpcode { #define DEF(name, oargs, iargs, cargs, flags) INDEX_op_ ## name, #include "tcg/tcg-opc.h" @@ -526,6 +520,7 @@ struct TCGContext { uint8_t page_bits; uint8_t tlb_dyn_max_bits; #endif + uint8_t insn_start_words; TCGRegSet reserved_regs; intptr_t current_frame_offset; @@ -597,7 +592,7 @@ struct TCGContext { TCGTemp *reg_to_temp[TCG_TARGET_NB_REGS]; uint16_t gen_insn_end_off[TCG_MAX_INSNS]; - uint64_t gen_insn_data[TCG_MAX_INSNS][TARGET_INSN_START_WORDS]; + uint64_t *gen_insn_data; /* Exit to translator on overflow. */ sigjmp_buf jmp_trans; diff --git a/accel/tcg/perf.c b/accel/tcg/perf.c index 65e35ea3b9..f5a1eda39f 100644 --- a/accel/tcg/perf.c +++ b/accel/tcg/perf.c @@ -311,7 +311,8 @@ void perf_report_code(uint64_t guest_pc, TranslationBlock *tb, const void *start) { struct debuginfo_query *q; - size_t insn; + size_t insn, start_words; + uint64_t *gen_insn_data; if (!perfmap && !jitdump) { return; @@ -325,9 +326,12 @@ void perf_report_code(uint64_t guest_pc, TranslationBlock *tb, debuginfo_lock(); /* Query debuginfo for each guest instruction. */ + gen_insn_data = tcg_ctx->gen_insn_data; + start_words = tcg_ctx->insn_start_words; + for (insn = 0; insn < tb->icount; insn++) { /* FIXME: This replicates the restore_state_to_opc() logic. */ - q[insn].address = tcg_ctx->gen_insn_data[insn][0]; + q[insn].address = gen_insn_data[insn * start_words + 0]; if (tb_cflags(tb) & CF_PCREL) { q[insn].address |= (guest_pc & TARGET_PAGE_MASK); } else { diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 5cea9acd5a..67b838e16b 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -64,6 +64,7 @@ #include "tb-context.h" #include "internal.h" #include "perf.h" +#include "tcg/insn-start-words.h" TBContext tb_ctx; @@ -127,22 +128,26 @@ static int64_t decode_sleb128(const uint8_t **pp) static int encode_search(TranslationBlock *tb, uint8_t *block) { uint8_t *highwater = tcg_ctx->code_gen_highwater; + uint64_t *insn_data = tcg_ctx->gen_insn_data; + uint16_t *insn_end_off = tcg_ctx->gen_insn_end_off; uint8_t *p = block; int i, j, n; for (i = 0, n = tb->icount; i < n; ++i) { - uint64_t prev; + uint64_t prev, curr; for (j = 0; j < TARGET_INSN_START_WORDS; ++j) { if (i == 0) { prev = (!(tb_cflags(tb) & CF_PCREL) && j == 0 ? tb->pc : 0); } else { - prev = tcg_ctx->gen_insn_data[i - 1][j]; + prev = insn_data[(i - 1) * TARGET_INSN_START_WORDS + j]; } - p = encode_sleb128(p, tcg_ctx->gen_insn_data[i][j] - prev); + curr = insn_data[i * TARGET_INSN_START_WORDS + j]; + p = encode_sleb128(p, curr - prev); } - prev = (i == 0 ? 0 : tcg_ctx->gen_insn_end_off[i - 1]); - p = encode_sleb128(p, tcg_ctx->gen_insn_end_off[i] - prev); + prev = (i == 0 ? 0 : insn_end_off[i - 1]); + curr = insn_end_off[i]; + p = encode_sleb128(p, curr - prev); /* Test for (pending) buffer overflow. The assumption is that any one row beginning below the high water mark cannot overrun @@ -358,6 +363,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, tcg_ctx->tlb_fast_offset = (int)offsetof(ArchCPU, neg.tlb.f) - (int)offsetof(ArchCPU, env); #endif + tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS; tb_overflow: @@ -451,7 +457,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, fprintf(logfile, "OUT: [size=%d]\n", gen_code_size); fprintf(logfile, " -- guest addr 0x%016" PRIx64 " + tb prologue\n", - tcg_ctx->gen_insn_data[insn][0]); + tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]); chunk_start = tcg_ctx->gen_insn_end_off[insn]; disas(logfile, tb->tc.ptr, chunk_start); @@ -464,7 +470,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, size_t chunk_end = tcg_ctx->gen_insn_end_off[insn]; if (chunk_end > chunk_start) { fprintf(logfile, " -- guest addr 0x%016" PRIx64 "\n", - tcg_ctx->gen_insn_data[insn][0]); + tcg_ctx->gen_insn_data[insn * TARGET_INSN_START_WORDS]); disas(logfile, tb->tc.ptr + chunk_start, chunk_end - chunk_start); chunk_start = chunk_end; diff --git a/target/i386/helper.c b/target/i386/helper.c index 682d10d98a..36bf2107e7 100644 --- a/target/i386/helper.c +++ b/target/i386/helper.c @@ -29,7 +29,7 @@ #endif #include "qemu/log.h" #ifdef CONFIG_TCG -#include "tcg/tcg.h" +#include "tcg/insn-start-words.h" #endif void cpu_sync_avx_hflag(CPUX86State *env) diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 110f157601..782a5751b7 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -26,7 +26,7 @@ #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #endif -#include "tcg/tcg.h" +#include "tcg/insn-start-words.h" #define TO_SPR(group, number) (((group) << 11) + (number)) diff --git a/tcg/tcg.c b/tcg/tcg.c index d369367c5a..a339e3e3d8 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1501,6 +1501,8 @@ void tcg_func_start(TCGContext *s) tcg_debug_assert(s->tlb_fast_offset < 0); tcg_debug_assert(s->tlb_fast_offset >= MIN_TLB_MASK_TABLE_OFS); #endif + + tcg_debug_assert(s->insn_start_words > 0); } static TCGTemp *tcg_temp_alloc(TCGContext *s) @@ -2445,7 +2447,7 @@ static void tcg_dump_ops(TCGContext *s, FILE *f, bool have_prefs) nb_oargs = 0; col += ne_fprintf(f, "\n ----"); - for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { + for (i = 0, k = s->insn_start_words; i < k; ++i) { col += ne_fprintf(f, " %016" PRIx64, tcg_get_insn_start_param(op, i)); } @@ -6024,7 +6026,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) #ifdef CONFIG_PROFILER TCGProfile *prof = &s->prof; #endif - int i, num_insns; + int i, start_words, num_insns; TCGOp *op; #ifdef CONFIG_PROFILER @@ -6147,6 +6149,10 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) s->pool_labels = NULL; #endif + start_words = s->insn_start_words; + s->gen_insn_data = + tcg_malloc(sizeof(uint64_t) * s->gen_tb->icount * start_words); + num_insns = -1; QTAILQ_FOREACH(op, &s->ops, link) { TCGOpcode opc = op->opc; @@ -6172,8 +6178,8 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) assert(s->gen_insn_end_off[num_insns] == off); } num_insns++; - for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { - s->gen_insn_data[num_insns][i] = + for (i = 0; i < start_words; ++i) { + s->gen_insn_data[num_insns * start_words + i] = tcg_get_insn_start_param(op, i); } break; @@ -6219,7 +6225,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb, uint64_t pc_start) return -2; } } - tcg_debug_assert(num_insns >= 0); + tcg_debug_assert(num_insns + 1 == s->gen_tb->icount); s->gen_insn_end_off[num_insns] = tcg_current_code_size(s); /* Generate TB finalization at the end of block */ From patchwork Mon Jun 5 20:15:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689227 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2285401wru; Mon, 5 Jun 2023 13:17:22 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4nb5vg+q4rcPl1bdYF7ai6C5PimNuPJi9R6fDU/iTHmgJPTDAgxoWydlnVTy9BxEy8RXzD X-Received: by 2002:ad4:596b:0:b0:629:fa4a:a6a3 with SMTP id eq11-20020ad4596b000000b00629fa4aa6a3mr83072qvb.20.1685996242708; Mon, 05 Jun 2023 13:17:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996242; cv=none; d=google.com; s=arc-20160816; b=b4FeXtAFe6s2Pvzr+onBFSeKrHZ64Dy6Z8laYfZiRLqwfcxSxTJQCpoiLgh5zeNBVh fXXaasDLrlAREwGaN/yjKjZ9Pi7nkXaf9njfUfcT5b8xWsR91JpJkx6BWBWCFFCBXXNQ gmjBoQdmn+NsVLBnF3jaLg0XMMwaG9Bm6HWLTlVXfWF6fQgCVj4ohsizj8y9OP7l6S/R kDWSp2W6iDOVAREaQZSVqnQADwOLZURPmEF8AkZt3cDrb54J0vpxvYCe7p/yjEv/tFOE U0UQ31a6ijb3dpeseri6KT2VNL7LcsoT9Y6iIyEFwn7pio6Sc5HjEqufZk5dydhM4jYc CYxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=H+UrwJ0Uc9kZfK3DxO9f4YdqZ7tw2V2PPN3Y5ahvr5k=; b=Tsz1afgeYSdBc/BTBKRsrknWMCGmWf/GNgq7niy0fZAjU5Pn+vtZqwzTKWyso6TX/z hhlkwkgDb3hAhOk+5phagbCHlD3hmZ0xKS1M1yr9h/mww2eRsEVHJ7dcEHXchnGs7Gfe 1/sRBQ/TPa+vlyIamZnB7SSByN5aY0XLbHNt8xGJzbX28pXuRsKQELGdHSYmvrv26ANV oE9opd3E2xikZ8nWuoYzDnYJcW9uhFnsQZwnPswbUO4ioQTSy3Qcfa6/bPw3CX4mWc5n G6eCdusTVnMepBFAYRDF/MjYwS6eCaT/f6UkJ2YbAEo5GDryB0Nw65Dw+Nap9cbdarMI gBvA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k6CDihM8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ib6-20020a0562141c8600b00621120c51c2si5210618qvb.591.2023.06.05.13.17.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:17:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=k6CDihM8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gcw-0001z5-KF; Mon, 05 Jun 2023 16:16:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gck-0001vD-65 for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:18 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcg-00041B-HC for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:17 -0400 Received: by mail-pf1-x433.google.com with SMTP id d2e1a72fcca58-64d44b198baso3830868b3a.0 for ; Mon, 05 Jun 2023 13:16:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996173; x=1688588173; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=H+UrwJ0Uc9kZfK3DxO9f4YdqZ7tw2V2PPN3Y5ahvr5k=; b=k6CDihM83jniika2t/cbIrG5vq9fFnpj1kt1/RSTm37U8gkYEGwfu1W6cBWUe54Ku/ az2ksGqImtF0RlA0NsYLQBZ9o8ceFrkTREsVKxHMauvRmE/6JpCakDyidw32vsVuaqHI /tCWcDK+BWnE0YAHxTw7kuAYunC3poJwcrS3wGvY7wUxiGQY5l0N6bYhyj5NbIrViLxC BIqb33tzmJ9kY0OXFfynjjvNGFOvrDn4dkM9nkKo6GikIdZA1A7l3eJSSLELKb1pevZ+ QsDje79JYa0uI9OhMuQe0oaHuca5cdVEoTfRpnDUpVSLiSIpq26t1D94YcvYazjgJKx6 v//g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996173; x=1688588173; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=H+UrwJ0Uc9kZfK3DxO9f4YdqZ7tw2V2PPN3Y5ahvr5k=; b=OMlTbK85egvJpEg6EsRuWJ7FkjEZKXEZ0/G8HUxAH+De4PrGoXgAcGil0yW6riD5c+ kcpCY27GEXw3mWo5kUNfuxciuCVbOBH60mKyDwd8ZhbV8YA9FWbK1sY15e3tY9pgyOi+ qpAPYiGrMgesdmDSY3b/f4TxvSQvy5vjF9apkpky12WFX/44kT5U3j5t+3gbpvsdsSMD Ch+u5nVZA3fj/fDJ6suQ250/1g2q1mUJ0rNQ3ie9jwQ4FXrj5CHj2HuQoosASNTI1xJU 3Aq/VyPOSK7yJdIOgaHu0xp0/uFvWslSdpc0eY7NLc+hmJM5jHvX6DstZqIMNzaGToKd qotA== X-Gm-Message-State: AC+VfDzCZNjQN0fB93uTH4Ds9AHGKuqaE6ApDyNS3t32V1vhi66j+nhk /ugQk3Qp6D+JvhIQk7K4zFRdak3pE8ElJGby2uM= X-Received: by 2002:a05:6a00:139c:b0:63b:54e4:871b with SMTP id t28-20020a056a00139c00b0063b54e4871bmr107140pfg.8.1685996173315; Mon, 05 Jun 2023 13:16:13 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 27/52] tcg: Add guest_mo to TCGContext Date: Mon, 5 Jun 2023 13:15:23 -0700 Message-Id: <20230605201548.1596865-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This replaces of TCG_GUEST_DEFAULT_MO in tcg-op-ldst.c. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 + accel/tcg/translate-all.c | 5 +++++ tcg/tcg-op-ldst.c | 4 +--- 3 files changed, 7 insertions(+), 3 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 813c733910..9f607e2664 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -521,6 +521,7 @@ struct TCGContext { uint8_t tlb_dyn_max_bits; #endif uint8_t insn_start_words; + TCGBar guest_mo; TCGRegSet reserved_regs; intptr_t current_frame_offset; diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 67b838e16b..200de2793c 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -364,6 +364,11 @@ TranslationBlock *tb_gen_code(CPUState *cpu, (int)offsetof(ArchCPU, neg.tlb.f) - (int)offsetof(ArchCPU, env); #endif tcg_ctx->insn_start_words = TARGET_INSN_START_WORDS; +#ifdef TCG_GUEST_DEFAULT_MO + tcg_ctx->guest_mo = TCG_GUEST_DEFAULT_MO; +#else + tcg_ctx->guest_mo = TCG_MO_ALL; +#endif tb_overflow: diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 3c00bf0c95..9bcf63b041 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -104,9 +104,7 @@ static void gen_ldst_i64(TCGOpcode opc, TCGv_i64 v, TCGTemp *addr, MemOpIdx oi) static void tcg_gen_req_mo(TCGBar type) { -#ifdef TCG_GUEST_DEFAULT_MO - type &= TCG_GUEST_DEFAULT_MO; -#endif + type &= tcg_ctx->guest_mo; type &= ~TCG_TARGET_DEFAULT_MO; if (type) { tcg_gen_mb(type | TCG_BAR_SC); From patchwork Mon Jun 5 20:15:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689226 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2285318wru; Mon, 5 Jun 2023 13:17:10 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ74sk9UpzJQwa7SA52t1UbghIPh6hw5qcxblKihZO1QQx7VDhqUJ/4rdvKobQTRiFf4feba X-Received: by 2002:a05:622a:349:b0:3f3:8f39:3473 with SMTP id r9-20020a05622a034900b003f38f393473mr9946164qtw.26.1685996230658; Mon, 05 Jun 2023 13:17:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996230; cv=none; d=google.com; s=arc-20160816; b=XP98TFof/rH6pYOCJ6F6BWnh1DHG5bP8uBwclc2379IAQj35mWEkhiphp2Nqicg2nb v2Av0xY5bMRwQRQSOutOrbc/BAQDTXPTkUQRt9tz/TTOXuKFlSgID+3OGPjGVJ/taYDJ yCGACbrcv59e8LtRzLgUJgtZCtVglrjS7/Yio8zw2jYdNoEOxYNRnzqKD6Y5Q53R1N1I zVCKnOhyXu8mDbyDdOojx4zzHC9KUg6zfG7VWICITTR4Ah2QN7xxJ3bw5Qscvxdly66x W09g6AJ+LfOzWDWgHH8XX93QTVPAxbGvS08jAZ7cInmtR2c7l0TG66/+cNWqAFMC7d9M iCSw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=N6gCotNJADYlI+Iq7qcqhdrgKIsALIeK+sX1hBJ35+c=; b=MSLUG/gjmsqsrLcv6QBWnFcxUFk3CbZjK98M7B7N0RGo3EL0htygFXxKbmDyTI2pIh +JbJq7VYeTH5PsXKkSmXLYihn0+MMc9NHJnE+b2nGq1AYYyd+sLTH6f1NvoqJfSGQbsQ bIVi1TMTtvfPFZFc+vVfRI513OUuNLLXxJ3KayF/n1Wxk72HfB6nUSSEqXaK0AZUk4HV CIz5N3zYRXXbGTE4JpuVVDR/HfkS/yem8Q2nYzfLgaGuTxfqo1ou64EdQQDogx1ljj8B Y73gyN1hd62KUTiZgF6By7cQMWpMT8zpPOs5WFa5CBHVw0Y/GCrZ5RdMg90jayeDUen8 B5UQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N5kI5gQW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id n19-20020a05622a041300b003ef3fba077asi5081665qtx.558.2023.06.05.13.17.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:17:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N5kI5gQW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gcs-0001xj-P8; Mon, 05 Jun 2023 16:16:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gck-0001vb-Lz for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:19 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gch-0003nm-1D for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:18 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-650c8cb68aeso3084570b3a.3 for ; Mon, 05 Jun 2023 13:16:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996174; x=1688588174; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N6gCotNJADYlI+Iq7qcqhdrgKIsALIeK+sX1hBJ35+c=; b=N5kI5gQWcK663zgbSDcfV6GeOzc1zbabB60uxt99Lytt9SoXflhCHFtk6j9ANt4574 l4K3n+U55FPdV22h8igAwWMrs0pL/P9A1cXzpaliQ8K4YCFK9bLBt51Z6tVcf0AhliCG LPjPkIApLqT9qI5/TG6a1wykwUcbmkAIMG79ucv1Q/LkpcT9rLhKyVuSIX2S8S+G2Fqt ZAyjEKK9OKsKQT6lETYE1BRv6AtL1vWmQbettph7FVB+ECzrLNjFBO+ZoDOgrZ9QBoKR An8BLu8Z40EXeR0W//5zX7UkOW3KI0xfE44bOStTLAcAmpwYGpl1mK8hpwE+6uytqXse A1Ig== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996174; x=1688588174; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N6gCotNJADYlI+Iq7qcqhdrgKIsALIeK+sX1hBJ35+c=; b=KB9qh/GiCOu/V3RSzCGV6tcr2aOOtuLWsQxQPVu4Tv1foN6aNQ4bRwSOyNn3gr5MDT My0VjL1EYXbxTNmgWxRUjsHZujYhBZAMdiQ59OvHZTyi1g2Kujc3V8xM7SUqIvG+iISR 8fFn6TFvq9ZfroWMDLK0j+78xtabVYMxsyaxGCxBOEG+yiYSVSvxQqVPKAaR9GbTWnnk xlgLNqRv0I2CUu0lPft12KGC7eko/6kSw8a5ubJdSjmLemmtOATfhUpIRstECA4yGKTT gPrZNP4HA8cARHu38BiKuE1WqQnUfW7B1gzPGmRv1bmjt+PkrA4TGvFQhGqJNJ6z9Sz5 lwHQ== X-Gm-Message-State: AC+VfDyJeQD+rbIxVyIWt5jVNgZAQcrBikn4xzw3GXIF93GsmgKsADuY SJLDHx3poZjY+jtpQbFIhc6aQgY0VLfekKO1sds= X-Received: by 2002:a05:6a00:198c:b0:64d:6a78:1575 with SMTP id d12-20020a056a00198c00b0064d6a781575mr592131pfl.30.1685996174243; Mon, 05 Jun 2023 13:16:14 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Anton Johansson Subject: [PULL 28/52] tcg: Move TLB_FLAGS_MASK check out of get_alignment_bits Date: Mon, 5 Jun 2023 13:15:24 -0700 Message-Id: <20230605201548.1596865-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The replacement isn't ideal, as the raw count of bits is not easily synced with exec/cpu-all.h, but it does remove from tcg.h the target dependency on TARGET_PAGE_BITS_MIN which is built into TLB_FLAGS_MASK. Reviewed-by: Anton Johansson Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 3 +++ include/tcg/tcg.h | 4 ---- tcg/tcg-op-ldst.c | 18 ++++++++++++++++-- 3 files changed, 19 insertions(+), 6 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 78d258af44..09bf4c0cc6 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -314,6 +314,9 @@ CPUArchState *cpu_copy(CPUArchState *env); * * Use TARGET_PAGE_BITS_MIN so that these bits are constant * when TARGET_PAGE_BITS_VARY is in effect. + * + * The count, if not the placement of these bits is known + * to tcg/tcg-op-ldst.c, check_max_alignment(). */ /* Zero if TLB entry is valid. */ #define TLB_INVALID_MASK (1 << (TARGET_PAGE_BITS_MIN - 1)) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 9f607e2664..635fa53fdb 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -305,10 +305,6 @@ static inline unsigned get_alignment_bits(MemOp memop) /* A specific alignment requirement. */ a = a >> MO_ASHIFT; } -#if defined(CONFIG_SOFTMMU) - /* The requested alignment cannot overlap the TLB flags. */ - tcg_debug_assert((TLB_FLAGS_MASK & ((1 << a) - 1)) == 0); -#endif return a; } diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 9bcf63b041..46a5977b35 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -32,11 +32,23 @@ #include "tcg-internal.h" -static inline MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) +static void check_max_alignment(unsigned a_bits) +{ +#if defined(CONFIG_SOFTMMU) + /* + * The requested alignment cannot overlap the TLB flags. + * FIXME: Must keep the count up-to-date with "exec/cpu-all.h". + */ + tcg_debug_assert(a_bits + 6 <= tcg_ctx->page_bits); +#endif +} + +static MemOp tcg_canonicalize_memop(MemOp op, bool is64, bool st) { - /* Trigger the asserts within as early as possible. */ unsigned a_bits = get_alignment_bits(op); + check_max_alignment(a_bits); + /* Prefer MO_ALIGN+MO_XX over MO_ALIGN_XX+MO_XX */ if (a_bits == (op & MO_SIZE)) { op = (op & ~MO_AMASK) | MO_ALIGN; @@ -491,6 +503,7 @@ static void tcg_gen_qemu_ld_i128_int(TCGv_i128 val, TCGTemp *addr, TCGv_i64 ext_addr = NULL; TCGOpcode opc; + check_max_alignment(get_alignment_bits(memop)); tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); /* TODO: For now, force 32-bit hosts to use the helper. */ @@ -599,6 +612,7 @@ static void tcg_gen_qemu_st_i128_int(TCGv_i128 val, TCGTemp *addr, TCGv_i64 ext_addr = NULL; TCGOpcode opc; + check_max_alignment(get_alignment_bits(memop)); tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); /* TODO: For now, force 32-bit hosts to use the helper. */ From patchwork Mon Jun 5 20:15:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689236 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2286572wru; Mon, 5 Jun 2023 13:20:51 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6jDGnHGJyi39pE812i/SBq4SbL9yzvs7V3SgRFTkwp+YS1BXDPSbRKCWWpZ2oyOBIIXxu0 X-Received: by 2002:a05:6214:20a3:b0:626:1adb:e0f9 with SMTP id 3-20020a05621420a300b006261adbe0f9mr9881167qvd.8.1685996451574; Mon, 05 Jun 2023 13:20:51 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996451; cv=none; d=google.com; s=arc-20160816; b=ois5B2XRjgeQunfThnD7xkaPAzLk6lYGgorv6o4lVJgZJIFqFZH156G9nzFGiDOVXU ovEEVc4oKYD8H12cdWrqM5z3MIsTdhSVED1SBChpaUd02jXGYdgEXq3l4qYR10ppTH+R nRwMa+lySKPkI5kT0IDsWpQC2YeQLEF2uep5vi6O0FyVsWAIMNohjIXFv6Z1ZkTpzQ20 t5YE7qv+380F9L8pCYHJrkuVkIJsLacfzPfLpPE4GuKgyaYmMozVc44q9FlCEKWk9QZ3 OnKDBoiJ2TlkiwSaPqDuoy2DP2PrN7SBYKhxi+jzKNlGo7iaXgTDXy6LC9xBt8s1+cGX ZIZQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LFVirlGNKOWg4+0ZpaYGnVk22AFhf0D/xfLqVNc1goc=; b=pRAdJCXlg+0KNoi3fA6BwzVF22zNi4uPLgDLu0FVQxBh7RZUagfNBSWCabHIu7AhBx frU4fVwww8JPofPNKcte5RzKXHCojwW2agKie4XHCYNqf9q+/RubQTsrTQLqigSYG5Xv 1E12SAe1rmtfg0jnMO9Q2RzI1fnlA19qgs40pE4t4z56Xtolzo/V9+cFgNkcuYhO7lkx nisVBXA4unnmTFHsR0gpA+mvVoYk5YAT2CQKnDZV3J5WX7z8ozjYRaL2l7WKBeivFpdS smniR76mm2iQ1du1yp/UFyHPagGbVjSqRJ+3WfgMW4ZklLKz0eoKM4N6/6liHSjd87uL yg/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UKBzzq+6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g7-20020a0562140ac700b0062377b26de3si5714885qvi.172.2023.06.05.13.20.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:20:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=UKBzzq+6; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gd1-00020q-0p; Mon, 05 Jun 2023 16:16:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gco-0001wu-Dt for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:23 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gci-000431-TK for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:22 -0400 Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-53f7bef98b7so4665074a12.3 for ; Mon, 05 Jun 2023 13:16:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996175; x=1688588175; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=LFVirlGNKOWg4+0ZpaYGnVk22AFhf0D/xfLqVNc1goc=; b=UKBzzq+68Eh9LXMuxRLI4jpSB5uG6EUUVPJ66GzFKi11XNwnzX69Lfy+PprwqpfUeC zHdYfLIIlG7MWhInZgO7ZKp+HV+oUN0NcOC8tlf2hPkUdikAMYZlIwmmt6dweKU05xKF 9cWt2la8WvNDBqFVPee3ZJO8BQ29AnUKT+udFLZD9K8YtQw464y+FdLH/u6EzWMnavO8 VVyaO1ukBvFElLGf5A3HRQU7wJDdXK/wZVBBiX68RYcf3QaJVkvnghWXiq/nZ1iqYCmF W/pnMqp6r65umOrX3AoftKvIBjHoMxkegJRnMzSY7lnvex3gjh8TZj9e6Hrt29bIo4z+ JiIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996175; x=1688588175; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LFVirlGNKOWg4+0ZpaYGnVk22AFhf0D/xfLqVNc1goc=; b=FXlUVS3DydE8X01N+TkBP5bX1wpY+jT6YycOMn5yOq0KKw/vJbkgUT5FT/I5J2jOMK el+NbHq+ODXco+g0DWJPSD1yLTNfZg1EvCmAp+CLfvNUNSijXjMzSJsIPH/iK8dbncz+ wBoP4pWHcwc8diK7cging4RYRgkJ8yY3p9gordGf06unqhjj33RsaEPKYfKkowBsKYyJ Rq0KjajgKVKh+Zhob4C5xDg+PKEr/7Ds3tAA/uhY2THJoihl/tZ17VjnV0pblYpi0ghw 6ZLxK1Lv51AXoskdr2g06oDPCzQzQQCe6irJ1K/yHMY14/L1QZoajJxkZgA9XhvEi6xM BYgQ== X-Gm-Message-State: AC+VfDxKLoYw7Y80PdUjI059GjduylohScslIfcMcoQ1qi/gtJXtRy5P v4vVieC15LorTul77n1EP6UjZ9EcE1ePOJVkqyY= X-Received: by 2002:a05:6a20:12c6:b0:10c:467a:536f with SMTP id v6-20020a056a2012c600b0010c467a536fmr204118pzg.14.1685996174977; Mon, 05 Jun 2023 13:16:14 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 29/52] tcg: Split tcg/tcg-op-gvec.h Date: Mon, 5 Jun 2023 13:15:25 -0700 Message-Id: <20230605201548.1596865-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Create tcg/tcg-op-gvec-common.h, moving everything that does not concern TARGET_LONG_BITS. Adjust tcg-op-gvec.c to use the new header. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec-common.h | 426 +++++++++++++++++++++++++++++ include/tcg/tcg-op-gvec.h | 444 +------------------------------ tcg/tcg-op-gvec.c | 2 +- 3 files changed, 437 insertions(+), 435 deletions(-) create mode 100644 include/tcg/tcg-op-gvec-common.h diff --git a/include/tcg/tcg-op-gvec-common.h b/include/tcg/tcg-op-gvec-common.h new file mode 100644 index 0000000000..e2683d487f --- /dev/null +++ b/include/tcg/tcg-op-gvec-common.h @@ -0,0 +1,426 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Target independent generic vector operation expansion + * + * Copyright (c) 2018 Linaro + */ + +#ifndef TCG_TCG_OP_GVEC_COMMON_H +#define TCG_TCG_OP_GVEC_COMMON_H + +/* + * "Generic" vectors. All operands are given as offsets from ENV, + * and therefore cannot also be allocated via tcg_global_mem_new_*. + * OPRSZ is the byte size of the vector upon which the operation is performed. + * MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleared. + * + * All sizes must be 8 or any multiple of 16. + * When OPRSZ is 8, the alignment may be 8, otherwise must be 16. + * Operands may completely, but not partially, overlap. + */ + +/* Expand a call to a gvec-style helper, with pointers to two vector + operands, and a descriptor (see tcg-gvec-desc.h). */ +typedef void gen_helper_gvec_2(TCGv_ptr, TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz, int32_t data, + gen_helper_gvec_2 *fn); + +/* Similarly, passing an extra data value. */ +typedef void gen_helper_gvec_2i(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); +void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, + uint32_t oprsz, uint32_t maxsz, int32_t data, + gen_helper_gvec_2i *fn); + +/* Similarly, passing an extra pointer (e.g. env or float_status). */ +typedef void gen_helper_gvec_2_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs, + TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, + int32_t data, gen_helper_gvec_2_ptr *fn); + +/* Similarly, with three vector operands. */ +typedef void gen_helper_gvec_3(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz, int32_t data, + gen_helper_gvec_3 *fn); + +/* Similarly, with four vector operands. */ +typedef void gen_helper_gvec_4(TCGv_ptr, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t cofs, uint32_t oprsz, uint32_t maxsz, + int32_t data, gen_helper_gvec_4 *fn); + +/* Similarly, with five vector operands. */ +typedef void gen_helper_gvec_5(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t cofs, uint32_t xofs, uint32_t oprsz, + uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn); + +typedef void gen_helper_gvec_3_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, + TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, + int32_t data, gen_helper_gvec_3_ptr *fn); + +typedef void gen_helper_gvec_4_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz, + uint32_t maxsz, int32_t data, + gen_helper_gvec_4_ptr *fn); + +typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, + TCGv_ptr, TCGv_ptr, TCGv_i32); +void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t cofs, uint32_t eofs, TCGv_ptr ptr, + uint32_t oprsz, uint32_t maxsz, int32_t data, + gen_helper_gvec_5_ptr *fn); + +/* Expand a gvec operation. Either inline or out-of-line depending on + the actual vector size and the operations supported by the host. */ +typedef struct { + /* Expand inline as a 64-bit or 32-bit integer. + Only one of these will be non-NULL. */ + void (*fni8)(TCGv_i64, TCGv_i64); + void (*fni4)(TCGv_i32, TCGv_i32); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec); + /* Expand out-of-line helper w/descriptor. */ + gen_helper_gvec_2 *fno; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The data argument to the out-of-line helper. */ + int32_t data; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Load dest as a 2nd source operand. */ + bool load_dest; +} GVecGen2; + +typedef struct { + /* Expand inline as a 64-bit or 32-bit integer. + Only one of these will be non-NULL. */ + void (*fni8)(TCGv_i64, TCGv_i64, int64_t); + void (*fni4)(TCGv_i32, TCGv_i32, int32_t); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, int64_t); + /* Expand out-of-line helper w/descriptor, data in descriptor. */ + gen_helper_gvec_2 *fno; + /* Expand out-of-line helper w/descriptor, data as argument. */ + gen_helper_gvec_2i *fnoi; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Load dest as a 3rd source operand. */ + bool load_dest; +} GVecGen2i; + +typedef struct { + /* Expand inline as a 64-bit or 32-bit integer. + Only one of these will be non-NULL. */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); + /* Expand out-of-line helper w/descriptor. */ + gen_helper_gvec_2i *fno; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The data argument to the out-of-line helper. */ + uint32_t data; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Load scalar as 1st source operand. */ + bool scalar_first; +} GVecGen2s; + +typedef struct { + /* Expand inline as a 64-bit or 32-bit integer. + Only one of these will be non-NULL. */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); + /* Expand out-of-line helper w/descriptor. */ + gen_helper_gvec_3 *fno; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The data argument to the out-of-line helper. */ + int32_t data; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Load dest as a 3rd source operand. */ + bool load_dest; +} GVecGen3; + +typedef struct { + /* + * Expand inline as a 64-bit or 32-bit integer. Only one of these will be + * non-NULL. + */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t); + /* Expand out-of-line helper w/descriptor, data in descriptor. */ + gen_helper_gvec_3 *fno; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Load dest as a 3rd source operand. */ + bool load_dest; +} GVecGen3i; + +typedef struct { + /* Expand inline as a 64-bit or 32-bit integer. + Only one of these will be non-NULL. */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec); + /* Expand out-of-line helper w/descriptor. */ + gen_helper_gvec_4 *fno; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The data argument to the out-of-line helper. */ + int32_t data; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; + /* Write aofs as a 2nd dest operand. */ + bool write_aofs; +} GVecGen4; + +typedef struct { + /* + * Expand inline as a 64-bit or 32-bit integer. Only one of these will be + * non-NULL. + */ + void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64, int64_t); + void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32, int32_t); + /* Expand inline with a host vector type. */ + void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec, int64_t); + /* Expand out-of-line helper w/descriptor, data in descriptor. */ + gen_helper_gvec_4 *fno; + /* The optional opcodes, if any, utilized by .fniv. */ + const TCGOpcode *opt_opc; + /* The vector element size, if applicable. */ + uint8_t vece; + /* Prefer i64 to v64. */ + bool prefer_i64; +} GVecGen4i; + +void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz, const GVecGen2 *); +void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, int64_t c, const GVecGen2i *); +void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, + uint32_t maxsz, TCGv_i64 c, const GVecGen2s *); +void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz, const GVecGen3 *); +void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz, int64_t c, + const GVecGen3i *); +void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, + uint32_t oprsz, uint32_t maxsz, const GVecGen4 *); +void tcg_gen_gvec_4i(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, + uint32_t oprsz, uint32_t maxsz, int64_t c, + const GVecGen4i *); + +/* Expand a specific vector operation. */ + +void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); + +/* Saturated arithmetic. */ +void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + +/* Min/max. */ +void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t c, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t s, uint32_t m); +void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t s, + uint32_t m, uint64_t imm); +void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s, + uint32_t m, TCGv_i32); +void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s, + uint32_t m, TCGv_i64); + +void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, + int64_t shift, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); + +/* + * Perform vector shift by vector element, modulo the element size. + * E.g. D[i] = A[i] << (B[i] % (8 << vece)). + */ +void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + +void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, + uint32_t aofs, uint32_t bofs, + uint32_t oprsz, uint32_t maxsz); + +/* + * Perform vector bit select: d = (b & a) | (c & ~a). + */ +void tcg_gen_gvec_bitsel(unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t cofs, + uint32_t oprsz, uint32_t maxsz); + +/* + * 64-bit vector operations. Use these when the register has been allocated + * with tcg_global_mem_new_i64, and so we cannot also address it via pointer. + * OPRSZ = MAXSZ = 8. + */ + +void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 a); +void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 a); +void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 a); + +void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); +void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); +void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); + +void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); +void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); +void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); + +void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); +void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); +void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); + +/* 32-bit vector operations. */ +void tcg_gen_vec_add8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); +void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); + +void tcg_gen_vec_sub8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); +void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); + +void tcg_gen_vec_shl8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); +void tcg_gen_vec_shl16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); +void tcg_gen_vec_shr8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); +void tcg_gen_vec_shr16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); +void tcg_gen_vec_sar8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); +void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); + +#endif diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index a8183bfeab..b0a81ad4bf 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -1,447 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ /* - * Generic vector operation expansion + * Target dependent generic vector operation expansion * * Copyright (c) 2018 Linaro - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see . */ #ifndef TCG_TCG_OP_GVEC_H #define TCG_TCG_OP_GVEC_H -/* - * "Generic" vectors. All operands are given as offsets from ENV, - * and therefore cannot also be allocated via tcg_global_mem_new_*. - * OPRSZ is the byte size of the vector upon which the operation is performed. - * MAXSZ is the byte size of the full vector; bytes beyond OPSZ are cleared. - * - * All sizes must be 8 or any multiple of 16. - * When OPRSZ is 8, the alignment may be 8, otherwise must be 16. - * Operands may completely, but not partially, overlap. - */ +#include "tcg/tcg-op-gvec-common.h" -/* Expand a call to a gvec-style helper, with pointers to two vector - operands, and a descriptor (see tcg-gvec-desc.h). */ -typedef void gen_helper_gvec_2(TCGv_ptr, TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_2_ool(uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz, int32_t data, - gen_helper_gvec_2 *fn); - -/* Similarly, passing an extra data value. */ -typedef void gen_helper_gvec_2i(TCGv_ptr, TCGv_ptr, TCGv_i64, TCGv_i32); -void tcg_gen_gvec_2i_ool(uint32_t dofs, uint32_t aofs, TCGv_i64 c, - uint32_t oprsz, uint32_t maxsz, int32_t data, - gen_helper_gvec_2i *fn); - -/* Similarly, passing an extra pointer (e.g. env or float_status). */ -typedef void gen_helper_gvec_2_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_2_ptr(uint32_t dofs, uint32_t aofs, - TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, - int32_t data, gen_helper_gvec_2_ptr *fn); - -/* Similarly, with three vector operands. */ -typedef void gen_helper_gvec_3(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_3_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t oprsz, uint32_t maxsz, int32_t data, - gen_helper_gvec_3 *fn); - -/* Similarly, with four vector operands. */ -typedef void gen_helper_gvec_4(TCGv_ptr, TCGv_ptr, TCGv_ptr, - TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_4_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t cofs, uint32_t oprsz, uint32_t maxsz, - int32_t data, gen_helper_gvec_4 *fn); - -/* Similarly, with five vector operands. */ -typedef void gen_helper_gvec_5(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, - TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_5_ool(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t cofs, uint32_t xofs, uint32_t oprsz, - uint32_t maxsz, int32_t data, gen_helper_gvec_5 *fn); - -typedef void gen_helper_gvec_3_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, - TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_3_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, - TCGv_ptr ptr, uint32_t oprsz, uint32_t maxsz, - int32_t data, gen_helper_gvec_3_ptr *fn); - -typedef void gen_helper_gvec_4_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, - TCGv_ptr, TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_4_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t cofs, TCGv_ptr ptr, uint32_t oprsz, - uint32_t maxsz, int32_t data, - gen_helper_gvec_4_ptr *fn); - -typedef void gen_helper_gvec_5_ptr(TCGv_ptr, TCGv_ptr, TCGv_ptr, TCGv_ptr, - TCGv_ptr, TCGv_ptr, TCGv_i32); -void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t cofs, uint32_t eofs, TCGv_ptr ptr, - uint32_t oprsz, uint32_t maxsz, int32_t data, - gen_helper_gvec_5_ptr *fn); - -/* Expand a gvec operation. Either inline or out-of-line depending on - the actual vector size and the operations supported by the host. */ -typedef struct { - /* Expand inline as a 64-bit or 32-bit integer. - Only one of these will be non-NULL. */ - void (*fni8)(TCGv_i64, TCGv_i64); - void (*fni4)(TCGv_i32, TCGv_i32); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec); - /* Expand out-of-line helper w/descriptor. */ - gen_helper_gvec_2 *fno; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The data argument to the out-of-line helper. */ - int32_t data; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; - /* Load dest as a 2nd source operand. */ - bool load_dest; -} GVecGen2; - -typedef struct { - /* Expand inline as a 64-bit or 32-bit integer. - Only one of these will be non-NULL. */ - void (*fni8)(TCGv_i64, TCGv_i64, int64_t); - void (*fni4)(TCGv_i32, TCGv_i32, int32_t); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec, int64_t); - /* Expand out-of-line helper w/descriptor, data in descriptor. */ - gen_helper_gvec_2 *fno; - /* Expand out-of-line helper w/descriptor, data as argument. */ - gen_helper_gvec_2i *fnoi; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; - /* Load dest as a 3rd source operand. */ - bool load_dest; -} GVecGen2i; - -typedef struct { - /* Expand inline as a 64-bit or 32-bit integer. - Only one of these will be non-NULL. */ - void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); - void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); - /* Expand out-of-line helper w/descriptor. */ - gen_helper_gvec_2i *fno; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The data argument to the out-of-line helper. */ - uint32_t data; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; - /* Load scalar as 1st source operand. */ - bool scalar_first; -} GVecGen2s; - -typedef struct { - /* Expand inline as a 64-bit or 32-bit integer. - Only one of these will be non-NULL. */ - void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64); - void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec); - /* Expand out-of-line helper w/descriptor. */ - gen_helper_gvec_3 *fno; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The data argument to the out-of-line helper. */ - int32_t data; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; - /* Load dest as a 3rd source operand. */ - bool load_dest; -} GVecGen3; - -typedef struct { - /* - * Expand inline as a 64-bit or 32-bit integer. Only one of these will be - * non-NULL. - */ - void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, int64_t); - void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, int32_t); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, int64_t); - /* Expand out-of-line helper w/descriptor, data in descriptor. */ - gen_helper_gvec_3 *fno; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; - /* Load dest as a 3rd source operand. */ - bool load_dest; -} GVecGen3i; - -typedef struct { - /* Expand inline as a 64-bit or 32-bit integer. - Only one of these will be non-NULL. */ - void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64); - void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec); - /* Expand out-of-line helper w/descriptor. */ - gen_helper_gvec_4 *fno; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The data argument to the out-of-line helper. */ - int32_t data; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; - /* Write aofs as a 2nd dest operand. */ - bool write_aofs; -} GVecGen4; - -typedef struct { - /* - * Expand inline as a 64-bit or 32-bit integer. Only one of these will be - * non-NULL. - */ - void (*fni8)(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_i64, int64_t); - void (*fni4)(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_i32, int32_t); - /* Expand inline with a host vector type. */ - void (*fniv)(unsigned, TCGv_vec, TCGv_vec, TCGv_vec, TCGv_vec, int64_t); - /* Expand out-of-line helper w/descriptor, data in descriptor. */ - gen_helper_gvec_4 *fno; - /* The optional opcodes, if any, utilized by .fniv. */ - const TCGOpcode *opt_opc; - /* The vector element size, if applicable. */ - uint8_t vece; - /* Prefer i64 to v64. */ - bool prefer_i64; -} GVecGen4i; - -void tcg_gen_gvec_2(uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz, const GVecGen2 *); -void tcg_gen_gvec_2i(uint32_t dofs, uint32_t aofs, uint32_t oprsz, - uint32_t maxsz, int64_t c, const GVecGen2i *); -void tcg_gen_gvec_2s(uint32_t dofs, uint32_t aofs, uint32_t oprsz, - uint32_t maxsz, TCGv_i64 c, const GVecGen2s *); -void tcg_gen_gvec_3(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t oprsz, uint32_t maxsz, const GVecGen3 *); -void tcg_gen_gvec_3i(uint32_t dofs, uint32_t aofs, uint32_t bofs, - uint32_t oprsz, uint32_t maxsz, int64_t c, - const GVecGen3i *); -void tcg_gen_gvec_4(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, - uint32_t oprsz, uint32_t maxsz, const GVecGen4 *); -void tcg_gen_gvec_4i(uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t cofs, - uint32_t oprsz, uint32_t maxsz, int64_t c, - const GVecGen4i *); - -/* Expand a specific vector operation. */ - -void tcg_gen_gvec_mov(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_not(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_neg(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_abs(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_add(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_sub(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_mul(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_addi(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_muli(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t c, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_adds(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_subs(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_muls(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); - -/* Saturated arithmetic. */ -void tcg_gen_gvec_ssadd(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_sssub(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_usadd(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_ussub(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); - -/* Min/max. */ -void tcg_gen_gvec_smin(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_umin(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_smax(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_umax(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_and(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_or(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_xor(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_andc(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_orc(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_nand(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_nor(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_eqv(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_xori(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t c, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_dup_mem(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t s, uint32_t m); -void tcg_gen_gvec_dup_imm(unsigned vece, uint32_t dofs, uint32_t s, - uint32_t m, uint64_t imm); -void tcg_gen_gvec_dup_i32(unsigned vece, uint32_t dofs, uint32_t s, - uint32_t m, TCGv_i32); -void tcg_gen_gvec_dup_i64(unsigned vece, uint32_t dofs, uint32_t s, - uint32_t m, TCGv_i64); - -#if TARGET_LONG_BITS == 64 -# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64 -#else -# define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32 +#ifndef TARGET_LONG_BITS +#error must include QEMU headers #endif -void tcg_gen_gvec_shli(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_shri(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_sari(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_rotli(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_rotri(unsigned vece, uint32_t dofs, uint32_t aofs, - int64_t shift, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_shls(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_shrs(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs, - TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); - -/* - * Perform vector shift by vector element, modulo the element size. - * E.g. D[i] = A[i] << (B[i] % (8 << vece)). - */ -void tcg_gen_gvec_shlv(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_shrv(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_sarv(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_rotlv(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); -void tcg_gen_gvec_rotrv(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t oprsz, uint32_t maxsz); - -void tcg_gen_gvec_cmp(TCGCond cond, unsigned vece, uint32_t dofs, - uint32_t aofs, uint32_t bofs, - uint32_t oprsz, uint32_t maxsz); - -/* - * Perform vector bit select: d = (b & a) | (c & ~a). - */ -void tcg_gen_gvec_bitsel(unsigned vece, uint32_t dofs, uint32_t aofs, - uint32_t bofs, uint32_t cofs, - uint32_t oprsz, uint32_t maxsz); - -/* - * 64-bit vector operations. Use these when the register has been allocated - * with tcg_global_mem_new_i64, and so we cannot also address it via pointer. - * OPRSZ = MAXSZ = 8. - */ - -void tcg_gen_vec_neg8_i64(TCGv_i64 d, TCGv_i64 a); -void tcg_gen_vec_neg16_i64(TCGv_i64 d, TCGv_i64 a); -void tcg_gen_vec_neg32_i64(TCGv_i64 d, TCGv_i64 a); - -void tcg_gen_vec_add8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); -void tcg_gen_vec_add16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); -void tcg_gen_vec_add32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); - -void tcg_gen_vec_sub8_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); -void tcg_gen_vec_sub16_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); -void tcg_gen_vec_sub32_i64(TCGv_i64 d, TCGv_i64 a, TCGv_i64 b); - -void tcg_gen_vec_shl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); -void tcg_gen_vec_shl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); -void tcg_gen_vec_shr8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); -void tcg_gen_vec_shr16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); -void tcg_gen_vec_sar8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); -void tcg_gen_vec_sar16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t); -void tcg_gen_vec_rotl8i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); -void tcg_gen_vec_rotl16i_i64(TCGv_i64 d, TCGv_i64 a, int64_t c); - -/* 32-bit vector operations. */ -void tcg_gen_vec_add8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); -void tcg_gen_vec_add16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); - -void tcg_gen_vec_sub8_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); -void tcg_gen_vec_sub16_i32(TCGv_i32 d, TCGv_i32 a, TCGv_i32 b); - -void tcg_gen_vec_shl8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); -void tcg_gen_vec_shl16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); -void tcg_gen_vec_shr8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); -void tcg_gen_vec_shr16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); -void tcg_gen_vec_sar8i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); -void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); - #if TARGET_LONG_BITS == 64 +#define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i64 #define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i64 #define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i64 #define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i64 @@ -454,8 +28,8 @@ void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); #define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i64 #define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i64 #define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i64 - -#else +#elif TARGET_LONG_BITS == 32 +#define tcg_gen_gvec_dup_tl tcg_gen_gvec_dup_i32 #define tcg_gen_vec_add8_tl tcg_gen_vec_add8_i32 #define tcg_gen_vec_sub8_tl tcg_gen_vec_sub8_i32 #define tcg_gen_vec_add16_tl tcg_gen_vec_add16_i32 @@ -468,6 +42,8 @@ void tcg_gen_vec_sar16i_i32(TCGv_i32 d, TCGv_i32 a, int32_t); #define tcg_gen_vec_shl16i_tl tcg_gen_vec_shl16i_i32 #define tcg_gen_vec_shr16i_tl tcg_gen_vec_shr16i_i32 #define tcg_gen_vec_sar16i_tl tcg_gen_vec_sar16i_i32 +#else +# error #endif #endif diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 7a9599e49e..95a588d6d2 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -21,7 +21,7 @@ #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op-common.h" -#include "tcg/tcg-op-gvec.h" +#include "tcg/tcg-op-gvec-common.h" #include "tcg/tcg-gvec-desc.h" #define MAX_UNROLL 4 From patchwork Mon Jun 5 20:15:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689273 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2289186wru; Mon, 5 Jun 2023 13:28:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5uUhWHnncG/tArUpkzNkn/RVyda/r5NS1nNtN6vRFcFltUhiiFPyaGnm60Bxzwyc8Pk6it X-Received: by 2002:a05:6214:d85:b0:616:5f27:b96a with SMTP id e5-20020a0562140d8500b006165f27b96amr8150262qve.27.1685996927152; Mon, 05 Jun 2023 13:28:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996927; cv=none; d=google.com; s=arc-20160816; b=GujdmQHDd8xXFTy65/dE0VG47EH8I2k8Nn4nax33JU7YxLk0pEjoItzICgGCJWtjN2 opgSwQz2g0gnU9yHoNfJIS8weSgb5UaW5AXCbJfNR3VjmqftH1AI0g0VDYdyocoX/DXz eJVJh/txR4uAlgDtmFpyeAk6dOqfsLTPRIbVZVb3lDunN+DVO27vK1mYthSlbpErIp27 xaYxh1Av/MQr0JBloJ7JpbR8jt2uR5DDd/s/8GzR9eFU0Ygk66WOLDEw6fY6Balo/qs7 9QqhJrJ7VfSQVIdvweXbwaZI1IHHU1KciLROc5blafMGmOtXRYQW9bp1Fa8a/S1fQKk2 xp2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=QQUG9TNMAhGpe5iTw0NjCb9NduwuP3cDZzAY6JDjg7s=; b=RtHuuLauep1xzdOyr80WknZTG1KE6RGIgBcPuY4te5MHmMAnbxGS7ALfpYTvk/Am2R NQUep4kwKi5pJqioS1+GOejKjXNpZlAyfaL1jgKzqDl0/gMkiCPLHebsasW2mdfF1+G2 AvgKJqj1ZsAVAj6ZYR5X/wf8tGK+4RSSOu2s8bCrnWdrlCfhZ8F+zLze3yIbf2WTcej+ pLhrz1qx2hejiZaEusni4aPyYr2bROYIzJvKqEpOHtr17BklHURFJCVmOlw/eNn5bFb1 0ZvsWAtVeqNkPUGtUlFDgDoioMj5f/Yx7KJDywlFGwRxe8Xg7xWmGD9dy7L/C/54yT8r XLAw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A1ibxh1Q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h20-20020a05620a10b400b0075cdcd61ee0si5068655qkk.458.2023.06.05.13.28.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:28:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=A1ibxh1Q; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gd7-00027k-Us; Mon, 05 Jun 2023 16:16:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcm-0001w5-HP for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:21 -0400 Received: from mail-pf1-x42d.google.com ([2607:f8b0:4864:20::42d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gci-0003wa-Gv for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:19 -0400 Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-651e298be3fso5056884b3a.2 for ; Mon, 05 Jun 2023 13:16:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996176; x=1688588176; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QQUG9TNMAhGpe5iTw0NjCb9NduwuP3cDZzAY6JDjg7s=; b=A1ibxh1Qkibzo2eHJdY2uXXamA4TxyfF2AkSKBFzeSHfaMGqAuIfwXEK3snz7JwE4x 2bU3HPF+pKQvVIYbuJGEQ+fQZ9EpQalQj6jQtXkRGgTMsUq+sAFfrjHUT5voJydTVyP3 S9i/x/FwShNCuNIByONhPE6/x0AJPaO1q1Da0ff8TYZIDtfK1GE8An2FVVKdO3FU/sqe 3DkM7K85tycCaZHlZRsNAErPOF16vYlt7N2wzKB2zQ9qEMWcLPi33spdni63W65E/ZK8 svDPevKuejrM6s235bkbG19o/Jt6mV6w/f7MUlNUsJQVEs1n2ii1rfnm1jwYu6S23vuU Rlew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996176; x=1688588176; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QQUG9TNMAhGpe5iTw0NjCb9NduwuP3cDZzAY6JDjg7s=; b=CRUYJJp0l97VPJ9NTsfyVrIJYmtnJyh4PLcxHLKI4zLPRDGGp62us0LSbtpkcvlMNI jV1Gh+th162mUMO02juixjQikT+GNQVOz/dev1pvVgETxVDex4ofDcTMi5Uss1bq9gKp RRipVZ7y+Ul1e3bxeHpdPfRO0EDFReZMYBa9egOCsUgPIdNVPx+w18diREDvkt2pRH2g wvdIuhKoeld06RJgNSjE/oO7VxetRGZk5u/psmz0IyfiAOk2/nuo8g2HjpLi/S+i32a8 cW/xwe7Nx3mAnhknh70uM4IrORUKeOkedAMsgixvTkQzD8F/NNQ8RUptjEs3dgVMHKnE CwOw== X-Gm-Message-State: AC+VfDwf9HW+AuQIyn2GXLqVr1dIfM5UWvYAKy1s0JHvuhPEsbXyy2CY Z3GOf4RazTouNkFEoGPg19MfTWcQI+zaaqsI0NU= X-Received: by 2002:a05:6a00:2292:b0:643:9e7c:3829 with SMTP id f18-20020a056a00229200b006439e7c3829mr1014996pfe.12.1685996175735; Mon, 05 Jun 2023 13:16:15 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 30/52] tcg: Remove NO_CPU_IO_DEFS Date: Mon, 5 Jun 2023 13:15:26 -0700 Message-Id: <20230605201548.1596865-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42d; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org >From this remove, it's no longer clear what this is attempting to protect. The last time a use of this define was added to the source tree, as opposed to merely moved around, was 2008. There have been many cleanups since that time and this is no longer required for the build to succeed. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/ppc/cpu.h | 2 -- target/sparc/cpu.h | 2 -- accel/tcg/translate-all.c | 1 - tcg/tcg.c | 6 ------ 4 files changed, 11 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 0f9f2e1a0c..10c4ffa148 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1394,7 +1394,6 @@ void ppc_store_msr(CPUPPCState *env, target_ulong value); void ppc_cpu_list(void); /* Time-base and decrementer management */ -#ifndef NO_CPU_IO_DEFS uint64_t cpu_ppc_load_tbl(CPUPPCState *env); uint32_t cpu_ppc_load_tbu(CPUPPCState *env); void cpu_ppc_store_tbu(CPUPPCState *env, uint32_t value); @@ -1435,7 +1434,6 @@ int ppcemb_tlb_check(CPUPPCState *env, ppcemb_tlb_t *tlb, hwaddr booke206_tlb_to_page_size(CPUPPCState *env, ppcmas_tlb_t *tlb); #endif -#endif void ppc_store_fpscr(CPUPPCState *env, target_ulong val); void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit, diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index fb98843dad..3d090e8278 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -581,7 +581,6 @@ G_NORETURN void sparc_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, uintptr_t retaddr); G_NORETURN void cpu_raise_exception_ra(CPUSPARCState *, int, uintptr_t); -#ifndef NO_CPU_IO_DEFS /* cpu_init.c */ void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); void sparc_cpu_list(void); @@ -637,7 +636,6 @@ static inline int tlb_compare_context(const SparcTLBEntry *tlb, return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK); } -#endif #endif /* cpu-exec.c */ diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index 200de2793c..c4d081f5ad 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" -#define NO_CPU_IO_DEFS #include "trace.h" #include "disas/disas.h" #include "exec/exec-all.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index a339e3e3d8..41186f540f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -34,12 +34,6 @@ #include "qemu/cacheflush.h" #include "qemu/cacheinfo.h" #include "qemu/timer.h" - -/* Note: the long term plan is to reduce the dependencies on the QEMU - CPU definitions. Currently they are used for qemu_ld/st - instructions */ -#define NO_CPU_IO_DEFS - #include "exec/exec-all.h" #include "exec/tlb-common.h" #include "tcg/tcg-op-common.h" From patchwork Mon Jun 5 20:15:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689268 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288851wru; Mon, 5 Jun 2023 13:27:48 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ49XQ1ocYiW5Zp2yl9NGXbiI5UjNGcYzyxFwonGBvHqtsuj02NJ5lWh2mXYyrZT8ZFbypf1 X-Received: by 2002:a05:620a:2d92:b0:75b:23a1:8e7c with SMTP id tr18-20020a05620a2d9200b0075b23a18e7cmr711579qkn.77.1685996868113; Mon, 05 Jun 2023 13:27:48 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996868; cv=none; d=google.com; s=arc-20160816; b=iG+Iv9zDnT5THsD5TmlfQGaVw5YezzsmuTXq5XMH20zH7cR3ODI7AjvvKbPfMeugLS XiqWBgetw1JsDUis7B74S6aKHe6ZX/TPS3KgZldMyZ9NoOokZ+REuxRyoS+pVjEwmQ11 npSkPH2C+qxBNCAwDyPDFfsThLaHis9XB2LkXRREeYRgWjY4ctPuQO6AN2YfQLAYqT+Z FP8xxfMLMnbzOMosfy1A5JpSD3IUYI7XxLVgiuOZnt3MXsZGUgBQXIgUT9HpZaKPyG6h gDv7BP08OzKqXcgwfyIAB4vT5QLvdfxQv23jKjU8WR088/3Lm6y0VkaQlqMDAqFBdoWL wJIQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=JtgBRGxv4LHPMzETUNJDv9zePk7Nq2QT5FVC8r8aRSI=; b=h5FQX4/UtxruzQsB5IM0OBljq/s15xD0Dt7AAJSW04mWaGBvwWfxy3JFAPFMcEP1uB suVj/YuAEUYuU04r4j1QQ9jA7W9Xzoz3dIymEIaKa2oAaLhpMllSj+KBQdTUOvkSJusf 16v3Ktod4YiDTDuWGmJsz/L0IbnxOlvc/osc1SmMm5MJwxB845YWz1NCMa9AtMmgywxF v0DL5b7DCpImN9DkBORtkay4FIOh1EvjZNmfcBGoy2vukmtHeSYciyfk2mkWpLMs3e7M ZeYc2XJZvBc0fVcnW8jqcPYYy+PwaqzW31/muoXEIH+5vCgygARixIkprI6IYdMVtcGP XLVA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="khWtX/Cx"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id c22-20020a05620a165600b00757970ad032si5002789qko.86.2023.06.05.13.27.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:27:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="khWtX/Cx"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gd5-00025r-P2; Mon, 05 Jun 2023 16:16:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcr-0001xX-4H for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:26 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcj-00045f-Qi for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:23 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-65299178ac5so4817540b3a.1 for ; Mon, 05 Jun 2023 13:16:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996176; x=1688588176; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=JtgBRGxv4LHPMzETUNJDv9zePk7Nq2QT5FVC8r8aRSI=; b=khWtX/Cx5Mwl3P5pZnNM2SPo/0tGqQChHLciwte8WMqqtFdbDDJ9zl1hxh9Zy0wii7 ioCsIW6eHb4vxEV88kZnvxQ1n4i91rV9jUYgJDwBKlFQ08Tanui9+vJWRUBuIpuvlNLg WXUD6ciEUA/D1nusaCkfRE0fvntZf00pY9CvIMO7KQGLpQZw9oMtC1oMF7TyRqM2rRc6 doUP3AmU4K/3Et+lv8ToN0fmqwHd4oX995H8/cBUchTauN86jgqn6JnfCo4r5B+glt6E Xn1bJt0qfs2r3bnQq3SHuKccuXXZ2WmjYO/lq7v+hP4jkVgiIEL3+lvCSWzHtIsEVsoL MHRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996176; x=1688588176; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=JtgBRGxv4LHPMzETUNJDv9zePk7Nq2QT5FVC8r8aRSI=; b=TV8zce+TeY3IqOPynRrbOVFGU+pQF6k2jDgqcLK+3PjEgVcFUFzqZAKq0w89Iep/xM +0pWrGxLDmWieBHuZuEgwuYqbTIabATTEftJJJEQ1gXC3FFIxMUnxbz4ARQXphd3Q/qr d+rSKP8pYSsKLlAW/4F/EYYL2qAfNBjWiLgALIm98C8rODVXl7RAMADgEPH4552RCJ+G hR34vQ/t2RDxo8bbMRAmeSEJecIEpS5pWoRQZQS7O5sS15IJaLOGi++r5H0X5iHS7Lrg +jTd0lAyCTM0cgtSfW4fThqUuyVST7qIa2VfEN8+RsAEgBdTU6MN6eR49eTyp4aHhcF5 z9Vg== X-Gm-Message-State: AC+VfDxaXpkzW3PmFDBwCKHoGR9b+WcMfb9ocuQ0f6DcshKLCHL+Vhhf QpqEARbJe4FiAY6VfhxRmdIOW+48/4qEAxMQ04A= X-Received: by 2002:a05:6a00:1405:b0:64e:bce9:3229 with SMTP id l5-20020a056a00140500b0064ebce93229mr1036186pfu.9.1685996176605; Mon, 05 Jun 2023 13:16:16 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 31/52] exec-all: Widen tb_page_addr_t for user-only Date: Mon, 5 Jun 2023 13:15:27 -0700 Message-Id: <20230605201548.1596865-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is a step toward making TranslationBlock agnostic to the address size of the guest. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 3b1b57f6ad..ec0902c532 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -31,8 +31,8 @@ addresses in userspace mode. Define tb_page_addr_t to be an appropriate type. */ #if defined(CONFIG_USER_ONLY) -typedef abi_ulong tb_page_addr_t; -#define TB_PAGE_ADDR_FMT TARGET_ABI_FMT_lx +typedef vaddr tb_page_addr_t; +#define TB_PAGE_ADDR_FMT "%" VADDR_PRIx #else typedef ram_addr_t tb_page_addr_t; #define TB_PAGE_ADDR_FMT RAM_ADDR_FMT From patchwork Mon Jun 5 20:15:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689267 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288850wru; Mon, 5 Jun 2023 13:27:48 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5l8+i8CEAeeVH+MCnSzaUtrmPCkaP0rtqJFOXoww8pUnmE19c36VC5WzelCEzqYSB/3aFH X-Received: by 2002:a05:6214:765:b0:629:e646:bdbe with SMTP id f5-20020a056214076500b00629e646bdbemr6885061qvz.24.1685996867883; Mon, 05 Jun 2023 13:27:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996867; cv=none; d=google.com; s=arc-20160816; b=w/ReT7HDS0x4BsiGwNbvwd5dn12SqzBxXz8q79X3G3FDFl1nWpHGixmDVk/z+XJHzy x+EZuyCAabaq1OhizuTPYvtPw/zq+DrTd6iNEr93kpJy8M0JV+JjgcK3cxCYKFgW2g6L D55SY/ESGx2VtVk/y59l9EpSWTgtV9J/iTCqo24G0y+++fFSKqKHxeZKgyuln7X4vx3o Bm4WKEemB8/wsfb2nxYA6Kj+Ck/CViqjtQeNJFOvxNmrPjFop0aYoNj5II+4Rn9bSPZ0 ayAelQnKgGXvzjuKUTz6AIEADaMDWHlvBvwwRUt5fi57qpnZKQsWb0ZkvQEnlyvDrmmI aubQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+U9mZ3FA6jaY40YGmde+3aLN2iMAzeCKrJsFXalAAtk=; b=DVFkt28Zg2hb67L3gLBp3mA9Lf/YyootCd3NoczI+fCsrscNRLaWKpYPGLAln/kYJU IknBwa3AqcEWLtKt4AR3VpFfBK6Af+ChdZ9HaGd7IqW5stEl9y0uf7vy3B0KoN4YlYTy fmW3/65zlfu6Uw1wLi1QDPKSz2V6x1kLG3jARRDoD9ZOOHH1PwKIrHk2gP069foMEZYY hDtStqRZk+E5sAj2n7TJ8LOU0VCKcTslyBMwoAExGsCniYVsHFkVz7mUFCZgtBT89Hk5 7iY3a9jB2lGFXn9lKlGqnHBNwzL4iPLV/dLvp++jtjVwl2KKFC33Cw+q61pIw+s4mvr1 zs/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="xGp9/qjm"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id jv14-20020a05621429ee00b006258465cd73si5248054qvb.516.2023.06.05.13.27.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:27:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="xGp9/qjm"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gd4-00021U-0O; Mon, 05 Jun 2023 16:16:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcn-0001wr-VU for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:23 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gck-00046c-Nl for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:21 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-6549df4321aso2693798b3a.2 for ; Mon, 05 Jun 2023 13:16:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996177; x=1688588177; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+U9mZ3FA6jaY40YGmde+3aLN2iMAzeCKrJsFXalAAtk=; b=xGp9/qjmvB3DJS3BK5UocnC0PdvuJo647Iz7f4D6AOe0LDN5HD+dmAU70dJLJF4mb+ L8mUyyOgZ7Bd4vVL5kyGpaSGEWcpZsQfkC287SRIRYB/CaceQ5R0F4m5MgIRWeI9kZMk rZ8IISg2b9xm7/7qB2h08KDYGhrzYcEY3MHbXLBlIChuW9aTtMd3qWHLdIXAq5Bdxeqq WHpJyBQLKGE2by8Q0NMvdzRkePPe7156JP0+emux38iQXXEqo+vodEwOGguPvZ2D+JPP ThGcSc46nUg26o5IMx2KDITXUUPd4Ve5H+PVQfop1Nso9Y3mQhxwWqltxcMbSXECbnog LIOw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996177; x=1688588177; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+U9mZ3FA6jaY40YGmde+3aLN2iMAzeCKrJsFXalAAtk=; b=VcAZ/5D6P3mcWoguT+i6eGEqyyuoJ+V1RnCv8YawORNxrtj7pwQN3S1jWgOGokg2A/ BjxS55VvRo2UgteHtqahZnIaxmLhSOjLNuCjdIZ1hvmxbFeLaMTNmSNAeTbeerUQ1dbP Gur0wPUosT0RvBNH1e9zKbGNjfrIFLUvpMCiOrnsuxxe0RywFBe7z1sAao6FpcgtS9Tl u70FSTIGN9quAuZkgBKS8Dkddf+UVmT3FDGpvJ2+6CKRo61Lr/cD5lg+aj0Fr2HI72XA z4TnRLZSxTNmmPc9Ek8KKVvNpS1w8JbV6b8n1/9Y6MtoepuyaA+j6KCsNrmKWoQzU7R0 zhqA== X-Gm-Message-State: AC+VfDx3ujuJ/RtDKM4F9g8dV+sZTlpxVGeApSoH0dhQM4vtl3w/UAtR KHJ0dw1e3wwTS+zc8oP/RDZ85yuzJxf1F6pjpmU= X-Received: by 2002:a05:6a00:cd5:b0:63f:2f00:c6d with SMTP id b21-20020a056a000cd500b0063f2f000c6dmr1062711pfv.2.1685996177319; Mon, 05 Jun 2023 13:16:17 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 32/52] exec-all: Widen TranslationBlock pc and cs_base to 64-bits Date: Mon, 5 Jun 2023 13:15:28 -0700 Message-Id: <20230605201548.1596865-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This makes TranslationBlock agnostic to the address size of the guest. Use vaddr for pc, since that's always a virtual address. Use uint64_t for cs_base, since usage varies between guests. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 4 ++-- accel/tcg/cpu-exec.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index ec0902c532..dec17b1e62 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -516,7 +516,7 @@ struct TranslationBlock { * Unwind information is taken as offsets from the page, to be * deposited into the "current" PC. */ - target_ulong pc; + vaddr pc; /* * Target-specific data associated with the TranslationBlock, e.g.: @@ -525,7 +525,7 @@ struct TranslationBlock { * s390x: instruction data for EXECUTE, * sparc: the next pc of the instruction queue (for delay slots). */ - target_ulong cs_base; + uint64_t cs_base; uint32_t flags; /* flags defining in which context the code was generated */ uint32_t cflags; /* compile flags */ diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 60ca9e229e..1cf4f1fa22 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -297,7 +297,7 @@ static void log_cpu_exec(target_ulong pc, CPUState *cpu, { if (qemu_log_in_addr_range(pc)) { qemu_log_mask(CPU_LOG_EXEC, - "Trace %d: %p [" TARGET_FMT_lx + "Trace %d: %p [%08" PRIx64 "/" TARGET_FMT_lx "/%08x/%08x] %s\n", cpu->cpu_index, tb->tc.ptr, tb->cs_base, pc, tb->flags, tb->cflags, lookup_symbol(pc)); From patchwork Mon Jun 5 20:15:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689256 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288286wru; Mon, 5 Jun 2023 13:26:10 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4oMhN36WWkBlWuDRb1yzhRdyfkg53h4pEQNHN9hI7vsSMGGsk317MD6GFhuvp/xxLp6OwD X-Received: by 2002:a37:6303:0:b0:75b:23a1:361c with SMTP id x3-20020a376303000000b0075b23a1361cmr791454qkb.45.1685996770514; Mon, 05 Jun 2023 13:26:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996770; cv=none; d=google.com; s=arc-20160816; b=NClxmzKfytPj0zhow6UYt3AKvcSIp7XpFS6mDVPn1Zh9E6wqF9Sd1xV8IX2ginWx/Q ONeVYFU5QVU3Nydlk6JBBl6tiubeEVx3XBPE+cjGe/3FPOLA4MVfPzQ2lMt1WYlqXQaG mY3uf3E27S2AG70uq3G2Jwgw0AApH3eNqprk6HEEmc09J8I021AdSEKqlT9trR6qgpzY DRcYXPkAQTksNcjUWJArmpbJ+dYCOYPUD01gZgGFb+4GiMWaUp1/P+wuSyjvW+KKIQOq 9tDbwOINdUUMcIvufcym2N70YdMIBfjm0dddhKHsmkoOKkiDvDaAuXhQZ/kcGLm3T7yF uc4Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Gok/eEXph8JwhZ+2bEPl//fere5CiJb9U69eP8Df9l8=; b=C18KwHSSDX0Ik4tPfG7jl6ao29DBopGVEHxoaLQJkYZcJKTwWkvmOGiMMhgKoSUGg3 uVudtCp5dbRxTShyHMjLrS2+xq4ZPKUjHnCouklniOz8bsW4KPizVf3NjrliuJ+I6MKG gWFldbK6heDyuFVVLKoqkcRjoe3fyRFG5hhq6gyZbcL+d7LFUjLAXqloyhWe4iGiqV3t 0RUtT+a7aH1vwlvr5bf7eF6P/QWIZWdN6+jzuSdtyTmZx9RLOefbCk2QxbSh7MK8Q0Hu ypsOkolSSnbf2kDm+jik20hnBv15M3N6XGOcDCsIjMNSh6G9u3G8KS8lWwHdFasbrXBt A22Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z8J5ljeE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id l18-20020ae9f012000000b0075b299b1980si4783401qkg.384.2023.06.05.13.26.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:26:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Z8J5ljeE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gd3-00021N-RS; Mon, 05 Jun 2023 16:16:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcr-0001xY-5O for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:26 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcl-0003jW-7S for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:23 -0400 Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-655fce0f354so1323531b3a.0 for ; Mon, 05 Jun 2023 13:16:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996178; x=1688588178; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Gok/eEXph8JwhZ+2bEPl//fere5CiJb9U69eP8Df9l8=; b=Z8J5ljeE8g5U3TM4QPF4i2QwDIM0Hc4t266ZQW+Xc+bbk+jfhWkvIS8Z73evr46hCn HnBKVfZQksiN7vttc6GvqvXW3pp9CsR/wtFyrL6XGViULz4GO40fFW6mC7zm7fou/LYa TSBQNQ1sxPRPNh6FsfKAi1LrWWltvd3KVOyEbGnVhCOaTrw32LnrY6fKz5ByzUXcsBoc ALHDsh2wXHjfgbFwNhmutlqKSyv/x4WW+EGwCxA07B7Msv9xuHAVV1eNJv50+fz3Rj3A Xe1hWBXkwJMtso/dFm+IVeyCy2zitPelKCa+a+CVAMUziU9OlGK532szSozjWiA/KRM/ IC9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996178; x=1688588178; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Gok/eEXph8JwhZ+2bEPl//fere5CiJb9U69eP8Df9l8=; b=cy0tvLU2OOj6q7DdiCzQDtGPrIkSsbt+c04C7D3u9R6KC/RWhe57pdjfOc/lZc3B4w lSHPPI7xoxwUzjU715Kr/MNkShraLw/17VDbWCnyjStDjaYnQL2rAERyGTqLz2s93Wbb 8jJIle5ShZagYRmCB6goyuUAnqPLDqRfKaNgalkAjGY5qqFdH85Ieb4Hn1e8CZRSNs6W ydQn9AtVhrlKZWla6Hd798CLdN1bR9s+KnB57H6uXyC3fNXQJ0PlQfcfU51UhyNee74b f0qHC62h9/aFA5KWyHOykqvcVPsEL87qtX/iVWhYXxcaPJ1yczE4xqPN2pJOgLzftbY5 w34w== X-Gm-Message-State: AC+VfDxXDxDo+iYwlbHsFYetl8Ir8V41/CQDsbVYpQiy364x64YYpyZ1 ekxm+btQOqi5L8hl16JjMZU58j1auH+HG025UJ0= X-Received: by 2002:a05:6a00:17a4:b0:64d:123d:cc74 with SMTP id s36-20020a056a0017a400b0064d123dcc74mr940123pfg.4.1685996178238; Mon, 05 Jun 2023 13:16:18 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 33/52] tcg: Spit out exec/translation-block.h Date: Mon, 5 Jun 2023 13:15:29 -0700 Message-Id: <20230605201548.1596865-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is all that is required by tcg/ from exec-all.h. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 132 +-------------------------- include/exec/translation-block.h | 149 +++++++++++++++++++++++++++++++ tcg/tcg-op-ldst.c | 2 +- 3 files changed, 151 insertions(+), 132 deletions(-) create mode 100644 include/exec/translation-block.h diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index dec17b1e62..f01c7d57e8 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -24,20 +24,9 @@ #ifdef CONFIG_TCG #include "exec/cpu_ldst.h" #endif -#include "qemu/interval-tree.h" +#include "exec/translation-block.h" #include "qemu/clang-tsa.h" -/* Page tracking code uses ram addresses in system mode, and virtual - addresses in userspace mode. Define tb_page_addr_t to be an appropriate - type. */ -#if defined(CONFIG_USER_ONLY) -typedef vaddr tb_page_addr_t; -#define TB_PAGE_ADDR_FMT "%" VADDR_PRIx -#else -typedef ram_addr_t tb_page_addr_t; -#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT -#endif - /** * cpu_unwind_state_data: * @cpu: the cpu context @@ -478,8 +467,6 @@ int probe_access_full(CPUArchState *env, target_ulong addr, int size, CPUTLBEntryFull **pfull, uintptr_t retaddr); #endif -#define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ - /* Estimated block size for TB allocation. */ /* ??? The following is based on a 2015 survey of x86_64 host output. Better would seem to be some sort of dynamically sized TB array, @@ -490,123 +477,6 @@ int probe_access_full(CPUArchState *env, target_ulong addr, int size, #define CODE_GEN_AVG_BLOCK_SIZE 150 #endif -/* - * Translation Cache-related fields of a TB. - * This struct exists just for convenience; we keep track of TB's in a binary - * search tree, and the only fields needed to compare TB's in the tree are - * @ptr and @size. - * Note: the address of search data can be obtained by adding @size to @ptr. - */ -struct tb_tc { - const void *ptr; /* pointer to the translated code */ - size_t size; -}; - -struct TranslationBlock { - /* - * Guest PC corresponding to this block. This must be the true - * virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and - * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or - * privilege, must store those bits elsewhere. - * - * If CF_PCREL, the opcodes for the TranslationBlock are written - * such that the TB is associated only with the physical page and - * may be run in any virtual address context. In this case, PC - * must always be taken from ENV in a target-specific manner. - * Unwind information is taken as offsets from the page, to be - * deposited into the "current" PC. - */ - vaddr pc; - - /* - * Target-specific data associated with the TranslationBlock, e.g.: - * x86: the original user, the Code Segment virtual base, - * arm: an extension of tb->flags, - * s390x: instruction data for EXECUTE, - * sparc: the next pc of the instruction queue (for delay slots). - */ - uint64_t cs_base; - - uint32_t flags; /* flags defining in which context the code was generated */ - uint32_t cflags; /* compile flags */ - -/* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ -#define CF_COUNT_MASK 0x000001ff -#define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ -#define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ -#define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */ -#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ -#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ -#define CF_USE_ICOUNT 0x00020000 -#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */ -#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ -#define CF_NOIRQ 0x00100000 /* Generate an uninterruptible TB */ -#define CF_PCREL 0x00200000 /* Opcodes in TB are PC-relative */ -#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ -#define CF_CLUSTER_SHIFT 24 - - /* - * Above fields used for comparing - */ - - /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */ - uint16_t size; - uint16_t icount; - - struct tb_tc tc; - - /* - * Track tb_page_addr_t intervals that intersect this TB. - * For user-only, the virtual addresses are always contiguous, - * and we use a unified interval tree. For system, we use a - * linked list headed in each PageDesc. Within the list, the lsb - * of the previous pointer tells the index of page_next[], and the - * list is protected by the PageDesc lock(s). - */ -#ifdef CONFIG_USER_ONLY - IntervalTreeNode itree; -#else - uintptr_t page_next[2]; - tb_page_addr_t page_addr[2]; -#endif - - /* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */ - QemuSpin jmp_lock; - - /* The following data are used to directly call another TB from - * the code of this one. This can be done either by emitting direct or - * indirect native jump instructions. These jumps are reset so that the TB - * just continues its execution. The TB can be linked to another one by - * setting one of the jump targets (or patching the jump instruction). Only - * two of such jumps are supported. - */ -#define TB_JMP_OFFSET_INVALID 0xffff /* indicates no jump generated */ - uint16_t jmp_reset_offset[2]; /* offset of original jump target */ - uint16_t jmp_insn_offset[2]; /* offset of direct jump insn */ - uintptr_t jmp_target_addr[2]; /* target address */ - - /* - * Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps. - * Each TB can have two outgoing jumps, and therefore can participate - * in two lists. The list entries are kept in jmp_list_next[2]. The least - * significant bit (LSB) of the pointers in these lists is used to encode - * which of the two list entries is to be used in the pointed TB. - * - * List traversals are protected by jmp_lock. The destination TB of each - * outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock - * can be acquired from any origin TB. - * - * jmp_dest[] are tagged pointers as well. The LSB is set when the TB is - * being invalidated, so that no further outgoing jumps from it can be set. - * - * jmp_lock also protects the CF_INVALID cflag; a jump must not be chained - * to a destination TB that has CF_INVALID set. - */ - uintptr_t jmp_list_head; - uintptr_t jmp_list_next[2]; - uintptr_t jmp_dest[2]; -}; - /* Hide the qatomic_read to make code a little easier on the eyes */ static inline uint32_t tb_cflags(const TranslationBlock *tb) { diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h new file mode 100644 index 0000000000..5119924927 --- /dev/null +++ b/include/exec/translation-block.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: LGPL-2.1-or-later */ +/* + * Definition of TranslationBlock. + * Copyright (c) 2003 Fabrice Bellard + */ + +#ifndef EXEC_TRANSLATION_BLOCK_H +#define EXEC_TRANSLATION_BLOCK_H + +#include "qemu/atomic.h" +#include "qemu/thread.h" +#include "qemu/interval-tree.h" +#include "exec/cpu-common.h" +#include "exec/target_page.h" + +/* + * Page tracking code uses ram addresses in system mode, and virtual + * addresses in userspace mode. Define tb_page_addr_t to be an + * appropriate type. + */ +#if defined(CONFIG_USER_ONLY) +typedef vaddr tb_page_addr_t; +#define TB_PAGE_ADDR_FMT "%" VADDR_PRIx +#else +typedef ram_addr_t tb_page_addr_t; +#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT +#endif + +/* + * Translation Cache-related fields of a TB. + * This struct exists just for convenience; we keep track of TB's in a binary + * search tree, and the only fields needed to compare TB's in the tree are + * @ptr and @size. + * Note: the address of search data can be obtained by adding @size to @ptr. + */ +struct tb_tc { + const void *ptr; /* pointer to the translated code */ + size_t size; +}; + +struct TranslationBlock { + /* + * Guest PC corresponding to this block. This must be the true + * virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and + * targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or + * privilege, must store those bits elsewhere. + * + * If CF_PCREL, the opcodes for the TranslationBlock are written + * such that the TB is associated only with the physical page and + * may be run in any virtual address context. In this case, PC + * must always be taken from ENV in a target-specific manner. + * Unwind information is taken as offsets from the page, to be + * deposited into the "current" PC. + */ + vaddr pc; + + /* + * Target-specific data associated with the TranslationBlock, e.g.: + * x86: the original user, the Code Segment virtual base, + * arm: an extension of tb->flags, + * s390x: instruction data for EXECUTE, + * sparc: the next pc of the instruction queue (for delay slots). + */ + uint64_t cs_base; + + uint32_t flags; /* flags defining in which context the code was generated */ + uint32_t cflags; /* compile flags */ + +/* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */ +#define CF_COUNT_MASK 0x000001ff +#define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */ +#define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */ +#define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */ +#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */ +#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */ +#define CF_USE_ICOUNT 0x00020000 +#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */ +#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */ +#define CF_NOIRQ 0x00100000 /* Generate an uninterruptible TB */ +#define CF_PCREL 0x00200000 /* Opcodes in TB are PC-relative */ +#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */ +#define CF_CLUSTER_SHIFT 24 + + /* + * Above fields used for comparing + */ + + /* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */ + uint16_t size; + uint16_t icount; + + struct tb_tc tc; + + /* + * Track tb_page_addr_t intervals that intersect this TB. + * For user-only, the virtual addresses are always contiguous, + * and we use a unified interval tree. For system, we use a + * linked list headed in each PageDesc. Within the list, the lsb + * of the previous pointer tells the index of page_next[], and the + * list is protected by the PageDesc lock(s). + */ +#ifdef CONFIG_USER_ONLY + IntervalTreeNode itree; +#else + uintptr_t page_next[2]; + tb_page_addr_t page_addr[2]; +#endif + + /* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */ + QemuSpin jmp_lock; + + /* The following data are used to directly call another TB from + * the code of this one. This can be done either by emitting direct or + * indirect native jump instructions. These jumps are reset so that the TB + * just continues its execution. The TB can be linked to another one by + * setting one of the jump targets (or patching the jump instruction). Only + * two of such jumps are supported. + */ +#define TB_JMP_OFFSET_INVALID 0xffff /* indicates no jump generated */ + uint16_t jmp_reset_offset[2]; /* offset of original jump target */ + uint16_t jmp_insn_offset[2]; /* offset of direct jump insn */ + uintptr_t jmp_target_addr[2]; /* target address */ + + /* + * Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps. + * Each TB can have two outgoing jumps, and therefore can participate + * in two lists. The list entries are kept in jmp_list_next[2]. The least + * significant bit (LSB) of the pointers in these lists is used to encode + * which of the two list entries is to be used in the pointed TB. + * + * List traversals are protected by jmp_lock. The destination TB of each + * outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock + * can be acquired from any origin TB. + * + * jmp_dest[] are tagged pointers as well. The LSB is set when the TB is + * being invalidated, so that no further outgoing jumps from it can be set. + * + * jmp_lock also protects the CF_INVALID cflag; a jump must not be chained + * to a destination TB that has CF_INVALID set. + */ + uintptr_t jmp_list_head; + uintptr_t jmp_list_next[2]; + uintptr_t jmp_dest[2]; +}; + +/* The alignment given to TranslationBlock during allocation. */ +#define CODE_GEN_ALIGN 16 + +#endif /* EXEC_TRANSLATION_BLOCK_H */ diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 46a5977b35..a4f51bfb6e 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -23,11 +23,11 @@ */ #include "qemu/osdep.h" -#include "exec/exec-all.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op-common.h" #include "tcg/tcg-mo.h" +#include "exec/translation-block.h" #include "exec/plugin-gen.h" #include "tcg-internal.h" From patchwork Mon Jun 5 20:15:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689274 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2289193wru; Mon, 5 Jun 2023 13:28:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4+hNUYcF2kHpkdyVPpuY9QLnqvCBjj2Qre/5USSKoMEFsfgf8zW7j5HDRTViqRuvLCKJW/ X-Received: by 2002:a05:620a:2714:b0:75d:538a:8bb1 with SMTP id b20-20020a05620a271400b0075d538a8bb1mr674144qkp.26.1685996929004; Mon, 05 Jun 2023 13:28:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996928; cv=none; d=google.com; s=arc-20160816; b=k1SNF+yBA1el8KomCdJfo5gpCqXGIKKTDeaaRXFOt0RVyJrgmGT5LZGwKQPqF99xo7 lKBSmX0QY9kyzY4jJoJXURRDNRztNkJFhiWv1gfoE+PwqgiLzFeiG+oNHnLjMinhKMtP FwK3J7Uhs5WGoVNlUX4eaxxwctVtvyC6trqsbiF5BdVfIhPa1vBxDGTKbOP7FaY58lM6 t6Yv9iuBC0+9HHLGAjHhpUijJHdNUD5cjgfAZJ3vo+mhNWygyddz8yH4RGkFgp4AhqTH grOkya6foy3Qc2LoRvbCpSh7w/UZjYj4kdMAuV6Ulel4Y/0Q+6lkvScf7CdtzwIh726W WT9Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=DOw547N7yM8bTiNoT1okAN1BhhlZBz/7YQeuKCCYwGE=; b=L9Evu7yH+7BTUxvA1m0jgpI9PIXgvS9De6HZ97RXgjqbk+47CplGjZc+7J/ZwsbJOk uz2FNz/LGLuc6hGyiyjh1qyeWkzngk7zQnREQctbsigU+EoPHmJTaSBaFtVi+U1g0oxu rNlVoIRpFVW3M34baZKDite8gfPoQRGxft2xv5SMPziUCWpOav6O+NWjp90iKurLzx2O +QN9s/OhWtmOAqZIdE0owUDGfY21hpE8Y0w+nx5tfhYB5RVeBO8cbycQQB84Ffw48H0N PMrBEMEXYatYQ7UjebAErkJSbFTdPdRcKRR4VvHX4w5ynWjzsmd0zhEI672TNydJlLnL PxLA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xc4aDQ26; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id kc25-20020a056214411900b005eef65c2850si5328072qvb.25.2023.06.05.13.28.48 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:28:48 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xc4aDQ26; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gd7-000278-48; Mon, 05 Jun 2023 16:16:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcp-0001xK-Gh for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:24 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcm-00048V-Cm for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:23 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-64d24136685so3817935b3a.1 for ; Mon, 05 Jun 2023 13:16:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996179; x=1688588179; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=DOw547N7yM8bTiNoT1okAN1BhhlZBz/7YQeuKCCYwGE=; b=xc4aDQ262Pc47vKf2z0ffe3qqINGb1vtxL79bpeKsphk5E7k81xFK6BFXr8bQotaUU 7uX3H2V6WwHV5efDx6EReMD/QNJOPbT7TMkWkOM2yh3FPfd+zJy6L5F+dmg+ceXr8i3Z 5/lXi0mWLrbBVM50o+9ZtZPC0QpuHiMmlDKfqucr4RolExo4me2yoe7wwMRQBLJTuvMq DZa71EJq9pj8mH0645iM/fMOS+JWwba8eHDBw3zEzqQ76+nIzEKy9jhrQLzCT/NRRZad +YrJGlfflxpI23acCAR08K6zmwGUgQuc8vIHn5246W1LDAQhm99+eEv82jMonx3QLuwd LbPA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996179; x=1688588179; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=DOw547N7yM8bTiNoT1okAN1BhhlZBz/7YQeuKCCYwGE=; b=bpxCSC+a4khUg5jyMSn0ETeWvLAx3YOWjZZDonOLgsLSaeiJJPVsWuE/0yn90EJkav k7EenOETe5NDm/cQH4b45xGEPiBZ+CHSpScEWCeXxM/WZ111Vv/mazxId2tHfQSKyR7x iEKt+CrJ9N6xn6F8Na/da3PFlUWgO749detFO70lHCaj2UOkRe+omgsYz1TkOwXztO4T ZN/5hZxxzYAKeGFkp/FkPsRcIGop/OPn3vs258jqED+Af9t5yMmCODo7bzio4kaCXadB mWN4ANV4hNxrv6Ekid7coCc0TZqognam2oZdk1XQW2hJPOS7hT6H+MhxxItOeJajTS1r ruAw== X-Gm-Message-State: AC+VfDwsYMzP1z+Ai1Z1uP6/PSWptnIrMPxIPprYJN6h+E5F9aNiX2w+ is+SOWI6fvX8MgeClpZJz0du/f0xOPKMc6kikYw= X-Received: by 2002:a05:6a00:4403:b0:659:14c8:1f0b with SMTP id br3-20020a056a00440300b0065914c81f0bmr650609pfb.4.1685996179058; Mon, 05 Jun 2023 13:16:19 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 34/52] include/exec: Remove CODE_GEN_AVG_BLOCK_SIZE Date: Mon, 5 Jun 2023 13:15:30 -0700 Message-Id: <20230605201548.1596865-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The last use was removed with 2ac01d6dafab. Fixes: 2ac01d6dafab ("translate-all: use a binary search tree to track TBs in TBContext") Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/exec-all.h | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index f01c7d57e8..698943d58f 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -467,16 +467,6 @@ int probe_access_full(CPUArchState *env, target_ulong addr, int size, CPUTLBEntryFull **pfull, uintptr_t retaddr); #endif -/* Estimated block size for TB allocation. */ -/* ??? The following is based on a 2015 survey of x86_64 host output. - Better would seem to be some sort of dynamically sized TB array, - adapting to the block sizes actually being produced. */ -#if defined(CONFIG_SOFTMMU) -#define CODE_GEN_AVG_BLOCK_SIZE 400 -#else -#define CODE_GEN_AVG_BLOCK_SIZE 150 -#endif - /* Hide the qatomic_read to make code a little easier on the eyes */ static inline uint32_t tb_cflags(const TranslationBlock *tb) { From patchwork Mon Jun 5 20:15:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689230 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2285670wru; Mon, 5 Jun 2023 13:18:13 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6H2+9/A/ToiK2dUnlHgccklgzKKfI3ksEhxiPWNA5xd+FIxJlzKkeo8LGIrzhk5cLcsGlT X-Received: by 2002:a05:620a:2443:b0:75e:5140:3a61 with SMTP id h3-20020a05620a244300b0075e51403a61mr1059671qkn.59.1685996293018; Mon, 05 Jun 2023 13:18:13 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996293; cv=none; d=google.com; s=arc-20160816; b=mOcKIxRzMFUKkpE14SCRgPY6bdXCic9qDtISCMsY9W7lir4CfeuTy6Kpcrq3mjGV38 sv9DM6jvVKhqTzPjgNDmDK+GcbeUXJbp0KPruCwoABwAzum8HErzRyFOBYpD/KRPnh3x AtlQ/QHfFaPBlEQ0fnTW2hyHNwSzjajtUEWEZsCGeFdSukqyhK9OO/AIFFFF/wFb+rCP wpAhwzEsQmqXSLKTr5hp2wj5RQk2SQZYSToGRQKaBaEpv6eRLzmN3JRALjXkjKao1Gu4 bI+QAbvjRo4+QGPi8jWxU3x1CmImTVtIJiJOs1k4jBC/vBmB7X4K4ODLQy9/mllmy+BC Vxhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=xY0gdY3mFmvqQJx7Z0kC7jESuG/hEwDX/j1iXrJVIOE=; b=U0f2W5+zPvsxNFr+oYYGBB7cL+LO7TDkdI7D6xM+My5+lYn3ZpNqvx/YWsRpfOpOmy mrcu2ml0Imat53z8FJfQVUekvjfsarcPgPJjlNxJpSQJftcRjU13wzYLWlvdCrYWYueS c+SrBosBjYfrJ3gDaf7O6oz8uwFi6wZnLuUZqLabdLJSmGKY8I2ojliXt/cBwJRzQt7X tDX/xHSCcZTGzjnmF/lGNnqVJ7whe/0vvOkn/u5Um1QK3LSJw9+or5r2Edo3w0veCZzx g6xzFITQ7IR7d46BjGQCWgbZo2Jdi/sA1KOZmu9loRvMLa8Pp1DIAcmLdc9my71pyaxh oV2g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a+80+gLA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h19-20020a05620a10b300b0075b3a9f2067si4901201qkk.80.2023.06.05.13.18.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:18:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=a+80+gLA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gcw-0001zC-Kp; Mon, 05 Jun 2023 16:16:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcr-0001xT-49 for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:26 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcn-00049m-Bu for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:24 -0400 Received: by mail-pg1-x52b.google.com with SMTP id 41be03b00d2f7-51b4ef5378bso4829321a12.1 for ; Mon, 05 Jun 2023 13:16:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996180; x=1688588180; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xY0gdY3mFmvqQJx7Z0kC7jESuG/hEwDX/j1iXrJVIOE=; b=a+80+gLAt8FIUPG/B+QoPqpv4GbwyJr7kQJfSPPsEh1k2unjaA7AUlrRn5FXicXE+B IxXECb4kqr5GFV6vulzwkJrxabUW1DaX5Vek6NmKHbvSnLV1jbQ3bcbWV3tIW03xyHDr l8PxaPA0tnCdv9JzMb5d1bWWmpcvQAQB/0+B6r84hamc+wdk1MRW+CF7upTSzuDjesXH gXPOH1KYhcVE/G2KiFV2kiPWD+yF9TDqxCe3Cc/sMfwDc4huLsTb+nje/agpN8Uxtrsv kYcpE+TR/1pfigkt33lPsABVQtBACCDtpRWOpMHDrbUg0Bo2aq4FwKI8fuMGdwrK3gFt /ORQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996180; x=1688588180; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xY0gdY3mFmvqQJx7Z0kC7jESuG/hEwDX/j1iXrJVIOE=; b=bDCskQD1GUGcHNAArK3RePvrFgJEQO+/mViy+VcU/NtUL8l+VfKPzdqneRyKdmATHX nGjmnL4nz95r6EyKAnD72jWv0ckPePdIhmxAVCIZ0mPlGgvK+M8XJ1/ymT3Z3XhQSZGZ s2nzl14uUnsl1+IMlSgNfPUTOyW1yQT4vSkStRCkD0R/p3CgTSTbBSlJnIr5oXEZovHb s0t/gtIIl+mklERHL9i6xGGTgL7huxoJQCseR1B1oIzn/rn6a5wsFapu8HTIFxAvPK0c OrVRVKyywaG3AuJY+4BuIbGoNr7gwy9FkLNnGvo/ntxo4bnqbOjRotJdjLe2tCinH5Bd EbXQ== X-Gm-Message-State: AC+VfDxmmj5YXiUo6E0UCdYH0ZgDc4myO8nmc6uaLLBT4f8f1GGJoqan x+A7IGvWXcGyqllD8KBjL0xZxG3jsaWriPX2eQk= X-Received: by 2002:a05:6a20:d90c:b0:114:b89c:f10b with SMTP id jd12-20020a056a20d90c00b00114b89cf10bmr111027pzb.31.1685996180003; Mon, 05 Jun 2023 13:16:20 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 35/52] accel/tcg: Move most of gen-icount.h into translator.c Date: Mon, 5 Jun 2023 13:15:31 -0700 Message-Id: <20230605201548.1596865-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The only usage of gen_tb_start and gen_tb_end are here. Move the static icount_start_insn variable into a local within translator_loop. Simplify the two subroutines by passing in the existing local cflags variable. Leave only the declaration of gen_io_start in gen-icount.h. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/gen-icount.h | 79 +------------------------------------ accel/tcg/translator.c | 83 ++++++++++++++++++++++++++++++++++++++- 2 files changed, 82 insertions(+), 80 deletions(-) diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h index f6de79a6b4..6006af4c06 100644 --- a/include/exec/gen-icount.h +++ b/include/exec/gen-icount.h @@ -1,83 +1,6 @@ #ifndef GEN_ICOUNT_H #define GEN_ICOUNT_H -#include "exec/exec-all.h" - -/* Helpers for instruction counting code generation. */ - -static TCGOp *icount_start_insn; - -static inline void gen_io_start(void) -{ - tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, - offsetof(ArchCPU, parent_obj.can_do_io) - - offsetof(ArchCPU, env)); -} - -static inline void gen_tb_start(const TranslationBlock *tb) -{ - TCGv_i32 count = tcg_temp_new_i32(); - - tcg_gen_ld_i32(count, cpu_env, - offsetof(ArchCPU, neg.icount_decr.u32) - - offsetof(ArchCPU, env)); - - if (tb_cflags(tb) & CF_USE_ICOUNT) { - /* - * We emit a sub with a dummy immediate argument. Keep the insn index - * of the sub so that we later (when we know the actual insn count) - * can update the argument with the actual insn count. - */ - tcg_gen_sub_i32(count, count, tcg_constant_i32(0)); - icount_start_insn = tcg_last_op(); - } - - /* - * Emit the check against icount_decr.u32 to see if we should exit - * unless we suppress the check with CF_NOIRQ. If we are using - * icount and have suppressed interruption the higher level code - * should have ensured we don't run more instructions than the - * budget. - */ - if (tb_cflags(tb) & CF_NOIRQ) { - tcg_ctx->exitreq_label = NULL; - } else { - tcg_ctx->exitreq_label = gen_new_label(); - tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); - } - - if (tb_cflags(tb) & CF_USE_ICOUNT) { - tcg_gen_st16_i32(count, cpu_env, - offsetof(ArchCPU, neg.icount_decr.u16.low) - - offsetof(ArchCPU, env)); - /* - * cpu->can_do_io is cleared automatically here at the beginning of - * each translation block. The cost is minimal and only paid for - * -icount, plus it would be very easy to forget doing it in the - * translator. Doing it here means we don't need a gen_io_end() to - * go with gen_io_start(). - */ - tcg_gen_st_i32(tcg_constant_i32(0), cpu_env, - offsetof(ArchCPU, parent_obj.can_do_io) - - offsetof(ArchCPU, env)); - } -} - -static inline void gen_tb_end(const TranslationBlock *tb, int num_insns) -{ - if (tb_cflags(tb) & CF_USE_ICOUNT) { - /* - * Update the num_insn immediate parameter now that we know - * the actual insn count. - */ - tcg_set_insn_param(icount_start_insn, 2, - tcgv_i32_arg(tcg_constant_i32(num_insns))); - } - - if (tcg_ctx->exitreq_label) { - gen_set_label(tcg_ctx->exitreq_label); - tcg_gen_exit_tb(tb, TB_EXIT_REQUESTED); - } -} +void gen_io_start(void); #endif diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 6120ef2a92..b0d0015c70 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -18,6 +18,84 @@ #include "exec/plugin-gen.h" #include "exec/replay-core.h" + +void gen_io_start(void) +{ + tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, + offsetof(ArchCPU, parent_obj.can_do_io) - + offsetof(ArchCPU, env)); +} + +static TCGOp *gen_tb_start(uint32_t cflags) +{ + TCGv_i32 count = tcg_temp_new_i32(); + TCGOp *icount_start_insn = NULL; + + tcg_gen_ld_i32(count, cpu_env, + offsetof(ArchCPU, neg.icount_decr.u32) - + offsetof(ArchCPU, env)); + + if (cflags & CF_USE_ICOUNT) { + /* + * We emit a sub with a dummy immediate argument. Keep the insn index + * of the sub so that we later (when we know the actual insn count) + * can update the argument with the actual insn count. + */ + tcg_gen_sub_i32(count, count, tcg_constant_i32(0)); + icount_start_insn = tcg_last_op(); + } + + /* + * Emit the check against icount_decr.u32 to see if we should exit + * unless we suppress the check with CF_NOIRQ. If we are using + * icount and have suppressed interruption the higher level code + * should have ensured we don't run more instructions than the + * budget. + */ + if (cflags & CF_NOIRQ) { + tcg_ctx->exitreq_label = NULL; + } else { + tcg_ctx->exitreq_label = gen_new_label(); + tcg_gen_brcondi_i32(TCG_COND_LT, count, 0, tcg_ctx->exitreq_label); + } + + if (cflags & CF_USE_ICOUNT) { + tcg_gen_st16_i32(count, cpu_env, + offsetof(ArchCPU, neg.icount_decr.u16.low) - + offsetof(ArchCPU, env)); + /* + * cpu->can_do_io is cleared automatically here at the beginning of + * each translation block. The cost is minimal and only paid for + * -icount, plus it would be very easy to forget doing it in the + * translator. Doing it here means we don't need a gen_io_end() to + * go with gen_io_start(). + */ + tcg_gen_st_i32(tcg_constant_i32(0), cpu_env, + offsetof(ArchCPU, parent_obj.can_do_io) - + offsetof(ArchCPU, env)); + } + + return icount_start_insn; +} + +static void gen_tb_end(const TranslationBlock *tb, uint32_t cflags, + TCGOp *icount_start_insn, int num_insns) +{ + if (cflags & CF_USE_ICOUNT) { + /* + * Update the num_insn immediate parameter now that we know + * the actual insn count. + */ + tcg_set_insn_param(icount_start_insn, 2, + tcgv_i32_arg(tcg_constant_i32(num_insns))); + } + + if (tcg_ctx->exitreq_label) { + gen_set_label(tcg_ctx->exitreq_label); + tcg_gen_exit_tb(tb, TB_EXIT_REQUESTED); + } +} + bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest) { /* Suppress goto_tb if requested. */ @@ -34,6 +112,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, const TranslatorOps *ops, DisasContextBase *db) { uint32_t cflags = tb_cflags(tb); + TCGOp *icount_start_insn; bool plugin_enabled; /* Initialize DisasContext */ @@ -55,7 +134,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ /* Start translating. */ - gen_tb_start(db->tb); + icount_start_insn = gen_tb_start(cflags); ops->tb_start(db, cpu); tcg_debug_assert(db->is_jmp == DISAS_NEXT); /* no early exit */ @@ -112,7 +191,7 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, /* Emit code to exit the TB, as indicated by db->is_jmp. */ ops->tb_stop(db, cpu); - gen_tb_end(db->tb, db->num_insns); + gen_tb_end(tb, cflags, icount_start_insn, db->num_insns); if (plugin_enabled) { plugin_gen_tb_end(cpu); From patchwork Mon Jun 5 20:15:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689237 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2286713wru; Mon, 5 Jun 2023 13:21:17 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7dDLLfsQ0CQunRywommon/JXJXLHAmYwhL6GIXam3WkYULNOALtp7paTCiclfiEo7kFMRp X-Received: by 2002:a05:620a:4398:b0:75d:50bb:b181 with SMTP id a24-20020a05620a439800b0075d50bbb181mr863678qkp.44.1685996477215; Mon, 05 Jun 2023 13:21:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996477; cv=none; d=google.com; s=arc-20160816; b=hLwLgn6W0fwP3dZcKazi+Jyg9OKrH21s3bQIojM/d+9sjO6JvAsZA+VZ8Ya9ct0u4Z VJaAtV6/dI05cXMDTBXXwqfFGN71kGDAWyGJQ38tJRJJFow4Jm+ohh0vx05mNFPDxQwl gxDl1zF64FbO+9OjfA+X7/9uQLlPWCjGt28C24uXwqVZmZnEcB34zYQWpX+96Eo19quO 9MeXsCcuQqLmF6iTvTdDBe/Tz7OesvxEGtwwZXnlgRNMrO0v3zyGhwC+BaXukXdvKzo3 Ce3DjiD4aZdShHnJdOU2dbRlQxgMfg9n3pxZ4OyUir+c0fAPX0aTD4flYFmoZrhodZfV 5NuA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=39mWmY5c7wx6bryKhal7sYA/iwI65PMpFXPjVbPs1no=; b=C7e1tbeeb2BwOkGyZyngeNAuOGZONFA/DNOaxSkieTm7SH0iI31x747W3EUebUGBb+ Q9niIMy3OVvUr3n/KMUDf9npbqIVLnPHVxdb20ao1kueJgf365UH575g9xyeVHMT08EN 6B6ajw/NWzIQcyKz//hqoeCwwCHdG5fvXmW4HrRAXwHZbrxNbjHfVGzOQtMXGfhdBsEP YiRUTLmkKx8h2uoa9fjUgTLoZVlGoPMpDYz/WEt0CPYUJomIc+D4Q81IWNRsg3l4RlhR Y+FgnV5bvZ83vH+0P03hsYz/iKXeBTP4HAOp0A8LP8hCsaoDLfhT1LHSdM8j86x8hdyO /FSQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XglvqthW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id ow29-20020a05620a821d00b0075c974ced1csi4790101qkn.721.2023.06.05.13.21.17 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:21:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XglvqthW; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GdB-0002Fj-R8; Mon, 05 Jun 2023 16:16:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gct-0001yX-LO for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:28 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcn-0003kp-Ux for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:27 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-655d1fc8ad8so1363876b3a.1 for ; Mon, 05 Jun 2023 13:16:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996181; x=1688588181; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=39mWmY5c7wx6bryKhal7sYA/iwI65PMpFXPjVbPs1no=; b=XglvqthWMdFWHlNowcqgxdM8D1xVnF8TeAoRbbabkYb+FHE6+2jjoH5C4sw2390G2p pj2HOc8BKwjn2mUEg/HnHjQbU9S/xsChGhHjlGPB07ZVJ3YYl+1luWwkAE1qU3BtGcEg UyaS9lNV22sH2FfKEGNKDICO6E4AUgwxsyamze9aAKKCiKqSoheQ3Sf1YiwbcDkMz6MD TiNt93IJm/IRYcpMtERdyDkgSjcFkhv/Tjgyib+5QwS9MMu8IrUIUosyGJ3FFXItE4/d yFfOk5oFghgH+WPIiJXLGo0aTGeYjh1oDvGTmPAzM4Y6QlcmObUo8RJKiIjDv6von05i Sp/g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996181; x=1688588181; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=39mWmY5c7wx6bryKhal7sYA/iwI65PMpFXPjVbPs1no=; b=NkibrHTJkFj0hETYkPF7RWCPYzup/6yNzw30QOoT4b9EhJO2Ua+J81UeMgs7A3DP+I S9QT5KGEpbqvnAz9A1EMKDyrxcpYME1zZOqMoK2j/Ilnc45VBqFrPSisjvdx0QgY2+Wm ebKwsdaAX0Y8UTU6KnK3vn4pvtgzruS7y7YcjI9X6Jxc1lG3vFhJ9LJFW5lo8Pdaz+gq Z+qOjX9mncLU4dTG/1snUgAp+cb1MTH9/yBZx0uiJy5hpqZAQN1oci6HTK9E8DNFPQgi fbXb9K0xkW9QzIaelbOdpbbc03S5EDsyDzkHcLzMPbbgUKROXnKLtL6lXFD+bToLVUUu 8/Ag== X-Gm-Message-State: AC+VfDyJQQV4UuaFgtkg2uuDXESqkj9oVTLCHUbFFpo9ZvbtBoQa/OO5 thPaY5ZZ1joc005aXtWsjg2JI2B+s5cvzNj0c1M= X-Received: by 2002:a05:6a00:2309:b0:647:e45f:1a4c with SMTP id h9-20020a056a00230900b00647e45f1a4cmr908105pfh.11.1685996180797; Mon, 05 Jun 2023 13:16:20 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 36/52] accel/tcg: Introduce translator_io_start Date: Mon, 5 Jun 2023 13:15:32 -0700 Message-Id: <20230605201548.1596865-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org New wrapper around gen_io_start which takes care of the USE_ICOUNT check, as well as marking the DisasContext to end the TB. Remove exec/gen-icount.h. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- MAINTAINERS | 1 - include/exec/gen-icount.h | 6 -- include/exec/translator.h | 10 +++ target/arm/cpregs.h | 4 +- accel/tcg/translator.c | 27 ++++++- target/alpha/translate.c | 15 +--- target/arm/tcg/translate-a64.c | 23 +++--- target/arm/tcg/translate-mve.c | 1 - target/arm/tcg/translate-neon.c | 1 - target/arm/tcg/translate-vfp.c | 4 +- target/arm/tcg/translate.c | 20 ++--- target/avr/translate.c | 1 - target/cris/translate.c | 2 - target/hppa/translate.c | 5 +- target/i386/tcg/translate.c | 52 +++---------- target/loongarch/translate.c | 2 - target/m68k/translate.c | 2 - target/microblaze/translate.c | 2 - target/mips/tcg/translate.c | 29 +++---- target/nios2/translate.c | 1 - target/openrisc/translate.c | 9 +-- target/ppc/translate.c | 13 +--- target/riscv/translate.c | 2 - target/rx/translate.c | 2 - target/s390x/tcg/translate.c | 6 +- target/sh4/translate.c | 2 - target/sparc/translate.c | 75 +++++-------------- target/tricore/translate.c | 2 - target/xtensa/translate.c | 27 ++----- target/loongarch/insn_trans/trans_extra.c.inc | 4 +- .../insn_trans/trans_privileged.c.inc | 4 +- .../riscv/insn_trans/trans_privileged.c.inc | 8 +- target/riscv/insn_trans/trans_rvi.c.inc | 24 ++---- 33 files changed, 117 insertions(+), 269 deletions(-) delete mode 100644 include/exec/gen-icount.h diff --git a/MAINTAINERS b/MAINTAINERS index 2366f64d3d..55668d6336 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2867,7 +2867,6 @@ F: ui/cocoa.m Main loop M: Paolo Bonzini S: Maintained -F: include/exec/gen-icount.h F: include/qemu/main-loop.h F: include/sysemu/runstate.h F: include/sysemu/runstate-action.h diff --git a/include/exec/gen-icount.h b/include/exec/gen-icount.h deleted file mode 100644 index 6006af4c06..0000000000 --- a/include/exec/gen-icount.h +++ /dev/null @@ -1,6 +0,0 @@ -#ifndef GEN_ICOUNT_H -#define GEN_ICOUNT_H - -void gen_io_start(void); - -#endif diff --git a/include/exec/translator.h b/include/exec/translator.h index 797fef7515..c1a1203789 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -160,6 +160,16 @@ void translator_loop(CPUState *cpu, TranslationBlock *tb, int *max_insns, */ bool translator_use_goto_tb(DisasContextBase *db, target_ulong dest); +/** + * translator_io_start + * @db: Disassembly context + * + * If icount is enabled, set cpu->can_to_io, adjust db->is_jmp to + * DISAS_TOO_MANY if it is still DISAS_NEXT, and return true. + * Otherwise return false. + */ +bool translator_io_start(DisasContextBase *db); + /* * Translator Load Functions * diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index b04d344a9f..14785686f6 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -67,8 +67,8 @@ enum { ARM_CP_ALIAS = 1 << 8, /* * Flag: Register does I/O and therefore its accesses need to be marked - * with gen_io_start() and also end the TB. In particular, registers which - * implement clocks or timers require this. + * with translator_io_start() and also end the TB. In particular, + * registers which implement clocks or timers require this. */ ARM_CP_IO = 1 << 9, /* diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index b0d0015c70..7a130e706e 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -12,20 +12,43 @@ #include "tcg/tcg.h" #include "tcg/tcg-op.h" #include "exec/exec-all.h" -#include "exec/gen-icount.h" #include "exec/log.h" #include "exec/translator.h" #include "exec/plugin-gen.h" #include "exec/replay-core.h" -void gen_io_start(void) +static void gen_io_start(void) { tcg_gen_st_i32(tcg_constant_i32(1), cpu_env, offsetof(ArchCPU, parent_obj.can_do_io) - offsetof(ArchCPU, env)); } +bool translator_io_start(DisasContextBase *db) +{ + uint32_t cflags = tb_cflags(db->tb); + + if (!(cflags & CF_USE_ICOUNT)) { + return false; + } + if (db->num_insns == db->max_insns && (cflags & CF_LAST_IO)) { + /* Already started in translator_loop. */ + return true; + } + + gen_io_start(); + + /* + * Ensure that this instruction will be the last in the TB. + * The target may override this to something more forceful. + */ + if (db->is_jmp == DISAS_NEXT) { + db->is_jmp = DISAS_TOO_MANY; + } + return true; +} + static TCGOp *gen_tb_start(uint32_t cflags) { TCGv_i32 count = tcg_temp_new_i32(); diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 545e5743c3..1f7dd078d8 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -96,8 +96,6 @@ static TCGv cpu_lock_value; static TCGv cpu_pal_ir[31]; #endif -#include "exec/gen-icount.h" - void alpha_translate_init(void) { #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUAlphaState, V) } @@ -1236,8 +1234,7 @@ static DisasJumpType gen_mfpr(DisasContext *ctx, TCGv va, int regno) case 249: /* VMTIME */ helper = gen_helper_get_vmtime; do_helper: - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&ctx->base)) { helper(va); return DISAS_PC_STALE; } else { @@ -1298,8 +1295,7 @@ static DisasJumpType gen_mtpr(DisasContext *ctx, TCGv vb, int regno) case 251: /* ALARM */ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&ctx->base)) { ret = DISAS_PC_STALE; } gen_helper_set_alarm(cpu_env, vb); @@ -2335,13 +2331,10 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn) case 0xC000: /* RPCC */ va = dest_gpr(ctx, ra); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - gen_helper_load_pcc(va, cpu_env); + if (translator_io_start(&ctx->base)) { ret = DISAS_PC_STALE; - } else { - gen_helper_load_pcc(va, cpu_env); } + gen_helper_load_pcc(va, cpu_env); break; case 0xE000: /* RC */ diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index bc0cb98955..8d45dbf8fc 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -28,7 +28,6 @@ #include "internals.h" #include "qemu/host-utils.h" #include "semihosting/semihost.h" -#include "exec/gen-icount.h" #include "exec/log.h" #include "cpregs.h" #include "translate-a64.h" @@ -1552,9 +1551,7 @@ static bool trans_ERET(DisasContext *s, arg_ERET *a) tcg_gen_ld_i64(dst, cpu_env, offsetof(CPUARMState, elr_el[s->current_el])); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&s->base); gen_helper_exception_return(cpu_env, dst); /* Must exit loop to check un-masked IRQs */ @@ -1582,9 +1579,8 @@ static bool trans_ERETA(DisasContext *s, arg_reta *a) offsetof(CPUARMState, elr_el[s->current_el])); dst = auth_branch_target(s, dst, cpu_X[31], !a->m); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + + translator_io_start(&s->base); gen_helper_exception_return(cpu_env, dst); /* Must exit loop to check un-masked IRQs */ @@ -2044,6 +2040,7 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, uint32_t key = ENCODE_AA64_CP_REG(CP_REG_ARM64_SYSREG_CP, crn, crm, op0, op1, op2); const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key); + bool need_exit_tb = false; TCGv_ptr tcg_ri = NULL; TCGv_i64 tcg_rt; @@ -2171,8 +2168,9 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, return; } - if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { - gen_io_start(); + if (ri->type & ARM_CP_IO) { + /* I/O operations must end the TB here (whether read or write) */ + need_exit_tb = translator_io_start(&s->base); } tcg_rt = cpu_reg(s, rt); @@ -2202,10 +2200,6 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, } } - if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { - /* I/O operations must end the TB here (whether read or write) */ - s->base.is_jmp = DISAS_UPDATE_EXIT; - } if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* * A write to any coprocessor regiser that ends a TB @@ -2217,6 +2211,9 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread, * but allow this to be suppressed by the register definition * (usually only necessary to work around guest bugs). */ + need_exit_tb = true; + } + if (need_exit_tb) { s->base.is_jmp = DISAS_UPDATE_EXIT; } } diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c index 31fb2110f1..2ad3c40975 100644 --- a/target/arm/tcg/translate-mve.c +++ b/target/arm/tcg/translate-mve.c @@ -21,7 +21,6 @@ #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/exec-all.h" -#include "exec/gen-icount.h" #include "translate.h" #include "translate-a32.h" diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c index af8685a4ac..6fac577abd 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -24,7 +24,6 @@ #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/exec-all.h" -#include "exec/gen-icount.h" #include "translate.h" #include "translate-a32.h" diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index dd782aacf4..95ac8d9db3 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -24,7 +24,6 @@ #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "exec/exec-all.h" -#include "exec/gen-icount.h" #include "translate.h" #include "translate-a32.h" @@ -117,9 +116,8 @@ static void gen_preserve_fp_state(DisasContext *s, bool skip_context_update) * so we must mark it as an IO operation for icount (and cause * this to be the last insn in the TB). */ - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { + if (translator_io_start(&s->base)) { s->base.is_jmp = DISAS_UPDATE_EXIT; - gen_io_start(); } gen_helper_v7m_preserve_fp_state(cpu_env); /* diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 379f266256..7caf6d802d 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -34,7 +34,6 @@ #include "cpregs.h" #include "translate.h" #include "translate-a32.h" -#include "exec/gen-icount.h" #include "exec/helper-proto.h" #define HELPER_H "helper.h" @@ -2908,9 +2907,7 @@ static void gen_rfe(DisasContext *s, TCGv_i32 pc, TCGv_i32 cpsr) * appropriately depending on the new Thumb bit, so it must * be called after storing the new PC. */ - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&s->base); gen_helper_cpsr_write_eret(cpu_env, cpsr); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp = DISAS_EXIT; @@ -4559,7 +4556,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, uint32_t key = ENCODE_CP_REG(cpnum, is64, s->ns, crn, crm, opc1, opc2); const ARMCPRegInfo *ri = get_arm_cp_reginfo(s->cp_regs, key); TCGv_ptr tcg_ri = NULL; - bool need_exit_tb; + bool need_exit_tb = false; uint32_t syndrome; /* @@ -4704,8 +4701,9 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, g_assert_not_reached(); } - if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) { - gen_io_start(); + if (ri->type & ARM_CP_IO) { + /* I/O operations must end the TB here (whether read or write) */ + need_exit_tb = translator_io_start(&s->base); } if (isread) { @@ -4787,10 +4785,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, } } - /* I/O operations must end the TB here (whether read or write) */ - need_exit_tb = ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && - (ri->type & ARM_CP_IO)); - if (!isread && !(ri->type & ARM_CP_SUPPRESS_TB_END)) { /* * A write to any coprocessor register that ends a TB @@ -8047,9 +8041,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a, int min_n) if (exc_return) { /* Restore CPSR from SPSR. */ tmp = load_cpu_field(spsr); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&s->base); gen_helper_cpsr_write_eret(cpu_env, tmp); /* Must exit loop to check un-masked IRQs */ s->base.is_jmp = DISAS_EXIT; diff --git a/target/avr/translate.c b/target/avr/translate.c index 4fa40b568a..ef2edd7415 100644 --- a/target/avr/translate.c +++ b/target/avr/translate.c @@ -29,7 +29,6 @@ #include "exec/helper-gen.h" #include "exec/log.h" #include "exec/translator.h" -#include "exec/gen-icount.h" #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" diff --git a/target/cris/translate.c b/target/cris/translate.c index 3c21826cc2..1445cd8bb5 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -88,8 +88,6 @@ static TCGv env_btaken; static TCGv env_btarget; static TCGv env_pc; -#include "exec/gen-icount.h" - /* This is the state at translation time. */ typedef struct DisasContext { DisasContextBase base; diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 2c50fa72c3..d33813d173 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -364,8 +364,6 @@ static TCGv_reg cpu_psw_v; static TCGv_reg cpu_psw_cb; static TCGv_reg cpu_psw_cb_msb; -#include "exec/gen-icount.h" - void hppa_translate_init(void) { #define DEF_VAR(V) { &cpu_##V, #V, offsetof(CPUHPPAState, V) } @@ -2090,8 +2088,7 @@ static bool trans_mfctl(DisasContext *ctx, arg_mfctl *a) /* FIXME: Respect PSW_S bit. */ nullify_over(ctx); tmp = dest_gpr(ctx, rt); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&ctx->base)) { gen_helper_read_interval_timer(tmp); ctx->base.is_jmp = DISAS_IAQ_N_STALE; } else { diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c index d509105505..5cf14311a6 100644 --- a/target/i386/tcg/translate.c +++ b/target/i386/tcg/translate.c @@ -78,8 +78,6 @@ static TCGv cpu_seg_base[6]; static TCGv_i64 cpu_bndl[4]; static TCGv_i64 cpu_bndu[4]; -#include "exec/gen-icount.h" - typedef struct DisasContext { DisasContextBase base; @@ -3933,10 +3931,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) !(s->cpuid_ext_features & CPUID_EXT_RDRAND)) { goto illegal_op; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp = DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_helper_rdrand(s->T0, cpu_env); rm = (modrm & 7) | REX_B(s); gen_op_mov_reg_v(s, dflag, rm, s->T0); @@ -4974,10 +4969,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) SVM_IOIO_TYPE_MASK | SVM_IOIO_STR_MASK)) { break; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp = DISAS_TOO_MANY; - } + translator_io_start(&s->base); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { gen_repz_ins(s, ot); } else { @@ -4992,10 +4984,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_STR_MASK)) { break; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp = DISAS_TOO_MANY; - } + translator_io_start(&s->base); if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) { gen_repz_outs(s, ot); } else { @@ -5014,10 +5003,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) { break; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp = DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_helper_in_func(ot, s->T1, s->tmp2_i32); gen_op_mov_reg_v(s, ot, R_EAX, s->T1); gen_bpt_io(s, s->tmp2_i32, ot); @@ -5030,10 +5016,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!gen_check_io(s, ot, s->tmp2_i32, 0)) { break; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp = DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_op_mov_v_reg(s, ot, s->T1, R_EAX); tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32); @@ -5047,10 +5030,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!gen_check_io(s, ot, s->tmp2_i32, SVM_IOIO_TYPE_MASK)) { break; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp = DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_helper_in_func(ot, s->T1, s->tmp2_i32); gen_op_mov_reg_v(s, ot, R_EAX, s->T1); gen_bpt_io(s, s->tmp2_i32, ot); @@ -5063,10 +5043,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) if (!gen_check_io(s, ot, s->tmp2_i32, 0)) { break; } - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp = DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_op_mov_v_reg(s, ot, s->T1, R_EAX); tcg_gen_trunc_tl_i32(s->tmp3_i32, s->T1); gen_helper_out_func(ot, s->tmp2_i32, s->tmp3_i32); @@ -5674,10 +5651,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) case 0x131: /* rdtsc */ gen_update_cc_op(s); gen_update_eip_cur(s); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp = DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_helper_rdtsc(cpu_env); break; case 0x133: /* rdpmc */ @@ -6133,10 +6107,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } gen_update_cc_op(s); gen_update_eip_cur(s); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp = DISAS_TOO_MANY; - } + translator_io_start(&s->base); gen_helper_rdtscp(cpu_env); break; @@ -6490,10 +6461,7 @@ static bool disas_insn(DisasContext *s, CPUState *cpu) } ot = (CODE64(s) ? MO_64 : MO_32); - if (tb_cflags(s->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - s->base.is_jmp = DISAS_TOO_MANY; - } + translator_io_start(&s->base); if (b & 2) { gen_svm_check_intercept(s, SVM_EXIT_WRITE_CR0 + reg); gen_op_mov_v_reg(s, ot, s->T0, rm); diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 67140ada56..1cf27a4611 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -24,8 +24,6 @@ TCGv cpu_gpr[32], cpu_pc; static TCGv cpu_lladdr, cpu_llval; -#include "exec/gen-icount.h" - #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" #undef HELPER_H diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 90ca51fb9e..551ef9e52a 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -65,8 +65,6 @@ static TCGv NULL_QREG; /* Used to distinguish stores from bad addressing modes. */ static TCGv store_dummy; -#include "exec/gen-icount.h" - void m68k_tcg_init(void) { char *p; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7a5d1066da..7e7f837c63 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -58,8 +58,6 @@ static TCGv_i32 cpu_iflags; static TCGv cpu_res_addr; static TCGv_i32 cpu_res_val; -#include "exec/gen-icount.h" - /* This is the state at translation time. */ typedef struct DisasContext { DisasContextBase base; diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index bff1859b86..312ed66989 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -1215,8 +1215,6 @@ static TCGv_i32 hflags; TCGv_i32 fpu_fcr0, fpu_fcr31; TCGv_i64 fpu_f64[32]; -#include "exec/gen-icount.h" - static const char regnames_HI[][4] = { "HI0", "HI1", "HI2", "HI3", }; @@ -5670,9 +5668,8 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (sel) { case CP0_REG09__COUNT: /* Mark as an IO operation because we read the time. */ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); + gen_helper_mfc0_count(arg, cpu_env); /* * Break the TB to be able to take timer interrupts immediately @@ -6111,14 +6108,13 @@ cp0_unimplemented: static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *register_name = "invalid"; + bool icount; if (sel != 0) { check_insn(ctx, ISA_MIPS_R1); } - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + icount = translator_io_start(&ctx->base); switch (reg) { case CP0_REGISTER_00: @@ -6856,7 +6852,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) trace_mips_translate_c0("mtc0", register_name, reg, sel); /* For simplicity assume that all writes can cause interrupts. */ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + if (icount) { /* * DISAS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. @@ -7173,9 +7169,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (sel) { case CP0_REG09__COUNT: /* Mark as an IO operation because we read the time. */ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_mfc0_count(arg, cpu_env); /* * Break the TB to be able to take timer interrupts immediately @@ -7601,14 +7595,13 @@ cp0_unimplemented: static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *register_name = "invalid"; + bool icount; if (sel != 0) { check_insn(ctx, ISA_MIPS_R1); } - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + icount = translator_io_start(&ctx->base); switch (reg) { case CP0_REGISTER_00: @@ -8336,7 +8329,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) trace_mips_translate_c0("dmtc0", register_name, reg, sel); /* For simplicity assume that all writes can cause interrupts. */ - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { + if (icount) { /* * DISAS_STOP isn't sufficient, we need to ensure we break out of * translated code to check for pending interrupts. @@ -11147,9 +11140,7 @@ void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) gen_store_gpr(t0, rt); break; case 2: - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_rdhwr_cc(t0, cpu_env); gen_store_gpr(t0, rt); /* diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 28c1d700e1..a365ad8293 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -32,7 +32,6 @@ #include "exec/cpu_ldst.h" #include "exec/translator.h" #include "qemu/qemu-print.h" -#include "exec/gen-icount.h" #include "semihosting/semihost.h" #define HELPER_H "helper.h" diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 06e6eae952..7760329e75 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -31,7 +31,6 @@ #include "exec/helper-proto.h" #include "exec/helper-gen.h" -#include "exec/gen-icount.h" #include "exec/log.h" @@ -828,8 +827,7 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a) check_r0_write(dc, a->d); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&dc->base)) { if (dc->delayed_branch) { tcg_gen_mov_tl(cpu_pc, jmp_pc); tcg_gen_discard_tl(jmp_pc); @@ -848,9 +846,8 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a) { TCGv spr = tcg_temp_new(); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); + /* * For SR, we will need to exit the TB to recognize the new * exception state. For NPC, in theory this counts as a branch diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 67d7ee0a70..519f66bb05 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -80,8 +80,6 @@ static TCGv cpu_reserve_val2; static TCGv cpu_fpscr; static TCGv_i32 cpu_access_type; -#include "exec/gen-icount.h" - void ppc_translate_init(void) { int i; @@ -300,16 +298,7 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp, static void gen_icount_io_start(DisasContext *ctx) { - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - /* - * An I/O instruction must be last in the TB. - * Chain to the next TB, and let the code from gen_tb_start - * decide if we need to return to the main loop. - * Doing this first also allows this value to be overridden. - */ - ctx->base.is_jmp = DISAS_TOO_MANY; - } + translator_io_start(&ctx->base); } #if !defined(CONFIG_USER_ONLY) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index ed968162da..933b11c50d 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -46,8 +46,6 @@ static TCGv load_val; static TCGv pm_mask; static TCGv pm_base; -#include "exec/gen-icount.h" - /* * If an operation is being performed on less than TARGET_LONG_BITS, * it may require the inputs to be sign- or zero-extended; which will diff --git a/target/rx/translate.c b/target/rx/translate.c index 89dbec26f9..08cabbde61 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -73,8 +73,6 @@ static TCGv_i64 cpu_acc; #define cpu_sp cpu_regs[0] -#include "exec/gen-icount.h" - /* decoder helper */ static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn, int i, int n) diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index 60b17585a7..7c549cd8d0 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -38,7 +38,6 @@ #include "qemu/log.h" #include "qemu/host-utils.h" #include "exec/cpu_ldst.h" -#include "exec/gen-icount.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -6354,10 +6353,7 @@ static DisasJumpType translate_one(CPUS390XState *env, DisasContext *s) /* input/output is the special case for icount mode */ if (unlikely(insn->flags & IF_IO)) { - icount = tb_cflags(s->base.tb) & CF_USE_ICOUNT; - if (icount) { - gen_io_start(); - } + icount = translator_io_start(&s->base); } } diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 76f46d268b..49c87d7a01 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -75,8 +75,6 @@ static TCGv cpu_fregs[32]; /* internal register indexes */ static TCGv cpu_flags, cpu_delayed_pc, cpu_delayed_cond; -#include "exec/gen-icount.h" - void sh4_translate_init(void) { int i; diff --git a/target/sparc/translate.c b/target/sparc/translate.c index ebaf376500..bad2ec90a0 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -66,8 +66,6 @@ static TCGv cpu_wim; /* Floating point registers */ static TCGv_i64 cpu_fpr[TARGET_DPREGS]; -#include "exec/gen-icount.h" - typedef struct DisasContext { DisasContextBase base; target_ulong pc; /* current Program Counter: integer or DYNAMIC_PC */ @@ -3217,16 +3215,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) r_const = tcg_constant_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&dc->base)) { + dc->base.is_jmp = DISAS_EXIT; } gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr, r_const); gen_store_gpr(dc, rd, cpu_dst); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - /* I/O operations in icount mode must end the TB */ - dc->base.is_jmp = DISAS_EXIT; - } } break; case 0x5: /* V9 rdpc */ @@ -3269,16 +3263,12 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) r_const = tcg_constant_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, stick)); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&dc->base)) { + dc->base.is_jmp = DISAS_EXIT; } gen_helper_tick_get_count(cpu_dst, cpu_env, r_tickptr, r_const); gen_store_gpr(dc, rd, cpu_dst); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - /* I/O operations in icount mode must end the TB */ - dc->base.is_jmp = DISAS_EXIT; - } } break; case 0x19: /* System tick compare */ @@ -3399,15 +3389,11 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) r_const = tcg_constant_i32(dc->mem_idx); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); + if (translator_io_start(&dc->base)) { + dc->base.is_jmp = DISAS_EXIT; } gen_helper_tick_get_count(cpu_tmp0, cpu_env, r_tickptr, r_const); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - /* I/O operations in icount mode must end the TB */ - dc->base.is_jmp = DISAS_EXIT; - } } break; case 5: // tba @@ -4212,10 +4198,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) r_tickptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); - if (tb_cflags(dc->base.tb) & - CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_tick_set_limit(r_tickptr, cpu_tick_cmpr); /* End TB to handle timer interrupt */ @@ -4235,10 +4218,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) r_tickptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, stick)); - if (tb_cflags(dc->base.tb) & - CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_tick_set_count(r_tickptr, cpu_tmp0); /* End TB to handle timer interrupt */ @@ -4258,10 +4238,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) r_tickptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, stick)); - if (tb_cflags(dc->base.tb) & - CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_tick_set_limit(r_tickptr, cpu_stick_cmpr); /* End TB to handle timer interrupt */ @@ -4369,10 +4346,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) r_tickptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, tick)); - if (tb_cflags(dc->base.tb) & - CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_tick_set_count(r_tickptr, cpu_tmp0); /* End TB to handle timer interrupt */ @@ -4384,14 +4358,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) break; case 6: // pstate save_state(dc); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_wrpstate(cpu_env, cpu_tmp0); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - /* I/O ops in icount mode must end the TB */ + if (translator_io_start(&dc->base)) { dc->base.is_jmp = DISAS_EXIT; } + gen_helper_wrpstate(cpu_env, cpu_tmp0); dc->npc = DYNAMIC_PC; break; case 7: // tl @@ -4401,14 +4371,10 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) dc->npc = DYNAMIC_PC; break; case 8: // pil - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - gen_helper_wrpil(cpu_env, cpu_tmp0); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - /* I/O ops in icount mode must end the TB */ + if (translator_io_start(&dc->base)) { dc->base.is_jmp = DISAS_EXIT; } + gen_helper_wrpil(cpu_env, cpu_tmp0); break; case 9: // cwp gen_helper_wrcwp(cpu_env, cpu_tmp0); @@ -4499,10 +4465,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) r_tickptr = tcg_temp_new_ptr(); tcg_gen_ld_ptr(r_tickptr, cpu_env, offsetof(CPUSPARCState, hstick)); - if (tb_cflags(dc->base.tb) & - CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_tick_set_limit(r_tickptr, cpu_hstick_cmpr); /* End TB to handle timer interrupt */ @@ -5125,9 +5088,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) goto priv_insn; dc->npc = DYNAMIC_PC; dc->pc = DYNAMIC_PC; - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_done(cpu_env); goto jmp_insn; case 1: @@ -5135,9 +5096,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) goto priv_insn; dc->npc = DYNAMIC_PC; dc->pc = DYNAMIC_PC; - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_retry(cpu_env); goto jmp_insn; default: diff --git a/target/tricore/translate.c b/target/tricore/translate.c index eee935bbaf..8e4f99478c 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -55,8 +55,6 @@ static TCGv cpu_PSW_SV; static TCGv cpu_PSW_AV; static TCGv cpu_PSW_SAV; -#include "exec/gen-icount.h" - static const char *regnames_a[] = { "a0" , "a1" , "a2" , "a3" , "a4" , "a5" , "a6" , "a7" , "a8" , "a9" , "sp" , "a11" , diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 11bb8c079b..b7386ff0f0 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -94,8 +94,6 @@ static TCGv_i32 cpu_exclusive_val; static GHashTable *xtensa_regfile_table; -#include "exec/gen-icount.h" - static char *sr_name[256]; static char *ur_name[256]; @@ -577,9 +575,7 @@ static int gen_postprocess(DisasContext *dc, int slot) #ifndef CONFIG_USER_ONLY if (op_flags & XTENSA_OP_CHECK_INTERRUPTS) { - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_check_interrupts(cpu_env); } #endif @@ -2129,9 +2125,7 @@ static void translate_rsr_ccount(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_update_ccount(cpu_env); tcg_gen_mov_i32(arg[0].out, cpu_SR[par[0]]); #endif @@ -2447,9 +2441,7 @@ static void translate_waiti(DisasContext *dc, const OpcodeArg arg[], #ifndef CONFIG_USER_ONLY TCGv_i32 pc = tcg_constant_i32(dc->base.pc_next); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_waiti(cpu_env, pc, tcg_constant_i32(arg[0].imm)); #endif } @@ -2514,9 +2506,7 @@ static void translate_wsr_ccompare(DisasContext *dc, const OpcodeArg arg[], uint32_t id = par[0] - CCOMPARE; assert(id < dc->config->nccompare); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); tcg_gen_mov_i32(cpu_SR[par[0]], arg[0].in); gen_helper_update_ccompare(cpu_env, tcg_constant_i32(id)); #endif @@ -2526,9 +2516,7 @@ static void translate_wsr_ccount(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { #ifndef CONFIG_USER_ONLY - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&dc->base); gen_helper_wsr_ccount(cpu_env, arg[0].in); #endif } @@ -2715,10 +2703,7 @@ static void translate_xsr_ccount(DisasContext *dc, const OpcodeArg arg[], #ifndef CONFIG_USER_ONLY TCGv_i32 tmp = tcg_temp_new_i32(); - if (tb_cflags(dc->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } - + translator_io_start(&dc->base); gen_helper_update_ccount(cpu_env); tcg_gen_mov_i32(tmp, cpu_SR[par[0]]); gen_helper_wsr_ccount(cpu_env, arg[0].in); diff --git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc index ad713cd61e..06f4de4515 100644 --- a/target/loongarch/insn_trans/trans_extra.c.inc +++ b/target/loongarch/insn_trans/trans_extra.c.inc @@ -39,9 +39,7 @@ static bool gen_rdtime(DisasContext *ctx, arg_rr *a, TCGv dst1 = gpr_dst(ctx, a->rd, EXT_NONE); TCGv dst2 = gpr_dst(ctx, a->rj, EXT_NONE); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_rdtime_d(dst1, cpu_env); if (word) { tcg_gen_sextract_tl(dst1, dst1, high ? 32 : 0, 32); diff --git a/target/loongarch/insn_trans/trans_privileged.c.inc b/target/loongarch/insn_trans/trans_privileged.c.inc index 5a04352b01..02bca7ca23 100644 --- a/target/loongarch/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/insn_trans/trans_privileged.c.inc @@ -185,9 +185,7 @@ static bool check_csr_flags(DisasContext *ctx, const CSRInfo *csr, bool write) if ((csr->flags & CSRFL_READONLY) && write) { return false; } - if ((csr->flags & CSRFL_IO) && - (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT)) { - gen_io_start(); + if ((csr->flags & CSRFL_IO) && translator_io_start(&ctx->base)) { ctx->base.is_jmp = DISAS_EXIT_UPDATE; } else if ((csr->flags & CSRFL_EXITTB) && write) { ctx->base.is_jmp = DISAS_EXIT_UPDATE; diff --git a/target/riscv/insn_trans/trans_privileged.c.inc b/target/riscv/insn_trans/trans_privileged.c.inc index 7c2837194c..528baa1652 100644 --- a/target/riscv/insn_trans/trans_privileged.c.inc +++ b/target/riscv/insn_trans/trans_privileged.c.inc @@ -77,9 +77,7 @@ static bool trans_sret(DisasContext *ctx, arg_sret *a) #ifndef CONFIG_USER_ONLY if (has_ext(ctx, RVS)) { decode_save_opc(ctx); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_sret(cpu_pc, cpu_env); exit_tb(ctx); /* no chaining */ ctx->base.is_jmp = DISAS_NORETURN; @@ -96,9 +94,7 @@ static bool trans_mret(DisasContext *ctx, arg_mret *a) { #ifndef CONFIG_USER_ONLY decode_save_opc(ctx); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_mret(cpu_pc, cpu_env); exit_tb(ctx); /* no chaining */ ctx->base.is_jmp = DISAS_NORETURN; diff --git a/target/riscv/insn_trans/trans_rvi.c.inc b/target/riscv/insn_trans/trans_rvi.c.inc index c70c495fc5..2031e9931e 100644 --- a/target/riscv/insn_trans/trans_rvi.c.inc +++ b/target/riscv/insn_trans/trans_rvi.c.inc @@ -813,9 +813,7 @@ static bool do_csrr(DisasContext *ctx, int rd, int rc) TCGv dest = dest_gpr(ctx, rd); TCGv_i32 csr = tcg_constant_i32(rc); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_csrr(dest, cpu_env, csr); gen_set_gpr(ctx, rd, dest); return do_csr_post(ctx); @@ -825,9 +823,7 @@ static bool do_csrw(DisasContext *ctx, int rc, TCGv src) { TCGv_i32 csr = tcg_constant_i32(rc); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_csrw(cpu_env, csr, src); return do_csr_post(ctx); } @@ -837,9 +833,7 @@ static bool do_csrrw(DisasContext *ctx, int rd, int rc, TCGv src, TCGv mask) TCGv dest = dest_gpr(ctx, rd); TCGv_i32 csr = tcg_constant_i32(rc); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_csrrw(dest, cpu_env, csr, src, mask); gen_set_gpr(ctx, rd, dest); return do_csr_post(ctx); @@ -851,9 +845,7 @@ static bool do_csrr_i128(DisasContext *ctx, int rd, int rc) TCGv desth = dest_gprh(ctx, rd); TCGv_i32 csr = tcg_constant_i32(rc); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_csrr_i128(destl, cpu_env, csr); tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh)); gen_set_gpr128(ctx, rd, destl, desth); @@ -864,9 +856,7 @@ static bool do_csrw_i128(DisasContext *ctx, int rc, TCGv srcl, TCGv srch) { TCGv_i32 csr = tcg_constant_i32(rc); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_csrw_i128(cpu_env, csr, srcl, srch); return do_csr_post(ctx); } @@ -878,9 +868,7 @@ static bool do_csrrw_i128(DisasContext *ctx, int rd, int rc, TCGv desth = dest_gprh(ctx, rd); TCGv_i32 csr = tcg_constant_i32(rc); - if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) { - gen_io_start(); - } + translator_io_start(&ctx->base); gen_helper_csrrw_i128(destl, cpu_env, csr, srcl, srch, maskl, maskh); tcg_gen_ld_tl(desth, cpu_env, offsetof(CPURISCVState, retxh)); gen_set_gpr128(ctx, rd, destl, desth); From patchwork Mon Jun 5 20:15:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689235 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2286568wru; Mon, 5 Jun 2023 13:20:51 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7ftXrO2IQhect+rfzHOg3LUC0MfSvqsdcrqq4sUpD6XtMltXDpvApYwlGvWBZCQLx1oRcL X-Received: by 2002:a05:6214:240e:b0:628:35b0:e957 with SMTP id fv14-20020a056214240e00b0062835b0e957mr11238454qvb.6.1685996450897; Mon, 05 Jun 2023 13:20:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996450; cv=none; d=google.com; s=arc-20160816; b=Wb2/Im3YQTl4ST80Vm6xtiJUOOLvaqx3kFVNx8RNFWf/3gUJOoUNszXzq1BZGIsJLP ggCvhuD3YZ4OahQebVsCzya10p54pit5DhNR0SIfOZjCquZI6Zo2I5mNzu0M5cfSkrUA L2XiGfTixXe5rGPScbmGb77JRXJShHVXtLsCTXry9b4Cw5lF7H2ekpv0/IoKogCJic7y 4brbbhXFeh6F19ojq7lzwS8ckKqmdAvAQTIKR3vjrdTMVQsyxYJODehEH0TXL5MJu5kT DtsnvRUYXCA+u02h8nusuIh/NMgopQnDpbaN1aUi4Ww7Bz5AtyfsEJdS2T6dF0ecbd78 WGsg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cmXIVGUQrmsy9JspNI/wMQlDfznCiNBwDmQf4l2r7fY=; b=l7cpYsDTU+/E7aKAW0s1Ckixu9HgYtLFJGMNCkwwGMibAbcWRQ9dIN82o45ojyRy0V f2qB22joaosayUcA/cSJIiVit9Ljo/PGKd1aF3T3ZbLKhBFhJrm93+WhD3H3d5OzSJoZ XQBurQR76/4mQbC23ToB7nxSghcB9YRitDw/m+J/8Jhwn+yNHBWsujV+EN4DMVIPN2j9 g7rwBZlNIQLL/CkkQfoCnyS5JE3WOmBOjvxrkXme1LTLin/Lj8Oxr3Sgkes1zAHWJI+6 Ab0Hy1vc+FFyandGsd99GAX/bfrI4gN4fOssbSWJXmPyKHg8EwW+tOe4zGnrC6PcwT5z JhJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sP1p2aKw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id jk14-20020ad45d4e000000b00627b7dfb83csi5332694qvb.553.2023.06.05.13.20.50 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:20:50 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sP1p2aKw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GdB-0002ET-Cx; Mon, 05 Jun 2023 16:16:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcs-0001xu-R8 for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:26 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcp-0004Bs-0K for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:26 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-656923b7c81so1296045b3a.1 for ; Mon, 05 Jun 2023 13:16:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996182; x=1688588182; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cmXIVGUQrmsy9JspNI/wMQlDfznCiNBwDmQf4l2r7fY=; b=sP1p2aKw3ibVarb988aAQhJqXhTkAZ9bFfsSOxtBT+V6CQrXRnVUfNhE9aPNVzd8Nx WKz17LqArnRgWaUQIxyyAJDJFnRMsKrWZcSYLJeik+30gqR0LWP3jCcBLx2ku8m5sAQ3 55taJ4CihSjUrMP9zh3FifbHaR6jojHL3QMdgIOB0dtk1KsRqQyaloTkTfM7zTMj5BOH M++z1F6Fct5RjSOxcLrTbuMu4d7DqoKsOWevYpbj1VpFmQvfxlqkXc2QHXdCqMsBMWTM QnFAqqd2w+jf2/L3fvAFb+wU04mZLNINO6rgH376U4kAkAFCYATS3J+CmtZmoZe8zvqa 188g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996182; x=1688588182; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cmXIVGUQrmsy9JspNI/wMQlDfznCiNBwDmQf4l2r7fY=; b=RhFNiXrdgJzs3+F5Jpn944A6jlmdTA0/gI+DJfnxIiT4/S1zIP/sZfAuE8l3uiBYzX uMhgHvlYCqPkm0gFznT1SJK3wwWSZqkR/Ed46+WDAdp9yl4mGWdSCiqTPxrcguLzJtqZ HyFM0U/kvma9vMwtldXsTBxelpgtcihrLj+cU0lI/ZJ+/kl+ScJEg3poMOxp+Wfdf9jf BP9j44yOOl6xMVRHBAdSW6G52EozfrBEzu9Gtg7oSKroMVOEl7Lo9MttO+aUvUOZepO1 oNIksif2JTG7keXTflNPRknWhMbjNCKaVGTiu67/riqB2UOY0wOAfPadiVjFw/0LCLXB 4QfA== X-Gm-Message-State: AC+VfDyKwkY0DyJ4h2yuAALet8k8Zv0Br4i513yn/SxZTzJwHhD6vIS2 8YFCyHLgxvF6B2SV9jdbKpIyp3yNh7FUMJ7cGUA= X-Received: by 2002:a05:6a00:1a50:b0:651:7133:3f59 with SMTP id h16-20020a056a001a5000b0065171333f59mr865540pfv.3.1685996181722; Mon, 05 Jun 2023 13:16:21 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 37/52] target/ppc: Inline gen_icount_io_start() Date: Mon, 5 Jun 2023 13:15:33 -0700 Message-Id: <20230605201548.1596865-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé Now that gen_icount_io_start() is a simple wrapper to translator_io_start(), inline it. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20230602095439.48102-1-philmd@linaro.org> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- target/ppc/translate.c | 63 ++++++++++++-------------- target/ppc/power8-pmu-regs.c.inc | 10 ++-- target/ppc/translate/branch-impl.c.inc | 2 +- 3 files changed, 35 insertions(+), 40 deletions(-) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 519f66bb05..37fd431870 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -296,15 +296,10 @@ static void gen_exception_nip(DisasContext *ctx, uint32_t excp, ctx->base.is_jmp = DISAS_NORETURN; } -static void gen_icount_io_start(DisasContext *ctx) -{ - translator_io_start(&ctx->base); -} - #if !defined(CONFIG_USER_ONLY) static void gen_ppc_maybe_interrupt(DisasContext *ctx) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_ppc_maybe_interrupt(cpu_env); } #endif @@ -541,13 +536,13 @@ void spr_write_ureg(DisasContext *ctx, int sprn, int gprn) #if !defined(CONFIG_USER_ONLY) void spr_read_decr(DisasContext *ctx, int gprn, int sprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_load_decr(cpu_gpr[gprn], cpu_env); } void spr_write_decr(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_decr(cpu_env, cpu_gpr[gprn]); } #endif @@ -556,13 +551,13 @@ void spr_write_decr(DisasContext *ctx, int sprn, int gprn) /* Time base */ void spr_read_tbl(DisasContext *ctx, int gprn, int sprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_load_tbl(cpu_gpr[gprn], cpu_env); } void spr_read_tbu(DisasContext *ctx, int gprn, int sprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_load_tbu(cpu_gpr[gprn], cpu_env); } @@ -579,13 +574,13 @@ void spr_read_atbu(DisasContext *ctx, int gprn, int sprn) #if !defined(CONFIG_USER_ONLY) void spr_write_tbl(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]); } void spr_write_tbu(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]); } @@ -602,44 +597,44 @@ void spr_write_atbu(DisasContext *ctx, int sprn, int gprn) #if defined(TARGET_PPC64) void spr_read_purr(DisasContext *ctx, int gprn, int sprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_load_purr(cpu_gpr[gprn], cpu_env); } void spr_write_purr(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_purr(cpu_env, cpu_gpr[gprn]); } /* HDECR */ void spr_read_hdecr(DisasContext *ctx, int gprn, int sprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_load_hdecr(cpu_gpr[gprn], cpu_env); } void spr_write_hdecr(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_hdecr(cpu_env, cpu_gpr[gprn]); } void spr_read_vtb(DisasContext *ctx, int gprn, int sprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_load_vtb(cpu_gpr[gprn], cpu_env); } void spr_write_vtb(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_vtb(cpu_env, cpu_gpr[gprn]); } void spr_write_tbu40(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_tbu40(cpu_env, cpu_gpr[gprn]); } @@ -784,19 +779,19 @@ void spr_write_dpdes(DisasContext *ctx, int sprn, int gprn) #if !defined(CONFIG_USER_ONLY) void spr_read_40x_pit(DisasContext *ctx, int gprn, int sprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env); } void spr_write_40x_pit(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]); } void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_store_spr(sprn, cpu_gpr[gprn]); gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]); /* We must stop translation as we may have rebooted */ @@ -805,19 +800,19 @@ void spr_write_40x_dbcr0(DisasContext *ctx, int sprn, int gprn) void spr_write_40x_sler(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]); } void spr_write_40x_tcr(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_40x_tcr(cpu_env, cpu_gpr[gprn]); } void spr_write_40x_tsr(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_40x_tsr(cpu_env, cpu_gpr[gprn]); } @@ -830,13 +825,13 @@ void spr_write_40x_pid(DisasContext *ctx, int sprn, int gprn) void spr_write_booke_tcr(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]); } void spr_write_booke_tsr(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]); } #endif @@ -2462,7 +2457,7 @@ static void gen_darn(DisasContext *ctx) if (l > 2) { tcg_gen_movi_i64(cpu_gpr[rD(ctx->opcode)], -1); } else { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); if (l == 0) { gen_helper_darn32(cpu_gpr[rD(ctx->opcode)]); } else { @@ -4056,7 +4051,7 @@ static void pmu_count_insns(DisasContext *ctx) * running with icount and we do not handle it beforehand, * the helper can trigger a 'bad icount read'. */ - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); /* Avoid helper calls when only PMC5-6 are enabled. */ if (!ctx->pmc_other) { @@ -4369,7 +4364,7 @@ static void gen_rfi(DisasContext *ctx) } /* Restore CPU state */ CHK_SV(ctx); - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_update_cfar(ctx, ctx->cia); gen_helper_rfi(cpu_env); ctx->base.is_jmp = DISAS_EXIT; @@ -4384,7 +4379,7 @@ static void gen_rfid(DisasContext *ctx) #else /* Restore CPU state */ CHK_SV(ctx); - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_update_cfar(ctx, ctx->cia); gen_helper_rfid(cpu_env); ctx->base.is_jmp = DISAS_EXIT; @@ -4399,7 +4394,7 @@ static void gen_rfscv(DisasContext *ctx) #else /* Restore CPU state */ CHK_SV(ctx); - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_update_cfar(ctx, ctx->cia); gen_helper_rfscv(cpu_env); ctx->base.is_jmp = DISAS_EXIT; @@ -4724,7 +4719,7 @@ static void gen_mtmsrd(DisasContext *ctx) t0 = tcg_temp_new(); t1 = tcg_temp_new(); - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); if (ctx->opcode & 0x00010000) { /* L=1 form only updates EE and RI */ @@ -4764,7 +4759,7 @@ static void gen_mtmsr(DisasContext *ctx) t0 = tcg_temp_new(); t1 = tcg_temp_new(); - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); if (ctx->opcode & 0x00010000) { /* L=1 form only updates EE and RI */ mask &= (1ULL << MSR_RI) | (1ULL << MSR_EE); diff --git a/target/ppc/power8-pmu-regs.c.inc b/target/ppc/power8-pmu-regs.c.inc index d900e13cad..c82feedaff 100644 --- a/target/ppc/power8-pmu-regs.c.inc +++ b/target/ppc/power8-pmu-regs.c.inc @@ -103,9 +103,9 @@ static void write_MMCR0_common(DisasContext *ctx, TCGv val) /* * helper_store_mmcr0 will make clock based operations that * will cause 'bad icount read' errors if we do not execute - * gen_icount_io_start() beforehand. + * translator_io_start() beforehand. */ - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_mmcr0(cpu_env, val); /* @@ -179,7 +179,7 @@ void spr_read_PMC(DisasContext *ctx, int gprn, int sprn) { TCGv_i32 t_sprn = tcg_constant_i32(sprn); - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_read_pmc(cpu_gpr[gprn], cpu_env, t_sprn); } @@ -212,7 +212,7 @@ void spr_write_PMC(DisasContext *ctx, int sprn, int gprn) { TCGv_i32 t_sprn = tcg_constant_i32(sprn); - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_pmc(cpu_env, t_sprn, cpu_gpr[gprn]); } @@ -248,7 +248,7 @@ void spr_write_MMCR0(DisasContext *ctx, int sprn, int gprn) void spr_write_MMCR1(DisasContext *ctx, int sprn, int gprn) { - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_helper_store_mmcr1(cpu_env, cpu_gpr[gprn]); } #else diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/branch-impl.c.inc index 29cfa11854..f9931b9d73 100644 --- a/target/ppc/translate/branch-impl.c.inc +++ b/target/ppc/translate/branch-impl.c.inc @@ -16,7 +16,7 @@ static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) { REQUIRE_INSNS_FLAGS2(ctx, ISA207S); - gen_icount_io_start(ctx); + translator_io_start(&ctx->base); gen_update_cfar(ctx, ctx->cia); gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]); From patchwork Mon Jun 5 20:15:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689228 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2285405wru; Mon, 5 Jun 2023 13:17:23 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6BbYbmJlquoNe/isOWecBt1Eb9ey0G+wxsQ9x0q/m/HzPU9+e8qI52VaulsA9aaXzl0GV3 X-Received: by 2002:a05:6214:c88:b0:625:aa1a:937a with SMTP id r8-20020a0562140c8800b00625aa1a937amr8634986qvr.54.1685996242829; Mon, 05 Jun 2023 13:17:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996242; cv=none; d=google.com; s=arc-20160816; b=S/HDoz9EYzvASP9ygE/c7oSi8Rl060OEyFaja2vOuIHG6TlNcafTNg0x4BHdUM5UFz TqAqSiG3FWm5O4H8oqt0rmp49ZVPOILtOyjGWO9knUstR2mrGpeiIlo2WA4PWdUC9rg4 hesJbW8WCil9wmR3uqpiacgSTFMsJPVcF4IaODRcudPLL4NkvfcbrzeR5yZw0DOQpztQ K5Q8grCyK5O5hII0aTNLoZjgFACi1sVq6YbCm1IoDQn6RmnFX+Sac65Wlx50KAMatyK/ hoR0TFpqBZ/JfUdzhjvcceJd4Kfvyybyt5Piq5oknUKunV9dRNtQuMFdQ+qX6lqIOCnY iwbg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=5rPTbSJPGH0y4Jg73winpnz5u/arUPeju4H53hE/UCY=; b=AWBIh5ZhGuKaDFbQOx1Ld5I8S4wj/kBXObjVmlPYwsNJmmX+YlWvoLwDZf+drw4nm6 XOGljzi+Mrww1bxKfAqDguUs6QeFF9CAC+vViRMPpEEus1JW2UyI+w1X7oHubYCxqLve i1VM1bo2ei3gZBNSKfGp067MeRMMMWXuAJL+J9DQZjbLRkr3S335AucbGXhe1DBXVDxR it2pj/vzb3MlTelSc5ekZVKmcx+TBqGlM4xbwaBwS99LDnJpPCjOnmUHjem6JfrOLTls Bz0RyC2k8AQi0DQWwp1xTte1CN3n54Buy7wYs1jZcEQ0pE57+tyGyiJEKmmvohYkY2D+ P9nA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tIG85Yix; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gs14-20020a056214226e00b005ef58991bebsi5182659qvb.530.2023.06.05.13.17.22 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:17:22 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tIG85Yix; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gd9-00029l-PV; Mon, 05 Jun 2023 16:16:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gcs-0001xk-Fw for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:26 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcq-0003nm-LD for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:26 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-650c8cb68aeso3084716b3a.3 for ; Mon, 05 Jun 2023 13:16:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996182; x=1688588182; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5rPTbSJPGH0y4Jg73winpnz5u/arUPeju4H53hE/UCY=; b=tIG85YixUtxsTJ/6bY1XfZ/jlwG1I2G6pBtjeUjgPfux6qxf0UfYMPfB8+bS7+j+cS er5TrZq9nLmieAM9/12Mhxbo3oLUzQBwnBoUzknbdE89OzQmYnNUZSKyoTsaEusqk1vE 3WUDiwleU6CRWiXaMOdo/kXvscrI123TSx+0BY+P0B1ZC4aJ8mZtCaaW3aI8mrIclRDG HHhyhJdGCqZz6mEnSKN2+8arVt4CU6+md/oWJCciIOwYwf5NnKcKui46XBlZ+w2XDK+/ zXBD1mb6ZFUnxvwKF1GkoD/VKVxJOlUYURyUcHUAYlb4QLXM7dEYLK1mq0GU7JfL++g+ tIzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996182; x=1688588182; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5rPTbSJPGH0y4Jg73winpnz5u/arUPeju4H53hE/UCY=; b=RDFQI9pGMeIULGClxjQV0F9ufDHx67E/sJIrues7Azv0xfGqI5DnQRQ+1J8klx63nC 4t2u74+aAfKjyKX65bKEHLHWrBsRrauCy8vkpxq+i37ngi8t2Q8KtMwJbuKEI0sTYQtr Vn6aVV+kedGpTGNYMgoCAQQ/hpAFN8+WZW38dS9oO53mZuJunubTeplUe2HPbuY+FWGs +/Ja/QYiKpD0EpE+gXjbE8Bj4/RSIhqnpxTxaIanpsXwFvu5WmX4BTALJeSSHpTKL9UW AC2vEIAXNkpq3npEHQ5uv7twIF4Yuww0DaVMgO8pCYj4/nY2cyUz9ujVrXENewhVLUxQ Nsig== X-Gm-Message-State: AC+VfDzX90Uzywk25zP/Jfac/PS5U9puUKYGh6ojRcBRk2uV/h4OcB6z HXj+3uo/OsYnxw5vbltx54IftF2aqNsZJz92ujs= X-Received: by 2002:a05:6a20:e18f:b0:114:7236:9777 with SMTP id ks15-20020a056a20e18f00b0011472369777mr129779pzb.21.1685996182679; Mon, 05 Jun 2023 13:16:22 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 38/52] accel/tcg: Move translator_fake_ldb out of line Date: Mon, 5 Jun 2023 13:15:34 -0700 Message-Id: <20230605201548.1596865-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This is used by exactly one host in extraordinary circumstances. This means that translator.h need not include plugin-gen.h; translator.c already includes plugin-gen.h. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/translator.h | 8 +------- accel/tcg/translator.c | 5 +++++ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index c1a1203789..228002a623 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -22,7 +22,6 @@ #include "qemu/bswap.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" -#include "exec/plugin-gen.h" #include "exec/translate-all.h" #include "tcg/tcg.h" @@ -229,12 +228,7 @@ translator_ldq_swap(CPUArchState *env, DisasContextBase *db, * re-synthesised for s390x "ex"). It ensures we update other areas of * the translator with details of the executed instruction. */ - -static inline void translator_fake_ldb(uint8_t insn8, abi_ptr pc) -{ - plugin_insn_append(pc, &insn8, sizeof(insn8)); -} - +void translator_fake_ldb(uint8_t insn8, abi_ptr pc); /* * Return whether addr is on the same page as where disassembly started. diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 7a130e706e..60a613c99d 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -345,3 +345,8 @@ uint64_t translator_ldq(CPUArchState *env, DisasContextBase *db, abi_ptr pc) plugin_insn_append(pc, &plug, sizeof(ret)); return ret; } + +void translator_fake_ldb(uint8_t insn8, abi_ptr pc) +{ + plugin_insn_append(pc, &insn8, sizeof(insn8)); +} From patchwork Mon Jun 5 20:15:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689231 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2285708wru; Mon, 5 Jun 2023 13:18:17 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5HZeIRjADjE1hvyRcnNruU6Lqmk7+kpSwhl4/O0hoEGcPdds+4rRaJiIgeO2qClrtd+aA4 X-Received: by 2002:a05:620a:260a:b0:75d:435c:c64e with SMTP id z10-20020a05620a260a00b0075d435cc64emr908250qko.17.1685996297108; Mon, 05 Jun 2023 13:18:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996297; cv=none; d=google.com; s=arc-20160816; b=ZVs+DMyj1ausJ//5FTtLHH9Vheb/5s0NhHP2i3xO8sYbZ2RwpqT+oeXtfY9NGm0zVD 3bxFSv6fPEx8qlYWoudKkET68pD+N0vYTeIqGLZdhCj8izHtG1VZLA/uotbPOEr1gOHi zX5KwmFffCcLhdo0T1Vg0HioNgjqjdMUiESKcYHX130JSQJ1UEPG8tdHAxbYgeKirjiT rp7dckkxwOnRIHTeM7nEeFQIfH4WIfnkswCS2Ppn/NNV9QrYuL1h0+gvizcQ5IRW8BXg cgt+xSsKPmKXmf3vGHnhBiSDKYtg91jXI5In13yFQ5BZqT75bbdacGumUtRCIivbmpTh qHlQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=2IczERNlolD1Q3LBjraMPYKc5d0zVB/raqEwGBfncQs=; b=kEjt/yWQkKyuAGdCvNSLTQUdqF9krCLcPmq5Ml+rt61GkS5gjJdkHKqSRQEZ785E/m ruKVaNRv8s4l+dJmp1ZIkIAuYSDKdejP58ig1LQNXkin82pKiCE+kNDRSaLCWo9kWpVh dDRdc6030wnd2HE8iR9bpYqysP1MmtiBBH/k49tgvCb81zWCKiBRpZfYRCEpQcJ9IC8e cTYDqA1HobPbmlPgObuWL8bq5uJOJgpN0owFVzydeL9SIqVSffCfQsTTysJTUKFgrOWr yFUb2NCMFvsqljDiYN6s9xasiRkCUzuUkOb+WzcBZHLkXm2Z95Ifq3/Mk7tS0Tr4M9rF jwew== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XYprmoZg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s9-20020ae9f709000000b0075d0c5038d8si5016223qkg.291.2023.06.05.13.18.16 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:18:17 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XYprmoZg; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GdA-0002A8-DF; Mon, 05 Jun 2023 16:16:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gct-0001yW-77 for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:28 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gcq-0003ri-SS for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:16:26 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-650c89c7e4fso5357753b3a.0 for ; Mon, 05 Jun 2023 13:16:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996183; x=1688588183; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2IczERNlolD1Q3LBjraMPYKc5d0zVB/raqEwGBfncQs=; b=XYprmoZgvFNC/Fl6lFi/PdfD9RZEmieqv0SZ0trzrZO5sLsf35RrNk45boN7mxZ8YO PHddfhJoE+/+FVrC+kJokF1HN14fnjGzPpTV4a9WfYpM1+oXAP6nX5ffCOdM6h4YAsJ3 EmMiJtTehWvcGztwF2pE7Sm2vo8H2D9jNo/1PJy9RdSRJeXGJR8jqEjpPmAnlKSoNVQ3 FpXaCtI9140E8W7LPQq6zbOUQPrMiN6ohTQRS732FA0TCNqP1OVur6/rSuf3zoy/JqkR Ukwkqit1DrCahORDl+CEbVcAneKokzO+Lf8j+8Jzcp+FnM0lvgUlbmh+cC8CUCzjN994 MBiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996183; x=1688588183; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2IczERNlolD1Q3LBjraMPYKc5d0zVB/raqEwGBfncQs=; b=Bpq+SMPn1q8kwLF093Ts72Uqs4CTB1x3O1VBMfFe/WrE+GiLJRnJs4el4iAvMq+0t2 w5QcQ9fb62JPZIdzp/SUaqBZUVqD+19+pU6UTx5+OOuCFpFonDU1rwsZnEzYIsBJ2kv8 AoOzdkhy7JlRk46k7GwAtXE5EnIFG78eS2Iu5oWNrquUP4l4XfsIieR0nkOh7GAajnrA g9ta14T6Q/pPEJSYpFbpznQRLOCj7+Y4SRnEXMwLxwZAKV7ajPfs/Ck6fjPhqMvTqID6 urOQ8oEB6UO3q0OdaSErulGnerz5vCvXRxqg4nfsGM11YGv/AuDoHnfqO5+ClB96fgda NC+A== X-Gm-Message-State: AC+VfDy1fH/XOz64NF6WylzngqQOpkbtwa8RKsSEXxLqqP8CU6cZscU6 x9W6MP+AllfWjCt8nfFEhK9wExev/lrGr1zn2sQ= X-Received: by 2002:a05:6a20:4426:b0:111:97f:6d9d with SMTP id ce38-20020a056a20442600b00111097f6d9dmr6710pzb.62.1685996183480; Mon, 05 Jun 2023 13:16:23 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id f18-20020aa78b12000000b0064d32771fa8sm5552924pfd.134.2023.06.05.13.16.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:16:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 39/52] target/arm: Tidy helpers for translation Date: Mon, 5 Jun 2023 13:15:35 -0700 Message-Id: <20230605201548.1596865-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move most includes from *translate*.c to translate.h, ensuring that we get the ordering correct. Ensure cpu.h is first. Use disas/disas.h instead of exec/log.h. Drop otherwise unused includes. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 3 +++ target/arm/tcg/translate-a64.c | 17 +++++------------ target/arm/tcg/translate-m-nocp.c | 2 -- target/arm/tcg/translate-mve.c | 3 --- target/arm/tcg/translate-neon.c | 3 --- target/arm/tcg/translate-sme.c | 6 ------ target/arm/tcg/translate-sve.c | 9 --------- target/arm/tcg/translate-vfp.c | 3 --- target/arm/tcg/translate.c | 17 +++++------------ 9 files changed, 13 insertions(+), 50 deletions(-) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 868a3abd0d..5b53b6215d 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -1,6 +1,9 @@ #ifndef TARGET_ARM_TRANSLATE_H #define TARGET_ARM_TRANSLATE_H +#include "cpu.h" +#include "tcg/tcg-op.h" +#include "tcg/tcg-op-gvec.h" #include "exec/translator.h" #include "exec/helper-gen.h" #include "internals.h" diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8d45dbf8fc..d9800337cf 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -18,20 +18,13 @@ */ #include "qemu/osdep.h" -#include "cpu.h" -#include "exec/exec-all.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "qemu/log.h" -#include "arm_ldst.h" #include "translate.h" -#include "internals.h" -#include "qemu/host-utils.h" -#include "semihosting/semihost.h" -#include "exec/log.h" -#include "cpregs.h" #include "translate-a64.h" -#include "qemu/atomic128.h" +#include "qemu/log.h" +#include "disas/disas.h" +#include "arm_ldst.h" +#include "semihosting/semihost.h" +#include "cpregs.h" static TCGv_i64 cpu_X[32]; static TCGv_i64 cpu_pc; diff --git a/target/arm/tcg/translate-m-nocp.c b/target/arm/tcg/translate-m-nocp.c index 9a89aab785..33f6478bb9 100644 --- a/target/arm/tcg/translate-m-nocp.c +++ b/target/arm/tcg/translate-m-nocp.c @@ -18,8 +18,6 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" #include "translate.h" #include "translate-a32.h" diff --git a/target/arm/tcg/translate-mve.c b/target/arm/tcg/translate-mve.c index 2ad3c40975..bbc7b3f4ce 100644 --- a/target/arm/tcg/translate-mve.c +++ b/target/arm/tcg/translate-mve.c @@ -18,9 +18,6 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "exec/exec-all.h" #include "translate.h" #include "translate-a32.h" diff --git a/target/arm/tcg/translate-neon.c b/target/arm/tcg/translate-neon.c index 6fac577abd..03913de047 100644 --- a/target/arm/tcg/translate-neon.c +++ b/target/arm/tcg/translate-neon.c @@ -21,9 +21,6 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "exec/exec-all.h" #include "translate.h" #include "translate-a32.h" diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c index b0812d9dd6..d0054e3f77 100644 --- a/target/arm/tcg/translate-sme.c +++ b/target/arm/tcg/translate-sme.c @@ -18,14 +18,8 @@ */ #include "qemu/osdep.h" -#include "cpu.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "tcg/tcg-gvec-desc.h" #include "translate.h" #include "translate-a64.h" -#include "fpu/softfloat.h" - /* * Include the generated decoder. diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c index 106baf311f..d9d5810dde 100644 --- a/target/arm/tcg/translate-sve.c +++ b/target/arm/tcg/translate-sve.c @@ -18,16 +18,7 @@ */ #include "qemu/osdep.h" -#include "cpu.h" -#include "exec/exec-all.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "tcg/tcg-gvec-desc.h" -#include "qemu/log.h" -#include "arm_ldst.h" #include "translate.h" -#include "internals.h" -#include "exec/log.h" #include "translate-a64.h" #include "fpu/softfloat.h" diff --git a/target/arm/tcg/translate-vfp.c b/target/arm/tcg/translate-vfp.c index 95ac8d9db3..359b1e3e96 100644 --- a/target/arm/tcg/translate-vfp.c +++ b/target/arm/tcg/translate-vfp.c @@ -21,9 +21,6 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "exec/exec-all.h" #include "translate.h" #include "translate-a32.h" diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 7caf6d802d..a68d3c7f6d 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -20,20 +20,13 @@ */ #include "qemu/osdep.h" -#include "cpu.h" -#include "internals.h" -#include "disas/disas.h" -#include "exec/exec-all.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "qemu/log.h" -#include "qemu/bitops.h" -#include "arm_ldst.h" -#include "semihosting/semihost.h" -#include "exec/log.h" -#include "cpregs.h" #include "translate.h" #include "translate-a32.h" +#include "qemu/log.h" +#include "disas/disas.h" +#include "arm_ldst.h" +#include "semihosting/semihost.h" +#include "cpregs.h" #include "exec/helper-proto.h" #define HELPER_H "helper.h" From patchwork Mon Jun 5 20:15:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689259 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288297wru; Mon, 5 Jun 2023 13:26:12 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4Vt3dpfXGnYHBD1uCgT1BDbXVi+OrhfhbBtbn10C+JBrTfKCTq/yrMki7HV/r/rjNIiyJb X-Received: by 2002:a05:622a:15d0:b0:3f6:a1c7:bfe9 with SMTP id d16-20020a05622a15d000b003f6a1c7bfe9mr8262209qty.15.1685996772654; Mon, 05 Jun 2023 13:26:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996772; cv=none; d=google.com; s=arc-20160816; b=iF4oAAtGce7V2U4sDxMSFW51Y79tJ0D6z5ReCyBtNeGpMBMsW0gQRgWPFKeoQeyluu a8jdMICrAcBkPoLU1iOCOe5LJtV5knF+Ur3Yn/MIP/w/gJ5uq0rDbPnxa20gRlj+WIlj d0Yoa7dxfziD7uaNVH30/q5BjHNvCCpxStl+URhL2HRRv7ar9lMpE9mQ1Bq4bIDbTI8l n4Cxp3JhU0DZqELgQvIiGMQnLc07A8uGgF9nsT9dRyAOHabeUeZz9baJxBMxNNvKcp+X SyZwN26SA/p0v1GjCyAH7iQKgiqPV1mNIk5jwPP/o2w7Q7Ax1YJ8DutRBiYtDLmCrZBs BSsA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=ho2ebAK9oxZJuEiRPgTWt9rbyluwjwTYfaQBgc6qN/k=; b=IKGUuXLJi8quwPxqw8R+U76OxjfgV7V2PlnMjnUfXWkgyxdRvY8XM1zNlGvUzjeWMK fU3LGMU9BSdbAJgQQ4rYDSWCKpMPLNNicigUIoabUpyqeDWp0PydHcZfVSoqkXngjcKq d/DsivbrXBF+a1Nkp32czK/Fzmq0mJ4qEOUTMoLXNL2qAQyX56XnH6WAY1ZdpxOZZIuB Dc/r/8wgGVxhiu56KJvk9gGO4ZX/hogr1VJHjtq5hwhl5jozhUWY0ugeN3hu+oAbEzy0 kV6h0R0AEJ+xK0soQJ9lY2lbGwCdiioNxhQpibDpPiTrolq/sJC2FIKX2E2bk/Zxhxf0 Yi8g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MZwwXC0G; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o13-20020a05622a044d00b003f7f583efecsi5199865qtx.376.2023.06.05.13.26.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:26:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=MZwwXC0G; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GgH-0007Dk-IT; Mon, 05 Jun 2023 16:19:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gfo-0006sL-Ks for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:32 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gfm-0005j1-8v for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:27 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1b02085bf8dso23997045ad.0 for ; Mon, 05 Jun 2023 13:19:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996365; x=1688588365; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ho2ebAK9oxZJuEiRPgTWt9rbyluwjwTYfaQBgc6qN/k=; b=MZwwXC0GInF8ZLp8bUYQoBVaVBR3lC8Q7adCvQYFLYW2GCoDm3DleEXmutSQfD2tdd 8LCkKahIu1AwWajSy8Ez/cgSkUb2aek5D3fUGRl4Y8p6L3y1kO44LbDvWJJRNfZDHWhr aykyNaOLBjVZgsM5r0kwKsMkbcTEXuA2HJ7T6IljDdYmo1/GdewevxxesKLm783gkheS ARB+EWKi6HDTKyrHQRlffo6Pm82lUZQ77DbVbvHP3BWpenxn8xT5S1RrPfvVcTVqE+BS um4x6QgI/Px6sBMPyTNCD2V789t/Xw8XGeGnUSJhW9LUIn+c3sKMhdhMtif/o7C+i0CD M8Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996365; x=1688588365; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ho2ebAK9oxZJuEiRPgTWt9rbyluwjwTYfaQBgc6qN/k=; b=S0gMLKp3R06VyWkKOtSaDzlH6w5HAJ7Zlvs/W6iuA+jwjKOHqAJcRy8dL9xXZ+WhQR vZmzcNqcf7JsF8VxMbH/aqt8/mEmsvm1bFnbCnl4u6sq6Vc4lXVGgOMDdM36wdh5wbCz pamuenhvlwTb7HvYb2+FxuiJkWHI3tj6IXFRVIeE9SYZO68FJSqSyrtIPK8EiAiVh65C CQNqZjjp1F2LWMJXXxw8R5tir1lVB99IF/WJVhyodLjtlDSJvwFyeRx62XHBIJRq3CIj 9EQxk8ypARlhiyPgfcmWcY42L8jvZf4IZqBZxhWrp0fVCypINfkaW6m3IBUcj/+RbIdD Xm5A== X-Gm-Message-State: AC+VfDxIpjQn7fu+uwHSFLw7w+oCy3u+Zt+QsmOGeGmC/BAV7P3BX4BI YBvImwrcGjXw3S5ZPAo6GJFJkTiScvyczHuN1Wg= X-Received: by 2002:a17:903:1250:b0:1b0:4680:3f with SMTP id u16-20020a170903125000b001b04680003fmr26696plh.41.1685996364747; Mon, 05 Jun 2023 13:19:24 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id w20-20020a170902c79400b001a980a23802sm7018184pla.111.2023.06.05.13.19.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:19:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 40/52] target/mips: Tidy helpers for translation Date: Mon, 5 Jun 2023 13:15:36 -0700 Message-Id: <20230605201548.1596865-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Move most includes from *translate*.c to translate.h, ensuring that we get the ordering correct. Ensure cpu.h is first. Use disas/disas.h instead of exec/log.h. Drop otherwise unused includes. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/mips/tcg/translate.h | 6 ++++-- target/mips/tcg/msa_translate.c | 3 --- target/mips/tcg/mxu_translate.c | 2 -- target/mips/tcg/octeon_translate.c | 4 +--- target/mips/tcg/rel6_translate.c | 2 -- target/mips/tcg/translate.c | 18 ++++++------------ target/mips/tcg/translate_addr_const.c | 1 - target/mips/tcg/tx79_translate.c | 4 +--- target/mips/tcg/vr54xx_translate.c | 3 --- 9 files changed, 12 insertions(+), 31 deletions(-) diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h index fa8bf55209..3b0498a47a 100644 --- a/target/mips/tcg/translate.h +++ b/target/mips/tcg/translate.h @@ -8,9 +8,11 @@ #ifndef TARGET_MIPS_TRANSLATE_H #define TARGET_MIPS_TRANSLATE_H -#include "qemu/log.h" -#include "exec/translator.h" +#include "cpu.h" #include "tcg/tcg-op.h" +#include "exec/translator.h" +#include "exec/helper-gen.h" +#include "qemu/log.h" #define MIPS_DEBUG_DISAS 0 diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c index 220cd3b048..b5b66fb38a 100644 --- a/target/mips/tcg/msa_translate.c +++ b/target/mips/tcg/msa_translate.c @@ -11,11 +11,8 @@ * SPDX-License-Identifier: LGPL-2.1-or-later */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "exec/helper-gen.h" #include "translate.h" #include "fpu_helper.h" -#include "internal.h" static int elm_n(DisasContext *ctx, int x); static int elm_df(DisasContext *ctx, int x); diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index be038b5f07..39348b3a91 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -16,8 +16,6 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "exec/helper-gen.h" #include "translate.h" /* diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c index 103c304d10..e25c4cbaa0 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -7,10 +7,8 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "exec/helper-gen.h" #include "translate.h" +#include "tcg/tcg-op-gvec.h" /* Include the auto-generated decoder. */ #include "decode-octeon.c.inc" diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c index d631851258..59f237ba3b 100644 --- a/target/mips/tcg/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c @@ -9,8 +9,6 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "exec/helper-gen.h" #include "translate.h" /* Include the auto-generated decoders. */ diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 312ed66989..f3da05ba3b 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -23,19 +23,13 @@ */ #include "qemu/osdep.h" -#include "cpu.h" -#include "internal.h" -#include "tcg/tcg-op.h" -#include "exec/translator.h" -#include "exec/helper-proto.h" -#include "exec/helper-gen.h" -#include "semihosting/semihost.h" - -#include "trace.h" -#include "exec/log.h" -#include "qemu/qemu-print.h" -#include "fpu_helper.h" #include "translate.h" +#include "internal.h" +#include "exec/helper-proto.h" +#include "semihosting/semihost.h" +#include "trace.h" +#include "disas/disas.h" +#include "fpu_helper.h" #define HELPER_H "helper.h" #include "exec/helper-info.c.inc" diff --git a/target/mips/tcg/translate_addr_const.c b/target/mips/tcg/translate_addr_const.c index a510da406c..6f4b39f715 100644 --- a/target/mips/tcg/translate_addr_const.c +++ b/target/mips/tcg/translate_addr_const.c @@ -11,7 +11,6 @@ * SPDX-License-Identifier: LGPL-2.1-or-later */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" #include "translate.h" bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa) diff --git a/target/mips/tcg/tx79_translate.c b/target/mips/tcg/tx79_translate.c index 3a45a1bfea..dd6fb8a7bd 100644 --- a/target/mips/tcg/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c @@ -8,10 +8,8 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "tcg/tcg-op-gvec.h" -#include "exec/helper-gen.h" #include "translate.h" +#include "tcg/tcg-op-gvec.h" /* Include the auto-generated decoder. */ #include "decode-tx79.c.inc" diff --git a/target/mips/tcg/vr54xx_translate.c b/target/mips/tcg/vr54xx_translate.c index 804672f84c..2c1f6cc527 100644 --- a/target/mips/tcg/vr54xx_translate.c +++ b/target/mips/tcg/vr54xx_translate.c @@ -10,10 +10,7 @@ */ #include "qemu/osdep.h" -#include "tcg/tcg-op.h" -#include "exec/helper-gen.h" #include "translate.h" -#include "internal.h" /* Include the auto-generated decoder. */ #include "decode-vr54xx.c.inc" From patchwork Mon Jun 5 20:15:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689255 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288291wru; Mon, 5 Jun 2023 13:26:11 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ67YDffB9h8E5BYau51ZPcQm+mp5FHOt1Zt0vI0kYVhQJ25QoN4CGxZ3yOjQP8sfOC/ywhG X-Received: by 2002:a05:6214:5089:b0:626:ff6:f489 with SMTP id kk9-20020a056214508900b006260ff6f489mr8738346qvb.17.1685996770786; Mon, 05 Jun 2023 13:26:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996770; cv=none; d=google.com; s=arc-20160816; b=HvtpaAxLm6dmV88FoLR32/JHXE3cGSYXNGLU1x479L6XqRIXx7J0tREI4WgIlbE4qO az38U6h9bwgncyphE0lNBzujEIzdTMP5Y/6Gg5lajac7q9QqxbWVx5vCuDWo5/SLGerp +LQsR7AohA2FwQaVxra7TBij+Ga0SkmxLJkPap/F43lbiDeCuL4Qlb5tpLrrZ1LyjHKf v415nnDI/gBaf11j2Oqy5o6PeuhLhZCRyv7BMZD18RqsVqNDQA29sfTMj1tYFp/q7/Me /dt2Kd5Y3ZLHfu63XwfnrGhnzpQWS5CtHDTgMfPFNiV6PNuhYMsBJ/P+2HI+YmnTU+9n PoxQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=WRpN/gEKoBKxUq8HSm115zlXgrzm+s7nqPytLNJQu4M=; b=xdR7iq/LuB2aqxMpJvQreIHKJOHyUEBysJ1ztdu6BZaN3L8GBPn3vGmzeilNkaKahQ ldNEg3PMjjhLyFwe7ypZvpYT1PlpV1f8IOc9Qzaqp6K3AzrzC35uDvaMkj8RPQP2Wu12 TSY7azB8MCBWSKs4oDybI83n3+ss4sBdj2tzHmtuZoxq6nbLULAAA9SRZ9dZqpBeU6MP OII1I2glYELSS35ieid1XXOoTQ+7U4spyt6k7BBLSZ/QAmeMNrZYzyInf9Vqn5IgW+J+ mEApn6l61tk1+sihs3sdksqR/C0hW+tmAL5F+A1JjVtWobMRZYqjaVmXWKui1trACc46 iMgQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QrpkG03w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 5-20020ac85945000000b003ef6035045asi5240257qtz.728.2023.06.05.13.26.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:26:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=QrpkG03w; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GgI-0007Hi-T9; Mon, 05 Jun 2023 16:19:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gfq-0006sg-7E for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:32 -0400 Received: from mail-pl1-x630.google.com ([2607:f8b0:4864:20::630]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gfn-0005jV-2e for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:29 -0400 Received: by mail-pl1-x630.google.com with SMTP id d9443c01a7336-1b01d912924so49326035ad.1 for ; Mon, 05 Jun 2023 13:19:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996366; x=1688588366; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WRpN/gEKoBKxUq8HSm115zlXgrzm+s7nqPytLNJQu4M=; b=QrpkG03w1BoGfcMpPLPNdM2lFuMkGxhvgjLuKC1wC2++xxCEkMo3x7t/XXwY7wDiX1 fWEp3wvR2z+wMKQlREtJDnGR12aqC+WkVZD8JfgZxV2WptRU2Os+nb1jiYc8ogEJYajW AJRMc7G9SuU5lxpr9T9c23FcdjMBF2EMHApy82mCszu0pGS5KwGbVcqLiSPUQDZA85nf VmjUeIWVxVpfgZGCTmN2h+iI5E+KalxsGguraeGp3M/JDcYQdGGcoGv6ezRPmCIDyEcv 5049IgHOxZfEYhSUojqFyFyIyaS7CDGrdzEhZFHSXaSu4uJuXbq99asBZgBGbsJgb7AQ HSng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996366; x=1688588366; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WRpN/gEKoBKxUq8HSm115zlXgrzm+s7nqPytLNJQu4M=; b=DsJ4vHMWKycGeR4C0TGKC8+udNZygJ5MzMyAHlU5ycfOLGxfWC6wrb7mZ05wBWbM1v OwfUpT1uDkGfa9bxjVX+6jTDu2UJ3XFvdoYxdatt2nxOQu1XscdLLgQibn6PUoCmIUcO CQEM/xeMJJBLMbfYh/wl44nJV8naZ3LsS1sF9ss2D6kkYjwi/GVZzGtNjoHJvXVobzXK U1AQQT1TNKfmFS0AAhgbbN/Lx5+543fSv/20r3Lr50BsBs7Fus7iu9jdew0PtQc69aBv BbWsWuw/srSRWXnhmfaL49rOfj64Ne0+CHNSCXTAuyx4zmWInYiNk2uzA1yYSL7pgCDh /y5g== X-Gm-Message-State: AC+VfDxl7BuP+s3suxk6wyroMjDBtjIJKId/jwKkQwKvhnH30jP6qpd8 bUJKv2rrqe6vzCDkKFpVngStZ3YGRTP8CJ5OVBA= X-Received: by 2002:a17:902:b195:b0:1b1:d0b2:b9b3 with SMTP id s21-20020a170902b19500b001b1d0b2b9b3mr74618plr.23.1685996365736; Mon, 05 Jun 2023 13:19:25 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id w20-20020a170902c79400b001a980a23802sm7018184pla.111.2023.06.05.13.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:19:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 41/52] target/*: Add missing includes of exec/translation-block.h Date: Mon, 5 Jun 2023 13:15:37 -0700 Message-Id: <20230605201548.1596865-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This had been pulled in via exec/exec-all.h, via exec/translator.h, but the include of exec-all.h will be removed. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/hexagon/translate.c | 1 + target/loongarch/translate.c | 3 +-- target/mips/tcg/translate.c | 1 + 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 770de58647..708339198e 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -22,6 +22,7 @@ #include "tcg/tcg-op-gvec.h" #include "exec/helper-gen.h" #include "exec/helper-proto.h" +#include "exec/translation-block.h" #include "exec/cpu_ldst.h" #include "exec/log.h" #include "internal.h" diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 1cf27a4611..3146a2d4ac 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -9,11 +9,10 @@ #include "cpu.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" - +#include "exec/translation-block.h" #include "exec/translator.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" - #include "exec/log.h" #include "qemu/qemu-print.h" #include "fpu/softfloat.h" diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index f3da05ba3b..74af91e4f5 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -26,6 +26,7 @@ #include "translate.h" #include "internal.h" #include "exec/helper-proto.h" +#include "exec/translation-block.h" #include "semihosting/semihost.h" #include "trace.h" #include "disas/disas.h" From patchwork Mon Jun 5 20:15:38 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689269 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288879wru; Mon, 5 Jun 2023 13:27:53 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6tfulwDRyPknumqa4DMz3VNAcBsP97xFv9OWCuRgiTAxGEXvENKhXGOuFUqJeNQIUU7BeY X-Received: by 2002:ac8:574c:0:b0:3f7:fac6:e3e4 with SMTP id 12-20020ac8574c000000b003f7fac6e3e4mr8867701qtx.66.1685996873167; Mon, 05 Jun 2023 13:27:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996873; cv=none; d=google.com; s=arc-20160816; b=lI2pl6giYUa1Uma45jnNMlESU+S4lL6ObDcFQrDDZEK1MzVcWY2jqSWoPyxSgi8Ypt CTsrbr7zwg6jjg9tLGPs54Z+i1a7jtvXr6CidGZfL3stuFgp3Yg33+MB3VrdcmmK7hh2 RWwi8ifU7QuEz905pLLXTulmrVE2zCaSc2Cn6gLBBpz0P3lGfvjLeu5YOZbew82jPNQ/ eSr1m2mQgDICvl/3JsKV7A8RgZi+cLF7k8hT2covEXg0mbtz1Fbo5jLe+WWwfz22P7Si iYMWYvrFZCeiT2dI5u8zJxibgtj631nHSvP3M68TUR638pv2YAgsN0DB3O5dPeIBASG2 ITDQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Vy1+4+EjeJN2rjgv7AIR8YQgARHZt7Wh5OCajfSPz44=; b=SfObyrv5JkQK5+RptWHtdTjJzSjhDDCRmP++4lY6oD9YM/+ygHJiCr5DSRVANMXXH0 RiZrv4yTjTDoJrW/mpD3srlPXGjSzDmnqLdiiXeWznI/tcOVHwNZX0v5Nmoey5asfbjB JfG/6h/Bj61gMXAfOy3EBdxg69wLZQMDXB/ekc/LM1rYhYBXrFtTZmvZpDcftO9OAYXX xyhHZ8nDR2HnPslLYopCPPjdMq6kPUl6pmXR2xXIUc8QihtSOdRaH9JBQFNpOJx9/vWf 3Kr8OXV1EiMPrW7DdB8q1+QKoCAIJ6zIxqiljRADxEFulpYfr7dchD0neNh2jP04kPQx QfEA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ce1Rnzf+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id j4-20020ac85f84000000b003f53624729bsi5390177qta.57.2023.06.05.13.27.53 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:27:53 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ce1Rnzf+; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gg4-0006wh-65; Mon, 05 Jun 2023 16:19:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gfq-0006t0-Fn for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:32 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gfn-0005jh-RJ for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:29 -0400 Received: by mail-pj1-x1033.google.com with SMTP id 98e67ed59e1d1-256712d65ceso2358193a91.1 for ; Mon, 05 Jun 2023 13:19:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996366; x=1688588366; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Vy1+4+EjeJN2rjgv7AIR8YQgARHZt7Wh5OCajfSPz44=; b=Ce1Rnzf+64b0JsRtu+tFIAf2rtgoz4sy4h3dAoBqVq2PRQx18/WxoTuxWRbD1oNRPR XusInUwhsiT0esQu2AuTDGHPlNybFFBpFL3ds8pv58HGdvXQjwQgVtdRWeO0ZESyHtq3 ptMa3CvvNBA8LWR/Ud6kZ02iS5UGNtjJLQDN3Z5nb4riEEzkguyJ3VSI5QraE7dQyUPK 0fwRm3ul37xbZ8InVdvy+5G0ztpLH95AlhrPd8/jKvwSRjKjDsD75sxhsZauBhk3ygB/ EpiGymtHM9cIN0JnF/DAV6TNJDCd7M3iimZuYcrQIj1oEZLiBEdapKVrI3GFhE1bU6cW +1bA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996366; x=1688588366; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Vy1+4+EjeJN2rjgv7AIR8YQgARHZt7Wh5OCajfSPz44=; b=UTrRawhOiS8EfKfdx05TRmdSF9RbVlUqFdZZFMOEXAxE6itZ0VqqcB3otJ56s50kXM +aE8whQaVEKa5DZyHHbm3Vpl5mITwZGSCMhhp4AjadTLzHVthj6SnPFBniuPD5GGmw/O 2jOQgk4jwLO+gvtjZhizldqLchS9ReyoEdgsNoo23xTdo+Ltn9t/kupkYUqHXNNm+81o JSafeaXP5FLyhokG8LZmtAjy+U0lA7uOzLykmNZWuze5KGj6myx0eRP+ilq/AQEL54G6 oXUs3CQARhxX1SgGFiUdBwVReQn1s/W4LBHyuriRHo4Z9aKw7z9i/IPtwjQyDWFm5SvD 9r7g== X-Gm-Message-State: AC+VfDwaapeq1jbxvFGdJqlWpIhCue1ce/l3ifbDXTtbtv7f0sTxSnzf ue9uPVkUc+P4EHXYu2O477RZR4g0MHDNQee3E9Y= X-Received: by 2002:a17:903:22cf:b0:1ae:40ed:4b8 with SMTP id y15-20020a17090322cf00b001ae40ed04b8mr55267plg.22.1685996366508; Mon, 05 Jun 2023 13:19:26 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id w20-20020a170902c79400b001a980a23802sm7018184pla.111.2023.06.05.13.19.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:19:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 42/52] target/arm: Add missing include of exec/exec-all.h Date: Mon, 5 Jun 2023 13:15:38 -0700 Message-Id: <20230605201548.1596865-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This had been pulled in via exec/translator.h, but the include of exec-all.h will be removed. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 5b53b6215d..4d88197715 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -4,6 +4,7 @@ #include "cpu.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" +#include "exec/exec-all.h" #include "exec/translator.h" #include "exec/helper-gen.h" #include "internals.h" From patchwork Mon Jun 5 20:15:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689266 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288816wru; Mon, 5 Jun 2023 13:27:40 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7wh8oIx+QycVh+94E32BihuPtacv3DrA9uCZBEjcwaHxIXDjg0t2CgP7Zt14EB15zXSGbL X-Received: by 2002:a05:6214:767:b0:623:8214:14c8 with SMTP id f7-20020a056214076700b00623821414c8mr7924708qvz.51.1685996860341; Mon, 05 Jun 2023 13:27:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996860; cv=none; d=google.com; s=arc-20160816; b=irj3YgAWKOPzfRV54Z0XSgcBsSBYeQdt+korXWrNJOSdXCjDotjmiZGukaKR8JkXp8 DCMxltg2Hl6z1DF7PCOP4IXs5WAe57sPdfdT+1RBsSzKi8ZcSS9oin3EW5l5tmDUzrOG OkZvc8N/uRwwiZ1kpW3fRc8T/4cug6uYwLLBiwY4sX1H87kk540WFYkWyLC/dNlQwEID 9kF9yRM3qAEbf+8UBx2CVW37Bd4eHe7TwK79YJAGR0hLwiEvtFcISeONBpImzJoSYyTt IF+XDKByNHYAr0Gw9xVUo2r6DTZzbIAurNiHsEPYJkFT1J9u6P1uqltEbNiLbby56GQ9 T6AQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=nAImCar6oyDgjZqzKCPoy2LdZjs1Hux2vEDU7Qe1ybQ=; b=N+LO3muy76Z/Envb9C54odrRbmIC6vtqkMODk8G1Uf6/U1EGBtEDo8ZF3FmRL3oFs4 3h6LZZ6bLvibim1DWtOIbcUNVAu+GIIiCobWyzqk+W/vhEHn+65gJuZWr9ASoD/z2sEf ybax+HrQoZxU2cgzIqa/rLPDtxblV+/fi2ZRYudl/Z7asyc6Yv0f21acglqH5ACY14jk PLxm47JynhMSTwg6UkA8ILA4VlA+Ms8WA6F6oOwiOULFc/uUL+Y6TltN0kduDPnI4Ncm eY17p+DnSBMw3HZo/cjJdckrcXPQcG52dkJ25WE6uOZ+U45nCmerfVlNo9LO0ggslSCF JSnQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="l/nPa24f"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id eo6-20020ad45946000000b005aadafa8f0esi5255148qvb.69.2023.06.05.13.27.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:27:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b="l/nPa24f"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GgI-0007GD-CF; Mon, 05 Jun 2023 16:19:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gfr-0006tG-Hl for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:32 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gfo-0005k6-Jj for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:30 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-653f9c7b3e4so1955562b3a.2 for ; Mon, 05 Jun 2023 13:19:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996367; x=1688588367; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=nAImCar6oyDgjZqzKCPoy2LdZjs1Hux2vEDU7Qe1ybQ=; b=l/nPa24fQUIv0eQA2WuXBq4Cctm5bbcT8k06GzuFhVZH2dwjQ8pglwBwlAlFfR6tK+ +jAUrnguNt3bgXJ658gR46qm5iPpD7bqtwE+Xskn+3rF5bI16zvVM5VaqkN46K8f/fjk TDHSazgOBdXqLnt4wdEE9/qGF0uQ9wtkj6SujlXN3PffIXK4TGMl4cdVYaVhf29FiRCz hAdieSxXCJesq8de7B0aweMGNdvmkLCxZPwIzaMDxWXFlPIjHexEBQrHsoTWqZUpWLZb ziHM4vURqkEpp02AVMugfKLzHQncKmruKniTFnbLVN4gZl+RmwE38Ercl8mJWz8TrJxS Y+Ow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996367; x=1688588367; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=nAImCar6oyDgjZqzKCPoy2LdZjs1Hux2vEDU7Qe1ybQ=; b=N+czNV5MadTKEj2+gA4smn7n5toniFif1ukCW7iIK+l9e7BAjAbGDNcfb4a44G7kYW ldVX14EKeBgavNPIaQRdzp5yjwW6zVnXJtIvtzkrucY/Omrw+HMa/3/Ofl9jlYhJY5T9 HMvtxbFnBwaL9W/mQbJsfRRWDAInsVWmT9JVsR+vP33QrMDtH0bXJyFzJQXY9FC1lUzL CrAPNbJFnu+I74FLni8KwN3TYQSC45hfQhhZABwQEcgRVvWMgGrBPrdYeTct/InLGfaM kLTxzoBXhswYFtEFFFegEhkYvThjkpJTZuUiSk06b+BLC58/ub4vxLvAlDK5q8zs1E3K F5Ag== X-Gm-Message-State: AC+VfDxrgLCc2JrhhwDoS1S3U+GX58WL2ulE1I82UxwQ50sDPAuL9kb1 RTjxghZ55yyjnfV/cN+JYkKbk6Sksm+gkX2Cgq4= X-Received: by 2002:a17:902:7c0c:b0:1b2:1b20:c45b with SMTP id x12-20020a1709027c0c00b001b21b20c45bmr1420740pll.54.1685996367323; Mon, 05 Jun 2023 13:19:27 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id w20-20020a170902c79400b001a980a23802sm7018184pla.111.2023.06.05.13.19.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:19:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 43/52] accel/tcg: Tidy includes for translator.[ch] Date: Mon, 5 Jun 2023 13:15:39 -0700 Message-Id: <20230605201548.1596865-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Reduce the header to only bswap.h and cpu_ldst.h. Move exec/translate-all.h to translator.c. Reduce tcg.h and tcg-op.h to tcg-op-common.h. Remove otherwise unused headers. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/translator.h | 6 +----- accel/tcg/translator.c | 8 +++----- 2 files changed, 4 insertions(+), 10 deletions(-) diff --git a/include/exec/translator.h b/include/exec/translator.h index 228002a623..224ae14aa7 100644 --- a/include/exec/translator.h +++ b/include/exec/translator.h @@ -18,12 +18,8 @@ * member in your target-specific DisasContext. */ - #include "qemu/bswap.h" -#include "exec/exec-all.h" -#include "exec/cpu_ldst.h" -#include "exec/translate-all.h" -#include "tcg/tcg.h" +#include "exec/cpu_ldst.h" /* for abi_ptr */ /** * gen_intermediate_code diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 60a613c99d..fda4e7f637 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -8,15 +8,13 @@ */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "qemu/error-report.h" -#include "tcg/tcg.h" -#include "tcg/tcg-op.h" #include "exec/exec-all.h" -#include "exec/log.h" #include "exec/translator.h" +#include "exec/translate-all.h" #include "exec/plugin-gen.h" -#include "exec/replay-core.h" - +#include "tcg/tcg-op-common.h" static void gen_io_start(void) { From patchwork Mon Jun 5 20:15:40 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689254 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288266wru; Mon, 5 Jun 2023 13:26:06 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5eGPFCzv3e1Lr65sSJUlwCgWjucrycUYx+tIl73AdUkWClcgMeHb1METqIEGwsLueJ+6vL X-Received: by 2002:a05:622a:2d4:b0:3f9:ab64:8bd3 with SMTP id a20-20020a05622a02d400b003f9ab648bd3mr2470263qtx.13.1685996766510; Mon, 05 Jun 2023 13:26:06 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996766; cv=none; d=google.com; s=arc-20160816; b=dfFM9f8YgmpPyB/UWNyXK2Np3n8LeyZqs8LLFdUp3UyAuEpj9EiVrjfRZkVwmb2ZuJ Zghp3tsm3gRSTcNirjr3OzdnbcQrk0jmOmLLBszFay1mOGCOgIJvCAmMXQpiki1avsoP sjcqKeEkEy9cujwxqc10L8VY6DceFfPtYj8GJPCfsoKU+ZlylqYkDq23AoaMqBwFNvfW CBwpaC1swMoIG/Pw/Otf30M50krzCn1iJH0JfPBNtk959n/kyEb5q2O3xewYud4sZAYY buPCgoE7huFN2W4E0eY59eS9thRAIbhk8sJ6wMd4mMPVvqYd3yidL1BdtTCqv/ewF9fO lcrg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=1+2aTZUDJhHk+1ynfemTk95bp++Vx2nuawcefQHRCuc=; b=DFrgVgkuwZJFzc2S2cROl4AKVh1Hrbjzh1wlMNeWZmtQLCFQIdVNWIX6Cfe6dhi8lo ks4675IKZyt/A40AKGvneS0K7zGKgfMfBU23tmdYiP8pPXa3OWC4plSqZvm4k9gzPWYv /J/IUWWfKfmU4Uz1FPigDadw4QUc3gN6V6u+dJGwSaIszAoZGb05tbAbyeSRkDzOV6Me O9DdwLK/z7Y28iE6WuvTYAjUDeRz4KiFJpgh4KrKIxyadyqVZPPAWGHYsqCaKPotUlhT Ii9JYeeHNKq0Xds7yV4trOwlwdrbp1xult6+ovGl29l7/HXsknhc5ROVZD100x5/d6Yp x4OQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ko6AfTqU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id o20-20020ac85a54000000b003ef595fac25si5188459qta.801.2023.06.05.13.26.06 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:26:06 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=Ko6AfTqU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gg8-00070y-V2; Mon, 05 Jun 2023 16:19:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gfr-0006ta-P3 for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:32 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gfp-0005kc-Oy for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:31 -0400 Received: by mail-pg1-x532.google.com with SMTP id 41be03b00d2f7-5343c3daff0so2824843a12.0 for ; Mon, 05 Jun 2023 13:19:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996368; x=1688588368; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1+2aTZUDJhHk+1ynfemTk95bp++Vx2nuawcefQHRCuc=; b=Ko6AfTqUBr/Ap/UafM3WeBuRiB9s7Vq9k2/oHgRM4qYjPYgBL88n+VzPqbiwoGfkn3 Ne3Se0Dj4k0ux2uh0Ji6BitHrniIsjk1ImsBzB9yi5hVGGMCDUWXEuZ2pZFvC+OuQID/ 944NLG4tarMgUz9Y+Nphsj9H6E4zjC1ZjIKqZIsAnhqw0mvIQ4vmO343PnWjKQQNOvMs CMu3+B1mc9AQZMld85elxAkknv7UPguSZ3ekIQ/1SfSfSZxoZ6rUoRrDeqZBrZX8+UwD UdmyfkNyoY8O5RmPHbT4PNN6Kv4F79e53qiG9SAfG7oPjFnEKJjjMp12CZ+xHjBdeEOM QZgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996368; x=1688588368; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1+2aTZUDJhHk+1ynfemTk95bp++Vx2nuawcefQHRCuc=; b=GeXLWZ1JFyAJ37hLVvQDNLVT0R0nBuM5CJP9cpVu+czNDVYWpbXxblapsYQCQ1NDCn VjDObBgNsYzPvqDo4zgxl0fvAqjiYUFfPO8aU7YTqWbgavrHG/W8hpuxlWs1enFLs6fd NE1wrqQNq8klZRb1aYU/eP5AL4sHt/iDMMbO7pZ83iQx7ac7AeRKD3gmiXcpTbh82Xtn 7sfCFSI/d6jToWUk63XxwMhOehiclrOY31aeB6WjJaZExZe7LfbhW3/49hyHixzB+8nO /vseg2HdFvzYA4Pl+gIIjBRWLjIfQw1Ux5eirVo3kZ9mFyl+aUaLBCgZ0WEZSDcQe/Qq CPKg== X-Gm-Message-State: AC+VfDzMk9FRnRaScmet05f6zTKgFGgW7Tj6N2+Ta8+cQGErlDf4n0BV 2YNiauwQWC9UajzoOP+PcE+Jjg8CX8eaLAKN1lI= X-Received: by 2002:a05:6a20:3d02:b0:10b:6b1f:acf1 with SMTP id y2-20020a056a203d0200b0010b6b1facf1mr136117pzi.29.1685996368079; Mon, 05 Jun 2023 13:19:28 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id w20-20020a170902c79400b001a980a23802sm7018184pla.111.2023.06.05.13.19.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:19:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 44/52] tcg: Fix PAGE/PROT confusion Date: Mon, 5 Jun 2023 13:15:40 -0700 Message-Id: <20230605201548.1596865-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The bug was hidden because they happen to have the same values. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/region.c | 18 +++++++++++++----- 1 file changed, 13 insertions(+), 5 deletions(-) diff --git a/tcg/region.c b/tcg/region.c index bef4c4756f..f8410ba5db 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -505,6 +505,14 @@ static int alloc_code_gen_buffer(size_t tb_size, int splitwx, Error **errp) return PROT_READ | PROT_WRITE; } #elif defined(_WIN32) +/* + * Local source-level compatibility with Unix. + * Used by tcg_region_init below. + */ +#define PROT_READ 1 +#define PROT_WRITE 2 +#define PROT_EXEC 4 + static int alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) { void *buf; @@ -525,7 +533,7 @@ static int alloc_code_gen_buffer(size_t size, int splitwx, Error **errp) region.start_aligned = buf; region.total_size = size; - return PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return PROT_READ | PROT_WRITE | PROT_EXEC; } #else static int alloc_code_gen_buffer_anon(size_t size, int prot, @@ -794,10 +802,10 @@ void tcg_region_init(size_t tb_size, int splitwx, unsigned max_cpus) * buffer -- let that one use hugepages throughout. * Work with the page protections set up with the initial mapping. */ - need_prot = PAGE_READ | PAGE_WRITE; + need_prot = PROT_READ | PROT_WRITE; #ifndef CONFIG_TCG_INTERPRETER if (tcg_splitwx_diff == 0) { - need_prot |= PAGE_EXEC; + need_prot |= PROT_EXEC; } #endif for (size_t i = 0, n = region.n; i < n; i++) { @@ -807,9 +815,9 @@ void tcg_region_init(size_t tb_size, int splitwx, unsigned max_cpus) if (have_prot != need_prot) { int rc; - if (need_prot == (PAGE_READ | PAGE_WRITE | PAGE_EXEC)) { + if (need_prot == (PROT_READ | PROT_WRITE | PROT_EXEC)) { rc = qemu_mprotect_rwx(start, end - start); - } else if (need_prot == (PAGE_READ | PAGE_WRITE)) { + } else if (need_prot == (PROT_READ | PROT_WRITE)) { rc = qemu_mprotect_rw(start, end - start); } else { g_assert_not_reached(); From patchwork Mon Jun 5 20:15:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689271 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2289056wru; Mon, 5 Jun 2023 13:28:24 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5DKiGxp6O5F/f/3T6dxI1tOJDf7iyKv/u2dpXFFPyB9JE29KpvX3fpIeGTMfxBHl9LLwRS X-Received: by 2002:ad4:5b8c:0:b0:626:199e:1b96 with SMTP id 12-20020ad45b8c000000b00626199e1b96mr8373193qvp.64.1685996903946; Mon, 05 Jun 2023 13:28:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996903; cv=none; d=google.com; s=arc-20160816; b=S6Ck7t18G2omtQPXc38G2p/q7cOv7Pfog0GkwDk7vtu0xXng60nlOtLZ4eOL9VnDYg C6sd7Szc4jtjD4jqTfARPbEXVb9iXzkM3PjITz1b4yrEj3sZl9AhuKr/Tuz2YLXDTFUy L584VeeNYHOyN56J15CpHandzHHDk7RUK50X70Rj3Tjh6QModFgqN9Y6yrUcLj5QY/8C uNv6gYN5aQx0FzQmV16PCL1NifCA66Z2McYrW0oqhjYBWKbjOYEdB6txqXczKTr52Egz aBWHQVks9XobR4sOJZntVTJx/knxz7aX3RUZYPICM7M4/0CQezdbZWwMqC8GphWZ7G+u H8ew== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lRZfmLEHt5BGsHL2wDYj2+9bUOvf3/u2iHm8wiPgZqI=; b=lkBcJ5H/N7F/CvTAXSfx3rsl9fFlDKoCH5TWKFcijnEMxSjCr4eyJvsVoOcmv2Y7kq l4mz2SzHtnOT6sfAUXEeXElO/3AWdV/dnAXNUuJO3qV+c8awSBZMYTipePRb67FXMwDu WvEKp/CZNf/H3R0D6AKE9G8PLqdUNlnWEyN3ZfLL7lCC3n6d3o3XuXI5HVZgzZH/J+Oj p+NitUD/g5QgTvB9ozoZDkGGKMPkaA0jk2fNHjO/SftIxSDpaG8oJFIVWQmJkOPrbnXe wSP5lsEhz+BjqGnX9T9IFlrzyJ0eXtBR7z0dfC0Vm9iEJVa7Y831P5GyflStcN+iiXaG aDKw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kJ0Bkroo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id jv14-20020a05621429ee00b005eda1d1d9aasi5210048qvb.598.2023.06.05.13.28.23 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:28:23 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=kJ0Bkroo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6Gg7-00070a-6I; Mon, 05 Jun 2023 16:19:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gft-0006tz-Kf for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:33 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gfq-0005l2-Ps for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:32 -0400 Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-543ae674f37so975183a12.1 for ; Mon, 05 Jun 2023 13:19:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996369; x=1688588369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=lRZfmLEHt5BGsHL2wDYj2+9bUOvf3/u2iHm8wiPgZqI=; b=kJ0Bkroo/DWziREa1n1noOetNp41O6Ox58UrIuhCJU4rx91T1V/BI8t2AqjfTSEcwV q0suTmJNw6CzrahEgC63C7mjCRqRALeAr3fAPGb3uUjy3x4GgrWdoH9+/wnz+Hn2edZO 6GSlAMsNnO26Gw0xtCDzTw9eZFylJXZ/tjJYOgvDUMARtMFKwUmcmaxkNB61D9KMmaN3 7/OTqJKFCT8cvovfeX3OjF9DftPq57Uvr9eNIDQ4LaEAnLP5nAW2mh/+VA9k1bNwj9+9 sAZ1i8vij/rS6eqJlCY+mqHPhSbiv+P+RoHliqr71a02RMwjVQj60v/dplGBSObEgB3h YgbQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996369; x=1688588369; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=lRZfmLEHt5BGsHL2wDYj2+9bUOvf3/u2iHm8wiPgZqI=; b=MoP2reL7z4R4Q6McIYhUv23f7D6KjULiAnXbVvsMCVSV4MoU+Jb+vSL3zsH2BLPAvC DkLxNG33u3E0gy43xDOrR5LM5a/TEb5wE8BHRyCtpelTP4iQM0G343pfOzHBsaNKg97s hPMQ//1WX5ub235w1fyyXpclrquMTZSmLT4WVaB7l412igh+36qHUclHryoUNqD+iFG9 r0RR3Vai9MIi/NMvJI87+bbCNKjdtqainjjB4N2YCbcEM0KaU7hoMrBM0y096zF+lDoB ZnBHB5qCxCH+QCsOfpXtaica2eDH2LBR2KnoaB6hwHn3YxfhLCKTF+lpVVusmKgOkUiI sCvQ== X-Gm-Message-State: AC+VfDx+i6L3RxYU60PbAHHZDIJeS5sht9vtQOWY28eE42GXDG19BpbN DcyIx0K9w1j1AeWoH7+HH/txY2ZovS0/ZcXFEEg= X-Received: by 2002:a05:6a20:7492:b0:10f:176d:6ae9 with SMTP id p18-20020a056a20749200b0010f176d6ae9mr195389pzd.1.1685996369177; Mon, 05 Jun 2023 13:19:29 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id w20-20020a170902c79400b001a980a23802sm7018184pla.111.2023.06.05.13.19.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:19:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 45/52] tcg: Move env defines out of NEED_CPU_H in helper-head.h Date: Mon, 5 Jun 2023 13:15:41 -0700 Message-Id: <20230605201548.1596865-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Since the change to CPUArchState, we have a common typedef that can always be used. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/helper-head.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index a355ef8ebe..28ceab0a46 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -22,6 +22,7 @@ #define dh_alias_f64 i64 #define dh_alias_ptr ptr #define dh_alias_cptr ptr +#define dh_alias_env ptr #define dh_alias_void void #define dh_alias_noreturn noreturn #define dh_alias(t) glue(dh_alias_, t) @@ -37,6 +38,7 @@ #define dh_ctype_f64 float64 #define dh_ctype_ptr void * #define dh_ctype_cptr const void * +#define dh_ctype_env CPUArchState * #define dh_ctype_void void #define dh_ctype_noreturn G_NORETURN void #define dh_ctype(t) dh_ctype_##t @@ -52,9 +54,6 @@ # endif # endif # define dh_ctype_tl target_ulong -# define dh_alias_env ptr -# define dh_ctype_env CPUArchState * -# define dh_typecode_env dh_typecode_ptr #endif /* We can't use glue() here because it falls foul of C preprocessor @@ -96,6 +95,7 @@ #define dh_typecode_f32 dh_typecode_i32 #define dh_typecode_f64 dh_typecode_i64 #define dh_typecode_cptr dh_typecode_ptr +#define dh_typecode_env dh_typecode_ptr #define dh_typecode(t) dh_typecode_##t #define dh_callflag_i32 0 From patchwork Mon Jun 5 20:15:42 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689263 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288453wru; Mon, 5 Jun 2023 13:26:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7DXvjNc9ICp/VQSqkApF7NppSTfv8WAc5ghA8yGQO5r7qBDa4X8P7bo0Fyjice1p5QSWEA X-Received: by 2002:a05:620a:8d0e:b0:75e:c30a:81b5 with SMTP id rb14-20020a05620a8d0e00b0075ec30a81b5mr741408qkn.9.1685996799040; Mon, 05 Jun 2023 13:26:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996799; cv=none; d=google.com; s=arc-20160816; b=MtYBlJgFBo4ixSdrE7H2sZ5Z899zALGKPN9gkee9MZfixuelhniKRRO/JwwLgTWOlH ybqXIRAXwrdZGP/KTFeda2Y9TUZJrxqctmQmh/ykge1qhy7Irxs4+ohLDFXJT7Ja7Syo KenUVP5IA5sNva4Ti+6OmkytYYjpTWPNy3pJxExiPS3+3TDlSo/w4eXJCE4Z9HNk+mOr HM0iv1k33IYYIQeA+hRZn0Iy59+ALcegCCDndl4IcQVchabMFr6CVpuZ5G1GUWuv1KgC oBNx+ryTaGI2xjQGx6tfYNA62ovTTKiTbelqdl9ZMa5AFiUrevqL4FHRkVWwpJC5SDat 6xaw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=06J6sEoIXDqd7QsL1obTrgiIStslrSK/3y4osdeVahY=; b=ZIjAyNg0l3aIk6ds+hQddt1oxFThBmTB5Wb7Tn7euy1fBRy7Ee+UKjW5knIUmi6poR 2slo6k+bogrzl6kcu3ZffajVcmFx4XVBcrAlSZA7vUACVOKB7FJFipj89yWgn2KU1NWe vhdbrEP7COr2g5mUhx1czkoGt1ZxMvxGcT0kTdzwSnD0coR7ucVNurQZINixh4QQUMxu qNgYUT5XjN3DuAuW+Lp4BNJjQhWW293YqjmkWvukvAnwcOsYbLDPZtz0DPByExwudIlM wQp/lIgedHRr5JXmPtqPgC2OeNvumXUbuQG0DZbj0J6j1TG38Tiig8bHmd6pFaHurRk1 GFdw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xd3xISj0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id d23-20020a05620a141700b0075d969ed4f0si656670qkj.691.2023.06.05.13.26.38 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:26:39 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=xd3xISj0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GgK-0007OS-4x; Mon, 05 Jun 2023 16:20:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gfv-0006uK-0d for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:35 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gfr-0005lS-7W for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:32 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1b04949e5baso46261595ad.0 for ; Mon, 05 Jun 2023 13:19:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996370; x=1688588370; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=06J6sEoIXDqd7QsL1obTrgiIStslrSK/3y4osdeVahY=; b=xd3xISj0aNwjMnyhWZ2hinG2d9Zal3hHG5huaK3v6lK0fBA+8TJUsknYKROGC6NKMZ XIUG5h0msNVdmyzXi0Zzm7vexME4ClJhZtGsH+ISUugvaTELDuaPKTV0aU0yY/VgdQK8 0MHgdq+/syoryxSOHIsTVlj/uGoIFtQ6HZESoUt6Vk+WBIGViloDcBEN/mEVfG5xUl+I YepyqWSGYHs1WM8KWdWVcnWrp2T7ZLmjPNKZwr/vav0ZOd1hDF+VYCNl1HWg7J7TIyLc scNaJFVlVS0bU85xps5DKNu9TDaRKAjsbroFNO5cZ0dEOxDjWbI8vVm94s+KzCFuFAa/ t6og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996370; x=1688588370; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=06J6sEoIXDqd7QsL1obTrgiIStslrSK/3y4osdeVahY=; b=BjtghECWPR5zqQ0ekuvb7ujC3BW0svInNOsWQi7GghEqhmOos0M0E/5nQGAcSjf83t dr6tHx8zuXfCpOT6LcET7VNSSg5/8/2v0fq1d9NtNWht78f5ZI3OGwqEzWtL/rbyN0xQ INioatBNUCuPERFbQxOgOQK/8ZU+0DVKrTdznJ/QBYcdW+KbfBXyVi3YwoNynWF30qJ9 2sWIEYicqGsEY7Aiu+PErNpBMM/i64+Ib60J2oiobI/5mmlx9OeT2Zm0SnaACRmrD3xE h16K3Qqoyv8yZZBfCtHJg5Qe4EOaoi0zqoDvabYt9anOxPANzQE5AH8e+IAifM+cvhX6 xnSw== X-Gm-Message-State: AC+VfDx1GGIHF87SAnjpDRB7wjGVW1U7gAFficZ5/8QBYDwx/0CXwm/R WQUqbD5V1l7zourKDnOwlQYMsWta9fw5m9ayuGc= X-Received: by 2002:a17:903:1208:b0:1ae:6135:a050 with SMTP id l8-20020a170903120800b001ae6135a050mr51703plh.19.1685996370028; Mon, 05 Jun 2023 13:19:30 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id w20-20020a170902c79400b001a980a23802sm7018184pla.111.2023.06.05.13.19.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:19:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 46/52] tcg: Remove target-specific headers from tcg.[ch] Date: Mon, 5 Jun 2023 13:15:42 -0700 Message-Id: <20230605201548.1596865-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This finally paves the way for tcg/ to be built once per mode. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg.h | 1 - accel/tcg/plugin-gen.c | 1 + tcg/region.c | 2 +- tcg/tcg-op.c | 2 +- tcg/tcg.c | 2 +- 5 files changed, 4 insertions(+), 4 deletions(-) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 635fa53fdb..a498f31967 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -25,7 +25,6 @@ #ifndef TCG_H #define TCG_H -#include "cpu.h" #include "exec/memop.h" #include "exec/memopidx.h" #include "qemu/bitops.h" diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 3e528f191d..5c13615112 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -43,6 +43,7 @@ * CPU's index into a TCG temp, since the first callback did it already. */ #include "qemu/osdep.h" +#include "cpu.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op.h" diff --git a/tcg/region.c b/tcg/region.c index f8410ba5db..2b28ed3556 100644 --- a/tcg/region.c +++ b/tcg/region.c @@ -30,8 +30,8 @@ #include "qemu/cacheinfo.h" #include "qemu/qtree.h" #include "qapi/error.h" -#include "exec/exec-all.h" #include "tcg/tcg.h" +#include "exec/translation-block.h" #include "tcg-internal.h" diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 8c1ad49c4e..c07de5d9f8 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -23,10 +23,10 @@ */ #include "qemu/osdep.h" -#include "exec/exec-all.h" #include "tcg/tcg.h" #include "tcg/tcg-temp-internal.h" #include "tcg/tcg-op-common.h" +#include "exec/translation-block.h" #include "exec/plugin-gen.h" #include "tcg-internal.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 41186f540f..3fcd0d9f32 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -34,7 +34,7 @@ #include "qemu/cacheflush.h" #include "qemu/cacheinfo.h" #include "qemu/timer.h" -#include "exec/exec-all.h" +#include "exec/translation-block.h" #include "exec/tlb-common.h" #include "tcg/tcg-op-common.h" From patchwork Mon Jun 5 20:15:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689251 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288164wru; Mon, 5 Jun 2023 13:25:49 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4pQ+BAK1VYFrrJeOPFLA7yxHxWSVKHuxWo7ocpO2DB/o6vo8rGUFg/O0QcM2C4YCqYa0YI X-Received: by 2002:a05:622a:134a:b0:3f9:ae23:5763 with SMTP id w10-20020a05622a134a00b003f9ae235763mr588432qtk.61.1685996749780; Mon, 05 Jun 2023 13:25:49 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996749; cv=none; d=google.com; s=arc-20160816; b=UDo2XlZ3jWdV8ynfElYDsurctJ6rVdAfI5W4iMi9qbP/b0DAOBAhWcHL+I6zh77Y6Q J5RaNX2Cva9MvRgnBZ46B90A4bkyh4aXZvgH0H6N58Tz7tnJ8ZP2SRN0ercb20WOpzXS 3S1jreuDOy8OHy0+9ksK4pifbO8XEOjokRVeyWa91dkjXa7UBpQD9yZVnQsNGCu9Gyl3 xnjrj8RqVxGts3gvjKmyZ3SFHRmMDGd6TtN9XpXWdJ+fXXxCAf1eTjQB1zJse0ESzE5j y4fef5sR22a37xl4Nh8zk+GV//yl5WZgd3Tc15TQViOmO2FW6sJipWw7jPnudXCXFF9S 4diA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=GIcDEqUeirfwvFOcbTVpqxhfnFcXIKTiky9PUX69mio=; b=KycJZOLuDEREOGCGsl/TgPNi61+LmUG0ERYyfxEl9gaJUwCyvroS2Zar2OJB2e9koG pJtDh8t2ntzsTLdg4jck80wg7TBsLH4gNDfuwRI/9vENUXx5nqkDZ7Li1jM21pGAErQu 5BxANY/ZT81gvSDFtLQhHMIwXqlmX9hMliKaYgGSa0YjrNqYoxhoq/JT+C/wV2VwW6n2 0W0uSIlSVmZ9qhXqrNLwUlylsztPAP7FkwSB8+p88kfkuSoojwYtCQEj2zmDaQivapYE QITPO36/ewxVTBeKWb45a5X34Y4PHbgsGEavUNGwmYOjK/l+gHK91pRBHha6fn0jvXeT t4eg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AjER9FBZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id 16-20020ac85710000000b003e4eb9adb9dsi5276865qtw.148.2023.06.05.13.25.49 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:25:49 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=AjER9FBZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GgI-0007Cs-7x; Mon, 05 Jun 2023 16:19:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gfw-0006v2-Qz for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:37 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gfs-0005ls-GA for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:34 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-652d1d3e040so2529715b3a.1 for ; Mon, 05 Jun 2023 13:19:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996371; x=1688588371; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GIcDEqUeirfwvFOcbTVpqxhfnFcXIKTiky9PUX69mio=; b=AjER9FBZQHjJvZCvKOsV/AcEDbenij+L47ht4Oqew48lCIJoRtfQtZinfzDUVNXpHB z4Dx1K+WBqplEylEMcaqh3k2kQiJHqS+23yoHpj8JPMFezfCLcK6MiCfa0HO56AHy31O jlSUrenAQmQtrR6zbr4/d4/CsWjMu4KIvPVG7xxfaAUU2z0oAVkKgqJhvp76d6tA9YCD I486fdSjpkFAInmYG+OYK4nRExb1f7acqdtFimYfu6DU35gq56ixclapldrcxnH3VV+6 y2qFHLhDLicMe4qzGY1TEb5IVF33CngKhv25CNMDpIG2Yex73u8jpbT8H+qEBbL42PXy jjOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996371; x=1688588371; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GIcDEqUeirfwvFOcbTVpqxhfnFcXIKTiky9PUX69mio=; b=fvz7NAMRltfP7Fs7jZriZMQV62jHlFMAHv4PdKo8vdTPIB1N5IJZNgaA7AN3udzyGB x3v/FYKAn00EPP8XcgIojsW9c7f3pUR9hh+b3byV/fLmVHWzvLdZ3K6DO3RWFBeecfJf dvSlczmxwpQKnPzVP03LAtASgsPlgjdLeLXim60+xrPzUthMW0v8Tl3MCeNtnyv+VnSg Z/sIwJ/ei8tMsUkT4NKP07BiRliXkWPZVA6REGeSrgLbdOipiaogv9D1OI0ayZuV+0sN 3VvT37Vg899VCkvKSMG+uRmXDV8HE2UY/JcczWjgDljJLSkJmSW5axjE342h0C9zLgL4 kqHw== X-Gm-Message-State: AC+VfDziIpTVrejUpKnDc3e4waJv1yloZnL2Woh9ji7SxTQK/Cul6Q4L K8BVTulfDPrJCQ2/oN9o4joEwnUXRyFgoI/NHfI= X-Received: by 2002:a05:6a20:94cb:b0:103:73a6:5cc1 with SMTP id ht11-20020a056a2094cb00b0010373a65cc1mr189656pzb.4.1685996370839; Mon, 05 Jun 2023 13:19:30 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id w20-20020a170902c79400b001a980a23802sm7018184pla.111.2023.06.05.13.19.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:19:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 47/52] plugins: Move plugin_insn_append to translator.c Date: Mon, 5 Jun 2023 13:15:43 -0700 Message-Id: <20230605201548.1596865-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org This function is only used in translator.c, and uses a target-specific typedef: abi_ptr. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/plugin-gen.h | 22 ---------------------- accel/tcg/translator.c | 21 +++++++++++++++++++++ 2 files changed, 21 insertions(+), 22 deletions(-) diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h index 3af0168e65..e9a976f815 100644 --- a/include/exec/plugin-gen.h +++ b/include/exec/plugin-gen.h @@ -29,25 +29,6 @@ void plugin_gen_insn_end(void); void plugin_gen_disable_mem_helpers(void); void plugin_gen_empty_mem_callback(TCGv_i64 addr, uint32_t info); -static inline void plugin_insn_append(abi_ptr pc, const void *from, size_t size) -{ - struct qemu_plugin_insn *insn = tcg_ctx->plugin_insn; - abi_ptr off; - - if (insn == NULL) { - return; - } - off = pc - insn->vaddr; - if (off < insn->data->len) { - g_byte_array_set_size(insn->data, off); - } else if (off > insn->data->len) { - /* we have an unexpected gap */ - g_assert_not_reached(); - } - - insn->data = g_byte_array_append(insn->data, from, size); -} - #else /* !CONFIG_PLUGIN */ static inline bool @@ -72,9 +53,6 @@ static inline void plugin_gen_disable_mem_helpers(void) static inline void plugin_gen_empty_mem_callback(TCGv_i64 addr, uint32_t info) { } -static inline void plugin_insn_append(abi_ptr pc, const void *from, size_t size) -{ } - #endif /* CONFIG_PLUGIN */ #endif /* QEMU_PLUGIN_GEN_H */ diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index fda4e7f637..918a455e73 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -285,6 +285,27 @@ static void *translator_access(CPUArchState *env, DisasContextBase *db, return host + (pc - base); } +static void plugin_insn_append(abi_ptr pc, const void *from, size_t size) +{ +#ifdef CONFIG_PLUGIN + struct qemu_plugin_insn *insn = tcg_ctx->plugin_insn; + abi_ptr off; + + if (insn == NULL) { + return; + } + off = pc - insn->vaddr; + if (off < insn->data->len) { + g_byte_array_set_size(insn->data, off); + } else if (off > insn->data->len) { + /* we have an unexpected gap */ + g_assert_not_reached(); + } + + insn->data = g_byte_array_append(insn->data, from, size); +#endif +} + uint8_t translator_ldub(CPUArchState *env, DisasContextBase *db, abi_ptr pc) { uint8_t ret; From patchwork Mon Jun 5 20:15:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689246 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2287631wru; Mon, 5 Jun 2023 13:24:12 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4xTJiTrhKjPHyByXpHUnW5eMNl1xU1HkSCWgc3VZxc6wNdEhCOG1jJsLgNpTEwoEJ0cN+d X-Received: by 2002:a1f:3f11:0:b0:462:f2ef:ef9e with SMTP id m17-20020a1f3f11000000b00462f2efef9emr2623688vka.11.1685996652506; Mon, 05 Jun 2023 13:24:12 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996652; cv=none; d=google.com; s=arc-20160816; b=osGTJiTMUaholQXJuoh3m8T2UgQZ6mD2A/X+axjGiZPQTloG2Vb5S+krs7h87oNsKR pflY7hobZXn4HDhKBFQvUx3Q/TPZirtqkJZ0ph6SDa4feXNgG+S/8+mfas33cR5mCJjv p5F1AEiXVpeTTtnSpOtCjM4fmdsZ3Z3E+uTpv67nSBymDG9A6SIgF72Cc+qtWcI9BRXh ZHX2mWP5QrR2AdpnGxwn7c2FEYBYtNr6zefQEU5XUadEK/eCy3yKDjRFf1rF3QPOT7fG JPDniCRd2dPxYMVhKnBnLt29Qaoj9nl6A/6vGlg0IeWCd9yoSefRaR/lSGzXJhMyohMG pRiQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=OkNu/07W1UabgEGL3O6iOC160FND+mo9VSEEjlVkKeY=; b=BAmmkCKRcCo+cSZ5oPZI9kAu+Tp8K2AUZ2fQ8BtDwpkp3/gbdLErCEoJKnROiLxRLK qPY16lpPuklAdLfdKui+1kN+yi5Lf9l+pGk5I3z9bVDI4TnO5CxFgGXTe879CqcP3WAs 4t9qKncJ1tiBu66NyRlU7Yd7g1cfFiwTcNO3h4I33H2Tc6aWihZGhEnmQ1NYnLNlubNb WA/UxrCLEyL3lvd9f8cSl7sAtX2/4wUhh1xKNlcfDUDq+Js6ewwXqAHQELwpr0/Qqmat 7KDWjLq81hi0lkWyccN/QFV9O5mIdEDSmW41wMFBTQjnUk+cldq4yDQA5BfaWnRBGs2y AZWg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XDGE2WGu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h7-20020ae9ec07000000b007456fcdeeedsi4788301qkg.672.2023.06.05.13.24.12 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:24:12 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=XDGE2WGu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GgP-0007qc-Nc; Mon, 05 Jun 2023 16:20:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gfx-0006vM-Kp for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:37 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gfs-0005mN-Pd for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:34 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-651ffcc1d3dso3032214b3a.3 for ; Mon, 05 Jun 2023 13:19:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996371; x=1688588371; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OkNu/07W1UabgEGL3O6iOC160FND+mo9VSEEjlVkKeY=; b=XDGE2WGu8l+ug47KQuZTMl/7P5Dn6IsEa5jHBxLwrX7ceKA7ax4dUvW4U9tHzcBPC+ 4Lkc2CgFn3Udxc9Jxnrb4OrnNOz4fs5QwRpplXh2LzbTQkOv+pRs3GtFy9goIfrTWI3p eOvIHofw0z0+fc+RQDrUQIYVOXViq5kDZf+zsjvSpAc2skqBf6NnWLKIpzQ3eGpCIMxw IeKI5ZPQ0o6zYkTvQA9m85YLm9Lo/m+DHksqDGh0i01wQlSNZr+nCGpEsvmGLmo9F2++ IwQ9oT72fs9pDHLfBiomyMwP4ZnjuaBfcVAL7wxp7lvf/wpR8u1LL8EEfdByN4X9ssr7 DNZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996371; x=1688588371; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OkNu/07W1UabgEGL3O6iOC160FND+mo9VSEEjlVkKeY=; b=ML96MxCFsuEoV8VFlfpI4q0POOea7heOXfnwXD3rpMFKRP4qXoEDQfr3ZR2UdGSQQ+ LCuGnvPiGjtsNx+6F4+QQqPIaP2jJ5U2iTx97a8H6FLm1M6xPXIPbFYaB9kN9pj2oPnR eEJ/j85E2sc7uTApK58OljQpQ/zDtCH69y+f6E2t35ae/k0PophNWUW09haO6WvWOO+N aKMA0sBQ+QdQzETBWQrKxdkpJ+TxEzIJ2VpHBrBjB72hvQkhj+Eg6qpiVClQVa4bmd3p guu548J5hh66MIiDQ1M7W6LLS0ppAoIg7jD9NCm5T8xBBEF3A+AGuZchH+XGw0E1PocH bttw== X-Gm-Message-State: AC+VfDwHDWJSFOHLttWdVDWQrzGTEcPqRtPtigWlQtBVzSIKFCdEX+zn Tk2Yc0ttjb0OjRobgSbITv2uf7LrTDCAj33jThc= X-Received: by 2002:a05:6a21:789c:b0:10f:1e5d:9045 with SMTP id bf28-20020a056a21789c00b0010f1e5d9045mr95764pzc.45.1685996371550; Mon, 05 Jun 2023 13:19:31 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id w20-20020a170902c79400b001a980a23802sm7018184pla.111.2023.06.05.13.19.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:19:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 48/52] plugins: Drop unused headers from exec/plugin-gen.h Date: Mon, 5 Jun 2023 13:15:44 -0700 Message-Id: <20230605201548.1596865-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Two headers are not required for the rest of the contents of plugin-gen.h. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/plugin-gen.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/include/exec/plugin-gen.h b/include/exec/plugin-gen.h index e9a976f815..52828781bc 100644 --- a/include/exec/plugin-gen.h +++ b/include/exec/plugin-gen.h @@ -12,8 +12,6 @@ #ifndef QEMU_PLUGIN_GEN_H #define QEMU_PLUGIN_GEN_H -#include "exec/cpu_ldst.h" -#include "qemu/plugin.h" #include "tcg/tcg.h" struct DisasContextBase; From patchwork Mon Jun 5 20:15:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689241 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2287297wru; Mon, 5 Jun 2023 13:23:10 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4YRTTPkZcPzyNcPvqtCwe+8oD0+HXKf4bFSe4XX2EineHTeLWAB8fwMb4+7sYdmLkVb2GY X-Received: by 2002:a37:688a:0:b0:75e:c92d:38d4 with SMTP id d132-20020a37688a000000b0075ec92d38d4mr402358qkc.4.1685996590601; Mon, 05 Jun 2023 13:23:10 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996590; cv=none; d=google.com; s=arc-20160816; b=ekA9ejbGoO8/CJ3VngXpKQdbUl4EBztjwV8OqhZIkawAZQm8e9xE3cW+hK1J0joWym jhsWRDrVIbgwCCMByhWPaTVizip1zf4u8TKozvbW5LshRp9qgqIuhJi1h175CsbFvwL3 X0h2ZluxM6UbNSMyv89nuQ7N1ZeQzfHcgiJikTYfB+GbASrxLhgelEGYqkrsn1kAv/ws 6Sb3uOg0Oendsy4/DlQ7UuqrJjjPNRvWUDRp7Lc77mpBDXk4digUCyIcrx+EGR0Ngsuo rXnrv3uc8kDLXfelno4TxYPcG6Fv+8027aOpQkDV6742+rjGnGPTj06eC3Vt8HmG2JoX q9pA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=yv/XPqbhv8nUeXb0hXO9bS/8b9QGtoWBmeHgg0dWk2g=; b=yFtCa20dCxzOsRrpnVf4u44Pb5EOcyLIdvc1Tgh3SCIksaRVjrgbJa8uUnp+//GKDp D/xK6IuKOH6CR/qeCKT+IY9k08i+fly4U/nAC4BGlu5xzzUMUm9lIB/YJigUFPLZLVrp yJQ2WEfMUC9uHWX98Q2Sqls/X5xz6LWS+l2qllkXhiL9AkE60jvyeBFxey8lEOZlWDS2 79WA3Gp79shW3yVChe61TPFM8pG7Qz9RVxv6XFxqs692gwiifyUEG97hGCbum0UVe4ft xv+z6LBE1K7ivXF0D5qeevbsrxwnmOBn6V554sq5T2MOfnLFqTZDIcVaRGGwjj3xTbBF 8XHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mceq8faz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id g6-20020a37e206000000b0075cb4e1e38bsi5010437qki.446.2023.06.05.13.23.10 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:23:10 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=mceq8faz; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GgP-0007z6-EW; Mon, 05 Jun 2023 16:20:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gfx-0006ve-Sn for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:38 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gfu-0005mt-5Y for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:35 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-1b00ffb4186so30783255ad.0 for ; Mon, 05 Jun 2023 13:19:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996372; x=1688588372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yv/XPqbhv8nUeXb0hXO9bS/8b9QGtoWBmeHgg0dWk2g=; b=mceq8fazmj1BbFrJ9pyZSLyj+m8ta2LquCTzxzegQM2tTy3e+VvWiT1Qe6qI/6NCRq fbarwypNWfz30nYWIIu3y9O9XLEh4C5FDGoIbZHN6S+erzZiE/AM1/UTP8oySF+n05q2 9L3jSgkJfvMYGD2w8yzQlR9siflu+O0J9P7EsdzkSgXkI1KVrOJpawhA+XPZIJ9OPLIr v2+9tmz0k+jGLc0lgYjKgGoNjGZnXizPbXqOLmjjjBYatCiX1RsV1fAo67LsTtHp6AM8 qbhBVSoc6c+CABjxhWtXngo11Qokpq3EmuZD61y42n9JXdIkcDF09MSqYbGZXEKncFc7 fi4Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996372; x=1688588372; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yv/XPqbhv8nUeXb0hXO9bS/8b9QGtoWBmeHgg0dWk2g=; b=ZxrxpTQYsrOQsjntgFN3wAK73oX7r6ouoZ+3mhVnKKLiRPRySZ4m3GDCQK+6im1iC4 pR0ovC1jF4Pm30e8Ui8b45tJYcCfbRPnuumLt8wT1r11MxoNgFP9I51LGWexdV2ZZ0p5 LpVBeA3bKSRUOFSkyeTWwJK3ACIGa0ZgmxGZUxNvMq4lXePpNdcPfXrfaf4eriMdbOnv f0yFrrUhD57ybJqxjcstTd2Mim7Lh+Ejg5v5C85OZNutCXnZQOQAfX3n9YXYlrjXSyW0 blkzMfffbr6qVHHIa4wi5zYw1M0t5gJwn8QOqfxVx7d0EPYm7abaQrTqwmKEJB0T+ZQn AtZw== X-Gm-Message-State: AC+VfDyiPtp2WqVOeeJ3lqI5ECw9/qKveVhXjJ7GL65V3ZmLgzgKJVG0 n94ZgpIPu40lSgwnGF73FNJqx7CYMHbWC+7/Sxk= X-Received: by 2002:a17:902:f802:b0:1b1:8900:5211 with SMTP id ix2-20020a170902f80200b001b189005211mr42519plb.28.1685996372260; Mon, 05 Jun 2023 13:19:32 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id w20-20020a170902c79400b001a980a23802sm7018184pla.111.2023.06.05.13.19.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:19:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 49/52] exec/poison: Do not poison CONFIG_SOFTMMU Date: Mon, 5 Jun 2023 13:15:45 -0700 Message-Id: <20230605201548.1596865-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org If CONFIG_USER_ONLY is ok generically, so is CONFIG_SOFTMMU, because they are exactly opposite. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/exec/poison.h | 1 - scripts/make-config-poison.sh | 5 +++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/exec/poison.h b/include/exec/poison.h index 256736e11a..e94ee8dfef 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -85,7 +85,6 @@ #pragma GCC poison CONFIG_HVF #pragma GCC poison CONFIG_LINUX_USER #pragma GCC poison CONFIG_KVM -#pragma GCC poison CONFIG_SOFTMMU #pragma GCC poison CONFIG_WHPX #pragma GCC poison CONFIG_XEN diff --git a/scripts/make-config-poison.sh b/scripts/make-config-poison.sh index 1892854261..2b36907e23 100755 --- a/scripts/make-config-poison.sh +++ b/scripts/make-config-poison.sh @@ -4,11 +4,12 @@ if test $# = 0; then exit 0 fi -# Create list of config switches that should be poisoned in common code... -# but filter out CONFIG_TCG and CONFIG_USER_ONLY which are special. +# Create list of config switches that should be poisoned in common code, +# but filter out several which are handled manually. exec sed -n \ -e' /CONFIG_TCG/d' \ -e '/CONFIG_USER_ONLY/d' \ + -e '/CONFIG_SOFTMMU/d' \ -e '/^#define / {' \ -e 's///' \ -e 's/ .*//' \ From patchwork Mon Jun 5 20:15:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689264 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288463wru; Mon, 5 Jun 2023 13:26:40 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4dW0CW+FwAsn5tDCESXwcNpPWVbjBObOCGcMRs/AB2lBGMtzcvfbJNH/gP9QkBRg3S5/OM X-Received: by 2002:a05:620a:19a1:b0:75d:517a:5b72 with SMTP id bm33-20020a05620a19a100b0075d517a5b72mr994748qkb.28.1685996800235; Mon, 05 Jun 2023 13:26:40 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996800; cv=none; d=google.com; s=arc-20160816; b=SHnLn8Zb3wTXtAzqKOFxvOTpQp/RKwUsL7gwYvgXPB7JuQM28On7Lnw3FgfxjifeVI pF9uV38NGFuzkir8cwKpQIcsRnKJjD+Agvjz3Fa8oqhKFcCTdNLnrIHZ05ObQYyzxmjV GyJ+dE1v8igkeVT70L/abmO9s+QsCF+7Le99D7C+ql+dEatEzw7Q1CPbQkGf+l/u3ua9 14g3Dcw3S/n4Sf8S5Kq/FWd6/Nhm0Lb0LSAM+tHso10/ZIqVlHKLC78m2oGPFw59yece 2owjKd8hWe6FhBfFopDFiWvpcDDXzA3eJpZdjBdByNOrgOjnwQyzPPOvr4LRMcucFmeQ 0Lxg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cVUkf4/bpXGdLPrfKhU6xJtb3KDITtWli9I9WGefa/0=; b=uu77xauF8J37fzX+QGDKeEqtJfhlzpBTkPwk98dDYdmw0CPp96O7o8sgU2OkBz+iua zNQct0VWAkJoTTs1Ph1Zz348BXeKALIB8ZHwQcek8wN9PAiH8+7ncliHs/KpLY+VRUF/ hdMwiFDraSGxQvOwFT5Pi2sfurzbn4omV3KeaGhhvvGUXm77scaNFPxqjTG8CVcIRQ0c 8nEa94oNrpynxC+2jZ/68nwM6iAFtNsZ923dWRxyVYW5IRunXLw4I9mJn2AGBq+CwmaX SvIb5VYhEs1Bv3euli1G9aa4RlX+zMhXgd/ijT6X6pAf8uP2vfImFQ15Qgdd5zUneVfs IIFA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N9mDjfNs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id h19-20020a37de13000000b0075b2f6649f6si4956654qkj.741.2023.06.05.13.26.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:26:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=N9mDjfNs; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GgK-0007QH-Qf; Mon, 05 Jun 2023 16:20:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gg9-00071c-3k for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:49 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gfv-0005nK-GH for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:47 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1b04949e4e9so25177415ad.3 for ; Mon, 05 Jun 2023 13:19:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996373; x=1688588373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cVUkf4/bpXGdLPrfKhU6xJtb3KDITtWli9I9WGefa/0=; b=N9mDjfNsXWSz4Boafb8M0ae/2t8lbhJzNqZtX6YI6nLAyEn1Bje9SCP0a3PPdrLIim DY6JfcQY4JB1dtXxRjLOJ2252SoXP6oy3b5uDG+SexHv14iHFOoDddTI0kYSnyzq1sOV qWOZ68NEEj2UqfTlSeIWi/dEi8tKOYax//bBSey3gqI+hpMS2OKNNOmYv4vaYTmRCK12 3VdcBVwCSx/iu5X0s3w5ZLI/qIEulKpyrm6/SLk2REMUflAbbiQA6Qoa8f/WSFETYMRX S8z0M7qo1ii0fVtKGyqMnVHNO9pAxcSQw/u079EOpu+hG2yc3abLPiVFu9jYSsr20bQs 4Vbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996373; x=1688588373; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cVUkf4/bpXGdLPrfKhU6xJtb3KDITtWli9I9WGefa/0=; b=W+BbEoYPeHDR0hunmcTlZlsaEzSNJ4NJWtaoIG1+rf23Cke0cUnDDR/lgtv2d6no35 MMbcoXKfK7YmoIVSHO0JzwI2vM0psqWjTKXpujpyQi46fm5ddbcvsVHLZL1W/Q+8Gx36 cQyBLkYCvAKdytxUAytfDNYNxmiohdmAuS2U3znrW33sFWh3e5n18opoC5R1Dtz4oZI0 c2UroJfkYBG3gIuk/z6+s4Ga1hyL6Q5I+qb+0fvMMLdwhxTqXbLB8EjIpK3IdKEtwac7 4eo2mYzwUfGTVumE/6qgiys1kDvDYqxTCMHNB4UsVeH5FYZe4w5lmrMPVbJo72EJ9g78 3BuQ== X-Gm-Message-State: AC+VfDys84I6Axrg+FDRMOso6TR4a0Fo/NoKIRwgADBWZrJcF+Yzf9ck jQlM+3tZ8r7KJzxrtKjKzwD5Bzl4U4KcS1NEQEY= X-Received: by 2002:a17:903:2602:b0:1af:b049:b32e with SMTP id jd2-20020a170903260200b001afb049b32emr3550862plb.56.1685996373090; Mon, 05 Jun 2023 13:19:33 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id w20-20020a170902c79400b001a980a23802sm7018184pla.111.2023.06.05.13.19.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:19:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 50/52] tcg: Build once for system and once for user-only Date: Mon, 5 Jun 2023 13:15:46 -0700 Message-Id: <20230605201548.1596865-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Create two static libraries for use by each execution mode. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/meson.build | 30 +++++++++++++++++++++++++++--- 1 file changed, 27 insertions(+), 3 deletions(-) diff --git a/tcg/meson.build b/tcg/meson.build index bdc185a485..565c60bc96 100644 --- a/tcg/meson.build +++ b/tcg/meson.build @@ -1,3 +1,7 @@ +if not get_option('tcg').allowed() + subdir_done() +endif + tcg_ss = ss.source_set() tcg_ss.add(files( @@ -14,8 +18,28 @@ tcg_ss.add(files( if get_option('tcg_interpreter') libffi = dependency('libffi', version: '>=3.0', required: true, method: 'pkg-config') - specific_ss.add(libffi) - specific_ss.add(files('tci.c')) + tcg_ss.add(libffi) + tcg_ss.add(files('tci.c')) endif -specific_ss.add_all(when: 'CONFIG_TCG', if_true: tcg_ss) +tcg_ss = tcg_ss.apply(config_host, strict: false) + +libtcg_user = static_library('tcg_user', + tcg_ss.sources() + genh, + name_suffix: 'fa', + c_args: '-DCONFIG_USER_ONLY', + build_by_default: have_user) + +tcg_user = declare_dependency(link_with: libtcg_user, + dependencies: tcg_ss.dependencies()) +user_ss.add(tcg_user) + +libtcg_softmmu = static_library('tcg_softmmu', + tcg_ss.sources() + genh, + name_suffix: 'fa', + c_args: '-DCONFIG_SOFTMMU', + build_by_default: have_system) + +tcg_softmmu = declare_dependency(link_with: libtcg_softmmu, + dependencies: tcg_ss.dependencies()) +softmmu_ss.add(tcg_softmmu) From patchwork Mon Jun 5 20:15:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689234 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2286442wru; Mon, 5 Jun 2023 13:20:28 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4e6iNi9PFxirR92Hgq+cC5qRT2/s0WFi0gmNEQgvmAWHfHTkWgZK+E13JJeXRDiuGHjoYZ X-Received: by 2002:a05:622a:1741:b0:3f9:a8af:88b2 with SMTP id l1-20020a05622a174100b003f9a8af88b2mr2807245qtk.25.1685996428194; Mon, 05 Jun 2023 13:20:28 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996428; cv=none; d=google.com; s=arc-20160816; b=wHfiGpC0+nVp6eSKeFv40huE69maKJsbIOMyjx0HoMmlvnMNtvpAnO8LiYsn1yGAKT llkCutoSFXksaTQDL4sS12yGTwHadfKSciaf4y23w9nBuKvGRYfBd5xsv8/FDWbIwxFU lwCTyGDyf+Ujgp/y1uKU98k+aLrIOAnG4YpMAUBnVzPEoOREiPupQcA25S1CrpPhwCDm 5GVaSbcXfd1MPideQIbyku9Y0jMLXuWIH56g85rRXtRXrnOkxKJ9+/i+FWjXb/sKCSaR Uq4j5BgfP8hJN331Oet730+nL+eVADgfkPCvvgBC+xmWy2CaTcQuevwTV2hpD7e+ZLtk hK3Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=NES3rUjYxvsEhP1PSaVSBmUCbjMXZRddYq+Gk3VmTrM=; b=w+qTJ76cMvXgvwYHY6bCYG+oEBHSJ10AEXoJyxmk2ZMnzRdYLlYcEjEvcWbCOCJ6V4 ZrJaXhz3jnF/IV2Mp+gaN6YJuIvdHCi/JQdZ9qkkhjN6TDVw3X5kLsFpMNIp9n7+aAiF UPYVEjzBxnscaChEoMjbPKc63y2aaOb+pV99E6NbqZ/J6dugM0W7Q25F2MuI2lkk33yT Fg4D4kCOMJcqvFkGaiZruYmpyE+cPEaDLNdDvjHID8J6f6osyqqIJz87hbgBfSsFEUY3 58TmuTEVrmfafPjArbBMIR2O3YlN7EUuRiIGOMHV/kivvxQJj8/WCFU7S0O33GVSroQ5 0t8A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tBSPMizc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id w4-20020ac857c4000000b003f6aa9086b7si5145553qta.790.2023.06.05.13.20.28 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:20:28 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=tBSPMizc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GgP-0007rf-Qb; Mon, 05 Jun 2023 16:20:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gg1-0006xc-T8 for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:43 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gfw-0005no-BB for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:39 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1b025d26f4fso46226905ad.1 for ; Mon, 05 Jun 2023 13:19:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996374; x=1688588374; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NES3rUjYxvsEhP1PSaVSBmUCbjMXZRddYq+Gk3VmTrM=; b=tBSPMizcoq94Za5n3BEBJ4e+DEKdf7hNtEWfA2/Jv7ln7/L1EuMd8XxjZgHId5JsF+ nVSlIqwYqgpSubvFtiBSSouiw7e1QyR87y2GSuZgYlt1kjLmI8nnQE76aHCO6V9os+dV p1P8XBEhUIot8qsEjH63vWSgbNpVopBntWw2aWMe3zRQoXfDW1Mr1HtCXhrskW0aXDOz 3P2o7UPM+OGq4mbeDGYC4pXDlm6ibm3YEigj3PkbkUcf6gVzXkq57dZ9HXkKQQiKViIf oolcrt27O+j4ed0hhanVdywOBNpIAX05l8DiTWnXXZ7ifxY2tsPPbG676izbfd4c7clo IOSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996374; x=1688588374; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NES3rUjYxvsEhP1PSaVSBmUCbjMXZRddYq+Gk3VmTrM=; b=KgdxHVz07VqkZgZp4aAyrJXRI0/jSJzB6mIXdIjlZBCX3txJ8yWc3eJhcCx9jaz37X q5uqeQQh2tqhpekHwFfbaWaruhJ/GdOkI1ee2UmIKu/SoJZc8juh4CdPZb8zX2AK+mZZ 5agJiFLrpNl9q2e62nSAYCEaO8Y/WzHBXx15ex9oaAjg6Cd64yHs27N34uCo8zeWOpCN pViCpy4h2XY9BjZfqgmWDdAj9Rz6uE3anrIYDfFjPrv5eZTl8FuF9TNlLHnUEbrLPuqN fET/JW7kgpdGzL0o+mG0eMWFLD57vvoZMXvjziMlqDypmwzUTaw9A3cDjiEKt1huzQ9Z qOwQ== X-Gm-Message-State: AC+VfDz8KC2WnJuYwKYvH3uXqS5pmojTIOaEyuXPz/945UuhW4SVr3II /uOxte1D4hfJBzBin0z7Y6rDlv2MD09JVvtD//0= X-Received: by 2002:a17:902:f68a:b0:1a6:71b1:a0b9 with SMTP id l10-20020a170902f68a00b001a671b1a0b9mr11621569plg.47.1685996373913; Mon, 05 Jun 2023 13:19:33 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id w20-20020a170902c79400b001a980a23802sm7018184pla.111.2023.06.05.13.19.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:19:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: Ilya Leoshkevich Subject: [PULL 51/52] accel/tcg: Unmap perf_marker Date: Mon, 5 Jun 2023 13:15:47 -0700 Message-Id: <20230605201548.1596865-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Ilya Leoshkevich Coverity complains that perf_marker is never unmapped. Fix by unmapping it in perf_exit(). Fixes: Coverity CID 1507929 Fixes: 5584e2dbe8c9 ("tcg: add perfmap and jitdump") Signed-off-by: Ilya Leoshkevich Message-Id: <20230605114134.1169974-1-iii@linux.ibm.com> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- accel/tcg/perf.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/accel/tcg/perf.c b/accel/tcg/perf.c index f5a1eda39f..cd1aa99a7e 100644 --- a/accel/tcg/perf.c +++ b/accel/tcg/perf.c @@ -111,6 +111,8 @@ static void write_perfmap_entry(const void *start, size_t insn, } static FILE *jitdump; +static size_t perf_marker_size; +static void *perf_marker = MAP_FAILED; #define JITHEADER_MAGIC 0x4A695444 #define JITHEADER_VERSION 1 @@ -190,7 +192,6 @@ void perf_enable_jitdump(void) { struct jitheader header; char jitdump_file[32]; - void *perf_marker; if (!use_rt_clock) { warn_report("CLOCK_MONOTONIC is not available, proceeding without jitdump"); @@ -210,7 +211,8 @@ void perf_enable_jitdump(void) * PERF_RECORD_MMAP or PERF_RECORD_MMAP2 event is of the form jit-%d.dump * and will process it as a jitdump file. */ - perf_marker = mmap(NULL, qemu_real_host_page_size(), PROT_READ | PROT_EXEC, + perf_marker_size = qemu_real_host_page_size(); + perf_marker = mmap(NULL, perf_marker_size, PROT_READ | PROT_EXEC, MAP_PRIVATE, fileno(jitdump), 0); if (perf_marker == MAP_FAILED) { warn_report("Could not map %s: %s, proceeding without jitdump", @@ -372,6 +374,11 @@ void perf_exit(void) perfmap = NULL; } + if (perf_marker != MAP_FAILED) { + munmap(perf_marker, perf_marker_size); + perf_marker = MAP_FAILED; + } + if (jitdump) { fclose(jitdump); jitdump = NULL; From patchwork Mon Jun 5 20:15:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 689253 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp2288255wru; Mon, 5 Jun 2023 13:26:05 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7mHufZ6Yrg4vUEGEY5kYNUlQ/eY4s297lR6/Mq6TzaV4rCzy8IvoRL0E6Hs/mDurPNuG1i X-Received: by 2002:a05:620a:56b:b0:75b:23a1:422 with SMTP id p11-20020a05620a056b00b0075b23a10422mr659301qkp.56.1685996765233; Mon, 05 Jun 2023 13:26:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685996765; cv=none; d=google.com; s=arc-20160816; b=MxqUE2KPmQ5p0/0Y7NmzvtTNN3BA1V6AboGpXvgYxbfddojGCVxvSBciwYBSyy1Vh+ VgNvlx111tkP/qnZIuWf3GB6oxDcpyl8oA0vCA6CCbbXuuKw0XStuQ8lEIXj3m1sXiO4 uZ8Rs/ZJrHvhaueMwCTOHHtPoWmgZGJoeP0uc8b+WuUhouWDYMTqK7lGxe0Clfvu+Iji tdgYh74cWRcRaohTgoMirHN3OdxkSDCFie3x1AhA5StSQK+lIjF7/FhBD5py7E53r3M9 BgSyreVxkftR7jkarITFQZTFu3TnYC/1hcQ9ooD0cxzvB42wnB0/G/5Ols33H04jj+4H WDPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=jsyqPtMTdNEpZg829naXwd7rY7o+p0Sx3i4U/bLMgWk=; b=RaCEqxQXkrG0GhHA1yX8OX24J9xdVvONhQQAga2ckB7+9NCfDtzIBLhdwGL7WLHSiS gB/Bxc8k2mxgBoTf5mtL+dWRtMzDhAfJYTFdalz8g/UzyYJ8a0tTgHP5AkgiYMzV3AgT Q3spQLDYGVwximSb7vgVdpErVZJ7m1m2U6TScVaqbIFW7gEuwMnTm28xKv1GZd8Hvc0G vszfOSXu+As5m8ICSDxAZFC6G6e89yOOA+ICcrFa3/WHt/lHAVgDp6V5tQjzZWzXHBuY lefCs05u3FigeM07gyLok36YJ40xhMr6+wK/GF+VNrfVO8sW2QNwOyZGK4DeyOFvxwNu 8fHw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nh5RFXsa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id s5-20020a05620a030500b0075b1827e151si4896139qkm.407.2023.06.05.13.26.05 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 05 Jun 2023 13:26:05 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=nh5RFXsa; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q6GgK-0007PD-F3; Mon, 05 Jun 2023 16:20:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q6Gg0-0006wb-Cb for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:43 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q6Gfw-0005o1-5f for qemu-devel@nongnu.org; Mon, 05 Jun 2023 16:19:37 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-1b025d26f4fso46227405ad.1 for ; Mon, 05 Jun 2023 13:19:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685996374; x=1688588374; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=jsyqPtMTdNEpZg829naXwd7rY7o+p0Sx3i4U/bLMgWk=; b=nh5RFXsavrU6NmJJ2DwwXqTNGTBxPhKQYo62dTXzowNoZVPmC5VN3/Lqt8jqRCSYzh 0brcakA4UJinYLLROcnXEC0L1U36XjvMekckHJA8a2CaXSwboeHLoRe5uZkzZa5fu/l/ RcwKlbR6tqIXUyWXyVRLRHiJ0z211UTGAvON5qwjdVWEbnp0VEDtsGyktkxwS66NWQX1 SKNujPGi7vSfki1t550gygnfMT8Bx0whfTKJKxXyIJ7q91u4lmGeVOG7r/O2qTUNMcY/ wrFe4kWyTtmBVoZ5jwWVl4JDWDgOiQYj6QoCxQaAqChtnQEDy7RuAlSuiaLbDnfc/JKm Z1Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685996374; x=1688588374; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=jsyqPtMTdNEpZg829naXwd7rY7o+p0Sx3i4U/bLMgWk=; b=UvOO/f1EiPw9w1MENvFOyQ3X2ssBBbZSnU7yKZnldT9E3Rg/O2kNtPWKjJNppZkKQe Y88LNeCBuVmIJDQWHne2Ks14McwxA6LElBpJRHaiJbZyKdCiwMhP1ihZUhdS5Nj6WGjj SO54SY5dGGoojFruqBMjUmyJX5KKZtCb35DpQfdl4oMhXGatko2z+sMzygVSOIs2hEE2 Sa7G24K+jIauiwd0b9Sx8qGto9wfUpU+yQhU76Utxq4SaCy+ANlMEC+4Ar90GGOfaNbM ljnyVwGD4GeuCE1FsEQDZIbvT7JRGURe6b9lcxAtP/Wgl3Xat/Fd1g904INkrsborBDF 8tkA== X-Gm-Message-State: AC+VfDzOnmQX/ydbgWZJ2ySMbnLBVlPLBc+hNc/7SjjweGMMJRPVf6PU +x7SVTqebsLMgx5W+3vWgF6JkFSbXV/OBIe1S6I= X-Received: by 2002:a17:903:489:b0:1b0:25ab:a9eb with SMTP id jj9-20020a170903048900b001b025aba9ebmr65190plb.8.1685996374641; Mon, 05 Jun 2023 13:19:34 -0700 (PDT) Received: from stoup.. ([2602:ae:1598:4c01:3f85:a600:6a3e:e465]) by smtp.gmail.com with ESMTPSA id w20-20020a170902c79400b001a980a23802sm7018184pla.111.2023.06.05.13.19.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 05 Jun 2023 13:19:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Subject: [PULL 52/52] tcg/tcg-op-vec: Remove left over _link_error() definitions Date: Mon, 5 Jun 2023 13:15:48 -0700 Message-Id: <20230605201548.1596865-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230605201548.1596865-1-richard.henderson@linaro.org> References: <20230605201548.1596865-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Philippe Mathieu-Daudé In commit d56fea79f9 ("tcg: Move TCG_{LOW,HIGH} to tcg-internal.h") we replaced the "_link_error" definitions with modern QEMU_ERROR() attribute markup. We covered tcg-op.c but forgot to completely clean tcg-op-vec.c. Do it now. Signed-off-by: Philippe Mathieu-Daudé Message-Id: <20230605175647.88395-3-philmd@linaro.org> Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson --- tcg/tcg-op-vec.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index 35d67eeda0..64bc8a2156 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -24,17 +24,6 @@ #include "tcg/tcg-mo.h" #include "tcg-internal.h" - -/* Reduce the number of ifdefs below. This assumes that all uses of - TCGV_HIGH and TCGV_LOW are properly protected by a conditional that - the compiler can eliminate. */ -#if TCG_TARGET_REG_BITS == 64 -extern TCGv_i32 TCGV_LOW_link_error(TCGv_i64); -extern TCGv_i32 TCGV_HIGH_link_error(TCGv_i64); -#define TCGV_LOW TCGV_LOW_link_error -#define TCGV_HIGH TCGV_HIGH_link_error -#endif - /* * Vector optional opcode tracking. * Except for the basic logical operations (and, or, xor), and