From patchwork Fri Jun 2 21:49:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 688356 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9858EC7EE2D for ; Fri, 2 Jun 2023 21:50:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236734AbjFBVuD (ORCPT ); Fri, 2 Jun 2023 17:50:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48060 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236599AbjFBVt6 (ORCPT ); Fri, 2 Jun 2023 17:49:58 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 75DD41BB; Fri, 2 Jun 2023 14:49:57 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 352LndFO066071; Fri, 2 Jun 2023 16:49:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685742579; bh=LYknLycg/NlRXtea6zAhNjjVX0g50LoiliRcbXrGvUU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=f2+kQ5SSkX3kYl1TadOzrWt+/O2CMhcGea5V2AFNoqsutNfG5KIusSHecZKSsFTju RFXsZ7BuNXqFbs8AFp+BF7TnpNkRfR5zFfm+b3ohadXHS8c3UxuoHvKivLiTB6VFz5 8FLr620qTjzv5e/ZNDFZdIhYpsd8ZAa7UY4ojTsE= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 352LndjB059491 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 Jun 2023 16:49:39 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 2 Jun 2023 16:49:38 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 2 Jun 2023 16:49:38 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 352LncGs080640; Fri, 2 Jun 2023 16:49:38 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Nitin Yadav , Neha Malcom Francis , Sinthu Raja , Thejasvi Konduru , Dasnavis Sabiya Subject: [PATCH 1/8] arm64: dts: ti: k3-j784s4-evm: Fix main_i2c0 alias Date: Fri, 2 Jun 2023 16:49:30 -0500 Message-ID: <20230602214937.2349545-2-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230602214937.2349545-1-nm@ti.com> References: <20230602214937.2349545-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org main_i2c0 is aliased as i2c0 which creates a problem for u-boot R5 SPL attempting to reuse the same definition in the common board detection logic as it looks for the first i2c instance as the bus on which to detect the eeprom to understand the board variant involved. Switch main_i2c0 to i2c3 alias allowing us to introduce wkup_i2c0 and potentially space for mcu_i2c instances in the gap for follow on patches. Fixes: e20a06aca5c9 ("arm64: dts: ti: Add support for J784S4 EVM board") Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 490d0b8624f3..34e9bc89ac66 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -23,7 +23,7 @@ aliases { serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; - i2c0 = &main_i2c0; + i2c3 = &main_i2c0; }; memory@80000000 { From patchwork Fri Jun 2 21:49:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 688844 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 725DFC7EE29 for ; Fri, 2 Jun 2023 21:50:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236663AbjFBVt7 (ORCPT ); Fri, 2 Jun 2023 17:49:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236621AbjFBVtv (ORCPT ); Fri, 2 Jun 2023 17:49:51 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1BED41BB; Fri, 2 Jun 2023 14:49:49 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 352Lndr9072489; Fri, 2 Jun 2023 16:49:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685742579; bh=jI+nDGX8lCYqPRP99t/hL8phcW6w/q6DhsT4zyCBtC0=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=O+tIU+2JibWQuZknB270sKZnjx0hVqxmQrbJb/GGQItecNl7p2opJw5fctwWleuS0 Y43aQwrU3kjj99jmMx8Gbh02zcF+/y0OytnbBcz9mIapVZHj+WHJqditLnYeX2UaHa rQwlCSLVOWj7Z5t8wLX/+kmHG1GjS5CbMKQPCnHI= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 352LndkY017965 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 Jun 2023 16:49:39 -0500 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 2 Jun 2023 16:49:38 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 2 Jun 2023 16:49:38 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 352LnciY006133; Fri, 2 Jun 2023 16:49:38 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Nitin Yadav , Neha Malcom Francis , Sinthu Raja , Thejasvi Konduru , Dasnavis Sabiya Subject: [PATCH 2/8] arm64: dts: ti: k3-j784s4-evm: Add mcu and wakeup uarts Date: Fri, 2 Jun 2023 16:49:31 -0500 Message-ID: <20230602214937.2349545-3-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230602214937.2349545-1-nm@ti.com> References: <20230602214937.2349545-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add wakeup and MCU uart. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon --- Depends on https://lore.kernel.org/linux-arm-kernel/20230503083143.32369-1-t-konduru@ti.com/ arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 33 ++++++++++++++++++++++++ 1 file changed, 33 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 34e9bc89ac66..3f499e527523 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -20,6 +20,8 @@ chosen { }; aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; @@ -142,6 +144,24 @@ J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ }; &wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ + J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ @@ -167,6 +187,19 @@ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ }; }; +&wkup_uart0 { + /* Firmware usage */ + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; From patchwork Fri Jun 2 21:49:32 2023 Content-Type: text/plain; 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Fri, 2 Jun 2023 16:49:38 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 352LncaR119892; Fri, 2 Jun 2023 16:49:38 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Nitin Yadav , Neha Malcom Francis , Sinthu Raja , Thejasvi Konduru , Dasnavis Sabiya Subject: [PATCH 3/8] arm64: dts: ti: k3-j784s4-evm: Enable wakeup_i2c0 and eeprom Date: Fri, 2 Jun 2023 16:49:32 -0500 Message-ID: <20230602214937.2349545-4-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230602214937.2349545-1-nm@ti.com> References: <20230602214937.2349545-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon --- Depends on https://lore.kernel.org/linux-arm-kernel/20230503083143.32369-1-t-konduru@ti.com/ arch/arm64/boot/dts/ti/k3-j784s4-evm.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts index 3f499e527523..f394ab409934 100644 --- a/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts +++ b/arch/arm64/boot/dts/ti/k3-j784s4-evm.dts @@ -25,6 +25,7 @@ aliases { serial2 = &main_uart8; mmc0 = &main_sdhci0; mmc1 = &main_sdhci1; + i2c0 = &wkup_i2c0; i2c3 = &main_i2c0; }; @@ -153,6 +154,13 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ >; }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; + mcu_uart0_pins_default: mcu-uart0-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ @@ -194,6 +202,19 @@ &wkup_uart0 { pinctrl-0 = <&wkup_uart0_pins_default>; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &mcu_uart0 { status = "okay"; pinctrl-names = "default"; From patchwork Fri Jun 2 21:49:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 688360 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9CDF6C7EE2C for ; Fri, 2 Jun 2023 21:49:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236218AbjFBVtr (ORCPT ); Fri, 2 Jun 2023 17:49:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47872 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234452AbjFBVtq (ORCPT ); Fri, 2 Jun 2023 17:49:46 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 631A81A5; Fri, 2 Jun 2023 14:49:45 -0700 (PDT) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 352LndXs103177; Fri, 2 Jun 2023 16:49:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685742579; bh=bIyuqBK+kvVYM7dehcXOqfLT6uUfP92AHpUO2xjH8ME=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Bid3aBogEjfmd8NRwzNY8r+K9ko+6lakk4jQ5fnuDXZFerR1e8wRdOGfn+613FHt2 l+u8I8gMGeFHxzpk3RY7dY/QNRFO1tegl2pikZx/CM1JNlYH0dz/eOVVAGhbcRaXoc VAGSyRWzAS9vE3QthBg9syDhw2ciH4VZdKZMFo3A= Received: from DFLE106.ent.ti.com (dfle106.ent.ti.com [10.64.6.27]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 352LndAs017968 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 Jun 2023 16:49:39 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 2 Jun 2023 16:49:38 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 2 Jun 2023 16:49:38 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 352LncPL001300; Fri, 2 Jun 2023 16:49:38 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Nitin Yadav , Neha Malcom Francis , Sinthu Raja , Thejasvi Konduru , Dasnavis Sabiya Subject: [PATCH 4/8] arm64: dts: ti: k3-am69-sk: Fix main_i2c0 alias Date: Fri, 2 Jun 2023 16:49:33 -0500 Message-ID: <20230602214937.2349545-5-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230602214937.2349545-1-nm@ti.com> References: <20230602214937.2349545-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org main_i2c0 is aliased as i2c0 which creates a problem for u-boot R5 SPL attempting to reuse the same definition in the common board detection logic as it looks for the first i2c instance as the bus on which to detect the eeprom to understand the board variant involved. Switch main_i2c0 to i2c3 alias allowing us to introduce wkup_i2c0 and potentially space for mcu_i2c instances in the gap for follow on patches. Fixes: 635fb18ba008 ("arch: arm64: dts: Add support for AM69 Starter Kit") Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am69-sk.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index bc49ba534790..f364b7803115 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -23,7 +23,7 @@ chosen { aliases { serial2 = &main_uart8; mmc1 = &main_sdhci1; - i2c0 = &main_i2c0; + i2c3 = &main_i2c0; }; memory@80000000 { From patchwork Fri Jun 2 21:49:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 688845 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0173BC7EE2D for ; Fri, 2 Jun 2023 21:49:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233079AbjFBVt5 (ORCPT ); Fri, 2 Jun 2023 17:49:57 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47886 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234960AbjFBVts (ORCPT ); Fri, 2 Jun 2023 17:49:48 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2BA51A5; Fri, 2 Jun 2023 14:49:46 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 352Lnd4X103181; Fri, 2 Jun 2023 16:49:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685742579; bh=aSiMVBD0Dsirj+zKjn9Yb324EJecW4++8p9tcPc/uIk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=f//Flz2UAYRzfAbUYN8KHU7xqik5B9P5AlH9EDRlYHocIWlqBD5IVDb1LnMwdtL7u sJV5XGAfvPTDVA3a60Ki4JJtjSH1xrZ1YN7yt10pAKS8WWtvlsnhyHOhbjvwxpEuib /kgl3lQSezdUFd1hBPMdILThI6X2wSTEnBoZeIPA= Received: from DLEE111.ent.ti.com (dlee111.ent.ti.com [157.170.170.22]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 352Lndmw112438 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 Jun 2023 16:49:39 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE111.ent.ti.com (157.170.170.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 2 Jun 2023 16:49:39 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 2 Jun 2023 16:49:38 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 352LncXg080643; Fri, 2 Jun 2023 16:49:38 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Nitin Yadav , Neha Malcom Francis , Sinthu Raja , Thejasvi Konduru , Dasnavis Sabiya Subject: [PATCH 5/8] arm64: dts: ti: k3-am69-sk: Enable mcu network port Date: Fri, 2 Jun 2023 16:49:34 -0500 Message-ID: <20230602214937.2349545-6-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230602214937.2349545-1-nm@ti.com> References: <20230602214937.2349545-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable networking for NFS and basic networking functionality. Signed-off-by: Nishanth Menon --- Depends on https://lore.kernel.org/linux-arm-kernel/20230503083143.32369-1-t-konduru@ti.com/ arch/arm64/boot/dts/ti/k3-am69-sk.dts | 48 +++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index f364b7803115..ae41ff6249a1 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -24,6 +24,7 @@ aliases { serial2 = &main_uart8; mmc1 = &main_sdhci1; i2c3 = &main_i2c0; + ethernet0 = &mcu_cpsw_port1; }; memory@80000000 { @@ -139,6 +140,32 @@ J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ }; }; +&wkup_pmx2 { + mcu_cpsw_pins_default: mcu-cpsw-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ + J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ + J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ + J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ + J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ + J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ + J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ + J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ + J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ + J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ + J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ + J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ + >; + }; + + mcu_mdio_pins_default: mcu-mdio-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ + J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ + >; + }; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; @@ -178,3 +205,24 @@ &main_sdhci1 { &main_gpio0 { status = "okay"; }; + +&mcu_cpsw { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; +}; + +&davinci_mdio { + mcu_phy0: ethernet-phy@0 { + reg = <0>; + ti,rx-internal-delay = ; + ti,fifo-depth = ; + ti,min-output-impedance; + }; +}; + +&mcu_cpsw_port1 { + status = "okay"; + phy-mode = "rgmii-rxid"; + phy-handle = <&mcu_phy0>; +}; From patchwork Fri Jun 2 21:49:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 688359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E70B8C7EE2C for ; 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Fri, 2 Jun 2023 16:49:39 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 2 Jun 2023 16:49:38 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 2 Jun 2023 16:49:39 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 352LndBR006136; Fri, 2 Jun 2023 16:49:39 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Nitin Yadav , Neha Malcom Francis , Sinthu Raja , Thejasvi Konduru , Dasnavis Sabiya Subject: [PATCH 6/8] arm64: dts: ti: k3-am69-sk: Add mcu and wakeup uarts Date: Fri, 2 Jun 2023 16:49:35 -0500 Message-ID: <20230602214937.2349545-7-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230602214937.2349545-1-nm@ti.com> References: <20230602214937.2349545-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add wakeup and MCU uart. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon --- Depends on https://lore.kernel.org/linux-arm-kernel/20230503083143.32369-1-t-konduru@ti.com/ arch/arm64/boot/dts/ti/k3-am69-sk.dts | 31 +++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index ae41ff6249a1..409fcbaf0126 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -21,6 +21,8 @@ chosen { }; aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; serial2 = &main_uart8; mmc1 = &main_sdhci1; i2c3 = &main_i2c0; @@ -141,6 +143,22 @@ J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ }; &wkup_pmx2 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x070, PIN_INPUT, 0) /* (L37) WKUP_GPIO0_6.WKUP_UART0_CTSn */ + J721S2_WKUP_IOPAD(0x074, PIN_INPUT, 0) /* (L36) WKUP_GPIO0_7.WKUP_UART0_RTSn */ + J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ + J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ + J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ @@ -166,6 +184,19 @@ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ }; }; +&wkup_uart0 { + /* Firmware usage */ + status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; +}; + +&mcu_uart0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; From patchwork Fri Jun 2 21:49:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 688358 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E3B60C7EE2C for ; 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Fri, 2 Jun 2023 16:49:39 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 2 Jun 2023 16:49:39 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 2 Jun 2023 16:49:38 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 352Lndo3119895; Fri, 2 Jun 2023 16:49:39 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Nitin Yadav , Neha Malcom Francis , Sinthu Raja , Thejasvi Konduru , Dasnavis Sabiya Subject: [PATCH 7/8] arm64: dts: ti: k3-am69-sk: Enable wakeup_i2c0 and eeprom Date: Fri, 2 Jun 2023 16:49:36 -0500 Message-ID: <20230602214937.2349545-8-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230602214937.2349545-1-nm@ti.com> References: <20230602214937.2349545-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon --- Depends on https://lore.kernel.org/linux-arm-kernel/20230503083143.32369-1-t-konduru@ti.com/ arch/arm64/boot/dts/ti/k3-am69-sk.dts | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index 409fcbaf0126..a0e7872f31f2 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -25,6 +25,7 @@ aliases { serial1 = &mcu_uart0; serial2 = &main_uart8; mmc1 = &main_sdhci1; + i2c0 = &wkup_i2c0; i2c3 = &main_i2c0; ethernet0 = &mcu_cpsw_port1; }; @@ -152,6 +153,13 @@ J721S2_WKUP_IOPAD(0x04c, PIN_INPUT, 0) /* (K34) WKUP_UART0_TXD */ >; }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { + pinctrl-single,pins = < + J721S2_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ + J721S2_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ + >; + }; + mcu_uart0_pins_default: mcu-uart0-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ @@ -191,6 +199,19 @@ &wkup_uart0 { pinctrl-0 = <&wkup_uart0_pins_default>; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; + &mcu_uart0 { status = "okay"; pinctrl-names = "default"; From patchwork Fri Jun 2 21:49:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 688357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CF862C7EE2E for ; Fri, 2 Jun 2023 21:50:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236585AbjFBVuA (ORCPT ); Fri, 2 Jun 2023 17:50:00 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47960 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236665AbjFBVtw (ORCPT ); Fri, 2 Jun 2023 17:49:52 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 18791E40; Fri, 2 Jun 2023 14:49:50 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 352LndGD072497; Fri, 2 Jun 2023 16:49:39 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685742579; bh=XmH/7b2jgWDrCo4pqahu53GTXlvcTm6dtDowrecpg8I=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=GmuFXIMYpl5ojMmuJdJ/qmrNtwwaaYf2WEQVii+gpaDIzaS3qxSWtCZEo+ZJAou8B WlGnPToRaTyUveH6CZbHf9WUwI33/QobZN8vkq3SuHPlwmRzG0zUlLReDVjShNVaW8 hY07WNaCnqBQ0Lt+qPxOav7NoKgl06ET73wWtBmA= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 352Lndvj028993 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 2 Jun 2023 16:49:39 -0500 Received: from DFLE107.ent.ti.com (10.64.6.28) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Fri, 2 Jun 2023 16:49:39 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Fri, 2 Jun 2023 16:49:38 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 352LndbS001305; Fri, 2 Jun 2023 16:49:39 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Nitin Yadav , Neha Malcom Francis , Sinthu Raja , Thejasvi Konduru , Dasnavis Sabiya Subject: [PATCH 8/8] arm64: dts: ti: k3-am69-sk: Add pinmux for RPi Header Date: Fri, 2 Jun 2023 16:49:37 -0500 Message-ID: <20230602214937.2349545-9-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230602214937.2349545-1-nm@ti.com> References: <20230602214937.2349545-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Dasnavis Sabiya Add pinmux required to bring out the i2c and gpios on 40 pin RPi expansion header on AM69 SK board. Signed-off-by: Dasnavis Sabiya Signed-off-by: Nishanth Menon --- Depends on https://lore.kernel.org/linux-arm-kernel/20230503083143.32369-1-t-konduru@ti.com/ Changes since V1: * Rebased on the pinmux split up done from the dependency. * Some minor style fixups. V1: https://lore.kernel.org/linux-arm-kernel/20230316104743.482972-3-sabiya.d@ti.com/ arch/arm64/boot/dts/ti/k3-am69-sk.dts | 63 +++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am69-sk.dts b/arch/arm64/boot/dts/ti/k3-am69-sk.dts index a0e7872f31f2..093c6f8391e4 100644 --- a/arch/arm64/boot/dts/ti/k3-am69-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am69-sk.dts @@ -141,6 +141,25 @@ vdd_sd_dv_pins_default: vdd-sd-dv-pins-default { J784S4_IOPAD(0x0C4, PIN_INPUT, 7) /* (AD36) ECAP0_IN_APWM_OUT.GPIO0_49 */ >; }; + + rpi_header_gpio0_pins_default: rpi-header-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_IOPAD(0x0BC, PIN_INPUT, 7) /* (AD33) MCASP1_AFSX.GPIO0_47 */ + J784S4_IOPAD(0x06C, PIN_INPUT, 7) /* (AJ37) MCASP4_AFSX.GPIO0_27 */ + J784S4_IOPAD(0x0B4, PIN_INPUT, 7) /* (AL34) MCASP1_AXR4.GPIO0_45 */ + J784S4_IOPAD(0x0C0, PIN_INPUT, 7) /* (AD38) MCASP1_AXR0.GPIO0_48 */ + J784S4_IOPAD(0x00C, PIN_INPUT, 7) /* (AF33) MCAN13_TX.GPIO0_3 */ + J784S4_IOPAD(0x0B8, PIN_INPUT, 7) /* (AC34) MCASP1_ACLKX.GPIO0_46 */ + J784S4_IOPAD(0x090, PIN_INPUT, 7) /* (AC35) MCASP0_AXR8.GPIO0_36 */ + J784S4_IOPAD(0x0A8, PIN_INPUT, 7) /* (AF34) MCASP0_AXR14.GPIO0_42 */ + J784S4_IOPAD(0x0A4, PIN_INPUT, 7) /* (AJ36) MCASP0_AXR13.GPIO0_41 */ + J784S4_IOPAD(0x034, PIN_INPUT, 7) /* (AJ34) PMIC_WAKE0n.GPIO0_13 */ + J784S4_IOPAD(0x0CC, PIN_INPUT, 7) /* (AM37) SPI0_CS0.GPIO0_51 */ + J784S4_IOPAD(0x08C, PIN_INPUT, 7) /* (AE35) MCASP0_AXR7.GPIO0_35 */ + J784S4_IOPAD(0x008, PIN_INPUT, 7) /* (AJ33) MCAN12_RX.GPIO0_2 */ + J784S4_IOPAD(0x004, PIN_INPUT, 7) /* (AG36) MCAN12_TX.GPIO0_1 */ + >; + }; }; &wkup_pmx2 { @@ -167,6 +186,13 @@ J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ >; }; + mcu_i2c0_pins_default: mcu-i2c0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0a0, PIN_INPUT_PULLUP, 0) /* (M35) MCU_I2C0_SCL */ + J784S4_WKUP_IOPAD(0x0a4, PIN_INPUT_PULLUP, 0) /* (G34) MCU_I2C0_SDA */ + >; + }; + mcu_cpsw_pins_default: mcu-cpsw-pins-default { pinctrl-single,pins = < J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ @@ -190,6 +216,28 @@ J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ >; }; + + mcu_rpi_hdr1_gpio0_pins_default: mcu-rpi-hdr1-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x118, PIN_INPUT, 7) /* (N34) WKUP_GPIO0_66 */ + J784S4_WKUP_IOPAD(0x05c, PIN_INPUT, 7) /* (J34) WKUP_GPIO0_1 */ + J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ + J784S4_WKUP_IOPAD(0x058, PIN_INPUT, 7) /* (H38) WKUP_GPIO0_0 */ + J784S4_WKUP_IOPAD(0x0b8, PIN_INPUT, 7) /* (M37) WKUP_GPIO0_56 */ + J784S4_WKUP_IOPAD(0x114, PIN_INPUT, 7) /* (M36) WKUP_GPIO0_57 */ + J784S4_WKUP_IOPAD(0x094, PIN_INPUT, 7) /* (K37) WKUP_GPIO0_15 */ + J784S4_WKUP_IOPAD(0x064, PIN_INPUT, 7) /* (J36) WKUP_GPIO0_3 */ + J784S4_WKUP_IOPAD(0x11c, PIN_INPUT, 7) /* (M34) WKUP_GPIO0_67 */ + >; + }; +}; + +&wkup_pmx3 { + mcu_rpi_hdr2_gpio0_pins_default: mcu-rpi-hdr2-gpio0-pins-default { + pinctrl-single,pins = < + J784S4_WKUP_IOPAD(0x0, PIN_INPUT, 7) /* (M33) WKUP_GPIO0_49 */ + >; + }; }; &wkup_uart0 { @@ -212,12 +260,25 @@ eeprom@51 { }; }; +&wkup_gpio0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_rpi_hdr1_gpio0_pins_default>, <&mcu_rpi_hdr2_gpio0_pins_default>; +}; + &mcu_uart0 { status = "okay"; pinctrl-names = "default"; pinctrl-0 = <&mcu_uart0_pins_default>; }; +&mcu_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&mcu_i2c0_pins_default>; + clock-frequency = <400000>; +}; + &main_uart8 { status = "okay"; pinctrl-names = "default"; @@ -256,6 +317,8 @@ &main_sdhci1 { &main_gpio0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&rpi_header_gpio0_pins_default>; }; &mcu_cpsw {