From patchwork Thu Jun 1 18:31:43 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 688438 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A433FC7EE2E for ; Thu, 1 Jun 2023 18:32:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232776AbjFAScN (ORCPT ); Thu, 1 Jun 2023 14:32:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232062AbjFAScH (ORCPT ); Thu, 1 Jun 2023 14:32:07 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 92A411A1; Thu, 1 Jun 2023 11:32:05 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 351IVr3h091645; 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Thu, 1 Jun 2023 13:31:53 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 351IVrmY033837; Thu, 1 Jun 2023 13:31:53 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Neha Malcom Francis Subject: [PATCH 1/9] arm64: dts: ti: k3-j721e-sk: Add missing uart pinmuxes Date: Thu, 1 Jun 2023 13:31:43 -0500 Message-ID: <20230601183151.1000157-2-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230601183151.1000157-1-nm@ti.com> References: <20230601183151.1000157-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Rather than depend on the default pinmuxes, explicitly describe the pinmux Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 31 ++++++++++++++++++++++++-- 1 file changed, 29 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index c04e845547fa..c068fa46f60e 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -302,6 +302,13 @@ J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ >; }; + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ + J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ + >; + }; + main_i2c0_pins_default: main-i2c0-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */ @@ -495,6 +502,22 @@ J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */ >; }; + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xf0, PIN_INPUT, 2) /* (D26) MCU_I3C0_SCL.MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xf4, PIN_OUTPUT, 2)/* (D25) MCU_I3C0_SDA.MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0)/* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + wkup_i2c0_pins_default: wkup-i2c0-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */ @@ -513,11 +536,14 @@ J721E_WKUP_IOPAD(0xdc, PIN_INPUT, 7) /* (H27) WKUP_GPIO0_11 */ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { @@ -530,7 +556,8 @@ &main_uart0 { &main_uart1 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_sdhci0 { From patchwork Thu Jun 1 18:31:44 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 687873 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C2A1EC7EE2A for ; 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Thu, 1 Jun 2023 13:31:53 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Jun 2023 13:31:53 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Jun 2023 13:31:53 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 351IVr9O002966; Thu, 1 Jun 2023 13:31:53 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Neha Malcom Francis Subject: [PATCH 2/9] arm64: dts: ti: k3-j721e-sk: Enable wakeup_i2c0 and eeprom Date: Thu, 1 Jun 2023 13:31:44 -0500 Message-ID: <20230601183151.1000157-3-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230601183151.1000157-1-nm@ti.com> References: <20230601183151.1000157-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index c068fa46f60e..b1d7f3dd084b 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -540,6 +540,19 @@ &wkup_uart0 { pinctrl-0 = <&wkup_uart0_pins_default>; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@51 { + /* AT24C512C-MAHM-T */ + compatible = "atmel,24c512"; + reg = <0x51>; + }; +}; + &mcu_uart0 { status = "okay"; pinctrl-names = "default"; From patchwork Thu Jun 1 18:31:45 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 687870 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4EEFEC7EE2F for ; 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Thu, 1 Jun 2023 13:31:54 -0500 Received: from DFLE101.ent.ti.com (10.64.6.22) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Jun 2023 13:31:53 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Jun 2023 13:31:53 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 351IVrm5033840; Thu, 1 Jun 2023 13:31:53 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Neha Malcom Francis Subject: [PATCH 3/9] arm64: dts: ti: j721e-som/common-proc-board: Add product links Date: Thu, 1 Jun 2023 13:31:45 -0500 Message-ID: <20230601183151.1000157-4-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230601183151.1000157-1-nm@ti.com> References: <20230601183151.1000157-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add product links to get reference to schematics and design files Signed-off-by: Nishanth Menon --- We missed this during the initial days of k3 patches, but it is never late to cleanup.. arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 2 ++ arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 58c25178f330..5222ec03022f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/ + * + * Product Link: https://www.ti.com/tool/J721EXCPXEVM */ /dts-v1/; diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index bc15de6ab8ac..b6dca6e4501c 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0 /* * Copyright (C) 2019-2020 Texas Instruments Incorporated - https://www.ti.com/ + * + * Product Link: https://www.ti.com/tool/J721EXSOMXEVM */ /dts-v1/; From patchwork Thu Jun 1 18:31:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 688436 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A51CDC7EE23 for ; Thu, 1 Jun 2023 18:32:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232537AbjFAScS (ORCPT ); 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Thu, 1 Jun 2023 13:31:54 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE108.ent.ti.com (10.64.6.29) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Jun 2023 13:31:53 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Jun 2023 13:31:53 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 351IVr2x002969; Thu, 1 Jun 2023 13:31:53 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Neha Malcom Francis Subject: [PATCH 4/9] arm64: dts: ti: j721e-common-proc-board: Add uart pinmux Date: Thu, 1 Jun 2023 13:31:46 -0500 Message-ID: <20230601183151.1000157-5-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230601183151.1000157-1-nm@ti.com> References: <20230601183151.1000157-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Explicitly define the pinmux rather than depend on bootloader configured pinmux for the platform. Signed-off-by: Nishanth Menon --- .../dts/ti/k3-j721e-common-proc-board.dts | 62 +++++++++++++++++-- 1 file changed, 58 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 5222ec03022f..25111c86511f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -174,6 +174,36 @@ dp_connector_in: endpoint { }; &main_pmx0 { + main_uart0_pins_default: main-uart0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */ + J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */ + J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */ + J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */ + >; + }; + + main_uart1_pins_default: main-uart1-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */ + J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */ + >; + }; + + main_uart2_pins_default: main-uart2-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */ + J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */ + >; + }; + + main_uart4_pins_default: main-uart4-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */ + J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */ + >; + }; + sw10_button_pins_default: sw10-button-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */ @@ -295,6 +325,22 @@ J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */ }; &wkup_pmx0 { + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + + mcu_uart0_pins_default: mcu-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */ + J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */ + J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */ + J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */ + >; + }; + sw11_button_pins_default: sw11-button-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */ @@ -369,32 +415,40 @@ J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */ &wkup_uart0 { /* Wakeup UART is used by System firmware */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &mcu_uart0 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&mcu_uart0_pins_default>; }; &main_uart0 { status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&main_uart0_pins_default>; /* Shared with ATF on this platform */ power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>; }; &main_uart1 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart1_pins_default>; }; &main_uart2 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart2_pins_default>; }; &main_uart4 { status = "okay"; - /* Default pinmux */ + pinctrl-names = "default"; + pinctrl-0 = <&main_uart4_pins_default>; }; &main_gpio2 { From patchwork Thu Jun 1 18:31:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 688439 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4F028C7EE23 for ; Thu, 1 Jun 2023 18:32:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232583AbjFAScK (ORCPT ); Thu, 1 Jun 2023 14:32:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37144 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230467AbjFAScH (ORCPT ); Thu, 1 Jun 2023 14:32:07 -0400 Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F0FC19B; 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Thu, 1 Jun 2023 13:31:53 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 351IVrPA059321; Thu, 1 Jun 2023 13:31:53 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Neha Malcom Francis Subject: [PATCH 5/9] arm64: dts: ti: k3-j721e-som-p0: Enable wakeup_i2c0 and eeprom Date: Thu, 1 Jun 2023 13:31:47 -0500 Message-ID: <20230601183151.1000157-6-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230601183151.1000157-1-nm@ti.com> References: <20230601183151.1000157-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Enable wakeup_i2c and use un-used pinmux. While at it, describe the board detection eeprom present on the board. Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi index b6dca6e4501c..a0be8d2edac6 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-som-p0.dtsi @@ -169,6 +169,19 @@ J721E_WKUP_IOPAD(0x002c, PIN_OUTPUT, 0) /* MCU_OSPI0_CSn0 */ }; }; +&wkup_i2c0 { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_i2c0_pins_default>; + clock-frequency = <400000>; + + eeprom@50 { + /* CAV24C256WE-GT3 */ + compatible = "atmel,24c256"; + reg = <0x50>; + }; +}; + &ospi0 { pinctrl-names = "default"; pinctrl-0 = <&mcu_fss0_ospi0_pins_default>; From patchwork Thu Jun 1 18:31:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 687874 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03121C77B7A for ; Thu, 1 Jun 2023 18:32:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231622AbjFAScH (ORCPT ); Thu, 1 Jun 2023 14:32:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231670AbjFAScH (ORCPT ); Thu, 1 Jun 2023 14:32:07 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0211F199; Thu, 1 Jun 2023 11:32:03 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 351IVs7a014497; Thu, 1 Jun 2023 13:31:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685644314; bh=chdMv7Vs3/5FBu/acWe2Sy5+HMzkjW7UkGviZexNVuo=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Xgg0Y13dxmCEslkustbgIatgDJbZz+Pn8YvHRgHsBquvCB3UPr3/LiQI63hSOR1n5 NJwMZClqsCJZHAhQLAFSZ6Ros3Ry01PYm7w8u2Q/QsZrdjRsimgUzHJloZZJ/CTZ5M 55VfZqCvHWKEv/1/S04UlmH9v33/oshryNJmjy/E= Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 351IVs6W023105 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 1 Jun 2023 13:31:54 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Jun 2023 13:31:53 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Jun 2023 13:31:53 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 351IVr8t002972; Thu, 1 Jun 2023 13:31:53 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Neha Malcom Francis Subject: [PATCH 6/9] arm64: dts: ti: k3-j721e-beagleboneai64: Add wakeup_uart pinmux Date: Thu, 1 Jun 2023 13:31:48 -0500 Message-ID: <20230601183151.1000157-7-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230601183151.1000157-1-nm@ti.com> References: <20230601183151.1000157-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define the wakeup uart pin-mux for completeness. This allows the device tree usage in bootloader and firmwares that can configure the same appropriately. Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts index c13246a9ed8f..bc53ca566a68 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-beagleboneai64.dts @@ -531,6 +531,13 @@ J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */ >; }; + wkup_uart0_pins_default: wkup-uart0-pins-default { + pinctrl-single,pins = < + J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */ + J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */ + >; + }; + mcu_usbss1_pins_default: mcu-usbss1-pins-default { pinctrl-single,pins = < J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO0_30 */ @@ -541,6 +548,8 @@ J721E_WKUP_IOPAD(0x3c, PIN_OUTPUT_PULLUP, 5) /* (A23) MCU_OSPI1_LBCLKO.WKUP_GPIO &wkup_uart0 { /* Wakeup UART is used by TIFS firmware. */ status = "reserved"; + pinctrl-names = "default"; + pinctrl-0 = <&wkup_uart0_pins_default>; }; &main_uart0 { From patchwork Thu Jun 1 18:31:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 688437 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 52929C7EE2A for ; Thu, 1 Jun 2023 18:32:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232823AbjFAScP (ORCPT ); Thu, 1 Jun 2023 14:32:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37168 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232540AbjFAScJ (ORCPT ); Thu, 1 Jun 2023 14:32:09 -0400 Received: from fllv0015.ext.ti.com (fllv0015.ext.ti.com [198.47.19.141]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CFA3D97; Thu, 1 Jun 2023 11:32:08 -0700 (PDT) Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 351IVsZO104375; Thu, 1 Jun 2023 13:31:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685644314; bh=HE60QwLLDuey6C/5HbF5mH4FcvSJCSPJ//dfbnVvh1s=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qfqQxXQxhAcwzizVEYhPf2R6ljjMj8esiUyN0wDyq3JjHjZKwT9wc/mfWuVt/zsP0 CDGfop0tv/6+jLpJLVo70cyiIUohXdjRXHAjC6QlumLVAZ/4AmXoKUEpmMtYaPowHW LCfupWxsoxVTG1ljg8lcWIBDeclWA06B4EUCj3G4= Received: from DFLE103.ent.ti.com (dfle103.ent.ti.com [10.64.6.24]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 351IVsl9008362 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 1 Jun 2023 13:31:54 -0500 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Jun 2023 13:31:54 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Jun 2023 13:31:54 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id 351IVrw5033846; Thu, 1 Jun 2023 13:31:53 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Neha Malcom Francis Subject: [PATCH 7/9] arm64: dts: ti: k3-j721e-sk: Define aliases at board level Date: Thu, 1 Jun 2023 13:31:49 -0500 Message-ID: <20230601183151.1000157-8-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230601183151.1000157-1-nm@ti.com> References: <20230601183151.1000157-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define the aliases at the board level instead of using generic aliases at SoC level. Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e-sk.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts index b1d7f3dd084b..9945c4ab8abb 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-sk.dts @@ -16,6 +16,15 @@ / { compatible = "ti,j721e-sk", "ti,j721e"; model = "Texas Instruments J721E SK"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + ethernet0 = &cpsw_port1; + mmc1 = &main_sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; }; From patchwork Thu Jun 1 18:31:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 687872 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5ED3C7EE2F for ; Thu, 1 Jun 2023 18:32:13 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232674AbjFAScL (ORCPT ); Thu, 1 Jun 2023 14:32:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37148 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231992AbjFAScH (ORCPT ); Thu, 1 Jun 2023 14:32:07 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 917C319F; Thu, 1 Jun 2023 11:32:05 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 351IVshI091649; Thu, 1 Jun 2023 13:31:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685644314; bh=ZOkhynB1EGFmE6jr3YpCwfdJRd5OuBYOeE/Tgvc1wHY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qvJUu3f5d9fm8/tawVP7R6mnyY16n+ckOVgUaqH6N79c2+ojMGedayJCjkmPxUjiG 6ngUbin37Vfeh014HgdmKcYpIxW8dCCht3j0P3YaIpsF90koI44b8/W1ECdT5n+dgO LfpwwS809NFMFg3bFpRyvEpoH+CtkeS8dpH0RFz0= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 351IVsDw104517 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 1 Jun 2023 13:31:54 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Jun 2023 13:31:54 -0500 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Jun 2023 13:31:53 -0500 Received: from localhost (ileaxei01-snat2.itg.ti.com [10.180.69.6]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 351IVsl1097122; Thu, 1 Jun 2023 13:31:54 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Neha Malcom Francis Subject: [PATCH 8/9] arm64: dts: ti: k3-j721e-common-proc-board: Define aliases at board level Date: Thu, 1 Jun 2023 13:31:50 -0500 Message-ID: <20230601183151.1000157-9-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230601183151.1000157-1-nm@ti.com> References: <20230601183151.1000157-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Define the aliases at the board level instead of using generic aliases at SoC level. Signed-off-by: Nishanth Menon --- .../arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 25111c86511f..b524a65ab43f 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -17,6 +17,18 @@ / { compatible = "ti,j721e-evm", "ti,j721e"; model = "Texas Instruments J721e EVM"; + aliases { + serial0 = &wkup_uart0; + serial1 = &mcu_uart0; + serial2 = &main_uart0; + serial3 = &main_uart1; + serial4 = &main_uart2; + serial6 = &main_uart4; + ethernet0 = &cpsw_port1; + mmc0 = &main_sdhci0; + mmc1 = &main_sdhci1; + }; + chosen { stdout-path = "serial2:115200n8"; }; From patchwork Thu Jun 1 18:31:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nishanth Menon X-Patchwork-Id: 688440 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C1D1C7EE23 for ; Thu, 1 Jun 2023 18:32:10 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232326AbjFAScI (ORCPT ); Thu, 1 Jun 2023 14:32:08 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231659AbjFAScH (ORCPT ); Thu, 1 Jun 2023 14:32:07 -0400 Received: from lelv0142.ext.ti.com (lelv0142.ext.ti.com [198.47.23.249]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01D64198; Thu, 1 Jun 2023 11:32:03 -0700 (PDT) Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0142.ext.ti.com (8.15.2/8.15.2) with ESMTP id 351IVsNF014503; Thu, 1 Jun 2023 13:31:54 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1685644314; bh=ljdWyCG/YPepgV3LFhefxbvf55IoYuxJocOURow7p0c=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TtO7yQKVmT6G/FwBhH6zMhLGHN19AqD5i2Fxk1HUb4TyL6DgG7T0SlVwqf3bb/fWy iSzbkmxHX1zz+z8jmOElwJLz9GsudP72MFz/UmVFQCkPi1/MEtxQdl1c4DYeq5RmvY BJk2O1eQgzuVtRiiJMAo/FdzLqgMD7EYLoyGI2ZA= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 351IVsld104520 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Thu, 1 Jun 2023 13:31:54 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 1 Jun 2023 13:31:54 -0500 Received: from lelv0326.itg.ti.com (10.180.67.84) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 1 Jun 2023 13:31:54 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 351IVswd002975; Thu, 1 Jun 2023 13:31:54 -0500 From: Nishanth Menon To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , Udit Kumar , Neha Malcom Francis Subject: [PATCH 9/9] arm64: dts: ti: k3-j721e: Drop SoC level aliases Date: Thu, 1 Jun 2023 13:31:51 -0500 Message-ID: <20230601183151.1000157-10-nm@ti.com> X-Mailer: git-send-email 2.40.0 In-Reply-To: <20230601183151.1000157-1-nm@ti.com> References: <20230601183151.1000157-1-nm@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Drop the SoC level aliases as these need to be done at board level. Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-j721e.dtsi | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e.dtsi b/arch/arm64/boot/dts/ti/k3-j721e.dtsi index 6227838d8402..540d3781b37a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e.dtsi @@ -18,25 +18,6 @@ / { #address-cells = <2>; #size-cells = <2>; - aliases { - serial0 = &wkup_uart0; - serial1 = &mcu_uart0; - serial2 = &main_uart0; - serial3 = &main_uart1; - serial4 = &main_uart2; - serial5 = &main_uart3; - serial6 = &main_uart4; - serial7 = &main_uart5; - serial8 = &main_uart6; - serial9 = &main_uart7; - serial10 = &main_uart8; - serial11 = &main_uart9; - ethernet0 = &cpsw_port1; - mmc0 = &main_sdhci0; - mmc1 = &main_sdhci1; - mmc2 = &main_sdhci2; - }; - chosen { }; cpus {