From patchwork Thu Jun 1 17:00:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 687788 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E023EC7EE2A for ; Thu, 1 Jun 2023 17:00:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231607AbjFARAZ (ORCPT ); Thu, 1 Jun 2023 13:00:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43100 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229598AbjFARAX (ORCPT ); Thu, 1 Jun 2023 13:00:23 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B2629196; Thu, 1 Jun 2023 10:00:22 -0700 (PDT) Received: from [192.168.122.1] (84-115-214-73.cable.dynamic.surfer.at [84.115.214.73]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 893EECFC8B; Thu, 1 Jun 2023 17:00:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=z3ntu; t=1685638820; bh=liwsTCjCFh4bjc2tccmTcIdepPTZlH+GSHh7zUBFyD8=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=AbIqqufT4U2JyvBx09ZBvo75XZHM4bIwgCyV3j9PFAIPzHhEZ4XZ6CYsQ38VaqFj7 w/XwM6+vsw/85bUVuYYIk9JDUhQ3ECJ/myLFRLOIg8VjJmK6e0yPsVMd/UrfO7+lfA 1arFyu7DJSzuM0/w8XRFkOeCgVtHgAh2pEaAfyCM= From: Luca Weiss Date: Thu, 01 Jun 2023 19:00:08 +0200 Subject: [PATCH v3 1/7] dt-bindings: msm: dsi-phy-28nm: Document msm8226 compatible MIME-Version: 1.0 Message-Id: <20230308-msm8226-mdp-v3-1-b6284145d67a@z3ntu.xyz> References: <20230308-msm8226-mdp-v3-0-b6284145d67a@z3ntu.xyz> In-Reply-To: <20230308-msm8226-mdp-v3-0-b6284145d67a@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Conor Dooley X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1755; i=luca@z3ntu.xyz; h=from:subject:message-id; bh=liwsTCjCFh4bjc2tccmTcIdepPTZlH+GSHh7zUBFyD8=; b=owEBbQKS/ZANAwAIAXLYQ7idTddWAcsmYgBkeM6c0sP+UId+y6wLfEJfVjt2h7jHBbz6Gk6jE sJE4cDlaJmJAjMEAAEIAB0WIQQ5utIvCCzakboVj/py2EO4nU3XVgUCZHjOnAAKCRBy2EO4nU3X VpHGD/9VT1CjSGY7weNbH6UOmol+5VjzWZKCzcHe9+j4peI3wQ7d6DOwDf3k4a1ebyxpgeSOjAz ttH1Qs6DPRfHK+u5D/73nqAJ8M+dh3fmXctEQb0tV4SOI9I69fEevpno3sltLIdEGxEVZAchtF+ X/XVaKAVRm7S5syZqIZZ1+lVO98mVVOfg3+uJknd+Q/F/qtB4j1120hFEh8lRWeb2unbhvaq/mU xsn41+E9Faw7ChQ8AbPW5KI/vELcA7hZnkawh9UN8hz+ZNkIACaWzHlEdWKyUr0YR7LhWFJE1MY QfU7zs0MEMOQldL6Se/eoB7OdCyWi69UM67uGJVA3cir87m78Yj6BBJhj7fHbzOoCRwAo4cQiU7 mRxUaGgpxET/dkpIvCePgl3Pcq1GrqiStLxWcvEVN9sBEfpJmD/HEZeeWsft8/Z09PEUNaibepq NvzpqKVbf3lz+yErUDWvIVGTDVhgCtGpBF0QvAtyY/l3Ax5XOzFFlzmeUurmx65tYPdlSsulqYK OUVkx5vBwWkS59zkFK0ByRKvsiT42mTTpHXSoGxGlVzo5EuDdDqXWMdNfZOhWrZZxgcAf+EBpn1 2s6sAS4nMoXLFmQR8A/AOU6cgm//Ahy62XpxzFXkW+pt3Lzt+PL9w/CKJmmBjkpbHBruRluUcDN oIMGhmHvpIPLuWA== X-Developer-Key: i=luca@z3ntu.xyz; a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The MSM8226 SoC uses a slightly different 28nm dsi phy. Add a new compatible for it. And while we're at it, in the dsi-phy-28nm.yaml move the 8960 compatible to its correct place so its sorted alphabetically. Acked-by: Conor Dooley Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml | 3 ++- Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml | 1 + 2 files changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml index cf4a338c4661..62fb3e484eb2 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-28nm.yaml @@ -15,10 +15,11 @@ allOf: properties: compatible: enum: + - qcom,dsi-phy-28nm-8226 + - qcom,dsi-phy-28nm-8960 - qcom,dsi-phy-28nm-hpm - qcom,dsi-phy-28nm-hpm-fam-b - qcom,dsi-phy-28nm-lp - - qcom,dsi-phy-28nm-8960 reg: items: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml index b0100105e428..db9f07c6142d 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdss.yaml @@ -125,6 +125,7 @@ patternProperties: - qcom,dsi-phy-14nm-660 - qcom,dsi-phy-14nm-8953 - qcom,dsi-phy-20nm + - qcom,dsi-phy-28nm-8226 - qcom,dsi-phy-28nm-hpm - qcom,dsi-phy-28nm-lp - qcom,hdmi-phy-8084 From patchwork Thu Jun 1 17:00:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 689409 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E07FFC7EE37 for ; Thu, 1 Jun 2023 17:00:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231890AbjFARAZ (ORCPT ); Thu, 1 Jun 2023 13:00:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231575AbjFARAY (ORCPT ); Thu, 1 Jun 2023 13:00:24 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3A6C3197; Thu, 1 Jun 2023 10:00:23 -0700 (PDT) Received: from [192.168.122.1] (84-115-214-73.cable.dynamic.surfer.at [84.115.214.73]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 5E65ECFC90; Thu, 1 Jun 2023 17:00:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=z3ntu; t=1685638821; bh=5WHPkyvk4StYMkcwb4dHhrbj0F9n7jmIYVJjvJu7XrI=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=g1h4SGg6jLrQKsf7dBGdwKpSaOjiCWrLK9MF6xRZ2UY0dYHaROEG28MxYDrW9+P4t TsYf4FUF24cYLNMcKXFMXb4UQ/3wEOJ4YtlQnV5w2rObAPFn2PA0hG3a3cPtX/tncr 6ACOA/0ZnGPltI1K2QQlIYyIDD+cEAYlEo+7x+L4= From: Luca Weiss Date: Thu, 01 Jun 2023 19:00:09 +0200 Subject: [PATCH v3 2/7] dt-bindings: display/msm: dsi-controller-main: Add msm8226 compatible MIME-Version: 1.0 Message-Id: <20230308-msm8226-mdp-v3-2-b6284145d67a@z3ntu.xyz> References: <20230308-msm8226-mdp-v3-0-b6284145d67a@z3ntu.xyz> In-Reply-To: <20230308-msm8226-mdp-v3-0-b6284145d67a@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Conor Dooley X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1112; i=luca@z3ntu.xyz; h=from:subject:message-id; bh=5WHPkyvk4StYMkcwb4dHhrbj0F9n7jmIYVJjvJu7XrI=; b=owEBbQKS/ZANAwAIAXLYQ7idTddWAcsmYgBkeM6d88QPY84BJrJS1MOopM6cc6EnFLuxfLGMs A1Mm2N7hg2JAjMEAAEIAB0WIQQ5utIvCCzakboVj/py2EO4nU3XVgUCZHjOnQAKCRBy2EO4nU3X Vj1uEADZ9MzzvOg6cssb2m+khXt/QvEhFRpqib9jb8iBlt08Oyb4O8UWIoJNKDCR+HIyoFFc+i7 o3NdEGVflpzzeGCTU8sJZeFB/x7qd5lmT0v/qvzgTgRiqK8DeOs/EtgzjkE8i+oa4cu/0yo/+oB QdW68MO/B4ZeXxQZAArHMmBnPoidM7xL2rIb5DQg7ofAFjzIROgm5BTe1QmTZVxHGm5pDMF74+q ZIErHOKdC8xO7KhRnSerssRUA2o5VqHlZjkgbFL+RhgI3n3dsUkOOyb3cI6BfleSVz2seqhU1sH bUGXfV2K+Uv9Srrv7qhLkN5vdSMk8YWOJgBA175yAJILJkVHJXd17iK5eqoM2uYxYTYHV7Rh1Md HiEuZpyTWLgDZ06c1gaJRkyrzx0vXthZiTDH6skrrnEqr26f6uiDOT3ND0biyDg8WY8LDhWlUzq igouSEVcKFbZWItOjLsydZN2/AgAhwHq5165jRrQ6ai3R8y1NjhZAE2Vg35q/Vum3RhT+VmnA4c tjUOm90QPkelYm0jyrYme1eviJr+woscJqXEMS3jxp7VkxInsNWhlw79PXjjlcRpoGo1wQ1N868 ZC5g0E+mtnGb7LgKR93PyU4GSlMLyPghOBYMSXQO3hK9Gox1nKWjb2mgHNpUZAtsQDIO9rbqK0R 0p/YtXsXwo1DyvQ== X-Developer-Key: i=luca@z3ntu.xyz; a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the compatible for the DSI found on MSM8226. Acked-by: Conor Dooley Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index 130e16d025bc..660e0f496826 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -15,6 +15,7 @@ properties: - items: - enum: - qcom,apq8064-dsi-ctrl + - qcom,msm8226-dsi-ctrl - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl - qcom,msm8974-dsi-ctrl @@ -256,6 +257,7 @@ allOf: compatible: contains: enum: + - qcom,msm8226-dsi-ctrl - qcom,msm8974-dsi-ctrl then: properties: From patchwork Thu Jun 1 17:00:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 687787 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1F2BC7EE39 for ; Thu, 1 Jun 2023 17:00:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232166AbjFARA0 (ORCPT ); Thu, 1 Jun 2023 13:00:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43118 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231631AbjFARAZ (ORCPT ); Thu, 1 Jun 2023 13:00:25 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 09F6918D; Thu, 1 Jun 2023 10:00:23 -0700 (PDT) Received: from [192.168.122.1] (84-115-214-73.cable.dynamic.surfer.at [84.115.214.73]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 3DD5BCFC91; Thu, 1 Jun 2023 17:00:21 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=z3ntu; t=1685638822; bh=u5Pebo6nZ9QZwWZHlwTcKLHf8y3TFQkR66oBJVT1aM0=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=qv2YZ8znYq1IcODOJwK/zFcSnVmgt7tYuII4dKSP3nuBZeuMtDoqaMBc2GeEPwx10 hTs8mQuv66cNBs5BVFVSHKEG0Tqw1xchkQGac/0i96jwDoFJeBTU/MSAh9cQt7Y9l7 OZxtLuBjsY8oda/RiDORQR2gCSUmhWP0Ac8ZiSwk= From: Luca Weiss Date: Thu, 01 Jun 2023 19:00:10 +0200 Subject: [PATCH v3 3/7] dt-bindings: display/msm: qcom,mdp5: Add msm8226 compatible MIME-Version: 1.0 Message-Id: <20230308-msm8226-mdp-v3-3-b6284145d67a@z3ntu.xyz> References: <20230308-msm8226-mdp-v3-0-b6284145d67a@z3ntu.xyz> In-Reply-To: <20230308-msm8226-mdp-v3-0-b6284145d67a@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss , Conor Dooley X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=837; i=luca@z3ntu.xyz; h=from:subject:message-id; bh=u5Pebo6nZ9QZwWZHlwTcKLHf8y3TFQkR66oBJVT1aM0=; b=owEBbQKS/ZANAwAIAXLYQ7idTddWAcsmYgBkeM6efGQ0BIg2q8eurvW7D4x7buZEuenq22o52 ab4WF5e5kiJAjMEAAEIAB0WIQQ5utIvCCzakboVj/py2EO4nU3XVgUCZHjOngAKCRBy2EO4nU3X VmqREACinz8LWg598lYRVLWSHTQl+HIIR2HIAedEms+PS/+o7vIjPJXMqpgSI9YBWlDgsZc6iS2 q+UIJrMttaOnhP8B59SZolCCrsEDeE6GGOaL+4QnMhbHeN1hKisKlIOIkkcympl2NqL76LN+StZ a3vLQ1xGCA7cCa0NUjjtdsvkE367TDgItt43hlF7x1YKvGIQ6RWQLUAp75RYqmJlJbG2EmF/oqX 1MZVQ+zAvCWC962UvuUrLrDLDcO1U9yZNSJVAn6DGBDS47RwTNKHZQdgKIwY4HEHp+Hz95oDdeT Ht3KJYMtfQ/gXEB9ZtahSWDsjp33I3fGliFhfVtpg7EtXI8zIvkv98ggAMaXFZmeWIsYZiTA2NF 4wxiut+7c6vYYo3iJZThQtPmjEM9jedLrmnKYsi0uh0pYrH1lquNPLLfsjyg/UEXOD+2R16UD64 5xtJi6/BCsXMpoDh+4e4s9noQ6gxDxNjVbK8EfHGXIZPp84DkKAIblQUNurkEZBc8wv6cwNrltt qt9a+PI2xo/jZdwtdcPin37tYhjDZnMZ+1PLLpXnSmzcCGPW3iN9syxCWn2g1dFUSqsY8htRifv 962emdsXUc5ZYE9HcNGbLraZ/IsN0sYn4DxFOaqKVA67gF6qGXY70jqilpeO8z/rW3q83athuOV 28WYLYIftXoOxJQ== X-Developer-Key: i=luca@z3ntu.xyz; a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the compatible for the MDP5 found on MSM8226. Acked-by: Conor Dooley Signed-off-by: Luca Weiss --- Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml index a763cf8da122..2fe032d0e8f8 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml @@ -22,6 +22,7 @@ properties: - items: - enum: - qcom,apq8084-mdp5 + - qcom,msm8226-mdp5 - qcom,msm8916-mdp5 - qcom,msm8917-mdp5 - qcom,msm8953-mdp5 From patchwork Thu Jun 1 17:00:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 687785 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 34668C77B7E for ; Thu, 1 Jun 2023 17:01:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232417AbjFARBQ (ORCPT ); Thu, 1 Jun 2023 13:01:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43902 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232411AbjFARBE (ORCPT ); Thu, 1 Jun 2023 13:01:04 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 488DBE61; Thu, 1 Jun 2023 10:00:54 -0700 (PDT) Received: from [192.168.122.1] (84-115-214-73.cable.dynamic.surfer.at [84.115.214.73]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 15043CFC92; Thu, 1 Jun 2023 17:00:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=z3ntu; t=1685638822; bh=Jm/DdiEm/EekWEu0ec6gDTbUQ0p4VEB89p93cuEm6n4=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=AlU5UvedF4QUAVYwX4BDXDHpiAuc4iOLwpIdq39UeU8zYn0OTNsV6dQZAjUwXPtKo JBZ7/NgEH10zNtk3VVzwQbZziA7q5rfsWGvlkTaobCTYvN39DXml4jCsXHEJ+nR6Lx eZTMyZMWSQprU8YFYbFthPh+HmmHbt7+WYO0FsBw= From: Luca Weiss Date: Thu, 01 Jun 2023 19:00:11 +0200 Subject: [PATCH v3 4/7] drm/msm/mdp5: Add MDP5 configuration for MSM8226 MIME-Version: 1.0 Message-Id: <20230308-msm8226-mdp-v3-4-b6284145d67a@z3ntu.xyz> References: <20230308-msm8226-mdp-v3-0-b6284145d67a@z3ntu.xyz> In-Reply-To: <20230308-msm8226-mdp-v3-0-b6284145d67a@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=2734; i=luca@z3ntu.xyz; h=from:subject:message-id; bh=Jm/DdiEm/EekWEu0ec6gDTbUQ0p4VEB89p93cuEm6n4=; b=owEBbQKS/ZANAwAIAXLYQ7idTddWAcsmYgBkeM6fYU+7o/XkxueT0obX8SuJUz4ZGFUVdqcb0 sha9DpnFO+JAjMEAAEIAB0WIQQ5utIvCCzakboVj/py2EO4nU3XVgUCZHjOnwAKCRBy2EO4nU3X Vkl3D/0XJavl8qtEyvMTHH4vkLUEAc0Zx5egxwfV/0TpHTmC0VGddlo/czdAKGuJ19vdWDiDuIJ dQzmegIs0katqQzMl/MOkNr/y6KHGovc403DCZMdj8nmjQNZa/l3pY5OmuJ4FjyBv/qyppj6owo JcUPzkTmRgIR1cYoN02Bcjo4AWbk5oK+uaXvNNzEiE4+DIqtQhBhuJ5CFmBWHOqUtOiMiUWB0FR wjgnpHFPyAmlHDS3W3dxXXLrOKVEFXYlbMqxOmDstzf+2MIcXOEXPcsu8z+z+FDPDiCXOooWf1D R9DF+i/x428eyS/3MkVUgprJWk1Z9AcXRC53y9yd/HzKFYl5F8lf60rswmphgubUnhHir85CCXr j9eX4vDHX1FTWbtAe9uZLbalQXn6pm0ufxUvJ26gCzG2Dsx3tRP0+0ipDaFiC7BTzTVpS5Wl668 o7CqAnZXU7oVOkhebQ1PeSHz1uiYtuC4IGOzrRuYrrQEUuPqt5UHsfuB7tpxbgM99ixZ6IFQFwJ RGTCKFS7/FvgfwhXV/aD4jALXBKAkWeREkkEfuwl4W5VlFbIcntFjtiAXCNbHwby5sDJDq0UVTB VoS0perIoe2cwXx/rV3oB1I7MTX08Ncdbhf0jmPmxVcKVbEqJduwEB+No1eIqd1mt7KnNUNW04+ mNStLDtRH0J7GLw== X-Developer-Key: i=luca@z3ntu.xyz; a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the required config for the v1.1 MDP5 found on MSM8226. Reviewed-by: Dmitry Baryshkov Signed-off-by: Luca Weiss Reviewed-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c | 82 ++++++++++++++++++++++++++++++++ 1 file changed, 82 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c index 2eec2d78f32a..694d54341337 100644 --- a/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c +++ b/drivers/gpu/drm/msm/disp/mdp5/mdp5_cfg.c @@ -103,6 +103,87 @@ static const struct mdp5_cfg_hw msm8x74v1_config = { .max_clk = 200000000, }; +static const struct mdp5_cfg_hw msm8x26_config = { + .name = "msm8x26", + .mdp = { + .count = 1, + .caps = MDP_CAP_SMP | + 0, + }, + .smp = { + .mmb_count = 7, + .mmb_size = 4096, + .clients = { + [SSPP_VIG0] = 1, + [SSPP_DMA0] = 4, + [SSPP_RGB0] = 7, + }, + }, + .ctl = { + .count = 2, + .base = { 0x00500, 0x00600 }, + .flush_hw_mask = 0x0003ffff, + }, + .pipe_vig = { + .count = 1, + .base = { 0x01100 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SCALE | + MDP_PIPE_CAP_CSC | + 0, + }, + .pipe_rgb = { + .count = 1, + .base = { 0x01d00 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + MDP_PIPE_CAP_SCALE | + 0, + }, + .pipe_dma = { + .count = 1, + .base = { 0x02900 }, + .caps = MDP_PIPE_CAP_HFLIP | + MDP_PIPE_CAP_VFLIP | + 0, + }, + .lm = { + .count = 2, + .base = { 0x03100, 0x03d00 }, + .instances = { + { .id = 0, .pp = 0, .dspp = 0, + .caps = MDP_LM_CAP_DISPLAY, }, + { .id = 1, .pp = -1, .dspp = -1, + .caps = MDP_LM_CAP_WB }, + }, + .nb_stages = 2, + .max_width = 2048, + .max_height = 0xFFFF, + }, + .dspp = { + .count = 1, + .base = { 0x04500 }, + }, + .pp = { + .count = 1, + .base = { 0x21a00 }, + }, + .intf = { + .base = { 0x00000, 0x21200 }, + .connect = { + [0] = INTF_DISABLED, + [1] = INTF_DSI, + }, + }, + .perf = { + .ab_inefficiency = 100, + .ib_inefficiency = 200, + .clk_inefficiency = 125 + }, + .max_clk = 200000000, +}; + static const struct mdp5_cfg_hw msm8x74v2_config = { .name = "msm8x74", .mdp = { @@ -1236,6 +1317,7 @@ static const struct mdp5_cfg_hw sdm660_config = { static const struct mdp5_cfg_handler cfg_handlers_v1[] = { { .revision = 0, .config = { .hw = &msm8x74v1_config } }, + { .revision = 1, .config = { .hw = &msm8x26_config } }, { .revision = 2, .config = { .hw = &msm8x74v2_config } }, { .revision = 3, .config = { .hw = &apq8084_config } }, { .revision = 6, .config = { .hw = &msm8x16_config } }, From patchwork Thu Jun 1 17:00:12 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 689406 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D29FEC7EE31 for ; Thu, 1 Jun 2023 17:01:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232252AbjFARBS (ORCPT ); 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a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the config for the v1.0.2 DSI found on MSM8226. We can reuse existing bits from other revisions that are identical for v1.0.2. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Luca Weiss Reviewed-by: Jeykumar Sankaran --- drivers/gpu/drm/msm/dsi/dsi_cfg.c | 2 ++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + 2 files changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/dsi_cfg.c index 29ccd755cc2e..8a5fb6df7210 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -245,6 +245,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] = { &apq8064_dsi_cfg, &msm_dsi_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0, &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_0_2, + &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1, &msm8974_apq8084_dsi_cfg, &msm_dsi_6g_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V1_1_1, diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/dsi_cfg.h index 91bdaf50bb1a..43f0dd74edb6 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -11,6 +11,7 @@ #define MSM_DSI_VER_MAJOR_V2 0x02 #define MSM_DSI_VER_MAJOR_6G 0x03 #define MSM_DSI_6G_VER_MINOR_V1_0 0x10000000 +#define MSM_DSI_6G_VER_MINOR_V1_0_2 0x10000002 #define MSM_DSI_6G_VER_MINOR_V1_1 0x10010000 #define MSM_DSI_6G_VER_MINOR_V1_1_1 0x10010001 #define MSM_DSI_6G_VER_MINOR_V1_2 0x10020000 From patchwork Thu Jun 1 17:00:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 689408 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFB44C83005 for ; Thu, 1 Jun 2023 17:00:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232182AbjFARA2 (ORCPT ); Thu, 1 Jun 2023 13:00:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229598AbjFARA1 (ORCPT ); Thu, 1 Jun 2023 13:00:27 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01B72196; Thu, 1 Jun 2023 10:00:25 -0700 (PDT) Received: from [192.168.122.1] (84-115-214-73.cable.dynamic.surfer.at [84.115.214.73]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id A3F2CCFC94; Thu, 1 Jun 2023 17:00:23 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=z3ntu; t=1685638824; bh=rnv3mbRpScpgrIa7uhlioBc67H4h1mLQDF3YL9pvLZQ=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=VgXlfDS+6xyp9LhAjAJhpNDUVczXBUcfXK3Yh7P1h/Z5zwxueBPR4b3kEBMhm+Zbf oqBNxIX8zCa+IbqzMhYn4z/l/2jVuIlBvwmnRKul1m3PahQLhB/T6xhuGsX8J6AWL0 F3PPssSuIshPAX6Erdw6It0+8+E2DQF8yRqpUBAs= From: Luca Weiss Date: Thu, 01 Jun 2023 19:00:13 +0200 Subject: [PATCH v3 6/7] drm/msm/dsi: Add phy configuration for MSM8226 MIME-Version: 1.0 Message-Id: <20230308-msm8226-mdp-v3-6-b6284145d67a@z3ntu.xyz> References: <20230308-msm8226-mdp-v3-0-b6284145d67a@z3ntu.xyz> In-Reply-To: <20230308-msm8226-mdp-v3-0-b6284145d67a@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org MSM8226 uses a modified PLL lock sequence compared to MSM8974, which is based on the function dsi_pll_enable_seq_m in the msm-3.10 kernel. Worth noting that the msm-3.10 downstream kernel also will try other sequences in case this one doesn't work, but during testing it has shown that the _m sequence succeeds first time also: .pll_enable_seqs[0] = dsi_pll_enable_seq_m, .pll_enable_seqs[1] = dsi_pll_enable_seq_m, .pll_enable_seqs[2] = dsi_pll_enable_seq_d, .pll_enable_seqs[3] = dsi_pll_enable_seq_d, .pll_enable_seqs[4] = dsi_pll_enable_seq_f1, .pll_enable_seqs[5] = dsi_pll_enable_seq_c, .pll_enable_seqs[6] = dsi_pll_enable_seq_e, We may need to expand this in the future. Signed-off-by: Luca Weiss --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 3 +- drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c | 97 ++++++++++++++++++++++++++++++ 3 files changed, 101 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c index bb09cbe8ff86..9d5795c58a98 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -541,6 +541,8 @@ static const struct of_device_id dsi_phy_dt_match[] = { .data = &dsi_phy_28nm_hpm_famb_cfgs }, { .compatible = "qcom,dsi-phy-28nm-lp", .data = &dsi_phy_28nm_lp_cfgs }, + { .compatible = "qcom,dsi-phy-28nm-8226", + .data = &dsi_phy_28nm_8226_cfgs }, #endif #ifdef CONFIG_DRM_MSM_DSI_20NM_PHY { .compatible = "qcom,dsi-phy-20nm", diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h index 7137a17ae523..8b640d174785 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -46,8 +46,9 @@ struct msm_dsi_phy_cfg { extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_hpm_famb_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs; -extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_28nm_8960_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_20nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_660_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_14nm_2290_cfgs; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c index 4c1bf55c5f38..ceec7bb87bf1 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_28nm.c @@ -37,6 +37,7 @@ /* v2.0.0 28nm LP implementation */ #define DSI_PHY_28NM_QUIRK_PHY_LP BIT(0) +#define DSI_PHY_28NM_QUIRK_PHY_8226 BIT(1) #define LPFR_LUT_SIZE 10 struct lpfr_cfg { @@ -377,6 +378,74 @@ static int dsi_pll_28nm_vco_prepare_hpm(struct clk_hw *hw) return ret; } +static int dsi_pll_28nm_vco_prepare_8226(struct clk_hw *hw) +{ + struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); + struct device *dev = &pll_28nm->phy->pdev->dev; + void __iomem *base = pll_28nm->phy->pll_base; + u32 max_reads = 5, timeout_us = 100; + bool locked; + u32 val; + int i; + + DBG("id=%d", pll_28nm->phy->id); + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_CAL_CFG1, 0x34); + + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 200); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + + for (i = 0; i < 7; i++) { + /* DSI Uniphy lock detect setting */ + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, + 0x0c, 100); + dsi_phy_write(base + REG_DSI_28nm_PHY_PLL_LKDET_CFG2, 0x0d); + + /* poll for PLL ready status */ + locked = pll_28nm_poll_for_ready(pll_28nm, + max_reads, timeout_us); + if (locked) + break; + + pll_28nm_software_reset(pll_28nm); + + /* + * PLL power up sequence. + * Add necessary delays recommended by hardware. + */ + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_PWRGEN_CFG, 0x00, 50); + + val = DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B; + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B; + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 100); + + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B; + val |= DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE; + dsi_phy_write_udelay(base + REG_DSI_28nm_PHY_PLL_GLB_CFG, val, 600); + } + + if (unlikely(!locked)) + DRM_DEV_ERROR(dev, "DSI PLL lock failed\n"); + else + DBG("DSI PLL Lock success"); + + return locked ? 0 : -EINVAL; +} + static int dsi_pll_28nm_vco_prepare_lp(struct clk_hw *hw) { struct dsi_pll_28nm *pll_28nm = to_pll_28nm(hw); @@ -471,6 +540,15 @@ static const struct clk_ops clk_ops_dsi_pll_28nm_vco_lp = { .is_enabled = dsi_pll_28nm_clk_is_enabled, }; +static const struct clk_ops clk_ops_dsi_pll_28nm_vco_8226 = { + .round_rate = dsi_pll_28nm_clk_round_rate, + .set_rate = dsi_pll_28nm_clk_set_rate, + .recalc_rate = dsi_pll_28nm_clk_recalc_rate, + .prepare = dsi_pll_28nm_vco_prepare_8226, + .unprepare = dsi_pll_28nm_vco_unprepare, + .is_enabled = dsi_pll_28nm_clk_is_enabled, +}; + /* * PLL Callbacks */ @@ -536,6 +614,8 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm, struct clk_hw **prov if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_LP) vco_init.ops = &clk_ops_dsi_pll_28nm_vco_lp; + else if (pll_28nm->phy->cfg->quirks & DSI_PHY_28NM_QUIRK_PHY_8226) + vco_init.ops = &clk_ops_dsi_pll_28nm_vco_8226; else vco_init.ops = &clk_ops_dsi_pll_28nm_vco_hpm; @@ -820,3 +900,20 @@ const struct msm_dsi_phy_cfg dsi_phy_28nm_lp_cfgs = { .quirks = DSI_PHY_28NM_QUIRK_PHY_LP, }; +const struct msm_dsi_phy_cfg dsi_phy_28nm_8226_cfgs = { + .has_phy_regulator = true, + .regulator_data = dsi_phy_28nm_regulators, + .num_regulators = ARRAY_SIZE(dsi_phy_28nm_regulators), + .ops = { + .enable = dsi_28nm_phy_enable, + .disable = dsi_28nm_phy_disable, + .pll_init = dsi_pll_28nm_init, + .save_pll_state = dsi_28nm_pll_save_state, + .restore_pll_state = dsi_28nm_pll_restore_state, + }, + .min_pll_rate = VCO_MIN_RATE, + .max_pll_rate = VCO_MAX_RATE, + .io_start = { 0xfd922b00 }, + .num_dsi_phy = 1, + .quirks = DSI_PHY_28NM_QUIRK_PHY_8226, +}; From patchwork Thu Jun 1 17:00:14 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Luca Weiss X-Patchwork-Id: 687786 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CB5FBC7EE32 for ; Thu, 1 Jun 2023 17:00:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232218AbjFARAb (ORCPT ); Thu, 1 Jun 2023 13:00:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232160AbjFARA1 (ORCPT ); Thu, 1 Jun 2023 13:00:27 -0400 Received: from mail.z3ntu.xyz (mail.z3ntu.xyz [128.199.32.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C5E6CD1; Thu, 1 Jun 2023 10:00:26 -0700 (PDT) Received: from [192.168.122.1] (84-115-214-73.cable.dynamic.surfer.at [84.115.214.73]) by mail.z3ntu.xyz (Postfix) with ESMTPSA id 70759CFC95; Thu, 1 Jun 2023 17:00:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=z3ntu.xyz; s=z3ntu; t=1685638825; bh=eKeJWu3f/K9fInmraz7fujMKEyoO5YqMeg0ocfPUaZk=; h=From:Date:Subject:References:In-Reply-To:To:Cc; b=pjAzBJB1NE9OKSaN9I3P20sycTyjb6pXf0Mw4byihxdSSGCuP2ZBjfRNv3CFxz1P6 HEc1M9yG9XlckffcoObCzgxTz2SNQx3wZB3yFl5vmjXRRr+1raQdOyNZ3tMQIPcBoN fSqf27cw0X0+JqnMeQ4Lrpu7+W6o7m/4PNo1teJM= From: Luca Weiss Date: Thu, 01 Jun 2023 19:00:14 +0200 Subject: [PATCH v3 7/7] ARM: dts: qcom: msm8226: Add mdss nodes MIME-Version: 1.0 Message-Id: <20230308-msm8226-mdp-v3-7-b6284145d67a@z3ntu.xyz> References: <20230308-msm8226-mdp-v3-0-b6284145d67a@z3ntu.xyz> In-Reply-To: <20230308-msm8226-mdp-v3-0-b6284145d67a@z3ntu.xyz> To: ~postmarketos/upstreaming@lists.sr.ht, phone-devel@vger.kernel.org, Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , David Airlie , Daniel Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Andy Gross , Bjorn Andersson , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=3498; i=luca@z3ntu.xyz; h=from:subject:message-id; bh=eKeJWu3f/K9fInmraz7fujMKEyoO5YqMeg0ocfPUaZk=; b=owEBbQKS/ZANAwAIAXLYQ7idTddWAcsmYgBkeM6h05rTstajjbAt+kVtioKTNC37puxYbWPQm BTuFhUuiQuJAjMEAAEIAB0WIQQ5utIvCCzakboVj/py2EO4nU3XVgUCZHjOoQAKCRBy2EO4nU3X Vv4hD/0WEov8+ZNLq0Q5ol0zU/7j43NKM1dVC6HyNyEHS5sRr4q3y8LKlQ/m3lzk2eKq89I6Zoa 0wA+H6g00UjIjDShXCCNLa/I0XkuwuGb4nXsF5fX/8OmCwRBBQX5XaP2m3DlkWivhe7xEj4qw+6 BoKeBzDn/g+lFAUKX8+616t3lCvpK1BRatKOMfqMnikGKSji0DdKH8ODP2qH0LsmmQETwEg4jb5 qQxBSRJ1vZf/OE9B7RVyCQTzimae1j++fugad5zuBDXLzgzJJDclMzlORxZr+k2hNuJM5GihgO7 IxNGErKKY7PTyfXRC2Zirh9PwcGbY3zX6tJ6uQbKDwRA8GzJ0g4Ib9DXegvW8Iloex7kvC3HZXi uZ68MJxFjDXvR/KpKQwoRppp6tJX8lRvivMnYa8zqJT3c/uetq1zkpedfG2Slas0QQxEK2WYCWY bVZk/gxbJpVOdfERXlpFbK/9m7/7Zn0yiN9csQ0R77W+dXgm1d8VlsNdTU3EHgHthNYS/Ymsxwr q/3qCeNr8VE/vRHDnVoEPIHEd9G1D9FxxWYSbr2/hcnm+LpucX2G4ENbWCp/64eFfLJLQfcuzOT PVe3yL89QxXqgV14B1ATyLSlO2TqQdhRgUNAnhhbJOOgXeO9dTc1ztTtmd1WoA0wqdjtRP8UIkW WgdUOM8ZyUlSCwA== X-Developer-Key: i=luca@z3ntu.xyz; a=openpgp; fpr=BD04DA24C971B8D587B2B8D7FAF69CF6CD2D02CD Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add the nodes that describe the mdss so that display can work on MSM8226. Signed-off-by: Luca Weiss --- arch/arm/boot/dts/qcom-msm8226.dtsi | 127 ++++++++++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/arch/arm/boot/dts/qcom-msm8226.dtsi b/arch/arm/boot/dts/qcom-msm8226.dtsi index 42acb9ddb8cc..9f53747d2990 100644 --- a/arch/arm/boot/dts/qcom-msm8226.dtsi +++ b/arch/arm/boot/dts/qcom-msm8226.dtsi @@ -636,6 +636,133 @@ smd-edge { label = "lpass"; }; }; + + mdss: display-subsystem@fd900000 { + compatible = "qcom,mdss"; + reg = <0xfd900000 0x100>, <0xfd924000 0x1000>; + reg-names = "mdss_phys", "vbif_phys"; + + power-domains = <&mmcc MDSS_GDSC>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "vsync"; + + interrupts = ; + + interrupt-controller; + #interrupt-cells = <1>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@fd900000 { + compatible = "qcom,msm8226-mdp5", "qcom,mdp5"; + reg = <0xfd900100 0x22000>; + reg-names = "mdp_phys"; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_VSYNC_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_mdp_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + }; + }; + + mdss_dsi0: dsi@fd922800 { + compatible = "qcom,msm8226-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0xfd922800 0x1f8>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + assigned-clocks = <&mmcc BYTE0_CLK_SRC>, + <&mmcc PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>; + + clocks = <&mmcc MDSS_MDP_CLK>, + <&mmcc MDSS_AHB_CLK>, + <&mmcc MDSS_AXI_CLK>, + <&mmcc MDSS_BYTE0_CLK>, + <&mmcc MDSS_PCLK0_CLK>, + <&mmcc MDSS_ESC0_CLK>, + <&mmcc MMSS_MISC_AHB_CLK>; + clock-names = "mdp_core", + "iface", + "bus", + "byte", + "pixel", + "core", + "core_mmss"; + + phys = <&mdss_dsi0_phy>; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&mdss_mdp_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + }; + + mdss_dsi0_phy: phy@fd922a00 { + compatible = "qcom,dsi-phy-28nm-8226"; + reg = <0xfd922a00 0xd4>, + <0xfd922b00 0x280>, + <0xfd922d80 0x30>; + reg-names = "dsi_pll", + "dsi_phy", + "dsi_phy_regulator"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&mmcc MDSS_AHB_CLK>, + <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "iface", + "ref"; + }; + }; }; timer {