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[209.51.188.17]) by mx.google.com with ESMTPS id dy30-20020a05620a60de00b007591606f36csi8525326qkb.696.2023.05.31.13.36.40 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 May 2023 13:36:40 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=w4dI9igE; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q4SYL-00078f-6b; Wed, 31 May 2023 16:36:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4SYF-00075O-WD for qemu-devel@nongnu.org; Wed, 31 May 2023 16:36:12 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q4SYE-0003AO-DB for qemu-devel@nongnu.org; Wed, 31 May 2023 16:36:11 -0400 Received: by mail-wm1-x333.google.com with SMTP id 5b1f17b1804b1-3f606912ebaso939665e9.3 for ; Wed, 31 May 2023 13:36:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685565368; x=1688157368; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=axVpU0i2p75LH2asCUomaSunVbrAGYJD7scBST0rZU4=; b=w4dI9igElL4S66mQ9PeZEGHEm2TRMeJISnLQ4j/7gJEv3yMR/8O/7L9VTf1mCwuHGy WXfNkzEDJGcf31Zj33BP1CWpJcEMpLeMfvsaSZDhD+3iWFRk1rDCv+e52/g8+bhLU6P+ PMVQvY3Urrs/G67vF7kmvVbu6vhXSTGbgIs50uwb90KOEcQ+uHR/soR2MilbxHIqAw7K g5IjRF9dxWIpcbwDfUa03Uhw4qsA4QiBc6aJM9HkGnDpuNF/xllFbfiXygllika60PS5 FRtxwwrTAE+MzNjqIr36N6rFSz0MjL1AEqiptgTt0sDtF0kR1tCGo83p3/iKrh2NcSsy hd6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685565368; x=1688157368; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=axVpU0i2p75LH2asCUomaSunVbrAGYJD7scBST0rZU4=; b=lGnOlXgeaJxF4psj/qP8rCqQG2PEx6fg9sNgKY10GYlh3dxj0JY/Croh/Kqw0IMTQo YFYke0lBvj34tYL+DNrOlH+c+qjH74ytwviDdGlTcTSJSVMx69aIdUMkkZW4dnREknKz cDU+cX2zyvUbQhPPgEzBBPbaSuVYujOemdd9IM3OjWVe2otDmEKqCgVLbZLQinMAIWZR Rk19kwj6kyNvlzXst75pF7WNpDWD6skzmOhwTDCkpZ0Cvgy5fXU0fgtkxhkkUNgKBQ2j 8h5l7Kb257JHh0edWJkWGkb3TF8izAeupZuYoUJOzzV0qf2Qbwca150pMKRzd4O3wAra PIHw== X-Gm-Message-State: AC+VfDzOYFOuTma1c2XgOR1JIay8BYkcjl8NVlWj/QKCMrFdup0AnEBz MzY9DDtN4cBKRtZ7jvgEunjL7jeqO6uq3E3qt2w= X-Received: by 2002:a7b:ce91:0:b0:3f6:89a:94c8 with SMTP id q17-20020a7bce91000000b003f6089a94c8mr301976wmj.24.1685565368541; Wed, 31 May 2023 13:36:08 -0700 (PDT) Received: from localhost.localdomain ([176.176.146.12]) by smtp.gmail.com with ESMTPSA id i7-20020a05600c290700b003f42d8dd7ffsm21935638wmd.19.2023.05.31.13.36.07 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 31 May 2023 13:36:08 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 01/15] hw/timer/arm_timer: Declare QOM types using DEFINE_TYPES() macro Date: Wed, 31 May 2023 22:35:45 +0200 Message-Id: <20230531203559.29140-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230531203559.29140-1-philmd@linaro.org> References: <20230531203559.29140-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=philmd@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org When multiple QOM types are registered in the same file, it is simpler to use the the DEFINE_TYPES() macro. Replace the type_init() / type_register_static() combination. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/timer/arm_timer.c | 35 +++++++++++++++-------------------- 1 file changed, 15 insertions(+), 20 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 69c8863472..e410b37a23 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -380,13 +380,6 @@ static void icp_pit_init(Object *obj) save themselves. */ } -static const TypeInfo icp_pit_info = { - .name = TYPE_INTEGRATOR_PIT, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(icp_pit_state), - .instance_init = icp_pit_init, -}; - static Property sp804_properties[] = { DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), @@ -402,18 +395,20 @@ static void sp804_class_init(ObjectClass *klass, void *data) k->vmsd = &vmstate_sp804; } -static const TypeInfo sp804_info = { - .name = TYPE_SP804, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(SP804State), - .instance_init = sp804_init, - .class_init = sp804_class_init, +static const TypeInfo arm_timer_types[] = { + { + .name = TYPE_INTEGRATOR_PIT, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(icp_pit_state), + .instance_init = icp_pit_init, + + }, { + .name = TYPE_SP804, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SP804State), + .instance_init = sp804_init, + .class_init = sp804_class_init, + } }; -static void arm_timer_register_types(void) -{ - type_register_static(&icp_pit_info); - type_register_static(&sp804_info); -} - -type_init(arm_timer_register_types) +DEFINE_TYPES(arm_timer_types) From patchwork Wed May 31 20:35:46 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687304 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1459304wru; Wed, 31 May 2023 13:37:14 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5uxFCKUDNf1dAyzsNjbuOFl9lF8UnPyNmOIdQi0PPp8xLXGjnVKPNb8LGgZ4xz0MJF1EsJ X-Received: by 2002:ac8:594d:0:b0:3dc:fa58:97fd with SMTP id 13-20020ac8594d000000b003dcfa5897fdmr7943885qtz.25.1685565413232; Wed, 31 May 2023 13:36:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685565413; cv=none; d=google.com; s=arc-20160816; b=Rhcfm/XO+wU2M0CSmMhXsruWSoINzxEZxpCa+1ZBDGDlYXtO4tOgd1010VQgUY+FUg y7sq/CKfoxyq1NuzqN4Ee7cWCUsQ4F7H5iR0Yuci3i6ZYNd4vFu0j4xH12vbFbN1wE7l amzdXPUE0MA3p5Frgr8W4deQprBjlu5Lx0f8RcVXxhfkiem3bc9Fo5Q4Axk32oF2t8Si VzQ0CcEP3VM9+xzYuCVL48B2bBwdf2xFb/4OsvR4yVcg9RwAUtliCi3/jCKgWrJEJP2/ jAfHCn8lxx2+S03TYHUR2yv7HoDxFZWV+q1ZZsmwCaJJbH8fE4Peq3o9KFjMjoHntzZ1 QUNg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=C6ZS1kmk8mZOQBkFwaVnQN91jrsnv+kxH/BK7lbOklA=; b=fPEvDTazJFRGiCYw/UTOYwobXCcMB4MsQkz3u1eRy0CZlh26xf+Yv3t5gLmjmQF8ao 6loVAcKVCdc94JdFASyYHXKp2c5ER9PXX+Nt4kdEgWb1NvxFlMVF3fZ06IFpyS5YUCza pQq8qqMKlNOahGZcN7PbeZQ0XbyFwHIxgC6KPYYAwPlwTdrfQ+k96FPxupVT4L8bbNlR Nz8PXLOvjYfDdakAU7cctiZ75yzZ9ZoAGWmCNebEJ/9Iu70vG5l3rIUcPQ6IWupTmZ3j YFgg/5sG9vnDzNr27hKcdxMO8FX8i0ryXtUjN4oFTzl9qheZh1Oobcwyufx566PjH4Wz OG1g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=LAa9SCOi; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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What follows the "Integrator/CP timer module." is strictly ICP related. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/timer/arm_timer.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index e410b37a23..36f6586f80 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -309,6 +309,21 @@ static void sp804_realize(DeviceState *dev, Error **errp) s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); } +static Property sp804_properties[] = { + DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), + DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sp804_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *k = DEVICE_CLASS(klass); + + k->realize = sp804_realize; + device_class_set_props(k, sp804_properties); + k->vmsd = &vmstate_sp804; +} + /* Integrator/CP timer module. */ #define TYPE_INTEGRATOR_PIT "integrator_pit" @@ -380,21 +395,6 @@ static void icp_pit_init(Object *obj) save themselves. */ } -static Property sp804_properties[] = { - DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), - DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), - DEFINE_PROP_END_OF_LIST(), -}; - -static void sp804_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *k = DEVICE_CLASS(klass); - - k->realize = sp804_realize; - device_class_set_props(k, sp804_properties); - k->vmsd = &vmstate_sp804; -} - static const TypeInfo arm_timer_types[] = { { .name = TYPE_INTEGRATOR_PIT, From patchwork Wed May 31 20:35:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687307 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1459509wru; Wed, 31 May 2023 13:37:50 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5oaJAf6w/ejHQ1kEsyPuYvrpwGX/zYuDDRd4mFaIrzAiUQYIR5ZmILGwf2vmh/WKpUsLWS X-Received: by 2002:a05:620a:3b17:b0:75b:23a1:445 with SMTP id tl23-20020a05620a3b1700b0075b23a10445mr5583530qkn.11.1685565470006; Wed, 31 May 2023 13:37:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685565469; cv=none; d=google.com; s=arc-20160816; b=mrFhtU8L5CCLvee1RzpkDeN4L9sKqmVwtFut45D/wr1hUG/n0VEajNL+DzjBF9O9Uv Grgxgo/DATwJTxCnLAhn7crr6GBEGMVFXtADJUXRpWuT+iee8V0NGJ+mmX0DBp3+5gri FQF1EKNISgL/pQQBRA2byMHkNrnHNQTBgQ6zkhoXX2TzjnHMz795juYbWQA+EMSLpeiB tqJyzR0Tpm6tm/Lb1cBXncX20rAj3GLbZ0GdAc1rvIad5VYhhC3lnneOSKnILhZMYwn3 xojaAuk9rinMe7T7ehrx8znyaYjTUIsGHUQHvTxbdIahHzjc2tne8yZho+AdACyPZ5dN Dchg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=E5b8V9q6QA/WPM4HyTDg8f1UskvZE7C+FUlDujJKJpg=; b=D3f3UzRoTNX2pMbxkXcqIzNH89YJAoRHHHHV8HswuRVx14Hpal+q0UP5yvdRkXvXq/ fRBqzWdZE41kqQevMl2E7MWhv8D7jtgfi3hkN0bEetwiksrnf+i41qoY18uzTwdL5PRj CfdZnWn1AHIqwAMiXi+a4JfHBAtcc9Rx9SX6gY6xz9efl5GFVLB8Re+Z1StfCBliO0tM LEFcjssv0sndOX86RW6YEBPLktvKkS7apkB46Q0kvufrz12bzyKi0/xsOlYFCbVQnnzV JhD2kkmscNeHb1EJFwMMgmkS9ASJkAptSGU4mnBscKQh5ADt8q5Lp1qabcjFm/NV6RWR tAow== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=X5nVFwk1; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/arm_timer.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 36f6586f80..5caf42649a 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -309,6 +309,15 @@ static void sp804_realize(DeviceState *dev, Error **errp) s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); } +static void sp804_unrealize(DeviceState *dev) +{ + SP804State *s = SP804(dev); + + for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { + qemu_free_irq(s->timer[i]->irq); + } +} + static Property sp804_properties[] = { DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), @@ -320,6 +329,7 @@ static void sp804_class_init(ObjectClass *klass, void *data) DeviceClass *k = DEVICE_CLASS(klass); k->realize = sp804_realize; + k->unrealize = sp804_unrealize; device_class_set_props(k, sp804_properties); k->vmsd = &vmstate_sp804; } From patchwork Wed May 31 20:35:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687309 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1459701wru; Wed, 31 May 2023 13:38:22 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ54khgZZ9Jpb5/bXE4iJbUZlJdYiPNUDBUA9hc9Dfb8suIe9MYNvAZcfEq0S7gpJz9ekUoY X-Received: by 2002:ad4:5d46:0:b0:621:363c:ea9f with SMTP id jk6-20020ad45d46000000b00621363cea9fmr10375852qvb.19.1685565501811; Wed, 31 May 2023 13:38:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685565501; cv=none; d=google.com; s=arc-20160816; b=Vc2ZsuL43uzFP21EHqQlD1aTmcLMEZfO9dWK0xm4aBwFgaqjGugtQm/jiGW60ee/Yq WU4FcOz2haWsnOQizL1CYcZu8QnZzhWh6b51Yfp8RiiFIei+xZfMrOwkHifQGU8LG4VQ jJavijHtwf3gfmEGPaX7W96xYEZciPfUfp0Ts8LTV6qfuVgEcp+dX5ue2HvKh9SMStgZ zP1DAlFp8MbA6AEpZOpb9y1mtIuuXXGw4kesUnxW4lneLDSylmIOW/19IlA7rYlm4gH2 f8oJ1RKKT6PRopGykfvhOiMtjnjQYc/JjN5nu5G63T0eBOx+GHHNGzvqTsfaxbOFRNU+ qvNA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=RDY2GDiaOE1sTafU5g56yTJAkbGCsjHJ/M+/hUiSBu4=; b=Hb1f+snQA4qHZ2uEuMJvAeAzO0+ihDdeohaXKgngZ6D4Fm+AmiBilGLYVQyEiERkXT EdRZVxoFaiFIcXPzUk5c8ReQH844NCDW9GrDt2Sfjcmiau6VFLvwHBHCCi87IXw1Qxfz tL0cKzWSyD0P1lQMc1GKqzNiA+4wSH2YHWA40AHK6Wj4v9nq1Frh9FAhuB/YFNH0itZs 0RmEwh7yb6ybZ2psC1t0lKFw5ZtVqbxCmyfq4nDo5QjbRVl3ul6FEisPxL7Lw6pINmy4 zcRU/wb8Nf6wwI8+gq/B+WecewD91i2iSdVK6Ip0TxNmx08fC5VzPhStMBOZsGleUEIe cQvw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=IHo+kDOw; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Wed, 31 May 2023 13:36:24 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 04/15] hw/timer/arm_timer: Remove pointless cast from void * Date: Wed, 31 May 2023 22:35:48 +0200 Message-Id: <20230531203559.29140-5-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230531203559.29140-1-philmd@linaro.org> References: <20230531203559.29140-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/timer/arm_timer.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 5caf42649a..3dda3a73f8 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -52,7 +52,7 @@ static void arm_timer_update(arm_timer_state *s) static uint32_t arm_timer_read(void *opaque, hwaddr offset) { - arm_timer_state *s = (arm_timer_state *)opaque; + arm_timer_state *s = opaque; switch (offset >> 2) { case 0: /* TimerLoad */ @@ -99,7 +99,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload) static void arm_timer_write(void *opaque, hwaddr offset, uint32_t value) { - arm_timer_state *s = (arm_timer_state *)opaque; + arm_timer_state *s = opaque; int freq; switch (offset >> 2) { @@ -154,7 +154,7 @@ static void arm_timer_write(void *opaque, hwaddr offset, static void arm_timer_tick(void *opaque) { - arm_timer_state *s = (arm_timer_state *)opaque; + arm_timer_state *s = opaque; s->int_level = 1; arm_timer_update(s); } @@ -214,7 +214,7 @@ static const uint8_t sp804_ids[] = { /* Merge the IRQs from the two component devices. */ static void sp804_set_irq(void *opaque, int irq, int level) { - SP804State *s = (SP804State *)opaque; + SP804State *s = opaque; s->level[irq] = level; qemu_set_irq(s->irq, s->level[0] || s->level[1]); @@ -223,7 +223,7 @@ static void sp804_set_irq(void *opaque, int irq, int level) static uint64_t sp804_read(void *opaque, hwaddr offset, unsigned size) { - SP804State *s = (SP804State *)opaque; + SP804State *s = opaque; if (offset < 0x20) { return arm_timer_read(s->timer[0], offset); @@ -255,7 +255,7 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, static void sp804_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - SP804State *s = (SP804State *)opaque; + SP804State *s = opaque; if (offset < 0x20) { arm_timer_write(s->timer[0], offset, value); @@ -349,7 +349,7 @@ struct icp_pit_state { static uint64_t icp_pit_read(void *opaque, hwaddr offset, unsigned size) { - icp_pit_state *s = (icp_pit_state *)opaque; + icp_pit_state *s = opaque; int n; /* ??? Don't know the PrimeCell ID for this device. */ @@ -365,7 +365,7 @@ static uint64_t icp_pit_read(void *opaque, hwaddr offset, static void icp_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - icp_pit_state *s = (icp_pit_state *)opaque; + icp_pit_state *s = opaque; int n; n = offset >> 8; From patchwork Wed May 31 20:35:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687317 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1460425wru; Wed, 31 May 2023 13:40:27 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6VnHwonkjXGFLoqpmymp00UHxEdXTBjEktI0gUc4RnVyoyfWOAbJYEtV4ye09aNboJ8Tqw X-Received: by 2002:a05:6214:1c48:b0:5f7:8b31:4522 with SMTP id if8-20020a0562141c4800b005f78b314522mr7875754qvb.5.1685565626773; Wed, 31 May 2023 13:40:26 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685565626; cv=none; d=google.com; s=arc-20160816; b=frKbbKOnZC4euWuEPXkisuuKWd4BztBMxVIkrOa9OlOR8Faj7e15816l6pkMhNDt2r Ua4sqskGu4E2AqlHvzjHdJELyeDaU5DQscN/hL7ryi6/cYVIJYpntYLah3YzrMKvI46T D5qLqsfAXNGkhpmBOLJpatgnz51VymPEAPeP8hkxNZhJjqaSviIlSS4Rr1ARsPYpt4s7 8K+gmsjjT8MUG/9gox1IaLvZNRE16IbZMFoPSZbCDFRdovSr1+t2TrZCw/6otm9kbKSt QJppqcvMfs5tS0ifWDh1+1Ciza9waiBlIYq5VnBz+G4KTAa4+P3Y9qH5fzd9H6rIppCa lDRw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=+bApdHpHvphQGH6iJkkAkav6K47Z8aVKSZsLKgEzGjI=; b=0OS4Jcm5kFgxjZHhlGs/K95Xcobuo+I7c9YeEX2w1aDPaGarI3M586cuQ/NWehOXTF AuDqbl/PKjMMhzSzEADpDNWIAhcCkBcunGjzipKaBB4Wd+KXzU9WX+ViM5IvGqpioIr/ BJqynNrAA3hBb1h2/RC/s7sAj6KNuYs0GMRH8YUBJD8O7Bjfa1jC1VcpdhhTPu0g91Ze C183fyBnZc8xxKu5AAGKxm+scooSqB3EVsC5RYp69MKBPay/aghxjO8MyxTvut9JDM73 xVJfroo+fJ4kTYws1MwKLL2IAubpfCZ2JG3OWHsaqBQRmB0GffkzpItjscvGOoPUilJE +Gqg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SjC2KJW2; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/timer/arm_timer.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 3dda3a73f8..fc8d25b0dc 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -337,9 +337,9 @@ static void sp804_class_init(ObjectClass *klass, void *data) /* Integrator/CP timer module. */ #define TYPE_INTEGRATOR_PIT "integrator_pit" -OBJECT_DECLARE_SIMPLE_TYPE(icp_pit_state, INTEGRATOR_PIT) +OBJECT_DECLARE_SIMPLE_TYPE(IntegratorPitState, INTEGRATOR_PIT) -struct icp_pit_state { +struct IntegratorPitState { SysBusDevice parent_obj; MemoryRegion iomem; @@ -349,7 +349,7 @@ struct icp_pit_state { static uint64_t icp_pit_read(void *opaque, hwaddr offset, unsigned size) { - icp_pit_state *s = opaque; + IntegratorPitState *s = opaque; int n; /* ??? Don't know the PrimeCell ID for this device. */ @@ -365,7 +365,7 @@ static uint64_t icp_pit_read(void *opaque, hwaddr offset, static void icp_pit_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - icp_pit_state *s = opaque; + IntegratorPitState *s = opaque; int n; n = offset >> 8; @@ -385,7 +385,7 @@ static const MemoryRegionOps icp_pit_ops = { static void icp_pit_init(Object *obj) { - icp_pit_state *s = INTEGRATOR_PIT(obj); + IntegratorPitState *s = INTEGRATOR_PIT(obj); SysBusDevice *dev = SYS_BUS_DEVICE(obj); /* Timer 0 runs at the system clock speed (40MHz). */ @@ -409,7 +409,7 @@ static const TypeInfo arm_timer_types[] = { { .name = TYPE_INTEGRATOR_PIT, .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(icp_pit_state), + .instance_size = sizeof(IntegratorPitState), .instance_init = icp_pit_init, }, { From patchwork Wed May 31 20:35:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687306 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1459493wru; Wed, 31 May 2023 13:37:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6eQSNiztIWvPYwOgDcGq5tEdG+s070ToQJN7KzLo5ckRGADUlqD9iocMULwI+QW7NVJ3OU X-Received: by 2002:a05:6214:300b:b0:616:7a62:a7d0 with SMTP id ke11-20020a056214300b00b006167a62a7d0mr7351894qvb.16.1685565467241; Wed, 31 May 2023 13:37:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685565467; cv=none; d=google.com; s=arc-20160816; b=OVyNrFK4+RhL1At6hj+BXg4IPcSHXOsXsbce8Tv7h1Oe0si118x67l2x9J/fIONaiR xsoOYBTvNxaiQrrap7V9CUIOZcOWy7ntMXaj4+igskL6pAfSiWvdWxmgZJtrOICFCoNK mLTiR0OfocXPKp0LzlZKSJoDE+hAyJWtANv9J/dX290xKgqh1IPEwXJ7IyTYUd/J8L0a yy5awIT/v6Ko7cAd81QGzCgUP5pdNpXIgB6ukAxdu9fXaBIhXn/zvz1UIsVloAlXL9g2 3AIq0BWXA/wOCJ24o980tk7BtNgm9q9tSNoGTSLKRMpB6mGY4DT/0rPbQtV8uWZ9uS2y 0PPw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=MVO2YZhj70IQRx0DkEHrVUKir9ojXgRvhsJpsCyyon4=; b=EYkUuO9lFITT9PR5+Aawmzs6hkdmJqvaPP2pAq7PUIafDSGvR49Iy3Oqw5xqrAQlih pLrrDiaIfhYsYVRQPcevs4FADGdFs7CSeKKqeqa+YXSODUJsKkwp10jHvqZRG0vaumJ9 5/h19Wsfq8LoX5n1QWVol2qmhIR8MCoouyXckuWI1T+EWxRI7DxAvV0wDZGlPJVblkFW 11B/PaL1wAW1v8c0VY/jbmsb70HnZqfBYPwh7HLMhBDJw8a97u4+Y+mJbGBtY4DleoZS bOoJ/WKCa8GKu6fXPb420vJaISNvi6CbZtKBXYfCOeJ+GZj2eBWsLLXzKA09eVZncCuZ FQTQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YXn2bcH5; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/timer/arm_timer.c | 30 +++++++++++++++--------------- 1 file changed, 15 insertions(+), 15 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index fc8d25b0dc..2cd8c99b4e 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -36,11 +36,11 @@ typedef struct { int freq; int int_level; qemu_irq irq; -} arm_timer_state; +} ArmTimerState; /* Check all active timers, and schedule the next timer interrupt. */ -static void arm_timer_update(arm_timer_state *s) +static void arm_timer_update(ArmTimerState *s) { /* Update interrupts. */ if (s->int_level && (s->control & TIMER_CTRL_IE)) { @@ -52,7 +52,7 @@ static void arm_timer_update(arm_timer_state *s) static uint32_t arm_timer_read(void *opaque, hwaddr offset) { - arm_timer_state *s = opaque; + ArmTimerState *s = opaque; switch (offset >> 2) { case 0: /* TimerLoad */ @@ -79,7 +79,7 @@ static uint32_t arm_timer_read(void *opaque, hwaddr offset) * Reset the timer limit after settings have changed. * May only be called from inside a ptimer transaction block. */ -static void arm_timer_recalibrate(arm_timer_state *s, int reload) +static void arm_timer_recalibrate(ArmTimerState *s, int reload) { uint32_t limit; @@ -99,7 +99,7 @@ static void arm_timer_recalibrate(arm_timer_state *s, int reload) static void arm_timer_write(void *opaque, hwaddr offset, uint32_t value) { - arm_timer_state *s = opaque; + ArmTimerState *s = opaque; int freq; switch (offset >> 2) { @@ -154,7 +154,7 @@ static void arm_timer_write(void *opaque, hwaddr offset, static void arm_timer_tick(void *opaque) { - arm_timer_state *s = opaque; + ArmTimerState *s = opaque; s->int_level = 1; arm_timer_update(s); } @@ -164,19 +164,19 @@ static const VMStateDescription vmstate_arm_timer = { .version_id = 1, .minimum_version_id = 1, .fields = (VMStateField[]) { - VMSTATE_UINT32(control, arm_timer_state), - VMSTATE_UINT32(limit, arm_timer_state), - VMSTATE_INT32(int_level, arm_timer_state), - VMSTATE_PTIMER(timer, arm_timer_state), + VMSTATE_UINT32(control, ArmTimerState), + VMSTATE_UINT32(limit, ArmTimerState), + VMSTATE_INT32(int_level, ArmTimerState), + VMSTATE_PTIMER(timer, ArmTimerState), VMSTATE_END_OF_LIST() } }; -static arm_timer_state *arm_timer_init(uint32_t freq) +static ArmTimerState *arm_timer_init(uint32_t freq) { - arm_timer_state *s; + ArmTimerState *s; - s = g_new0(arm_timer_state, 1); + s = g_new0(ArmTimerState, 1); s->freq = freq; s->control = TIMER_CTRL_IE; @@ -198,7 +198,7 @@ struct SP804State { SysBusDevice parent_obj; MemoryRegion iomem; - arm_timer_state *timer[2]; + ArmTimerState *timer[2]; uint32_t freq0, freq1; int level[2]; qemu_irq irq; @@ -343,7 +343,7 @@ struct IntegratorPitState { SysBusDevice parent_obj; MemoryRegion iomem; - arm_timer_state *timer[3]; + ArmTimerState *timer[3]; }; static uint64_t icp_pit_read(void *opaque, hwaddr offset, From patchwork Wed May 31 20:35:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687316 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1460369wru; Wed, 31 May 2023 13:40:18 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6yZhTdPmdrjKXWw9naP0kPB6TcoJMrt13nsTqjdeiNxw4UuezD48Grzzg0kV5VIqrdT/vF X-Received: by 2002:a05:620a:84c3:b0:75b:23a0:d9c9 with SMTP id pq3-20020a05620a84c300b0075b23a0d9c9mr7329963qkn.31.1685565618592; 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This will become our DeviceReset handler. Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/arm_timer.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 2cd8c99b4e..54318d0a57 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -172,13 +172,18 @@ static const VMStateDescription vmstate_arm_timer = { } }; +static void arm_timer_reset(ArmTimerState *s) +{ + s->control = TIMER_CTRL_IE; +} + static ArmTimerState *arm_timer_init(uint32_t freq) { ArmTimerState *s; s = g_new0(ArmTimerState, 1); s->freq = freq; - s->control = TIMER_CTRL_IE; + arm_timer_reset(s); s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_LEGACY); vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_arm_timer, s); From patchwork Wed May 31 20:35:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687310 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1459989wru; Wed, 31 May 2023 13:39:09 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7IEMEr1zFoQkTEtzJB/gHC1rnPSzGeKwD9z9eDAYGIx5JAKpukH+TRtx5eVCoOxDcJ0ALv X-Received: by 2002:a05:6214:230f:b0:621:1808:e93a with SMTP id gc15-20020a056214230f00b006211808e93amr7283969qvb.42.1685565548896; Wed, 31 May 2023 13:39:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685565548; cv=none; d=google.com; s=arc-20160816; b=AV7rbdqr6nILhDkMSJDbFYx3mHsU9acpiil1gc51IxnV9rIRWgL5hAIlb9Gu+m4ibi NkYn5EdiUhOaUNQTITeWWe0x4t+gU9gnjAZCMUGKmpxmUZYAa5ePnpy3t4fsJwEVjJlG ghOsBDNL3HeFTFABRlu0nBTwyK15r+TIuPcdNLpWaRDhbtwNremwNUad3hzsXX8AFtZ6 8ai1rKyhzfiF7fJ4mHi9RSZSagMUvTTYPNde/Kj7XG9/DorUjjfZVFjngDG2qMwoBCw3 8VKKcS4vtQR5nuJBb9eYfhm9Q+yg+e6SkBZJcGbivwkfI0B3m3WRwF05rXRJvLkcsc4l kI2A== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cqmxkSyXDcjXzwtphH1bFAgAKMWrKTeKoHsfOWjfasw=; b=WEYvgTeqbtiS8jMReRUSvlNQMq1aGOXx0v0NjTA74NroGEiQ38pEZXL7Fs/jdcaPf5 QLZcfPVf/TQ++zwH5sK1ViENXgoeNA9NK0jOw3ZWYapRQSIIK7KLXNJyb/aJDjOJejii vPrACmogIVP4vQ1Q0jyaFLtltoEObSyFCpG5bVR9uO5uFMr089PRAhMTwWfLPDoMXnit JXkHr1ZRwGZwoYsNoPtO+9SV+7ZLfGTpT1Z7ViqyNyXoznqcvAFocZa8WYX/VpKXBNr4 2q1qUTx3tanOmPCwOuQLEVvXnZc+wb9V8hTmlA+jGMNeyP0WJkcB9WdPG+A6OGBtU3o9 u3Pg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=fpTM2ur8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Here arm_timer_init() is a such combination, so rename it as arm_timer_new() to emphasis the returned device is already realized. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/timer/arm_timer.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 54318d0a57..1f4d66291a 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -177,7 +177,7 @@ static void arm_timer_reset(ArmTimerState *s) s->control = TIMER_CTRL_IE; } -static ArmTimerState *arm_timer_init(uint32_t freq) +static ArmTimerState *arm_timer_new(uint32_t freq) { ArmTimerState *s; @@ -308,8 +308,8 @@ static void sp804_realize(DeviceState *dev, Error **errp) { SP804State *s = SP804(dev); - s->timer[0] = arm_timer_init(s->freq0); - s->timer[1] = arm_timer_init(s->freq1); + s->timer[0] = arm_timer_new(s->freq0); + s->timer[1] = arm_timer_new(s->freq1); s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0); s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); } @@ -394,10 +394,10 @@ static void icp_pit_init(Object *obj) SysBusDevice *dev = SYS_BUS_DEVICE(obj); /* Timer 0 runs at the system clock speed (40MHz). */ - s->timer[0] = arm_timer_init(40000000); + s->timer[0] = arm_timer_new(40000000); /* The other two timers run at 1MHz. */ - s->timer[1] = arm_timer_init(1000000); - s->timer[2] = arm_timer_init(1000000); + s->timer[1] = arm_timer_new(1000000); + s->timer[2] = arm_timer_new(1000000); sysbus_init_irq(dev, &s->timer[0]->irq); sysbus_init_irq(dev, &s->timer[1]->irq); From patchwork Wed May 31 20:35:53 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687305 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1459327wru; Wed, 31 May 2023 13:37:17 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4Zv9I9kEzZOuzZrH9cQOKp5wnxYNAwC/r+vWvVsK4UjltQkpDz0S9lVVYSoPWddUZpfAri X-Received: by 2002:a05:622a:181c:b0:3f6:824e:5104 with SMTP id t28-20020a05622a181c00b003f6824e5104mr7618560qtc.28.1685565437281; Wed, 31 May 2023 13:37:17 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685565437; cv=none; d=google.com; s=arc-20160816; b=k5CEn3B/5hYsXBuxQ20LoPQospSKpkj1gJKpla3BsX3Ll7veCLAi2Yxd65v0TJ02IX i1Ca8/rVqYOllZddxFd8/bGjf8m9t+q1gKiaBJlVnzgvRAg0eY0PMUpFKazsGjcLyros yT0KSjG9+GlS2QPm/NWozSW4UB/I5x2c1v3CajOLA+9R9i5+QoxmF9HwMsYIZfUS+oYk t6ITNdFz1WpfY5LUlzUUbSEODo3BEBJI790RccrgSYzwexd4GsaJXZEPLGagaMLP1vgE 1jBx7IY3PN3uz/3WlX29LP7JZqqrFbRRjRPUAUA/kgvVXvMKf7EO39ltOJ5iT496lZru znAA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=8GbaCgAoqo6igmmE7O0gpO7G+XBPsTJBXDJ3HWvHR/E=; b=hjBR02y5KwBFFi6MSlSvGxhmKF9l4O9xlO5avS1YIOlhoi5B8UzdSudwYdAauVseXv +qYZAZfJMkOkQgJLzUfWDgrycCX364XF27A0KvdhA0VFpuxQmvBXIyLPyosdf+nzxOt3 gFyBIRUaz4ftUgOewxTgWCRhChIUB0tKcvHZNAdweyufa+Zw7L8UhfPODBOEUemXUvKE gRBOwEm4eC+g835xSZOVgjDmm6rsPQhAw0ALSy5YLc4fO3XsEDgzKmC6VbTPk1QMXB+d Vy1JLF+GSWqNiZSPTGWFhwNebrY0rc4J8z+nTd+LrsqjQfAqR1gQlmmDoAV5D8Sgss+C XYkA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=j+uiPxba; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/timer/arm_timer.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 1f4d66291a..510ec74a51 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -33,7 +33,7 @@ typedef struct { ptimer_state *timer; uint32_t control; uint32_t limit; - int freq; + uint32_t freq; int int_level; qemu_irq irq; } ArmTimerState; From patchwork Wed May 31 20:35:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687314 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1460248wru; Wed, 31 May 2023 13:39:56 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7+5tA9sE/cFFBU0Iapjkc0Y3XOt7qmxpAW3Hdup0IuyPpDOK3i7fzqieYI5gqoSLnzhu1z X-Received: by 2002:a05:6214:29ec:b0:625:b517:6dcb with SMTP id jv12-20020a05621429ec00b00625b5176dcbmr7500792qvb.5.1685565596424; Wed, 31 May 2023 13:39:56 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685565596; cv=none; d=google.com; s=arc-20160816; b=ZUAWSTPDNNYZJ6+dizrf4PLXJ35Edy5NvuFm5uAQHAHqxQIy4xf7sneDGkmIvm7DuS QkH2sMZtf1hxrNuS2ut6BOhZ9uihgSQ+w7Mc4fAiLNZ0GCuaBzV2sTlveF3x++IpNjXC hQ3R1172PuSIv8y301FAvZiJhXi8fJNhtt+fw0gw811GOmo/3PhFv80tSEkc66biQn3O N9msR+eJkvPbjU8GxuexeKKEyyqb0ybj+h3+L39S7IC8x2utrMf1Q3G0h9LDQy8Xa81J KfBzvoxMX55v0vMsMEYM04Gzvlx+fulVB/Z6uWhedcIPA48TFOEX/eDK0nZgaa+0SH/C LgCw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=uEwvjd8H0pBzSI4zIAJ+UnyR+kTgNch6Orzmem2MX0A=; b=cF8sUOS47Nh2/CW518GNAmWCtoeSmwqyPFSizd9InCerOZnHMuKYZPpBQC+dFKwA2L T/uuDc4rmacjFKlx0ebYiKwd0uxCyvrifmaxg4pZONaq0K7JYNqL2edC3+iPgd74U1He yxz8f6aiJQpIYqO1TygMiCuGW6HIXVUs2mlXga/cTiQHojUvklyet/RXgOyauHLelHfX p0eGTJjBf5HtpT8uj7oov/Smqulwc2j+XQvTyWDoqzQEGydgpnxD/RmYqkQeEpydQbk1 g1I9qOS3QeSmWR4SMY5T8JjRu497zLLSGz5Pt1ZAh0iNH7HDZu0gq0u5SgRwv2vFcYX+ X64g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=YWIISxO9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Be consistent and use another one for the frequencies. This will allow to simplify using for() loop statement in the next commit. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/timer/arm_timer.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 510ec74a51..4d31f917f6 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -204,7 +204,7 @@ struct SP804State { MemoryRegion iomem; ArmTimerState *timer[2]; - uint32_t freq0, freq1; + uint32_t freq[2]; int level[2]; qemu_irq irq; }; @@ -308,8 +308,8 @@ static void sp804_realize(DeviceState *dev, Error **errp) { SP804State *s = SP804(dev); - s->timer[0] = arm_timer_new(s->freq0); - s->timer[1] = arm_timer_new(s->freq1); + s->timer[0] = arm_timer_new(s->freq[0]); + s->timer[1] = arm_timer_new(s->freq[1]); s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0); s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); } @@ -324,8 +324,8 @@ static void sp804_unrealize(DeviceState *dev) } static Property sp804_properties[] = { - DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), - DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), + DEFINE_PROP_UINT32("freq0", SP804State, freq[0], 1000000), + DEFINE_PROP_UINT32("freq1", SP804State, freq[1], 1000000), DEFINE_PROP_END_OF_LIST(), }; From patchwork Wed May 31 20:35:55 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687312 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1460110wru; Wed, 31 May 2023 13:39:34 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6ygnaDSeIa90LwZcsfhWxIBcwSVeN9lw4RSmigZGi4n6R7MpJPOW7iNBFpOIVt48k3YKBg X-Received: by 2002:a05:620a:4148:b0:75b:23a0:deb4 with SMTP id k8-20020a05620a414800b0075b23a0deb4mr9147984qko.50.1685565574633; Wed, 31 May 2023 13:39:34 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685565574; cv=none; d=google.com; s=arc-20160816; b=GV0mEBkCyrg0afURaVUUDel+xBjWORgKEt7hVZoZTESUoRK8/PbMFWgO8fODvjoSAo 9f7xliv9jFe81WXBMQYzDDzvYagrmsXHJtKAcNsgZHMFVRonI9YOa/YRoB5StXMNCR2n l4g7lPj2brYS8GfLdPtvrqXI+gCkhreFirukHmnHpj0UZ9Qn9TXFDyqZNIdR3pz2XRtv 8GoDj7simAfS2B/ugtgFgwf3d3xX0NGzUzqE/0dHlxEEfmjk6M6W3mSdczf3cYXtpoJ3 9SYuPlqEarylC1F6rsX4RLmJmy9BOQGlpJmUMTk0lUAAtkbaSWHsR8LUYa/oKDBha54T O5qw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=LEve7XoaYuxNRaMbirKWz6mHRspgIpo3ijJ/vB0fM1Q=; b=IL3azibgHfst/QfxdOeWrdBoQ3/ObdrveVzaarYrmVMeUeXtBytgwBERv4Jz5f8/L+ ecv7sDHofIB+2uuNNn9AxFxn0va/loq4w00+WC8VgGzIUZXygc1RRFFfHs0QF8hOHnjj jT1ZOjcKX3Gv+tc6wwB/8l8ONQoPMbYVdnohspmjbxv9Ge6EIpue+rTe93l8jcd+JXMs Q0QhBP4E96eBnfQCWfYGix/NzBQql3J7xtGmJWPbuyPJtcS7OCTjqtOSwWW8ZVuo+zvp OEgIpwdM663uG9iZ/EKAHS+mbteDDE7Yq7X74ZPI5196AARp1xks5HRY/Lm98nTvWNLy kVqA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=hh1ypo1V; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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To avoid too much code churn in the next commits, iterate on the number of timers using a for() loop statement. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/timer/arm_timer.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 4d31f917f6..19789ad2c4 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -308,10 +308,10 @@ static void sp804_realize(DeviceState *dev, Error **errp) { SP804State *s = SP804(dev); - s->timer[0] = arm_timer_new(s->freq[0]); - s->timer[1] = arm_timer_new(s->freq[1]); - s->timer[0]->irq = qemu_allocate_irq(sp804_set_irq, s, 0); - s->timer[1]->irq = qemu_allocate_irq(sp804_set_irq, s, 1); + for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { + s->timer[i] = arm_timer_new(s->freq[i]); + s->timer[i]->irq = qemu_allocate_irq(sp804_set_irq, s, i); + } } static void sp804_unrealize(DeviceState *dev) @@ -390,18 +390,19 @@ static const MemoryRegionOps icp_pit_ops = { static void icp_pit_init(Object *obj) { + static const uint32_t tmr_freq[] = { + /* Timer 0 runs at the system clock speed (40MHz). */ + 40000000, + /* The other two timers run at 1MHz. */ + 1000000, 1000000 + }; IntegratorPitState *s = INTEGRATOR_PIT(obj); SysBusDevice *dev = SYS_BUS_DEVICE(obj); - /* Timer 0 runs at the system clock speed (40MHz). */ - s->timer[0] = arm_timer_new(40000000); - /* The other two timers run at 1MHz. */ - s->timer[1] = arm_timer_new(1000000); - s->timer[2] = arm_timer_new(1000000); - - sysbus_init_irq(dev, &s->timer[0]->irq); - sysbus_init_irq(dev, &s->timer[1]->irq); - sysbus_init_irq(dev, &s->timer[2]->irq); + for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { + s->timer[i] = arm_timer_new(tmr_freq[i]); + sysbus_init_irq(dev, &s->timer[i]->irq); + } memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, "icp_pit", 0x1000); From patchwork Wed May 31 20:35:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687308 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1459536wru; Wed, 31 May 2023 13:37:54 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4rvoaBqvEEJDdbfHUwcLC6Vkydkml1IVsn22z3/pzRZDQSVBtAXMHJDEqfXgJfGym3xX8X X-Received: by 2002:ac8:4e8d:0:b0:3f4:f1f8:9383 with SMTP id 13-20020ac84e8d000000b003f4f1f89383mr8290281qtp.52.1685565474489; Wed, 31 May 2023 13:37:54 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685565474; cv=none; d=google.com; s=arc-20160816; b=KoEULtMtZcodYvjw1hFwPT2vSg+c3Q4kxBOIwtJ6K7a6tC3D5WWPLLE+DXYYQ0njBY Ra2tJb8LTNTHjCZ+clq9t3NKZpBPeFn2k/g3JMUIHze4He5P4IxsoZOHYPSJiGfCGrxw Y4Pc1lpZKufMV5lPZ0Gr3o55CQBh9VCP38e4qbSI7AVKRBszBla3qxm0ClAot5DrDakP IuVfV1xA2SjN4KQVjY2oAPmQ53RuMkuZstp6MtcywvOSdcQG2B6uBiPBFgZe+YO/6f45 DkNLFOaKcq/BOohenJGVLwwR1zqOBcL84zUWzHcUhXJBvsiVmJdtuZMt/ztm/geMj3I7 eMQQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=tiC6CuBtjw1sGes9CKcEGdJAP6aAhbbs6USQHp8o0zw=; b=PlrT24NWI6pibiSLmbV+UPBHPDdUoTAtPovGSv+LfL4y3D4xD+I9uVADjsrDZi+kTj 9IIjmnn1qDhwzq9ooTpQnE9tGB09Bz2Qhfo2vP9c/rzEJlpbL60Fic7YDI1s4FanPbec EJXSfw618n081iiOZkYtlF4PY6UQZUiX+dHIgZKUlrg1Fw+qmsHuk2DWiPLkSqfM0IcQ YiU7L8dZkJswazuO+6Mn7SL1meMbVBSO2QUzygVv+i/6B65s7j6oZBNMK+3RYg9jK2L/ /3EM+lhW/X5lCv2ZLI1pFTJ1W9nO1ufO1dXz1iiUCNbU3lIkiDCOu9qRV5ZJ+4lYwmYi 3CAA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sX2nLNh8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id i12-20020ac85e4c000000b003f391f58d32si8601277qtx.776.2023.05.31.13.37.54 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 31 May 2023 13:37:54 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=sX2nLNh8; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1q4SZU-0000zW-IP; Wed, 31 May 2023 16:37:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1q4SZH-0000ny-E6 for qemu-devel@nongnu.org; Wed, 31 May 2023 16:37:17 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1q4SZF-0003Oj-OQ for qemu-devel@nongnu.org; Wed, 31 May 2023 16:37:15 -0400 Received: by mail-wm1-x329.google.com with SMTP id 5b1f17b1804b1-3f6dfc4dffaso1105895e9.0 for ; Wed, 31 May 2023 13:37:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1685565430; x=1688157430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=tiC6CuBtjw1sGes9CKcEGdJAP6aAhbbs6USQHp8o0zw=; b=sX2nLNh8/HMNxHC21LnZnEMCZ/Rmlhd8lW0RsR29ykrQBgiCyzgBdUPtrVvhJs732B tVlNUl4W4V2Smc0BqEhh5fJiRFci57Q/FFJeYzh0b3FduzqKNT+Ep/lj5NkFW2EUMO3z Hqe8126wP2Of99cBHYTB+Qaa6QNoku9VsdZceuPGe0otpBHRSukx9kP7asog4M5GK1m+ sede8DgssRwf6O+/suYKTBP2KEeg926wl7n/so8aqNWbJZwDcks6t2WG4/yFeyvCrX+k jCPykDpXiSoM6LkYIosTccMu2Vv1QjNXYFNAN6UhngoPwgYjHQwsx1Fv/gpY2/ssa+Ru RmVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1685565430; x=1688157430; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=tiC6CuBtjw1sGes9CKcEGdJAP6aAhbbs6USQHp8o0zw=; b=Nt1lJ4bLvkGB9H7fCFaQDPbzO43+9veKuiZHg+ozSR5RyZimvZKw7/vE78wPxn+Bqx 0l12O6cZ6uYTZv2xRagfb/8YUOt3YOanSynyvgNjGA1BBA/tQknLv4qE4ghoRUSupF5L bLHy7FDoSOLe+S4VD7CbAvRbA3b/y9c0/vIYJUW26MQ1weYZuA+bIAfsuEjV4XPCy7Xa YFmZ0mieVpMle0omR4Qgi/5ICwMKy7snybtxg5wSjIfmzna+dPJmB3PPXdN3uQRkv2Kr f4WRr6q2uJ7qdfEVf6sUUxeMhJYtg7c0liETalncson68Qnajns2ZmeBO3rhFd3qj+eL YayQ== X-Gm-Message-State: AC+VfDxEs1Tji/JMKUN5oLlq32zQv1xP6PgKOVEdulnfESGcK++G/7Nj mPE7/YbET3MGX49U9G7Zk1f/M+XAt7koRWnCO6Q= X-Received: by 2002:a05:600c:2210:b0:3f7:5e3:c1f2 with SMTP id z16-20020a05600c221000b003f705e3c1f2mr321295wml.8.1685565430398; Wed, 31 May 2023 13:37:10 -0700 (PDT) Received: from localhost.localdomain ([176.176.146.12]) by smtp.gmail.com with ESMTPSA id z18-20020a1c4c12000000b003f423f5b659sm21831888wmf.10.2023.05.31.13.37.09 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 31 May 2023 13:37:10 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Thomas Huth , qemu-arm@nongnu.org, Peter Maydell , Sergey Kambalin , =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= Subject: [PATCH 12/15] hw/timer/arm_timer: Pass timer output IRQ as parameter to arm_timer_new Date: Wed, 31 May 2023 22:35:56 +0200 Message-Id: <20230531203559.29140-13-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230531203559.29140-1-philmd@linaro.org> References: <20230531203559.29140-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philmd@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Both SP804State/IcpPitState peek at ArmTimerState internal state. This is fine so far but we want to convert ArmTimerState to QOM where peeking at QOM state internal should be avoided. ArmTimerState's IRQ is just a pointer, so we can pass/set it via argument, avoiding accessing ArmTimerState internal state except from the arm_timer_*() methods. Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/arm_timer.c | 15 +++++++++------ 1 file changed, 9 insertions(+), 6 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 19789ad2c4..6f444e1789 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -177,7 +177,7 @@ static void arm_timer_reset(ArmTimerState *s) s->control = TIMER_CTRL_IE; } -static ArmTimerState *arm_timer_new(uint32_t freq) +static ArmTimerState *arm_timer_new(uint32_t freq, qemu_irq irq_out) { ArmTimerState *s; @@ -185,6 +185,7 @@ static ArmTimerState *arm_timer_new(uint32_t freq) s->freq = freq; arm_timer_reset(s); + s->irq = irq_out; s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_LEGACY); vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_arm_timer, s); return s; @@ -207,6 +208,7 @@ struct SP804State { uint32_t freq[2]; int level[2]; qemu_irq irq; + qemu_irq irq_in[2]; }; static const uint8_t sp804_ids[] = { @@ -309,8 +311,8 @@ static void sp804_realize(DeviceState *dev, Error **errp) SP804State *s = SP804(dev); for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { - s->timer[i] = arm_timer_new(s->freq[i]); - s->timer[i]->irq = qemu_allocate_irq(sp804_set_irq, s, i); + s->irq_in[i] = qemu_allocate_irq(sp804_set_irq, s, i); + s->timer[i] = arm_timer_new(s->freq[i], s->irq_in[i]); } } @@ -319,7 +321,7 @@ static void sp804_unrealize(DeviceState *dev) SP804State *s = SP804(dev); for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { - qemu_free_irq(s->timer[i]->irq); + qemu_free_irq(s->irq_in[i]); } } @@ -349,6 +351,7 @@ struct IntegratorPitState { MemoryRegion iomem; ArmTimerState *timer[3]; + qemu_irq irq_in[3]; }; static uint64_t icp_pit_read(void *opaque, hwaddr offset, @@ -400,8 +403,8 @@ static void icp_pit_init(Object *obj) SysBusDevice *dev = SYS_BUS_DEVICE(obj); for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { - s->timer[i] = arm_timer_new(tmr_freq[i]); - sysbus_init_irq(dev, &s->timer[i]->irq); + s->timer[i] = arm_timer_new(tmr_freq[i], s->irq_in[i]); + sysbus_init_irq(dev, &s->irq_in[i]); } memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, From patchwork Wed May 31 20:35:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687315 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1460294wru; Wed, 31 May 2023 13:40:05 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ7MSgeohCJUtpd7N/Y15IYinCSAISHAVeO5gb1YNNGNDo4vrkkydFJjvchsJPNGAWnPZp6M X-Received: by 2002:a05:6214:e8e:b0:625:aa1a:b6de with SMTP id hf14-20020a0562140e8e00b00625aa1ab6demr7171812qvb.64.1685565605336; Wed, 31 May 2023 13:40:05 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685565605; cv=none; d=google.com; s=arc-20160816; b=HmyVcDuUa6oa41icIaZAOs2Ux2F5jYlTQD6LHWptSTuzJ9DjeaqFF9Xko1PgBogHbK iAzCP4+5peTE64GtqhrZ1eFn+WCO1lf/lqYGCugIpUmKqolcI66cI1lAYY1qLYyV3sQc AzrjE225sDTm5Kt4jl3oOG27jgNSL8oY9SMupgfCaLz3bhC2qxRvjGhqyTGSVmJISvEp Mx1dbXsaOBGpWXKPKFpsh3hW20qJyehqd5S8+26lAgDeW49IihoGV8OIEXzxgmQ6P+QH NY29pBXwgpCqRtBUWOmQ6BgBa0WUcxDMJCfYQ6cRoz85P8UdG0fwi+PoU1ajhPfZ7jlB zqKQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=0MtX4o0Ye6nhZ4tPfz5ErTCUaJJiVijCKFgjVroPJbY=; b=ftTSymz7dP7UDQLWzfYilJ81fwBLNr4iQWETrVNoe1ng+OiVnX1Na0Tzr+amXJQUA0 0KK9jDpF+iBuy2D/2lbZzWrkb+R8A1lwM39V7y5CEFE3x4+rUt60amXFznMQuII94pKp NlBsnZdWymLJhNeoAITXjGFDYOFubOizFg3DpL1V6W5KP1cVHI6dTwVaEQn/Ne9oJWnf L7HI7U92GQAVcSS3x6/zFRm481sLi4OxxRtmQ4sW4kkdFXnK/d8pfIZ19XEcyYwRSgha TUo/n49v2OYgTy0Z91WnYl8Ik350zA7c2lliuM1mBThNOUAE9itDvVaU/DraZVDeFogM Tx9Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=WHWopqF3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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As some sort of simplification to avoid to forward it, IcpPitState misuses it as ARM timer input IRQ. Fix that by using a simple IRQ forwarder handler. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Peter Maydell --- hw/timer/arm_timer.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 6f444e1789..874f9b63bc 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -352,6 +352,7 @@ struct IntegratorPitState { MemoryRegion iomem; ArmTimerState *timer[3]; qemu_irq irq_in[3]; + qemu_irq irq[3]; }; static uint64_t icp_pit_read(void *opaque, hwaddr offset, @@ -391,6 +392,13 @@ static const MemoryRegionOps icp_pit_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; +static void icp_pit_fwd_irq(void *opaque, int n, int level) +{ + IntegratorPitState *s = opaque; + + qemu_set_irq(s->irq[n], level); +} + static void icp_pit_init(Object *obj) { static const uint32_t tmr_freq[] = { @@ -402,9 +410,14 @@ static void icp_pit_init(Object *obj) IntegratorPitState *s = INTEGRATOR_PIT(obj); SysBusDevice *dev = SYS_BUS_DEVICE(obj); + qdev_init_gpio_in_named(DEVICE(obj), icp_pit_fwd_irq, + "timer-in", ARRAY_SIZE(s->timer)); + for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { s->timer[i] = arm_timer_new(tmr_freq[i], s->irq_in[i]); - sysbus_init_irq(dev, &s->irq_in[i]); + sysbus_init_irq(dev, &s->irq[i]); + sysbus_connect_irq(dev, i, + qdev_get_gpio_in_named(DEVICE(obj), "timer-in", i)); } memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, From patchwork Wed May 31 20:35:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687313 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1460117wru; Wed, 31 May 2023 13:39:35 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ5iKs0vfq/vsrbWJgFtUpq2IH1jTYaiVy9lh1OR1P+tTm9YjMrEEryISudmtcSkwY4G0NYd X-Received: by 2002:a05:622a:1ba0:b0:3f3:8057:9587 with SMTP id bp32-20020a05622a1ba000b003f380579587mr7457448qtb.20.1685565575157; Wed, 31 May 2023 13:39:35 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685565575; cv=none; d=google.com; s=arc-20160816; b=WLeZrJ1RaGbmvJPtTxzxTOAkn+WoeU7oA/ybef9e0vvbdor2RHW6oFk+4QU+RlgOfT 1CjNRxypfSgpt0tNmux9VW2w/ygRhu2r7zQAw85f0KsT1d+fWsPMVEgqhvJS47GFH6NM JIqU0yLPU2yqGSsGd4xo4TfOUE6Z5jpAevL9bBbSm/+GtBLv860fPKVD7u03QZ0iwIvI Ur2epOrt4l4BumKHY4K2W/0mdN3MuzZhzoKmSAlfz4bumUr2Jl0m6AaB+yhKdPWXT7+c KzKdPQwmBwS4dJ76NZb++nQ1qN6iTKGPkBd/+AXjT2HAdf+xEy+/Z+x7km2ZRYbhV0Af luhg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=cBL0tJ6A533UUXBJlMobIsNt8VadG3dvYB/dy1tc5wE=; b=LgM88PHid9buTC95YYOHhhMCDNxM+LkiPj1C9zFc06NnDGgDupe4w0zEiyNoR0Y4l1 058PvSbbxwj8izapK+nJV25o60pf3c7a6C1v8tHmBr1akScA92V7IoIUzYHI4QH7gzzo BnBvVgYXd4/u45UmYOvLhPPmD/LnBKdcydBrpWPyaxv69hqKbzFw7G28+Va0V+lyNC2W yXtemocnGi2D8oRPcCmWuvhwmu9ymJSeUI9mdcjqc3RAv2dV22Ox0WcXTW1dmImfW+hl 87gmg1qi05wbWrkXymjdaxIzu/0aaTRMkEoexTLzTTwed5qg7qpftzZC2tkeE9BC3Xu1 ic/A== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=n1B3RSb0; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/arm_timer.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 874f9b63bc..82123b40c0 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -416,8 +416,6 @@ static void icp_pit_init(Object *obj) for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { s->timer[i] = arm_timer_new(tmr_freq[i], s->irq_in[i]); sysbus_init_irq(dev, &s->irq[i]); - sysbus_connect_irq(dev, i, - qdev_get_gpio_in_named(DEVICE(obj), "timer-in", i)); } memory_region_init_io(&s->iomem, obj, &icp_pit_ops, s, @@ -427,12 +425,30 @@ static void icp_pit_init(Object *obj) save themselves. */ } +static void icp_pit_realize(DeviceState *dev, Error **errp) +{ + IntegratorPitState *s = INTEGRATOR_PIT(dev); + + for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + qdev_get_gpio_in_named(dev, "timer-in", i)); + } +} + +static void icp_pit_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *k = DEVICE_CLASS(klass); + + k->realize = icp_pit_realize; +} + static const TypeInfo arm_timer_types[] = { { .name = TYPE_INTEGRATOR_PIT, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(IntegratorPitState), .instance_init = icp_pit_init, + .class_init = icp_pit_class_init, }, { .name = TYPE_SP804, From patchwork Wed May 31 20:35:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 687311 Delivered-To: patch@linaro.org Received: by 2002:a5d:4d8a:0:0:0:0:0 with SMTP id b10csp1460078wru; Wed, 31 May 2023 13:39:27 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ78s8t+P1XZ6DRkEIDxbe3Ox+cAidRIBG66t+UZuxuOsqevw4qO6sCoz8/GaUcEoJzhRSST X-Received: by 2002:a05:620a:298c:b0:75b:23a0:e7bf with SMTP id r12-20020a05620a298c00b0075b23a0e7bfmr9051008qkp.32.1685565567221; Wed, 31 May 2023 13:39:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1685565567; cv=none; d=google.com; s=arc-20160816; b=yeMWOwXEVKjWJkSIsHpeZ8StnGRdfQn2kA6zd/uAGPCzQDpcdX18KOcTM3xZFyLCi1 /cJJiDb6Z9AjshmGehoIQMLioSrfyahR+sVpSiZTk6ICd4yWQcZuX9omdZx47duxD7in +3vSfzzMBvIQUTfhBLLcTauyIfx5BlfzTN0qtvQ2N9hoWFvKgmtKPWz8LXp77GoHUg0n qTX0DdW46cOvP4n2ZFqOZncHnNUT8nDV5xa1/R9/irpkUrdPHX0927gTrBRqjTJ3MxbG XhRtF5Agj2dm74gVMLPFWMsQDT19Q8t3h6ZI62kf3zfp7MdS1VyC7rqt2rS9jmDG5D/p JYBQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=sjhOm08stxYpC2nNilZ+r3P5phZDhdo7hj/kLX7dCFk=; b=IpaBWNMIQ3ktvXtL5FQXC8HnjHvmxFNZU2/6i50qPwcSWnE+UWB1XJ6Tzf8XQLDD2Q ctRvCkL6Om5rCsbcThrj/P6NA6XfnGn6cHaoW7FVBn5SRr8LghlQaVppS3rmW/nP9sJp ZYGdWs3tIBHiZqBcFAK76v638r3ye4byKSYow6+nKQmEjenJTXXsc3VpRpBA7iDeHmAv dgdz7cLJXQjzkuxT8d3DvtI98BXZtZQJUOkkpxXF8BWe7zU5/fWYHTVImbnfmV1b/ieM O59cFhjBAb4wmmetQOrpbEqb6BfwgomSr8Qp/dRM2iLNVdNwq4xTxdl2GCXHJ785ormb sHsQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=baHRiqQe; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Note in arm_timer_finalize() we release a ptimer handle which was previously leaked. ArmTimerState is directly embedded into SP804State/IcpPitState, and is initialized as a QOM child. Since the timer frequency belongs to ARM_TIMER, have it hold the QOM property. SP804State/IcpPitState directly access it. Similarly the SP804State/IcpPitState input IRQ becomes the ARM_TIMER sysbus output IRQ. Signed-off-by: Philippe Mathieu-Daudé --- hw/timer/arm_timer.c | 109 +++++++++++++++++++++++++++---------------- 1 file changed, 70 insertions(+), 39 deletions(-) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index 82123b40c0..a929fbba62 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -17,6 +17,7 @@ #include "qemu/module.h" #include "qemu/log.h" #include "qom/object.h" +#include "qapi/error.h" /* Common timer implementation. */ @@ -29,14 +30,18 @@ #define TIMER_CTRL_PERIODIC (1 << 6) #define TIMER_CTRL_ENABLE (1 << 7) -typedef struct { +#define TYPE_ARM_TIMER "arm-timer" +OBJECT_DECLARE_SIMPLE_TYPE(ArmTimerState, ARM_TIMER) + +struct ArmTimerState { + SysBusDevice parent_obj; ptimer_state *timer; uint32_t control; uint32_t limit; uint32_t freq; int int_level; qemu_irq irq; -} ArmTimerState; +}; /* Check all active timers, and schedule the next timer interrupt. */ @@ -172,23 +177,42 @@ static const VMStateDescription vmstate_arm_timer = { } }; -static void arm_timer_reset(ArmTimerState *s) +static void arm_timer_reset(DeviceState *dev) { + ArmTimerState *s = ARM_TIMER(dev); + s->control = TIMER_CTRL_IE; } -static ArmTimerState *arm_timer_new(uint32_t freq, qemu_irq irq_out) +static void arm_timer_init(Object *obj) { - ArmTimerState *s; + ArmTimerState *s = ARM_TIMER(obj); + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); - s = g_new0(ArmTimerState, 1); - s->freq = freq; - arm_timer_reset(s); - - s->irq = irq_out; s->timer = ptimer_init(arm_timer_tick, s, PTIMER_POLICY_LEGACY); - vmstate_register(NULL, VMSTATE_INSTANCE_ID_ANY, &vmstate_arm_timer, s); - return s; + + sysbus_init_irq(sbd, &s->irq); +} + +static void arm_timer_finalize(Object *obj) +{ + ArmTimerState *s = ARM_TIMER(obj); + + ptimer_free(s->timer); +} + +static Property arm_timer_properties[] = { + DEFINE_PROP_UINT32("freq", ArmTimerState, freq, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void arm_timer_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->reset = arm_timer_reset; + dc->vmsd = &vmstate_arm_timer; + device_class_set_props(dc, arm_timer_properties); } /* @@ -204,11 +228,9 @@ struct SP804State { SysBusDevice parent_obj; MemoryRegion iomem; - ArmTimerState *timer[2]; - uint32_t freq[2]; + ArmTimerState timer[2]; int level[2]; qemu_irq irq; - qemu_irq irq_in[2]; }; static const uint8_t sp804_ids[] = { @@ -233,10 +255,10 @@ static uint64_t sp804_read(void *opaque, hwaddr offset, SP804State *s = opaque; if (offset < 0x20) { - return arm_timer_read(s->timer[0], offset); + return arm_timer_read(&s->timer[0], offset); } if (offset < 0x40) { - return arm_timer_read(s->timer[1], offset - 0x20); + return arm_timer_read(&s->timer[1], offset - 0x20); } /* TimerPeriphID */ @@ -265,12 +287,12 @@ static void sp804_write(void *opaque, hwaddr offset, SP804State *s = opaque; if (offset < 0x20) { - arm_timer_write(s->timer[0], offset, value); + arm_timer_write(&s->timer[0], offset, value); return; } if (offset < 0x40) { - arm_timer_write(s->timer[1], offset - 0x20, value); + arm_timer_write(&s->timer[1], offset - 0x20, value); return; } @@ -304,6 +326,12 @@ static void sp804_init(Object *obj) memory_region_init_io(&s->iomem, obj, &sp804_ops, s, "sp804", 0x1000); sysbus_init_mmio(sbd, &s->iomem); + + qdev_init_gpio_in_named(DEVICE(obj), sp804_set_irq, + "timer-in", ARRAY_SIZE(s->timer)); + for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { + object_initialize_child(obj, "timer[*]", &s->timer[i], TYPE_ARM_TIMER); + } } static void sp804_realize(DeviceState *dev, Error **errp) @@ -311,23 +339,17 @@ static void sp804_realize(DeviceState *dev, Error **errp) SP804State *s = SP804(dev); for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { - s->irq_in[i] = qemu_allocate_irq(sp804_set_irq, s, i); - s->timer[i] = arm_timer_new(s->freq[i], s->irq_in[i]); - } -} - -static void sp804_unrealize(DeviceState *dev) -{ - SP804State *s = SP804(dev); - - for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { - qemu_free_irq(s->irq_in[i]); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, + qdev_get_gpio_in_named(dev, "timer-in", i)); } } static Property sp804_properties[] = { - DEFINE_PROP_UINT32("freq0", SP804State, freq[0], 1000000), - DEFINE_PROP_UINT32("freq1", SP804State, freq[1], 1000000), + DEFINE_PROP_UINT32("freq0", SP804State, timer[0].freq, 1000000), + DEFINE_PROP_UINT32("freq1", SP804State, timer[1].freq, 1000000), DEFINE_PROP_END_OF_LIST(), }; @@ -336,7 +358,6 @@ static void sp804_class_init(ObjectClass *klass, void *data) DeviceClass *k = DEVICE_CLASS(klass); k->realize = sp804_realize; - k->unrealize = sp804_unrealize; device_class_set_props(k, sp804_properties); k->vmsd = &vmstate_sp804; } @@ -350,8 +371,7 @@ struct IntegratorPitState { SysBusDevice parent_obj; MemoryRegion iomem; - ArmTimerState *timer[3]; - qemu_irq irq_in[3]; + ArmTimerState timer[3]; qemu_irq irq[3]; }; @@ -368,7 +388,7 @@ static uint64_t icp_pit_read(void *opaque, hwaddr offset, return 0; } - return arm_timer_read(s->timer[n], offset & 0xff); + return arm_timer_read(&s->timer[n], offset & 0xff); } static void icp_pit_write(void *opaque, hwaddr offset, @@ -383,7 +403,7 @@ static void icp_pit_write(void *opaque, hwaddr offset, return; } - arm_timer_write(s->timer[n], offset & 0xff, value); + arm_timer_write(&s->timer[n], offset & 0xff, value); } static const MemoryRegionOps icp_pit_ops = { @@ -414,7 +434,8 @@ static void icp_pit_init(Object *obj) "timer-in", ARRAY_SIZE(s->timer)); for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { - s->timer[i] = arm_timer_new(tmr_freq[i], s->irq_in[i]); + object_initialize_child(obj, "timer[*]", &s->timer[i], TYPE_ARM_TIMER); + qdev_prop_set_uint32(DEVICE(&s->timer[i]), "freq", tmr_freq[i]); sysbus_init_irq(dev, &s->irq[i]); } @@ -430,7 +451,10 @@ static void icp_pit_realize(DeviceState *dev, Error **errp) IntegratorPitState *s = INTEGRATOR_PIT(dev); for (unsigned i = 0; i < ARRAY_SIZE(s->timer); i++) { - sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, + if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) { + return; + } + sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer[i]), 0, qdev_get_gpio_in_named(dev, "timer-in", i)); } } @@ -444,6 +468,13 @@ static void icp_pit_class_init(ObjectClass *klass, void *data) static const TypeInfo arm_timer_types[] = { { + .name = TYPE_ARM_TIMER, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(ArmTimerState), + .instance_init = arm_timer_init, + .instance_finalize = arm_timer_finalize, + .class_init = arm_timer_class_init, + }, { .name = TYPE_INTEGRATOR_PIT, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(IntegratorPitState),