From patchwork Tue May 30 09:07:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 687671 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10056C7EE2F for ; Tue, 30 May 2023 09:08:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230104AbjE3JIW (ORCPT ); Tue, 30 May 2023 05:08:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32852 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229896AbjE3JIT (ORCPT ); Tue, 30 May 2023 05:08:19 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 01355DB; Tue, 30 May 2023 02:08:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685437698; x=1716973698; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=KDOtiesl3EnNNfJv3nhJSpdEkmq96eW6+SiGHrWHxNY=; b=Ie5Sga7kp8NEmZjp189/ECVxqs4JwJaTxlY+jha9ARd9u0tPHyLfi+Og EnrqapVecTk2Civa/+k8OlanXUaEoksSyeGMKMyUb+zeb4+LFl5xsYhZg hn662/mlOZDf1igVuy3V4/wqywKjfpheVIzUXh31/x4EjSYTSeM6xDXFV Fsah+OsFLItaIlf9wfdk9qet+uv4m8leEwnWW+qYbMw8/NIqHVadwfEpm KO79uN47DeTRnlNzUXT8CuSP2nGCKsU5AVxs8zRU20Zlgbzi6toAtLi7x OgdCCYK8bvtH+3fSWv97rHOtxZBXQvz464g/Kd+JKip49GMT/LhenQqeh A==; X-IronPort-AV: E=Sophos;i="6.00,203,1681196400"; d="scan'208";a="213680031" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 May 2023 02:08:18 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 30 May 2023 02:08:16 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 30 May 2023 02:08:12 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , , , , "Claudiu Beznea" Subject: [PATCH v3 1/3] dt-bindings: timer: atmel, at91sam9260-pit: convert to yaml Date: Tue, 30 May 2023 12:07:56 +0300 Message-ID: <20230530090758.1652329-2-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530090758.1652329-1-claudiu.beznea@microchip.com> References: <20230530090758.1652329-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Convert Microchip AT91 PIT bindings to YAML. Along with it clocks and clock-names bindings were added as the drivers needs it to ensure proper hardware functionality. Signed-off-by: Claudiu Beznea --- .../devicetree/bindings/arm/atmel-sysregs.txt | 12 --- .../bindings/timer/atmel,at91sam9260-pit.yaml | 99 +++++++++++++++++++ 2 files changed, 99 insertions(+), 12 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/atmel,at91sam9260-pit.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 67a66bf74895..54d3f586403e 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -4,18 +4,6 @@ Chipid required properties: - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" - reg : Should contain registers location and length -PIT Timer required properties: -- compatible: Should be "atmel,at91sam9260-pit" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for the PIT which is the IRQ line - shared across all System Controller members. - -PIT64B Timer required properties: -- compatible: Should be "microchip,sam9x60-pit64b" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for PIT64B timer -- clocks: Should contain the available clock sources for PIT64B timer. - System Timer (ST) required properties: - compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" - reg: Should contain registers location and length diff --git a/Documentation/devicetree/bindings/timer/atmel,at91sam9260-pit.yaml b/Documentation/devicetree/bindings/timer/atmel,at91sam9260-pit.yaml new file mode 100644 index 000000000000..d0f3f80db4cb --- /dev/null +++ b/Documentation/devicetree/bindings/timer/atmel,at91sam9260-pit.yaml @@ -0,0 +1,99 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/atmel,at91sam9260-pit.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip AT91 Periodic Interval Timer (PIT) + +maintainers: + - Claudiu Beznea + +description: + Microchip AT91 periodic interval timer provides the operating system scheduler + interrupt. It is designed to offer maximum accuracy and efficient management, + even for systems with long response time. + +properties: + compatible: + oneOf: + - items: + - const: microchip,sama7g5-pit64b + - const: microchip,sam9x60-pit64b + - items: + enum: + - atmel,at91sam9260-pit + - microchip,sam9x60-pit64b + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + minItems: 1 + maxItems: 2 + +required: + - compatible + - reg + - interrupts + - clocks + +allOf: + - if: + properties: + compatible: + contains: + const: atmel,at91sam9260-pit + then: + properties: + interrupts: + description: + Shared interrupt between all system controller members (power management + controller, watchdog, PIT, reset controller, real-time timer, real-time + clock, memory controller, debug unit, system timer). + clocks: + maxItems: 1 + + else: + properties: + clocks: + minItems: 2 + clock-names: + items: + - const: pclk + - const: gclk + required: + - clock-names + +unevaluatedProperties: false + +examples: + - | + /* AT91RM9200 */ + #include + #include + + pit: timer@fffffe40 { + compatible = "atmel,at91sam9260-pit"; + reg = <0xfffffe40 0x10>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_CORE PMC_MCK>; + }; + + - | + /* SAM9X60 */ + #include + #include + + pit64b: timer@f0028000 { + compatible = "microchip,sam9x60-pit64b"; + reg = <0xf0028000 0x100>; + interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; + clock-names = "pclk", "gclk"; + }; + +... From patchwork Tue May 30 09:07:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 687210 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0EE4AC7EE2E for ; Tue, 30 May 2023 09:08:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230307AbjE3JI2 (ORCPT ); Tue, 30 May 2023 05:08:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:32934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229896AbjE3JI0 (ORCPT ); Tue, 30 May 2023 05:08:26 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 907D9E5; Tue, 30 May 2023 02:08:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685437705; x=1716973705; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ePvnbcUZfBzS5LpYhed9C5KFLtkWzLLMmABvRa3FWyY=; b=Bi/5+wjvahKza26aAnpJDrHyaYWDOld4M53N2ud7F/PCyy5aVQGTKiQQ DyAtP3D9ZatiYkjmodVD5SM/eRNfvIhxuM8uoufz+vwolj5kZ1b3Z0xXH H7Wa9rkVDkh51+zts/dmGS77Ohwls7Q7X9jmBZTXZMxvZ04DvbJvhTpOL ueEcB7J34etaFlUpucYZL4DkRBBULJ01DEUAPhhsUJ8T/iK/HanV4cVrj EwDKvaNHcAUTchW4vLplifzAJg3FZDZ1fesS4xqiXcAyauggEaYMvqVeb pS/PrYCZdKgnnGOoe75aF+YNY09Lqgfk9lHRp4Ew05Lef/KS5S7k+nM12 Q==; X-IronPort-AV: E=Sophos;i="6.00,203,1681196400"; d="scan'208";a="154563340" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa6.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 May 2023 02:08:24 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 30 May 2023 02:08:21 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 30 May 2023 02:08:17 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , , , , "Claudiu Beznea" , Conor Dooley Subject: [PATCH v3 2/3] dt-bindings: watchdog: atmel,at91rm9200-wdt: convert to yaml Date: Tue, 30 May 2023 12:07:57 +0300 Message-ID: <20230530090758.1652329-3-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530090758.1652329-1-claudiu.beznea@microchip.com> References: <20230530090758.1652329-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Convert Microchip AT91RM9200 system timer watchdog bindings to YAML. Signed-off-by: Claudiu Beznea Reviewed-by: Conor Dooley --- .../watchdog/atmel,at91rm9200-wdt.yaml | 29 +++++++++++++++++++ .../watchdog/atmel-at91rm9200-wdt.txt | 9 ------ 2 files changed, 29 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/watchdog/atmel,at91rm9200-wdt.yaml delete mode 100644 Documentation/devicetree/bindings/watchdog/atmel-at91rm9200-wdt.txt diff --git a/Documentation/devicetree/bindings/watchdog/atmel,at91rm9200-wdt.yaml b/Documentation/devicetree/bindings/watchdog/atmel,at91rm9200-wdt.yaml new file mode 100644 index 000000000000..592e797df4c2 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/atmel,at91rm9200-wdt.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/atmel,at91rm9200-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip AT91RM9200 System Timer Watchdog + +maintainers: + - Nicolas Ferre + - Alexandre Belloni + - Claudiu Beznea + +properties: + compatible: + const: atmel,at91rm9200-wdt + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + watchdog { + compatible = "atmel,at91rm9200-wdt"; + }; + +... diff --git a/Documentation/devicetree/bindings/watchdog/atmel-at91rm9200-wdt.txt b/Documentation/devicetree/bindings/watchdog/atmel-at91rm9200-wdt.txt deleted file mode 100644 index d4d86cf8f9eb..000000000000 --- a/Documentation/devicetree/bindings/watchdog/atmel-at91rm9200-wdt.txt +++ /dev/null @@ -1,9 +0,0 @@ -Atmel AT91RM9200 System Timer Watchdog - -Required properties: -- compatible: must be "atmel,at91sam9260-wdt". - -Example: - watchdog@fffffd00 { - compatible = "atmel,at91rm9200-wdt"; - }; From patchwork Tue May 30 09:07:58 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Claudiu Beznea X-Patchwork-Id: 687670 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E5667C77B7A for ; Tue, 30 May 2023 09:08:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230232AbjE3JIs (ORCPT ); Tue, 30 May 2023 05:08:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:33312 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230054AbjE3JIm (ORCPT ); Tue, 30 May 2023 05:08:42 -0400 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.153.233]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3B39C106; Tue, 30 May 2023 02:08:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1685437715; x=1716973715; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=oJkUlU9Jd4ADpSSd4T0wXg07cVjw5hSawlz0KBTopVk=; b=14w9F/aSFQl8R0eZFD4CaZR0k3X8ui10QFKkaBlHB59yFvN6wwDngW3j Q0uAe87QWZr6L78biY0DHVZNb1LFuQUi/5gdhyoC8Y8oZ2TUp9H3Zuzka cXoP7fBEy7u7Bkj8WDUnQ0fEew2WHzAqjmXUSPV0OFCfxqTCpfwXiGNFa 4xQ2220T9TyZyW3RuPCdAC1Jo9mq5qOCK+Aut4e22xShFee+d2PMoHLFM kaXPSAFpdlDPWya5L0MEObI954smt9r0NFDuUcP3Is8GKftcupnPmp9gA IlMXkt7g01uZjppag6t+aFTZ+F/t3XTv0FoyuImcRHlFVtpmj2UZkbZZZ A==; X-IronPort-AV: E=Sophos;i="6.00,203,1681196400"; d="scan'208";a="227555122" X-Amp-Result: SKIPPED(no attachment in message) Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa1.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 May 2023 02:08:34 -0700 Received: from chn-vm-ex01.mchp-main.com (10.10.85.143) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.21; Tue, 30 May 2023 02:08:27 -0700 Received: from m18063-ThinkPad-T460p.mchp-main.com (10.10.115.15) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server id 15.1.2507.21 via Frontend Transport; Tue, 30 May 2023 02:08:22 -0700 From: Claudiu Beznea To: , , , , , , , , CC: , , , , "Claudiu Beznea" , Conor Dooley Subject: [PATCH v3 3/3] dt-bindings: timer: atmel,at91rm9200-st: convert to yaml Date: Tue, 30 May 2023 12:07:58 +0300 Message-ID: <20230530090758.1652329-4-claudiu.beznea@microchip.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230530090758.1652329-1-claudiu.beznea@microchip.com> References: <20230530090758.1652329-1-claudiu.beznea@microchip.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-watchdog@vger.kernel.org Convert Microchip AT91 system timer to YAML. Signed-off-by: Claudiu Beznea Reviewed-by: Conor Dooley --- .../devicetree/bindings/arm/atmel-sysregs.txt | 9 --- .../bindings/timer/atmel,at91rm9200-st.yaml | 66 +++++++++++++++++++ 2 files changed, 66 insertions(+), 9 deletions(-) create mode 100644 Documentation/devicetree/bindings/timer/atmel,at91rm9200-st.yaml diff --git a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt index 54d3f586403e..68c0eacb01ac 100644 --- a/Documentation/devicetree/bindings/arm/atmel-sysregs.txt +++ b/Documentation/devicetree/bindings/arm/atmel-sysregs.txt @@ -4,15 +4,6 @@ Chipid required properties: - compatible: Should be "atmel,sama5d2-chipid" or "microchip,sama7g5-chipid" - reg : Should contain registers location and length -System Timer (ST) required properties: -- compatible: Should be "atmel,at91rm9200-st", "syscon", "simple-mfd" -- reg: Should contain registers location and length -- interrupts: Should contain interrupt for the ST which is the IRQ line - shared across all System Controller members. -- clocks: phandle to input clock. -Its subnodes can be: -- watchdog: compatible should be "atmel,at91rm9200-wdt" - RAMC SDRAM/DDR Controller required properties: - compatible: Should be "atmel,at91rm9200-sdramc", "syscon" "atmel,at91sam9260-sdramc", diff --git a/Documentation/devicetree/bindings/timer/atmel,at91rm9200-st.yaml b/Documentation/devicetree/bindings/timer/atmel,at91rm9200-st.yaml new file mode 100644 index 000000000000..12d0bb7bd0c8 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/atmel,at91rm9200-st.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/atmel,at91rm9200-st.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip AT91 System Timer (ST) + +maintainers: + - Nicolas Ferre + - Alexandre Belloni + - Claudiu Beznea + +description: + Microchip AT91 system timer integrates a period interval timer, a watchdog + timer and a real-time timer. + +properties: + compatible: + items: + - const: atmel,at91rm9200-st + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + interrupts: + description: + Contain interrupt for the ST which is the IRQ line shared across all + system controller members (memory controller, debug unit, system timer, + real-time clock, power management controller). + maxItems: 1 + + clocks: + maxItems: 1 + + watchdog: + $ref: ../watchdog/atmel,at91rm9200-wdt.yaml + description: + Child node describing watchdog. + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include + + st: timer@fffffd00 { + compatible = "atmel,at91rm9200-st", "syscon", "simple-mfd"; + reg = <0xfffffd00 0x100>; + interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; + clocks = <&slow_xtal>; + + watchdog { + compatible = "atmel,at91rm9200-wdt"; + }; + }; + +...