From patchwork Thu May 25 04:03:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugo Villeneuve X-Patchwork-Id: 686359 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8B5D0C7EE31 for ; Thu, 25 May 2023 04:05:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238570AbjEYEFl (ORCPT ); Thu, 25 May 2023 00:05:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39240 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236779AbjEYEEX (ORCPT ); Thu, 25 May 2023 00:04:23 -0400 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 880D4194; Wed, 24 May 2023 21:04:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=oMgj+tKoLcLXXYaEiSRJStVpk7eDMdwwfoe9DPEgx18=; b=X9qxZM6/mjAYrAUtIhVpFVUZtU ZP2C8+4WM6+f+SMqUNUkynegFudfpBSVMpV2rSaGSQPd/cn2fRJsOh16cnqjZxhAOGv2Ie1NniUyQ XZc5Q7YilD+PkyFbsk15qoZdNcCV+44MRHZb02N9995ydMOuyMu1KOz+yOCArb+koSXk=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:52970 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1q22Cx-0001dB-0S; Thu, 25 May 2023 00:04:11 -0400 From: Hugo Villeneuve To: gregkh@linuxfoundation.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jirislaby@kernel.org, jringle@gridpoint.com, tomasz.mon@camlingroup.com, l.perczak@camlintechnologies.com Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, hugo@hugovil.com, linux-gpio@vger.kernel.org, Hugo Villeneuve Date: Thu, 25 May 2023 00:03:15 -0400 Message-Id: <20230525040324.3773741-3-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230525040324.3773741-1-hugo@hugovil.com> References: <20230525040324.3773741-1-hugo@hugovil.com> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH v3 02/11] serial: sc16is7xx: improve comments about variants X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Hugo Villeneuve Replace 740/750/760 with generic terms like 74x/75x/76x to account for variants like 741, 752 and 762. Signed-off-by: Hugo Villeneuve --- drivers/tty/serial/sc16is7xx.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index 5bd98e4316f5..00054bb49780 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -223,7 +223,7 @@ * trigger levels. Trigger levels from 4 characters to 60 characters are * available with a granularity of four. * - * When the trigger level setting in TLR is zero, the SC16IS740/750/760 uses the + * When the trigger level setting in TLR is zero, the SC16IS74x/75x/76x uses the * trigger level setting defined in FCR. If TLR has non-zero trigger level value * the trigger level defined in FCR is discarded. This applies to both transmit * FIFO and receive FIFO trigger level setting. @@ -234,7 +234,7 @@ #define SC16IS7XX_TLR_TX_TRIGGER(words) ((((words) / 4) & 0x0f) << 0) #define SC16IS7XX_TLR_RX_TRIGGER(words) ((((words) / 4) & 0x0f) << 4) -/* IOControl register bits (Only 750/760) */ +/* IOControl register bits (Only 75x/76x) */ #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ #define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */ #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ @@ -248,9 +248,9 @@ #define SC16IS7XX_EFCR_RTS_INVERT_BIT (1 << 5) /* RTS output inversion */ #define SC16IS7XX_EFCR_IRDA_MODE_BIT (1 << 7) /* IrDA mode * 0 = rate upto 115.2 kbit/s - * - Only 750/760 + * - Only 75x/76x * 1 = rate upto 1.152 Mbit/s - * - Only 760 + * - Only 76x */ /* EFR register bits */ From patchwork Thu May 25 04:03:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugo Villeneuve X-Patchwork-Id: 686358 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8D24DC7EE31 for ; Thu, 25 May 2023 04:06:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238649AbjEYEF7 (ORCPT ); Thu, 25 May 2023 00:05:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38986 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237734AbjEYEE3 (ORCPT ); Thu, 25 May 2023 00:04:29 -0400 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8FAA91A6; Wed, 24 May 2023 21:04:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=JzQwwWHfLn5GqJ+sUpssIPjhRdBj01gT2s8uoqlHWI4=; b=YJgReEa/vE2riAdBxkk5ViBMZs F8EVEKjd/h5NYSZ8FL+TWOdz/aaDrUNBHbuZ4qbjQ9HOx52QgkIeruEDteW69XE7Ji+nHcNL6TAJN RN2DHwkXn3+zgfWCLpQCBsLfxl+VX1cQLNtCDtL9DFAHcva5Vpdc6vAu9vRNQgtoXhWE=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:52970 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1q22D2-0001dB-Ii; Thu, 25 May 2023 00:04:17 -0400 From: Hugo Villeneuve To: gregkh@linuxfoundation.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jirislaby@kernel.org, jringle@gridpoint.com, tomasz.mon@camlingroup.com, l.perczak@camlintechnologies.com Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, hugo@hugovil.com, linux-gpio@vger.kernel.org, Hugo Villeneuve Date: Thu, 25 May 2023 00:03:17 -0400 Message-Id: <20230525040324.3773741-5-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230525040324.3773741-1-hugo@hugovil.com> References: <20230525040324.3773741-1-hugo@hugovil.com> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH v3 04/11] serial: sc16is7xx: add post reset delay X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Hugo Villeneuve Make sure we wait at least 3us before initiating communication with the device after reset. Signed-off-by: Hugo Villeneuve --- drivers/tty/serial/sc16is7xx.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index a7c4da3cfd2b..af7e66db54b4 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -1428,6 +1428,12 @@ static int sc16is7xx_probe(struct device *dev, regmap_write(s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, SC16IS7XX_IOCONTROL_SRESET_BIT); + /* + * After reset, the host must wait at least 3us before initializing a + * communication with the device. + */ + usleep_range(3, 5); + for (i = 0; i < devtype->nr_uart; ++i) { s->p[i].line = i; /* Initialize port data */ From patchwork Thu May 25 04:03:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugo Villeneuve X-Patchwork-Id: 686357 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 333B9C7EE31 for ; Thu, 25 May 2023 04:06:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238749AbjEYEGV (ORCPT ); Thu, 25 May 2023 00:06:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238125AbjEYEEh (ORCPT ); Thu, 25 May 2023 00:04:37 -0400 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EB31A1B5; Wed, 24 May 2023 21:04:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=oAW87YGFqDuCb1wMiNK8HhUC7h6jxZ7gmJadiuchbuo=; b=vzd6l2eDsrKJ2VXxs4taDBf9O4 Oc6N48Z1YTxaN2yl0G5InFPkYbU2KEuvAVEzFu++jEqX4jQkU+JNyeovO+Xs2OtA/uUn5I86gLMo9 2FguvfKwHawczsuTTkU5ddA7MzzVFzcfhbVrBWCIk9P430oYf6ei8yAT39I0RbcllF5I=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:52970 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1q22DE-0001dB-DC; Thu, 25 May 2023 00:04:28 -0400 From: Hugo Villeneuve To: gregkh@linuxfoundation.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jirislaby@kernel.org, jringle@gridpoint.com, tomasz.mon@camlingroup.com, l.perczak@camlintechnologies.com Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, hugo@hugovil.com, linux-gpio@vger.kernel.org, Hugo Villeneuve Date: Thu, 25 May 2023 00:03:20 -0400 Message-Id: <20230525040324.3773741-7-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230525040324.3773741-1-hugo@hugovil.com> References: <20230525040324.3773741-1-hugo@hugovil.com> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH v3 06/11] serial: sc16is7xx: fix bug when first setting GPIO direction X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Hugo Villeneuve When we want to configure a pin as an output pin with a value of logic 0, we end up as having a value of logic 1 on the output pin. Setting a logic 0 a second time (or more) after that will correctly output a logic 0 on the output pin. By default, all GPIO pins are configured as inputs. When we enter c16is7xx_gpio_direction_output() for the first time, we first set the desired value in IOSTATE, and then we configure the pin as an output. The datasheet states that writing to IOSTATE register will trigger a transfer of the value to the I/O pin configured as output, so if the pin is configured as an input, nothing will be transferred. Therefore, set the direction first in IODIR, and then set the desired value in IOSTATE. This is what is done in NXP application note AN10587. Fixes: dfeae619d781 ("serial: sc16is7xx") Signed-off-by: Hugo Villeneuve --- drivers/tty/serial/sc16is7xx.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index 8a2fc6f89d36..a5d8af0f6da0 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -1343,9 +1343,18 @@ static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, state |= BIT(offset); else state &= ~BIT(offset); - sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); + + /* + * If we write IOSTATE first, and then IODIR, the output value is not + * transferred to the corresponding I/O pin. + * The datasheet states that each register bit will be transferred to + * the corresponding I/O pin programmed as output when writing to + * IOSTATE. Therefore, configure direction first with IODIR, and then + * set value after with IOSTATE. + */ sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), BIT(offset)); + sc16is7xx_port_write(port, SC16IS7XX_IOSTATE_REG, state); return 0; } From patchwork Thu May 25 04:03:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugo Villeneuve X-Patchwork-Id: 686356 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5E765C7EE3A for ; Thu, 25 May 2023 04:06:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238809AbjEYEGX (ORCPT ); Thu, 25 May 2023 00:06:23 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39488 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S238427AbjEYEEl (ORCPT ); Thu, 25 May 2023 00:04:41 -0400 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DFDE51BD; Wed, 24 May 2023 21:04:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=JiheQ8Q8tkLBdJvTWHP7zHAZ71XGjHsp7B6ulAHNFcA=; b=U4DBiBAJsgcGOFh9IbpqBjXOUv UnAAVx9ROJmWFNzrvAmmE/W9hORoX+16rWwrjZ/iZBAz7BeiY0X4YBdISLjpm6AbfzSXgzd0ysQFX 9bsS9sigwl4GbOEGFBIbOt0l7HfHbCelI791/m+N14c3JNM0VNGDBsvJEcugZ8N0XuAc=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:52970 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1q22DH-0001dB-9Z; Thu, 25 May 2023 00:04:32 -0400 From: Hugo Villeneuve To: gregkh@linuxfoundation.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jirislaby@kernel.org, jringle@gridpoint.com, tomasz.mon@camlingroup.com, l.perczak@camlintechnologies.com Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, hugo@hugovil.com, linux-gpio@vger.kernel.org, Hugo Villeneuve Date: Thu, 25 May 2023 00:03:22 -0400 Message-Id: <20230525040324.3773741-9-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230525040324.3773741-1-hugo@hugovil.com> References: <20230525040324.3773741-1-hugo@hugovil.com> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH v3 08/11] serial: sc16is7xx: fix regression with GPIO configuration X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Hugo Villeneuve Commit 679875d1d880 ("sc16is7xx: Separate GPIOs from modem control lines") and commit 21144bab4f11 ("sc16is7xx: Handle modem status lines") changed the function of the GPIOs pins to act as modem control lines without any possibility of selecting GPIO function. As a consequence, applications that depends on GPIO lines configured by default as GPIO pins no longer work as expected. Also, the change to select modem control lines function was done only for channel A of dual UART variants (752/762). This was not documented in the log message. This new patch allows to specify GPIO or modem control line function in the device tree, and for each of the ports (A or B). This is done by using the new device-tree property named "modem-control-line-ports" (property added in separate patch). We also now reduce the number of exported GPIOs according to the modem-status-line-port DT property. Boards that need to have GPIOS configured as modem control lines should add that property to their device tree. Here is a list of boards using the sc16is7xx driver in their device tree and that may need to be modified: arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts mips/boot/dts/ingenic/cu1830-neo.dts mips/boot/dts/ingenic/cu1000-neo.dts Fixes: 679875d1d880 ("sc16is7xx: Separate GPIOs from modem control lines") Fixes: 21144bab4f11 ("sc16is7xx: Handle modem status lines") Signed-off-by: Hugo Villeneuve --- drivers/tty/serial/sc16is7xx.c | 65 +++++++++++++++++++++++----------- 1 file changed, 44 insertions(+), 21 deletions(-) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index a5d8af0f6da0..97ec532a0a19 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -236,7 +236,8 @@ /* IOControl register bits (Only 75x/76x) */ #define SC16IS7XX_IOCONTROL_LATCH_BIT (1 << 0) /* Enable input latching */ -#define SC16IS7XX_IOCONTROL_MODEM_BIT (1 << 1) /* Enable GPIO[7:4] as modem pins */ +#define SC16IS7XX_IOCONTROL_MODEM_A_BIT (1 << 1) /* Enable GPIO[7:4] as modem A pins */ +#define SC16IS7XX_IOCONTROL_MODEM_B_BIT (1 << 2) /* Enable GPIO[3:0] as modem B pins */ #define SC16IS7XX_IOCONTROL_SRESET_BIT (1 << 3) /* Software Reset */ /* EFCR register bits */ @@ -301,12 +302,12 @@ /* Misc definitions */ #define SC16IS7XX_FIFO_SIZE (64) #define SC16IS7XX_REG_SHIFT 2 +#define SC16IS7XX_GPIOS_PER_BANK 4 struct sc16is7xx_devtype { char name[10]; int nr_gpio; int nr_uart; - int has_mctrl; }; #define SC16IS7XX_RECONF_MD (1 << 0) @@ -336,6 +337,7 @@ struct sc16is7xx_port { struct clk *clk; #ifdef CONFIG_GPIOLIB struct gpio_chip gpio; + int gpio_configured; #endif unsigned char buf[SC16IS7XX_FIFO_SIZE]; struct kthread_worker kworker; @@ -447,35 +449,30 @@ static const struct sc16is7xx_devtype sc16is74x_devtype = { .name = "SC16IS74X", .nr_gpio = 0, .nr_uart = 1, - .has_mctrl = 0, }; static const struct sc16is7xx_devtype sc16is750_devtype = { .name = "SC16IS750", - .nr_gpio = 4, + .nr_gpio = 8, .nr_uart = 1, - .has_mctrl = 1, }; static const struct sc16is7xx_devtype sc16is752_devtype = { .name = "SC16IS752", - .nr_gpio = 0, + .nr_gpio = 8, .nr_uart = 2, - .has_mctrl = 1, }; static const struct sc16is7xx_devtype sc16is760_devtype = { .name = "SC16IS760", - .nr_gpio = 4, + .nr_gpio = 8, .nr_uart = 1, - .has_mctrl = 1, }; static const struct sc16is7xx_devtype sc16is762_devtype = { .name = "SC16IS762", - .nr_gpio = 0, + .nr_gpio = 8, .nr_uart = 2, - .has_mctrl = 1, }; static bool sc16is7xx_regmap_volatile(struct device *dev, unsigned int reg) @@ -1396,6 +1393,10 @@ static int sc16is7xx_probe(struct device *dev, return -ENOMEM; } +#ifdef CONFIG_GPIOLIB + s->gpio_configured = devtype->nr_gpio; +#endif /* CONFIG_GPIOLIB */ + /* Always ask for fixed clock rate from a property. */ device_property_read_u32(dev, "clock-frequency", &uartclk); @@ -1473,12 +1474,6 @@ static int sc16is7xx_probe(struct device *dev, SC16IS7XX_EFCR_RXDISABLE_BIT | SC16IS7XX_EFCR_TXDISABLE_BIT); - /* Use GPIO lines as modem status registers */ - if (devtype->has_mctrl) - sc16is7xx_port_write(&s->p[i].port, - SC16IS7XX_IOCONTROL_REG, - SC16IS7XX_IOCONTROL_MODEM_BIT); - /* Initialize kthread work structs */ kthread_init_work(&s->p[i].tx_work, sc16is7xx_tx_proc); kthread_init_work(&s->p[i].reg_work, sc16is7xx_reg_proc); @@ -1514,10 +1509,38 @@ static int sc16is7xx_probe(struct device *dev, prop, p, u) if (u < devtype->nr_uart) s->p[u].irda_mode = true; + + val = 0; + + of_property_for_each_u32(dev->of_node, "nxp,modem-control-line-ports", + prop, p, u) + if (u < devtype->nr_uart) { + /* Use GPIO lines as modem control lines */ + if (u == 0) + val |= SC16IS7XX_IOCONTROL_MODEM_A_BIT; + else if (u == 1) + val |= SC16IS7XX_IOCONTROL_MODEM_B_BIT; + +#ifdef CONFIG_GPIOLIB + if (s->gpio_configured >= + SC16IS7XX_GPIOS_PER_BANK) + s->gpio_configured -= + SC16IS7XX_GPIOS_PER_BANK; +#endif /* CONFIG_GPIOLIB */ + } + + if (val) + regmap_update_bits( + s->regmap, + SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, + SC16IS7XX_IOCONTROL_MODEM_A_BIT | + SC16IS7XX_IOCONTROL_MODEM_B_BIT, val); } #ifdef CONFIG_GPIOLIB - if (devtype->nr_gpio) { + dev_dbg(dev, "GPIOs to configure: %d\n", s->gpio_configured); + + if (s->gpio_configured) { /* Setup GPIO controller */ s->gpio.owner = THIS_MODULE; s->gpio.parent = dev; @@ -1527,7 +1550,7 @@ static int sc16is7xx_probe(struct device *dev, s->gpio.direction_output = sc16is7xx_gpio_direction_output; s->gpio.set = sc16is7xx_gpio_set; s->gpio.base = -1; - s->gpio.ngpio = devtype->nr_gpio; + s->gpio.ngpio = s->gpio_configured; s->gpio.can_sleep = 1; ret = gpiochip_add_data(&s->gpio, s); if (ret) @@ -1555,7 +1578,7 @@ static int sc16is7xx_probe(struct device *dev, return 0; #ifdef CONFIG_GPIOLIB - if (devtype->nr_gpio) + if (s->gpio_configured) gpiochip_remove(&s->gpio); out_thread: @@ -1581,7 +1604,7 @@ static void sc16is7xx_remove(struct device *dev) int i; #ifdef CONFIG_GPIOLIB - if (s->devtype->nr_gpio) + if (s->gpio_configured) gpiochip_remove(&s->gpio); #endif From patchwork Thu May 25 04:03:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugo Villeneuve X-Patchwork-Id: 686355 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19210C7EE32 for ; Thu, 25 May 2023 04:06:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S238864AbjEYEGe (ORCPT ); Thu, 25 May 2023 00:06:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:39794 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231764AbjEYEEv (ORCPT ); Thu, 25 May 2023 00:04:51 -0400 Received: from mail.hugovil.com (mail.hugovil.com [162.243.120.170]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5AD57E62; Wed, 24 May 2023 21:04:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=hugovil.com ; s=x; h=Subject:Content-Transfer-Encoding:MIME-Version:References: In-Reply-To:Message-Id:Date:Cc:To:From:Sender:Reply-To:Content-Type: Content-ID:Content-Description:Resent-Date:Resent-From:Resent-Sender: Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=9uFf80nuPq7IpOBCTtsrmsGYtNovsW/4uJuo42PakOo=; b=hZS8RhBGHMEWLID3br+gSAdS39 WNwEED5LXP+qFQrO0SMH4y60c3mBJasKvbCKoLvBfl7dcE1drHXktQSModQe0c9gXeMrMzRV8IVgR XTy5IQ0QncyR5VRTIM4p2KUUwtvNMtP35sRxeB6GinMfzzB5l+wz4CcO7mFLpQV2zIwY=; Received: from modemcable168.174-80-70.mc.videotron.ca ([70.80.174.168]:52970 helo=pettiford.lan) by mail.hugovil.com with esmtpa (Exim 4.92) (envelope-from ) id 1q22DJ-0001dB-5g; Thu, 25 May 2023 00:04:34 -0400 From: Hugo Villeneuve To: gregkh@linuxfoundation.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, conor+dt@kernel.org, jirislaby@kernel.org, jringle@gridpoint.com, tomasz.mon@camlingroup.com, l.perczak@camlintechnologies.com Cc: linux-serial@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, hugo@hugovil.com, linux-gpio@vger.kernel.org, Hugo Villeneuve Date: Thu, 25 May 2023 00:03:23 -0400 Message-Id: <20230525040324.3773741-10-hugo@hugovil.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20230525040324.3773741-1-hugo@hugovil.com> References: <20230525040324.3773741-1-hugo@hugovil.com> MIME-Version: 1.0 X-SA-Exim-Connect-IP: 70.80.174.168 X-SA-Exim-Mail-From: hugo@hugovil.com Subject: [PATCH v3 09/11] serial: sc16is7xx: add I/O register translation offset X-SA-Exim-Version: 4.2.1 (built Wed, 08 May 2019 21:11:16 +0000) X-SA-Exim-Scanned: Yes (on mail.hugovil.com) Precedence: bulk List-ID: X-Mailing-List: linux-serial@vger.kernel.org From: Hugo Villeneuve If the shared GPIO pins on a dual port/channel variant like the SC16IS752 are configured as GPIOs for port A, and modem control lines on port A, we need to translate the Linux GPIO offset to an offset that is compatible with the I/O registers of the SC16IS7XX (IOState, IODir and IOIntEna). Add a new variable to store that offset and set it when we detect that special case. Signed-off-by: Hugo Villeneuve --- drivers/tty/serial/sc16is7xx.c | 54 +++++++++++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) diff --git a/drivers/tty/serial/sc16is7xx.c b/drivers/tty/serial/sc16is7xx.c index 97ec532a0a19..c2cfd057ed9a 100644 --- a/drivers/tty/serial/sc16is7xx.c +++ b/drivers/tty/serial/sc16is7xx.c @@ -338,6 +338,7 @@ struct sc16is7xx_port { #ifdef CONFIG_GPIOLIB struct gpio_chip gpio; int gpio_configured; + int gpio_offset; #endif unsigned char buf[SC16IS7XX_FIFO_SIZE]; struct kthread_worker kworker; @@ -1298,12 +1299,50 @@ static const struct uart_ops sc16is7xx_ops = { }; #ifdef CONFIG_GPIOLIB + +/* + * We may need to translate the Linux GPIO offset to a SC16IS7XX offset. + * This is needed only for the case where a dual port variant is configured to + * have only port B as modem status lines. + * + * Example for SC16IS752/762 with upper bank (port A) set as GPIOs, and + * lower bank (port B) set as modem status lines (special case described above): + * + * Pin GPIO pin Linux GPIO SC16IS7XX + * name function offset offset + * -------------------------------------------------- + * GPIO7/RIA GPIO7 3 7 + * GPIO6/CDA GPIO6 2 6 + * GPIO5/DTRA GPIO5 1 5 + * GPIO4/DSRA GPIO4 0 4 + * GPIO3/RIB RIB N/A N/A + * GPIO2/CDB CDB N/A N/A + * GPIO1/DTRB DTRB N/A N/A + * GPIO0/DSRB DSRB N/A N/A + * + * Example for SC16IS750/760 with upper bank (7..4) set as modem status lines, + * and lower bank (3..0) as GPIOs: + * + * Pin GPIO pin Linux GPIO SC16IS7XX + * name function offset offset + * -------------------------------------------------- + * GPIO7/RI RI N/A N/A + * GPIO6/CD CD N/A N/A + * GPIO5/DTR DTR N/A N/A + * GPIO4/DSR DSR N/A N/A + * GPIO3 GPIO3 3 3 + * GPIO2 GPIO2 2 2 + * GPIO1 GPIO1 1 1 + * GPIO0 GPIO0 0 0 + */ + static int sc16is7xx_gpio_get(struct gpio_chip *chip, unsigned offset) { unsigned int val; struct sc16is7xx_port *s = gpiochip_get_data(chip); struct uart_port *port = &s->p[0].port; + offset += s->gpio_offset; val = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); return !!(val & BIT(offset)); @@ -1314,6 +1353,7 @@ static void sc16is7xx_gpio_set(struct gpio_chip *chip, unsigned offset, int val) struct sc16is7xx_port *s = gpiochip_get_data(chip); struct uart_port *port = &s->p[0].port; + offset += s->gpio_offset; sc16is7xx_port_update(port, SC16IS7XX_IOSTATE_REG, BIT(offset), val ? BIT(offset) : 0); } @@ -1324,6 +1364,7 @@ static int sc16is7xx_gpio_direction_input(struct gpio_chip *chip, struct sc16is7xx_port *s = gpiochip_get_data(chip); struct uart_port *port = &s->p[0].port; + offset += s->gpio_offset; sc16is7xx_port_update(port, SC16IS7XX_IODIR_REG, BIT(offset), 0); return 0; @@ -1336,6 +1377,8 @@ static int sc16is7xx_gpio_direction_output(struct gpio_chip *chip, struct uart_port *port = &s->p[0].port; u8 state = sc16is7xx_port_read(port, SC16IS7XX_IOSTATE_REG); + offset += s->gpio_offset; + if (val) state |= BIT(offset); else @@ -1395,6 +1438,7 @@ static int sc16is7xx_probe(struct device *dev, #ifdef CONFIG_GPIOLIB s->gpio_configured = devtype->nr_gpio; + s->gpio_offset = 0; #endif /* CONFIG_GPIOLIB */ /* Always ask for fixed clock rate from a property. */ @@ -1529,16 +1573,24 @@ static int sc16is7xx_probe(struct device *dev, #endif /* CONFIG_GPIOLIB */ } - if (val) + if (val) { +#ifdef CONFIG_GPIOLIB + /* Additional I/O regs offset. */ + if (val == SC16IS7XX_IOCONTROL_MODEM_B_BIT) + s->gpio_offset = SC16IS7XX_GPIOS_PER_BANK; +#endif /* CONFIG_GPIOLIB */ + regmap_update_bits( s->regmap, SC16IS7XX_IOCONTROL_REG << SC16IS7XX_REG_SHIFT, SC16IS7XX_IOCONTROL_MODEM_A_BIT | SC16IS7XX_IOCONTROL_MODEM_B_BIT, val); + } } #ifdef CONFIG_GPIOLIB dev_dbg(dev, "GPIOs to configure: %d\n", s->gpio_configured); + dev_dbg(dev, "GPIOs offset: %d\n", s->gpio_offset); if (s->gpio_configured) { /* Setup GPIO controller */