From patchwork Fri May 26 13:31:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shazad Hussain X-Patchwork-Id: 686196 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B184BC77B73 for ; Fri, 26 May 2023 13:32:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243684AbjEZNcQ (ORCPT ); Fri, 26 May 2023 09:32:16 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35380 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243704AbjEZNcM (ORCPT ); Fri, 26 May 2023 09:32:12 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8DA912F; Fri, 26 May 2023 06:32:09 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34QD09S0003717; Fri, 26 May 2023 13:32:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=2P6wC10aRXevD+aXA/LQ1UAN905Wp4mvJUp7ZwCVpDo=; b=FSSy8QQ05bYhus+z2VqGvrkNb2nb24RjOA1MJckGbcdKY/IF2BN1o2eibGbmPkeTLA5f WDIa/TYe2zc0w9ELGs7gfW/EmJfoMVyu1JwduPe4ie/WIlty439gzY1GxORxsbDQceaE dKZP4uqnHKvqWRP/NF4S7nnilLfNp5VSNR+AWMot8y5BlJBQhxPZ9Zr6PTgc10rgyKxt YFOw55jy7REU9qh6nbxNlHzftP6OyQkvRVVxSdCLbuTmxP/dnSkgLC8mhh4RB/l1OET8 9unA7tnnCqiRxl2s3cjC1sz16XEhhSpFbXOnpiAIjv1p9/bBmVhFxmhuq+ZZnc7juRdK Sw== Received: from nalasppmta03.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qtp4wh0bn-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 May 2023 13:32:05 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA03.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34QDW4Vc028704 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 May 2023 13:32:04 GMT Received: from hu-shazhuss-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 26 May 2023 06:32:01 -0700 From: Shazad Hussain To: , , , , CC: , Shazad Hussain , , , Subject: [PATCH v1 1/5] arm64: dts: qcom: sa8775p: add the QUPv3 #0 and #3 node Date: Fri, 26 May 2023 19:01:17 +0530 Message-ID: <20230526133122.16443-2-quic_shazhuss@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230526133122.16443-1-quic_shazhuss@quicinc.com> References: <20230526133122.16443-1-quic_shazhuss@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: qEoJbYckWNOtnn6WFM9G5kP5hhZlxnzu X-Proofpoint-ORIG-GUID: qEoJbYckWNOtnn6WFM9G5kP5hhZlxnzu X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-26_01,2023-05-25_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 phishscore=0 adultscore=0 clxscore=1015 suspectscore=0 malwarescore=0 bulkscore=0 impostorscore=0 mlxlogscore=907 lowpriorityscore=0 mlxscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305260114 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add zeroth and third instance of the QUPv3 engine to the sa8775p.dtsi. Signed-off-by: Shazad Hussain --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index fbe98ff1bcf8..27af8386a3f8 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -568,6 +568,19 @@ }; }; + qupv3_id_0: geniqup@9c0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0x9c0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; + iommus = <&apps_smmu 0x403 0x0>; + status = "disabled"; + }; + qupv3_id_1: geniqup@ac0000 { compatible = "qcom,geni-se-qup"; reg = <0x0 0x00ac0000 0x0 0x6000>; @@ -612,6 +625,19 @@ }; }; + qupv3_id_3: geniqup@bc0000 { + compatible = "qcom,geni-se-qup"; + reg = <0x0 0xbc0000 0x0 0x6000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + clock-names = "m-ahb", "s-ahb"; + clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, + <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; + iommus = <&apps_smmu 0x43 0x0>; + status = "disabled"; + }; + ufs_mem_hc: ufs@1d84000 { compatible = "qcom,sa8775p-ufshc", "qcom,ufshc", "jedec,ufs-2.0"; reg = <0x0 0x01d84000 0x0 0x3000>; From patchwork Fri May 26 13:31:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shazad Hussain X-Patchwork-Id: 686195 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFEE5C7EE23 for ; Fri, 26 May 2023 13:32:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243736AbjEZNcd (ORCPT ); Fri, 26 May 2023 09:32:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35588 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243728AbjEZNc3 (ORCPT ); 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Fri, 26 May 2023 13:32:18 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34QDWHqu015500 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 May 2023 13:32:17 GMT Received: from hu-shazhuss-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 26 May 2023 06:32:14 -0700 From: Shazad Hussain To: , , , , CC: , Shazad Hussain , , , Subject: [PATCH v1 3/5] arm64: dts: qcom: sa8775p: add missing spi nodes Date: Fri, 26 May 2023 19:01:19 +0530 Message-ID: <20230526133122.16443-4-quic_shazhuss@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230526133122.16443-1-quic_shazhuss@quicinc.com> References: <20230526133122.16443-1-quic_shazhuss@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: 0WiaP_fcwXGp5dBT694z3sznG0TbSUM_ X-Proofpoint-GUID: 0WiaP_fcwXGp5dBT694z3sznG0TbSUM_ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-26_01,2023-05-25_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 mlxlogscore=999 lowpriorityscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305260114 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the missing nodes of the SPI buses present on sa8775p platform. Signed-off-by: Shazad Hussain --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 399 ++++++++++++++++++++++++++ 1 file changed, 399 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index abcd6b17b8d1..5c7b838d239a 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -531,6 +531,27 @@ status = "disabled"; }; + spi14: spi@880000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x880000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c15: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x884000 0x0 0x4000>; @@ -552,6 +573,27 @@ status = "disabled"; }; + spi15: spi@884000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x884000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c16: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x888000 0x0 0x4000>; @@ -615,6 +657,27 @@ status = "disabled"; }; + spi17: spi@88c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x88c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + uart17: serial@88c000 { compatible = "qcom,geni-uart"; reg = <0x0 0x0088c000 0x0 0x4000>; @@ -651,6 +714,27 @@ status = "disabled"; }; + spi18: spi@890000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x890000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c19: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x894000 0x0 0x4000>; @@ -672,6 +756,27 @@ status = "disabled"; }; + spi19: spi@894000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x894000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c20: i2c@898000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x898000 0x0 0x4000>; @@ -692,6 +797,27 @@ power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; + + spi20: spi@898000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x898000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_0: geniqup@9c0000 { @@ -727,6 +853,27 @@ status = "disabled"; }; + spi0: spi@980000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x980000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c1: i2c@984000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x984000 0x0 0x4000>; @@ -748,6 +895,27 @@ status = "disabled"; }; + spi1: spi@984000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x984000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c2: i2c@988000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x988000 0x0 0x4000>; @@ -769,6 +937,27 @@ status = "disabled"; }; + spi2: spi@988000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x988000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c3: i2c@98c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x98c000 0x0 0x4000>; @@ -790,6 +979,27 @@ status = "disabled"; }; + spi3: spi@98c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x98c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c4: i2c@990000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x990000 0x0 0x4000>; @@ -811,6 +1021,27 @@ status = "disabled"; }; + spi4: spi@990000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x990000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c5: i2c@994000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x994000 0x0 0x4000>; @@ -831,6 +1062,27 @@ power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; + + spi5: spi@994000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0x994000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_0 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; qupv3_id_1: geniqup@ac0000 { @@ -866,6 +1118,27 @@ status = "disabled"; }; + spi7: spi@a80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c8: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa84000 0x0 0x4000>; @@ -887,6 +1160,27 @@ status = "disabled"; }; + spi8: spi@a84000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa84000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c9: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa88000 0x0 0x4000>; @@ -908,6 +1202,27 @@ status = "disabled"; }; + spi9: spi@a88000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c10: i2c@a8c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa8c000 0x0 0x4000>; @@ -929,6 +1244,27 @@ status = "disabled"; }; + spi10: spi@a8c000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + uart10: serial@a8c000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00a8c000 0x0 0x4000>; @@ -966,6 +1302,27 @@ status = "disabled"; }; + spi11: spi@a90000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa90000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c12: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa94000 0x0 0x4000>; @@ -987,6 +1344,27 @@ status = "disabled"; }; + spi12: spi@a94000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xa94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>, + <&aggre2_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + uart12: serial@a94000 { compatible = "qcom,geni-uart"; reg = <0x0 0x00a94000 0x0 0x4000>; @@ -1056,6 +1434,27 @@ power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; + + spi21: spi@b80000 { + compatible = "qcom,geni-spi"; + reg = <0x0 0xb80000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = ; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>, + <&aggre1_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", + "qup-config", + "qup-memory"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; }; ufs_mem_hc: ufs@1d84000 { From patchwork Fri May 26 13:31:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shazad Hussain X-Patchwork-Id: 686194 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DB29CC7EE2C for ; Fri, 26 May 2023 13:32:58 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243718AbjEZNc5 (ORCPT ); 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Fri, 26 May 2023 13:32:31 +0000 Received: from nalasex01b.na.qualcomm.com (nalasex01b.na.qualcomm.com [10.47.209.197]) by NALASPPMTA05.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34QDWVk6006374 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 26 May 2023 13:32:31 GMT Received: from hu-shazhuss-hyd.qualcomm.com (10.80.80.8) by nalasex01b.na.qualcomm.com (10.47.209.197) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Fri, 26 May 2023 06:32:27 -0700 From: Shazad Hussain To: , , , , CC: , Shazad Hussain , , , Subject: [PATCH v1 5/5] arm64: dts: qcom: sa8775p-ride: enable i2c11 Date: Fri, 26 May 2023 19:01:21 +0530 Message-ID: <20230526133122.16443-6-quic_shazhuss@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230526133122.16443-1-quic_shazhuss@quicinc.com> References: <20230526133122.16443-1-quic_shazhuss@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01b.na.qualcomm.com (10.47.209.197) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: AgdW1uKOA-wunjIC5mfJrgcF5h4JAaMe X-Proofpoint-GUID: AgdW1uKOA-wunjIC5mfJrgcF5h4JAaMe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-26_01,2023-05-25_03,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 spamscore=0 priorityscore=1501 bulkscore=0 impostorscore=0 mlxlogscore=951 lowpriorityscore=0 clxscore=1015 phishscore=0 malwarescore=0 mlxscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305260114 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This enables the i2c11 node on sa8775p-ride board for A2B controller and audio port expander. Signed-off-by: Shazad Hussain --- arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts index 4c000a5cb3c4..ab767cfa51ff 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts @@ -19,6 +19,7 @@ serial0 = &uart10; serial1 = &uart12; serial2 = &uart17; + i2c11 = &i2c11; i2c18 = &i2c18; spi16 = &spi16; ufshc1 = &ufs_mem_hc; @@ -260,6 +261,13 @@ }; }; +&i2c11 { + clock-frequency = <400000>; + pinctrl-0 = <&qup_i2c11_default>; + pinctrl-names = "default"; + status = "okay"; +}; + &i2c18 { clock-frequency = <400000>; pinctrl-0 = <&qup_i2c18_default>; @@ -370,6 +378,13 @@ bias-disable; }; + qup_i2c11_default: qup-i2c11-state { + pins = "gpio48", "gpio49"; + function = "qup1_se4"; + drive-strength = <2>; + bias-pull-up; + }; + qup_i2c18_default: qup-i2c18-state { pins = "gpio95", "gpio96"; function = "qup2_se4";