From patchwork Wed May 24 14:06:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Taniya Das X-Patchwork-Id: 686054 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC320C7EE2D for ; Wed, 24 May 2023 14:07:37 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235851AbjEXOHg (ORCPT ); Wed, 24 May 2023 10:07:36 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47810 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235833AbjEXOHe (ORCPT ); Wed, 24 May 2023 10:07:34 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E903312F; Wed, 24 May 2023 07:07:31 -0700 (PDT) Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 34ODK3KB007487; Wed, 24 May 2023 14:07:28 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-type; s=qcppdkim1; bh=IiWgxrw+DsmnbsHRWht4wn5W6abzsdX5Av7pdhDTV6o=; b=jPs8UZLt55Hk16ctxhVQQGg3eHmVFwNs6DcAc4+bh+FzuBM8OeFHAP5tdVl+V95nMUDy I8KoyAcTyFgXqMVPDT5SlTVwjMSdU2mP7T5S/uo1Jn5VoOhJ/x3tsiyWe3hMpu1siu5P p6g58livsdXd+v/i3y80Y9DOcwX3c9dMfghODTO3lEHsgMfWM9VMcN5L16IDJ7hn83xS +qkrN7OInCOjjbx7RY846fpYm8SwbO0Y6MKs/caK3LpsXuBFRpN/wTDe0xK7hIOTgfGF dFHT4Nehb/n45sDfpBXYio80SreL2HgfLMrpibWFTCPfNeiFi0DEMZxz3DC2s788YEjO 6A== Received: from nalasppmta01.qualcomm.com (Global_NAT1.qualcomm.com [129.46.96.20]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qscpms1ct-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 24 May 2023 14:07:28 +0000 Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 34OE7R32008889 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 24 May 2023 14:07:27 GMT Received: from hu-tdas-hyd.qualcomm.com (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Wed, 24 May 2023 07:07:23 -0700 From: Taniya Das To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley CC: Konrad Dybcio , , , , , Taniya Das , , , Subject: [PATCH V5 3/3] arm64: dts: qcom: sm8450: Add video clock controller Date: Wed, 24 May 2023 19:36:56 +0530 Message-ID: <20230524140656.7076-4-quic_tdas@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20230524140656.7076-1-quic_tdas@quicinc.com> References: <20230524140656.7076-1-quic_tdas@quicinc.com> MIME-Version: 1.0 X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01b.na.qualcomm.com (10.46.141.250) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: dTYX7K3DQsSAzGke1PENKLZsihxqonQj X-Proofpoint-GUID: dTYX7K3DQsSAzGke1PENKLZsihxqonQj X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.957,Hydra:6.0.573,FMLib:17.11.176.26 definitions=2023-05-24_09,2023-05-24_01,2023-05-22_02 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 adultscore=0 malwarescore=0 bulkscore=0 spamscore=0 suspectscore=0 mlxscore=0 phishscore=0 lowpriorityscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305240115 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add device node for video clock controller on Qualcomm SM8450 platform. Signed-off-by: Taniya Das --- Changes since V4: - Sort the DT node by unit address. - include videocc header. Changes since V3: - None. Changes since V2: - No changes. Changes since V1: - No changes. arch/arm64/boot/dts/qcom/sm8450.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) -- 2.17.1 diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi index 595533aeafc4..8bc6d1498b57 100644 --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -2572,6 +2573,18 @@ }; }; + videocc: clock-controller@aaf0000 { + compatible = "qcom,sm8450-videocc"; + reg = <0 0x0aaf0000 0 0x10000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>; + power-domains = <&rpmhpd SM8450_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + cci0: cci@ac15000 { compatible = "qcom,sm8450-cci", "qcom,msm8996-cci"; reg = <0 0x0ac15000 0 0x1000>;