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[93.5.22.158]) by smtp.googlemail.com with ESMTPSA id n4-20020a05600c294400b003f3157988f8sm2349559wmd.26.2023.05.25.07.50.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 25 May 2023 07:50:40 -0700 (PDT) From: Alexandre Mergnat Date: Thu, 25 May 2023 16:50:27 +0200 Subject: [PATCH v2 1/2] dt-bindings: clock: mediatek: replace unusable clock MIME-Version: 1.0 Message-Id: <20230517-fix-clk-index-v2-1-1b686cefcb7e@baylibre.com> References: <20230517-fix-clk-index-v2-0-1b686cefcb7e@baylibre.com> In-Reply-To: <20230517-fix-clk-index-v2-0-1b686cefcb7e@baylibre.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chen-Yu Tsai Cc: Markus Schneider-Pargmann , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, Alexandre Mergnat X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1018; i=amergnat@baylibre.com; h=from:subject:message-id; bh=OTCpf/cGWX/QOa+k7U0XGlCX28v0JhFQ08iD6/fULvs=; b=owEBbQKS/ZANAwAKAStGSZ1+MdRFAcsmYgBkb3W+pK5Qktvbj+oP/LMTRHEHloR67cHOvXTgd2LW dFOw9wSJAjMEAAEKAB0WIQQjG17X8+qqcA5g/osrRkmdfjHURQUCZG91vgAKCRArRkmdfjHURfElD/ 4hfHecM1fx+yBLw5NYTj/6RqIFsLxIIyQbHNLDQ5/s8ICD8S77k6rhGsLhdrps8Buh/RmvzxD4spRV kCYEfz6n5CwEktvF3Wzi3p0Ybmw+WMnk2mBiP4F5Q1243KtrAr6pJbKuOxuRRXTTOmhHCWhH28OlSz +DhTPwzTlXfMBhkL8bF36YRgFuCEDDKd4LXk7tLd2j0SptQp8vK4emu72Z0SknrP8ISVeDf+9kc9jW 2oFagHjJ93dMCu5s9qIuaMTvcgs6GtPcSf6HBxGKc2/6aSxnigUQr4N2Q2V5kwMrPadNIzqsXqG9Rt zoUskveZR0+Y4kH5SaNUpGIdOV9fTzEx/9ZBE5pCVFCxv7wE8sbLQuL8ydX/VRO8a527B0OMTmTwLC aHBhs2hbL/RiffOWhuyLwnhnsTm4Wxf6D4DrjkoEChXmgTCwCeYUXMo3AfU48Qp1Lwfkk3ElMXB7qI e38e1/pVG1tfdkhR/XFJvzDx1ATbsN6/wHC7+DB/1mBFU6PIM38y1FKiXe+zz7GT+kpgBmP+g4Pqmm v3NSNm7VP4tqy6NicpXR78U0hJHUREee7xc62d24qaHG0xqWZhSeU+5iEBDBtJ64xjeoYIcthDSMzS eTOhjSjMialozHY9QY+pZ6oa2mLQp2ydFlGWTKpnXc4qZV6ynS2OuIKU+6vg== X-Developer-Key: i=amergnat@baylibre.com; a=openpgp; fpr=231B5ED7F3EAAA700E60FE8B2B46499D7E31D445 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The “mcu_pm_bclk_ck_cg” clock is used by co-processors and should not be added to the kernel driver, otherwise the CPU just halt and the board is rebooted by the wathdog. Instead, add the "aes_top0_bclk_ck_cg" missing clock to prevent re-shuffling index and then preserve the ABI. Signed-off-by: Alexandre Mergnat --- include/dt-bindings/clock/mediatek,mt8365-clk.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/dt-bindings/clock/mediatek,mt8365-clk.h b/include/dt-bindings/clock/mediatek,mt8365-clk.h index f9aff1775810..0a841e7cc1c3 100644 --- a/include/dt-bindings/clock/mediatek,mt8365-clk.h +++ b/include/dt-bindings/clock/mediatek,mt8365-clk.h @@ -199,7 +199,7 @@ #define CLK_IFR_PWRAP_TMR 46 #define CLK_IFR_PWRAP_SPI 47 #define CLK_IFR_PWRAP_SYS 48 -#define CLK_IFR_MCU_PM_BK 49 +#define CLK_IFR_AES_TOP0_BK 49 #define CLK_IFR_IRRX_26M 50 #define CLK_IFR_IRRX_32K 51 #define CLK_IFR_I2C0_AXI 52