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Tue, 23 May 2023 07:57:02 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=amd.com; Received-SPF: Pass (protection.outlook.com: domain of amd.com designates 165.204.84.17 as permitted sender) receiver=protection.outlook.com; client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by CY4PEPF0000C978.mail.protection.outlook.com (10.167.241.139) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.6433.7 via Frontend Transport; Tue, 23 May 2023 07:57:01 +0000 Received: from localhost (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.34; Tue, 23 May 2023 02:57:00 -0500 From: Michal Simek To: , , , CC: Conor Dooley , Krishna Potthuri , Krzysztof Kozlowski , Linus Walleij , Michael Turquette , "Rob Herring" , Stephen Boyd , , , , Subject: [PATCH] dt-bindings: xilinx: Remove Rajan, Jolly and Manish Date: Tue, 23 May 2023 09:56:57 +0200 Message-ID: <9b252dd71c82593fa6b137eca2174d9ab6e57f7a.1684828606.git.michal.simek@amd.com> X-Mailer: git-send-email 2.36.1 MIME-Version: 1.0 X-Developer-Signature: v=1; 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Signed-off-by: Michal Simek Acked-by: Conor Dooley --- Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml | 2 -- .../bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml | 1 - .../bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml | 1 - .../devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml | 1 - 4 files changed, 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml index 93ae349cf9e9..5cbb34d0b61b 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,versal-clk.yaml @@ -8,8 +8,6 @@ title: Xilinx Versal clock controller maintainers: - Michal Simek - - Jolly Shah - - Rajan Vaja description: | The clock controller is a hardware block of Xilinx versal clock tree. It diff --git a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml index 6b62d5d83476..87ff9ee098f5 100644 --- a/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/snps,dw-umctl2-ddrc.yaml @@ -8,7 +8,6 @@ title: Synopsys DesignWare Universal Multi-Protocol Memory Controller maintainers: - Krzysztof Kozlowski - - Manish Narani - Michal Simek description: | diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml index 7864a1c994eb..75143db51411 100644 --- a/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,zynq-ddrc-a05.yaml @@ -8,7 +8,6 @@ title: Zynq A05 DDR Memory Controller maintainers: - Krzysztof Kozlowski - - Manish Narani - Michal Simek description: diff --git a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml index cdebfa991e06..24ad0614e61b 100644 --- a/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/xlnx,zynqmp-pinctrl.yaml @@ -8,7 +8,6 @@ title: Xilinx ZynqMP Pinctrl maintainers: - Sai Krishna Potthuri - - Rajan Vaja description: | Please refer to pinctrl-bindings.txt in this directory for details of the