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[176.184.48.94]) by smtp.gmail.com with ESMTPSA id n1-20020a05600c294100b003ee74c25f12sm13828813wmd.35.2023.05.22.23.44.15 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 22 May 2023 23:44:16 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , qemu-ppc@nongnu.org, Titus Rwantare , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Peter Maydell Subject: [PATCH 1/3] hw/mips/jazz: Fix modifying QOM class internal state from instance Date: Tue, 23 May 2023 08:44:06 +0200 Message-Id: <20230523064408.57941-2-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230523064408.57941-1-philmd@linaro.org> References: <20230523064408.57941-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org QOM object instance should not modify its class state (because all other objects instanciated from this class get affected). Instead of modifying the MIPSCPUClass 'no_data_aborts' field in the instance machine_init() handler, set it in the machine class_init handler. Since 2 machines require this, share the common code in a new machine_class_ignore_data_abort() helper. Inspired-by: Bernhard Beschow Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/mips/jazz.c | 41 +++++++++++++++++++++++------------------ 1 file changed, 23 insertions(+), 18 deletions(-) diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index ca4426a92c..de2e827bf8 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -128,7 +128,6 @@ static void mips_jazz_init(MachineState *machine, int bios_size, n, big_endian; Clock *cpuclk; MIPSCPU *cpu; - MIPSCPUClass *mcc; CPUMIPSState *env; qemu_irq *i8259; rc4030_dma *dmas; @@ -177,23 +176,6 @@ static void mips_jazz_init(MachineState *machine, env = &cpu->env; qemu_register_reset(main_cpu_reset, cpu); - /* - * Chipset returns 0 in invalid reads and do not raise data exceptions. - * However, we can't simply add a global memory region to catch - * everything, as this would make all accesses including instruction - * accesses be ignored and not raise exceptions. - * - * NOTE: this behaviour of raising exceptions for bad instruction - * fetches but not bad data accesses was added in commit 54e755588cf1e9 - * to restore behaviour broken by c658b94f6e8c206, but it is not clear - * whether the real hardware behaves this way. It is possible that - * real hardware ignores bad instruction fetches as well -- if so then - * we could replace this hijacking of CPU methods with a simple global - * memory region that catches all memory accesses, as we do on Malta. - */ - mcc = MIPS_CPU_GET_CLASS(cpu); - mcc->no_data_aborts = true; - /* allocate RAM */ memory_region_add_subregion(address_space, 0, machine->ram); @@ -414,6 +396,27 @@ void mips_pica61_init(MachineState *machine) mips_jazz_init(machine, JAZZ_PICA61); } +static void machine_class_ignore_data_abort(MachineClass *mc) +{ + MIPSCPUClass *mcc = MIPS_CPU_CLASS(mc); + + /* + * Chipset returns 0 in invalid reads and do not raise data exceptions. + * However, we can't simply add a global memory region to catch + * everything, as this would make all accesses including instruction + * accesses be ignored and not raise exceptions. + * + * NOTE: this behaviour of raising exceptions for bad instruction + * fetches but not bad data accesses was added in commit 54e755588cf1e9 + * to restore behaviour broken by c658b94f6e8c206, but it is not clear + * whether the real hardware behaves this way. It is possible that + * real hardware ignores bad instruction fetches as well -- if so then + * we could replace this hijacking of CPU methods with a simple global + * memory region that catches all memory accesses, as we do on Malta. + */ + mcc->no_data_aborts = true; +} + static void mips_magnum_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -423,6 +426,7 @@ static void mips_magnum_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_SCSI; mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); mc->default_ram_id = "mips_jazz.ram"; + machine_class_ignore_data_abort(mc); } static const TypeInfo mips_magnum_type = { @@ -440,6 +444,7 @@ static void mips_pica61_class_init(ObjectClass *oc, void *data) mc->block_default_type = IF_SCSI; mc->default_cpu_type = MIPS_CPU_TYPE_NAME("R4000"); mc->default_ram_id = "mips_jazz.ram"; + machine_class_ignore_data_abort(mc); } static const TypeInfo mips_pica61_type = { From patchwork Tue May 23 06:44:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 684891 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1557654wrt; Mon, 22 May 2023 23:45:39 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4wMvB4kwU298k9TlfPNknixLL1DwYXYcFvGltLG758kmLCvJvx14eZmarnXaH5bofqFpaL X-Received: by 2002:a05:622a:1a90:b0:3f6:82e8:a09f with SMTP id s16-20020a05622a1a9000b003f682e8a09fmr24422817qtc.50.1684824339727; Mon, 22 May 2023 23:45:39 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684824339; cv=none; d=google.com; s=arc-20160816; b=Yh9F6P7Iz3AcPF2GJLemR2W9cYnfIT1KWXRfbKFdqE1E2s9YjHJlgIPuG56VBEo4xO 4dxzt6E7Ev530bq0k2Qadl9mcO31GFE7Enr7ONXqyWYthWO0LGIcjAopj4aHZ10JeBLu UEmAXDf1NKF/epusVzJ5x6/1adHwOOzjit/ornQxSohAqTXpUZP5x1l+VJbnx0zAZ37r XP3xm86APtKzMXUKY3/Iqkqq2gpmTHVrCuJj0BhoIrTpH9OMHJrFrImqyMVUhvwnstYk /DLXdsvRfYb7JzeReR7oqqQUIV3+rqrtAT02JzKIWpBZ3zCrRvkauRlqPUumepRjjuPu 8Mlw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=gPBH60YOMI3nzrM9MwhgMu04H1kPb+OX0SImhK5mfvI=; b=P8xUvnZP+s7OZ4+sWdBfqUMElG/7SDc6PJgVU/7cazHXT+jil9tZl32aoTNg/IVMWe cTmH5XoYRIeKUaxrz23bDYay2PN5PGxq15XNVbFdSqznKYXCH5nA73tPz8DgD6h3Lf60 2rruobHZ7HVbxxHXvmVXLNvcPrNAHtZB/dYYC6cZsBLLIQPmav6JUpOIjC0dpdLqoMzh U0y/Q/YnNfgwRo66rlMRryOxWo7XsXmeBERMOKnSGNVB9/F0OEgBbasXtzeO84WXWRQT F6JXZHOjsc8U+/7YC37tgIk8t/fVn/taaU+3a+78gWnnuwMhElmI4MuWqZOTQY2EzZAH zNTg== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=RcOJBU55; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.48.94]) by smtp.gmail.com with ESMTPSA id f4-20020a1c6a04000000b003f1978bbcd6sm1421092wmc.3.2023.05.22.23.44.21 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 22 May 2023 23:44:22 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , qemu-ppc@nongnu.org, Titus Rwantare , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Stuart Yoder , Alexander Graf Subject: [PATCH 2/3] hw/ppc/e500plat: Fix modifying QOM class internal state from instance Date: Tue, 23 May 2023 08:44:07 +0200 Message-Id: <20230523064408.57941-3-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230523064408.57941-1-philmd@linaro.org> References: <20230523064408.57941-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org QOM object instance should not modify its class state (because all other objects instanciated from this class get affected). Instead of modifying the PPCE500MachineClass 'mpic_version' field in the instance machine_init() handler, set it in the machine class init handler (e500plat_machine_class_init). Inspired-by: Bernhard Beschow Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/ppc/e500plat.c | 25 +++++++++++-------------- 1 file changed, 11 insertions(+), 14 deletions(-) diff --git a/hw/ppc/e500plat.c b/hw/ppc/e500plat.c index 3032bd3f6d..c3b0ed01cf 100644 --- a/hw/ppc/e500plat.c +++ b/hw/ppc/e500plat.c @@ -30,18 +30,6 @@ static void e500plat_fixup_devtree(void *fdt) sizeof(compatible)); } -static void e500plat_init(MachineState *machine) -{ - PPCE500MachineClass *pmc = PPCE500_MACHINE_GET_CLASS(machine); - /* Older KVM versions don't support EPR which breaks guests when we announce - MPIC variants that support EPR. Revert to an older one for those */ - if (kvm_enabled() && !kvmppc_has_cap_epr()) { - pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20; - } - - ppce500_init(machine); -} - static void e500plat_machine_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, Error **errp) { @@ -81,7 +69,6 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data) pmc->pci_first_slot = 0x1; pmc->pci_nr_slots = PCI_SLOT_MAX - 1; pmc->fixup_devtree = e500plat_fixup_devtree; - pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_42; pmc->has_mpc8xxx_gpio = true; pmc->has_esdhc = true; pmc->platform_bus_base = 0xf00000000ULL; @@ -94,8 +81,18 @@ static void e500plat_machine_class_init(ObjectClass *oc, void *data) pmc->pci_mmio_bus_base = 0xE0000000ULL; pmc->spin_base = 0xFEF000000ULL; + if (kvm_enabled() && !kvmppc_has_cap_epr()) { + /* + * Older KVM versions don't support EPR which breaks guests when + * we announce MPIC variants that support EPR. Revert to an older + * one for those. + */ + pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_20; + } else { + pmc->mpic_version = OPENPIC_MODEL_FSL_MPIC_42; + } + mc->desc = "generic paravirt e500 platform"; - mc->init = e500plat_init; mc->max_cpus = 32; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("e500v2_v30"); mc->default_ram_id = "mpc8544ds.ram"; From patchwork Tue May 23 06:44:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 684888 Delivered-To: patch@linaro.org Received: by 2002:a5d:4e01:0:0:0:0:0 with SMTP id p1csp1557584wrt; Mon, 22 May 2023 23:45:21 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4KPDg27EmbYHP/Usny3SDGKew7PMl030ShryJ4TuleZFduZ5lz6bcpX0bLCw5++060iw7p X-Received: by 2002:a05:622a:34a:b0:3f2:f35:8e6f with SMTP id r10-20020a05622a034a00b003f20f358e6fmr21300239qtw.25.1684824321433; Mon, 22 May 2023 23:45:21 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684824321; cv=none; d=google.com; s=arc-20160816; b=yno8vR/Bm7mzdeTRfRx3YJnWSR8Um+NuOpfQEwpmvWCcWROP/63S0mjqqo5DIabZto sMlAZMYp4eP1hxY/wdt6A/snS0689s11oVmckpyF8/uPTkrjHG2lhB3buK9kTvtQ703K bpqnfKZ6efMYMrfehv4QDFr4gquPFwQJmFgkMd4lW/jRYOO1xqbswhf7qog/w5R+i2cG v+9RiD8O3CXY3H3DgdulKvcHSNfEu1dWyiJL91rATP3lZlYR60hDv3D4+LBC6A3nrsbo VkU5XDFAo3Z/STMo7qfwTKHRIUpGXqwi1V4jUiTI7rDwknz6R6mWBf97SO8rDY7SBFDH 814Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Y7vD03cErjYangTizc1GQ3mHeqbcUTk0o4KZmb+NjF8=; b=EWy/sEFAYcEcwWYuCn7b0rTBnp2FvKFSGLHGoJMIdxWuqCK8Z9Ftw+CFhkvqsbRmZQ 8zjEmlOT48jzFXxjIeVz5D1rwYoWGxbuH+u8jf8XCYkcYy1ceJ7CCyhlWxPlcmLS1yss vYknu5bXpkd0zwsKyF+ZFacc9BioLR0DymCcUVBSKJcCd02YIE3lQ/2//f/8RI097bge oap3ovSjP+d28y3mt7ujKxdt6sXMcq2QiDqtJCCHv07+a8I9OqR/YRbfABJADIWHeQik 2hf/KmZtKMM+RXMmRPHcJ4IvNsBE7SeNAI2ZCrg6ptGbQGJaxZPIroiv9SXNZYENyAyd cYNA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=SuYjnIFn; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[176.184.48.94]) by smtp.gmail.com with ESMTPSA id s9-20020a7bc389000000b003f60514bdd7sm4915475wmj.4.2023.05.22.23.44.27 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Mon, 22 May 2023 23:44:28 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Bernhard Beschow , =?utf-8?q?Herv=C3=A9_Poussineau?= , Aleksandar Rikalo , Jiaxun Yang , qemu-ppc@nongnu.org, Titus Rwantare , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Joel Stanley , Hao Wu , Corey Minyard Subject: [PATCH 3/3] hw/i2c/pmbus_device: Fix modifying QOM class internals from instance Date: Tue, 23 May 2023 08:44:08 +0200 Message-Id: <20230523064408.57941-4-philmd@linaro.org> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20230523064408.57941-1-philmd@linaro.org> References: <20230523064408.57941-1-philmd@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=philmd@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org QOM object instance should not modify its class state (because all other objects instanciated from this class get affected). Instead of modifying the PMBusDeviceClass 'device_num_pages' field the first time a instance is initialized (in pmbus_pages_alloc), introduce a new pmbus_pages_num() helper which returns the page number from the class without modifying the class state. The code logic become slighly simplified. Inspired-by: Bernhard Beschow Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson --- hw/i2c/pmbus_device.c | 17 ++++++++++------- 1 file changed, 10 insertions(+), 7 deletions(-) diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index 44fe4eddbb..8bc9d5108a 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -190,15 +190,18 @@ static void pmbus_quick_cmd(SMBusDevice *smd, uint8_t read) } } +static uint8_t pmbus_pages_num(PMBusDevice *pmdev) +{ + const PMBusDeviceClass *k = PMBUS_DEVICE_GET_CLASS(pmdev); + + /* some PMBus devices don't use the PAGE command, so they get 1 page */ + return k->device_num_pages ? : 1; +} + static void pmbus_pages_alloc(PMBusDevice *pmdev) { - /* some PMBus devices don't use the PAGE command, so they get 1 page */ - PMBusDeviceClass *k = PMBUS_DEVICE_GET_CLASS(pmdev); - if (k->device_num_pages == 0) { - k->device_num_pages = 1; - } - pmdev->num_pages = k->device_num_pages; - pmdev->pages = g_new0(PMBusPage, k->device_num_pages); + pmdev->num_pages = pmbus_pages_num(pmdev); + pmdev->pages = g_new0(PMBusPage, pmdev->num_pages); } void pmbus_check_limits(PMBusDevice *pmdev)