From patchwork Tue Jun 11 14:12:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 166458 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp2420351ilk; Tue, 11 Jun 2019 07:14:17 -0700 (PDT) X-Google-Smtp-Source: APXvYqysjz9NY1TjR6FDzpQ01V/JN9CjCWG1/J5YKhZgrg9cOV9uHwpHWn28Ah5xG11HouMDyW7h X-Received: by 2002:a17:902:7883:: with SMTP id q3mr75271232pll.89.1560262456955; Tue, 11 Jun 2019 07:14:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560262456; cv=none; d=google.com; s=arc-20160816; b=gIqwnu/AUk/THgIaTI5FqUYdpa0VlzGl798v2UnZTUq4I1NcKGff34XIo+kBfsAc7a y1OLsygM11dku3UTcW6tj3TDqk59f1C/iSq2ghjw+Ac5l+wA+PfUdsQWLqr/cfbMbwWS aPdop+4uR+kaCDNwaRM62MqL7jk1GItGrc+MRxfhlLqeawbfMmU9V2CnmXY9L0FSF5im 5G6JnIVb+wb/rqYeUnRy/ItRYeSEoF12Vr0+IATtbBHal/rfZNhB6/vJGcVhLF/BRziN IxnhOTPL1GUH6eYwqqwem1hmlGl4fbSTkx1GeJ9emkvTTA06X9VEWIc8Zdfga7RkdZjw E1Pg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from; bh=/xGCIta+xCkkImYqpEvDqQRggQ1mFba8O+TkGdyVlZw=; b=Nb4MyVG3L6uRAHZjzARNf2kk13u2gcLByH0UHj+2BJAkUVFJoviXZQ3v44nTMe2GCz 3pCQgmk52YNDQUBNdl/PQqZOLtkVrj8ZieOh8WApGQSWn0/HHg+PgPGG6jEeEngmMKxk yY6jYfBpcPGZqkPKIQrJIXEwLuCEoQG7HC2l/WZQwKX/vfYSZ2dsB2QW3v3i87xOjwSs XPmr/eubieC+6GB9RuygQOZYA4yI4ROg87IlcmlpvGov+HIhlM62Af/2qBPQLp2wEm28 rhVG6HR96BnJvPv8Exkik1pB4fkA3LffStLtDLzNc3F0x+KODxjKaTKIGCK3ZA1U8Nrk Q9QA== ARC-Authentication-Results: i=1; mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id g35si2515806pje.73.2019.06.11.07.14.16; Tue, 11 Jun 2019 07:14:16 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2389484AbfFKOOP (ORCPT + 30 others); Tue, 11 Jun 2019 10:14:15 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:18552 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1725811AbfFKOOP (ORCPT ); Tue, 11 Jun 2019 10:14:15 -0400 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 5BA30558FDF9C701A7F5; Tue, 11 Jun 2019 22:14:12 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.439.0; Tue, 11 Jun 2019 22:14:06 +0800 From: John Garry To: , , CC: , , , , , , , , , John Garry Subject: [PATCH v4 1/3] lib: logic_pio: Use logical PIO low-level accessors for !CONFIG_INDIRECT_PIO Date: Tue, 11 Jun 2019 22:12:52 +0800 Message-ID: <1560262374-67875-2-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1560262374-67875-1-git-send-email-john.garry@huawei.com> References: <1560262374-67875-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently we only use logical PIO low-level accessors for when CONFIG_INDIRECT_PIO is enabled. Otherwise we just use inb/out et all directly. It is useful to now use logical PIO accessors for all cases, so we can add legality checks to accesses. Such a check would be for ensuring that the PCI IO port has been IO remapped prior to the access. Using the logical PIO accesses will add a little processing overhead, but that's ok as IO port accesses are relatively slow anyway. Some changes are also made to stop spilling so many lines under CONFIG_INDIRECT_PIO. Signed-off-by: John Garry --- include/linux/logic_pio.h | 7 ++-- lib/logic_pio.c | 83 ++++++++++++++++++++++++++++----------- 2 files changed, 63 insertions(+), 27 deletions(-) -- 2.17.1 diff --git a/include/linux/logic_pio.h b/include/linux/logic_pio.h index cbd9d8495690..06d22b2ec99f 100644 --- a/include/linux/logic_pio.h +++ b/include/linux/logic_pio.h @@ -37,7 +37,7 @@ struct logic_pio_host_ops { size_t dwidth, unsigned int count); }; -#ifdef CONFIG_INDIRECT_PIO +#if defined(PCI_IOBASE) u8 logic_inb(unsigned long addr); void logic_outb(u8 value, unsigned long addr); void logic_outw(u16 value, unsigned long addr); @@ -102,6 +102,7 @@ void logic_outsl(unsigned long addr, const void *buffer, unsigned int count); #define outsl logic_outsl #endif +#if defined(CONFIG_INDIRECT_PIO) /* * We reserve 0x4000 bytes for Indirect IO as so far this library is only * used by the HiSilicon LPC Host. If needed, we can reserve a wider IO @@ -109,10 +110,10 @@ void logic_outsl(unsigned long addr, const void *buffer, unsigned int count); */ #define PIO_INDIRECT_SIZE 0x4000 #define MMIO_UPPER_LIMIT (IO_SPACE_LIMIT - PIO_INDIRECT_SIZE) -#else +#else /* CONFIG_INDIRECT_PIO */ #define MMIO_UPPER_LIMIT IO_SPACE_LIMIT #endif /* CONFIG_INDIRECT_PIO */ - +#endif /* PCI_IOBASE */ struct logic_pio_hwaddr *find_io_range_by_fwnode(struct fwnode_handle *fwnode); unsigned long logic_pio_trans_hwaddr(struct fwnode_handle *fwnode, resource_size_t hw_addr, resource_size_t size); diff --git a/lib/logic_pio.c b/lib/logic_pio.c index feea48fd1a0d..40d9428010e1 100644 --- a/lib/logic_pio.c +++ b/lib/logic_pio.c @@ -191,7 +191,8 @@ unsigned long logic_pio_trans_cpuaddr(resource_size_t addr) return ~0UL; } -#if defined(CONFIG_INDIRECT_PIO) && defined(PCI_IOBASE) +#if defined(PCI_IOBASE) +#if defined(CONFIG_INDIRECT_PIO) #define BUILD_LOGIC_IO(bw, type) \ type logic_in##bw(unsigned long addr) \ { \ @@ -200,11 +201,11 @@ type logic_in##bw(unsigned long addr) \ if (addr < MMIO_UPPER_LIMIT) { \ ret = read##bw(PCI_IOBASE + addr); \ } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ - struct logic_pio_hwaddr *entry = find_io_range(addr); \ + struct logic_pio_hwaddr *range = find_io_range(addr); \ + size_t sz = sizeof(type); \ \ - if (entry && entry->ops) \ - ret = entry->ops->in(entry->hostdata, \ - addr, sizeof(type)); \ + if (range && range->ops) \ + ret = range->ops->in(range->hostdata, addr, sz);\ else \ WARN_ON_ONCE(1); \ } \ @@ -216,49 +217,83 @@ void logic_out##bw(type value, unsigned long addr) \ if (addr < MMIO_UPPER_LIMIT) { \ write##bw(value, PCI_IOBASE + addr); \ } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ - struct logic_pio_hwaddr *entry = find_io_range(addr); \ + struct logic_pio_hwaddr *range = find_io_range(addr); \ + size_t sz = sizeof(type); \ \ - if (entry && entry->ops) \ - entry->ops->out(entry->hostdata, \ - addr, value, sizeof(type)); \ + if (range && range->ops) \ + range->ops->out(range->hostdata, \ + addr, value, sz); \ else \ WARN_ON_ONCE(1); \ } \ } \ \ -void logic_ins##bw(unsigned long addr, void *buffer, \ - unsigned int count) \ +void logic_ins##bw(unsigned long addr, void *buf, unsigned int cnt) \ { \ if (addr < MMIO_UPPER_LIMIT) { \ - reads##bw(PCI_IOBASE + addr, buffer, count); \ + reads##bw(PCI_IOBASE + addr, buf, cnt); \ } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ - struct logic_pio_hwaddr *entry = find_io_range(addr); \ + struct logic_pio_hwaddr *range = find_io_range(addr); \ + size_t sz = sizeof(type); \ \ - if (entry && entry->ops) \ - entry->ops->ins(entry->hostdata, \ - addr, buffer, sizeof(type), count); \ + if (range && range->ops) \ + range->ops->ins(range->hostdata, \ + addr, buf, sz, cnt); \ else \ WARN_ON_ONCE(1); \ } \ \ } \ \ -void logic_outs##bw(unsigned long addr, const void *buffer, \ - unsigned int count) \ +void logic_outs##bw(unsigned long addr, const void *buf, \ + unsigned int cnt) \ { \ if (addr < MMIO_UPPER_LIMIT) { \ - writes##bw(PCI_IOBASE + addr, buffer, count); \ + writes##bw(PCI_IOBASE + addr, buf, cnt); \ } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ - struct logic_pio_hwaddr *entry = find_io_range(addr); \ + struct logic_pio_hwaddr *range = find_io_range(addr); \ + size_t sz = sizeof(type); \ \ - if (entry && entry->ops) \ - entry->ops->outs(entry->hostdata, \ - addr, buffer, sizeof(type), count); \ + if (range && range->ops) \ + range->ops->outs(range->hostdata, \ + addr, buf, sz, cnt); \ else \ WARN_ON_ONCE(1); \ } \ } +#else /* CONFIG_INDIRECT_PIO */ + +#define BUILD_LOGIC_IO(bw, type) \ +type logic_in##bw(unsigned long addr) \ +{ \ + type ret = (type)~0; \ + \ + if (addr < MMIO_UPPER_LIMIT) \ + ret = read##bw(PCI_IOBASE + addr); \ + return ret; \ +} \ + \ +void logic_out##bw(type value, unsigned long addr) \ +{ \ + if (addr < MMIO_UPPER_LIMIT) \ + write##bw(value, PCI_IOBASE + addr); \ +} \ + \ +void logic_ins##bw(unsigned long addr, void *buf, unsigned int cnt) \ +{ \ + if (addr < MMIO_UPPER_LIMIT) \ + reads##bw(PCI_IOBASE + addr, buf, cnt); \ +} \ + \ +void logic_outs##bw(unsigned long addr, const void *buf, \ + unsigned int cnt) \ +{ \ + if (addr < MMIO_UPPER_LIMIT) \ + writes##bw(PCI_IOBASE + addr, buf, cnt); \ +} +#endif /* CONFIG_INDIRECT_PIO */ + BUILD_LOGIC_IO(b, u8) EXPORT_SYMBOL(logic_inb); EXPORT_SYMBOL(logic_insb); @@ -277,4 +312,4 @@ EXPORT_SYMBOL(logic_insl); EXPORT_SYMBOL(logic_outl); EXPORT_SYMBOL(logic_outsl); -#endif /* CONFIG_INDIRECT_PIO && PCI_IOBASE */ +#endif /* PCI_IOBASE */ From patchwork Tue Jun 11 14:12:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 166460 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp2420504ilk; Tue, 11 Jun 2019 07:14:24 -0700 (PDT) X-Google-Smtp-Source: APXvYqzv81LhYP7l485W3iaMAV/H8kPYWfngOItSXawuTRHxR5WwBOnkIQ5jcIA3AlZS6h8x8sO0 X-Received: by 2002:aa7:8292:: with SMTP id s18mr50810848pfm.111.1560262464338; Tue, 11 Jun 2019 07:14:24 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560262464; cv=none; d=google.com; s=arc-20160816; b=tJ8RjNGpFPdhl2H1ANwY+nRM2EImt1eEJ6HM14+XgBwpByUcYl+gWlwIQfyH0beLdF O8mxqBwtzR4zyexooJMM67hnoXVnDQvtXjPxnt31DavPvixawV0eN8IuOHq9bNJzgZiF FfXC74pffbm1eKJOPXL53e6A714ti7WaZzMfTfeesT1dg1gFqXVVrXgSyh9seszvw74a FDNFLi3mpYDEDsiLkpO/8j6jTQkjR5niLds8C1dyTfLGABGFKjlwuOF+bNvpLxnCs37L 6U4B2cE+FHMz0JlnqM2RYr2uyzvgbyWiV+1DFbR6QYzO+x1aBDLlvl2WJTntSiPN182O 2KnQ== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id g35si2515806pje.73.2019.06.11.07.14.24; Tue, 11 Jun 2019 07:14:24 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403829AbfFKOOX (ORCPT + 30 others); Tue, 11 Jun 2019 10:14:23 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:48818 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2388411AbfFKOOV (ORCPT ); Tue, 11 Jun 2019 10:14:21 -0400 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 6A777234335F00B61410; Tue, 11 Jun 2019 22:14:17 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.439.0; Tue, 11 Jun 2019 22:14:06 +0800 From: John Garry To: , , CC: , , , , , , , , , John Garry Subject: [PATCH v4 2/3] lib: logic_pio: Reject accesses to unregistered CPU MMIO regions Date: Tue, 11 Jun 2019 22:12:53 +0800 Message-ID: <1560262374-67875-3-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1560262374-67875-1-git-send-email-john.garry@huawei.com> References: <1560262374-67875-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Currently when accessing logical indirect PIO addresses in logic_{in, out}{,s}, we first ensure that the region is registered. However, no such check exists for CPU MMIO regions. The CPU MMIO regions would be registered by the PCI host (when PCI_IOBASE is defined) in pci_register_io_range(). We have seen scenarios when systems which don't have a PCI host, or they do but the PCI host probe fails, certain drivers attempts to still attempt to access PCI IO ports; examples are in [1] and [2]. Such is a case on an ARM64 system without a PCI host: root@(none)$ insmod hwmon/f71805f.ko Unable to handle kernel paging request at virtual address ffff7dfffee0002e Mem abort info: ESR = 0x96000046 Exception class = DABT (current EL), IL = 32 bits SET = 0, FnV = 0 EA = 0, S1PTW = 0 Data abort info: ISV = 0, ISS = 0x00000046 CM = 0, WnR = 1 swapper pgtable: 4k pages, 48-bit VAs, pgdp = (____ptrval____) [ffff7dfffee0002e] pgd=000000000141c003, pud=000000000141d003, pmd=0000000000000000 Internal error: Oops: 96000046 [#1] PREEMPT SMP Modules linked in: f71805f(+) CPU: 20 PID: 2736 Comm: insmod Not tainted 5.1.0-rc1-00003-g6f1bfec2a620-dirty #99 Hardware name: Huawei Taishan 2280 /D05, BIOS Hisilicon D05 IT21 Nemo 2.0 RC0 04/18/2018 pstate: 80000005 (Nzcv daif -PAN -UAO) pc : logic_outb+0x54/0xb8 lr : f71805f_find+0x2c/0x1b8 [f71805f] sp : ffff000025fbba90 x29: ffff000025fbba90 x28: ffff000008b944d0 x27: ffff000025fbbdf0 x26: 0000000000000100 x25: ffff801f8c270580 x24: ffff000011420000 x23: ffff000025fbbb3e x22: ffff000025fbbb40 x21: ffff000008b991b8 x20: 0000000000000087 x19: 000000000000002e x18: ffffffffffffffff x17: 0000000000000000 x16: 0000000000000000 x15: ffff00001127d6c8 x14: 0000000000000000 x13: 0000000000000000 x12: 0000000000000000 x11: 0000000000010820 x10: 0000841fdac40000 x9 : 0000000000000001 x8 : 0000000040000000 x7 : 0000000000210d00 x6 : 0000000000000000 x5 : ffff801fb6a46040 x4 : ffff841febeaeda0 x3 : 0000000000ffbffe x2 : ffff000025fbbb40 x1 : ffff7dfffee0002e x0 : ffff7dfffee00000 Process insmod (pid: 2736, stack limit = 0x(____ptrval____)) Call trace: logic_outb+0x54/0xb8 f71805f_find+0x2c/0x1b8 [f71805f] f71805f_init+0x38/0xe48 [f71805f] do_one_initcall+0x5c/0x198 do_init_module+0x54/0x1b0 load_module+0x1dc4/0x2158 __se_sys_init_module+0x14c/0x1e8 __arm64_sys_init_module+0x18/0x20 el0_svc_common+0x5c/0x100 el0_svc_handler+0x2c/0x80 el0_svc+0x8/0xc Code: d2bfdc00 f2cfbfe0 f2ffffe0 8b000021 (39000034) ---[ end trace 10ea80bde051bbfc ]--- root@(none)$ Well-behaved drivers call request_{muxed_}region() to grab the IO port region, but success here still doesn't actually mean that there is some IO port mapped in this region. This patch adds a check to ensure that the CPU MMIO region is registered prior to accessing the PCI IO ports. Any failed checks silently return. [1] https://lore.kernel.org/linux-pci/56F209A9.4040304@huawei.com [2] https://lore.kernel.org/linux-arm-kernel/e6995b4a-184a-d8d4-f4d4-9ce75d8f47c0@huawei.com/ Signed-off-by: John Garry --- lib/logic_pio.c | 60 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 19 deletions(-) -- 2.17.1 diff --git a/lib/logic_pio.c b/lib/logic_pio.c index 40d9428010e1..47d24f428908 100644 --- a/lib/logic_pio.c +++ b/lib/logic_pio.c @@ -126,7 +126,7 @@ static struct logic_pio_hwaddr *find_io_range(unsigned long pio) if (in_range(pio, range->io_start, range->size)) return range; } - pr_err("PIO entry token %lx invalid\n", pio); + return NULL; } @@ -197,11 +197,12 @@ unsigned long logic_pio_trans_cpuaddr(resource_size_t addr) type logic_in##bw(unsigned long addr) \ { \ type ret = (type)~0; \ + struct logic_pio_hwaddr *range = find_io_range(addr); \ \ if (addr < MMIO_UPPER_LIMIT) { \ - ret = read##bw(PCI_IOBASE + addr); \ + if (range) \ + ret = read##bw(PCI_IOBASE + addr); \ } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ - struct logic_pio_hwaddr *range = find_io_range(addr); \ size_t sz = sizeof(type); \ \ if (range && range->ops) \ @@ -214,10 +215,12 @@ type logic_in##bw(unsigned long addr) \ \ void logic_out##bw(type value, unsigned long addr) \ { \ + struct logic_pio_hwaddr *range = find_io_range(addr); \ + \ if (addr < MMIO_UPPER_LIMIT) { \ - write##bw(value, PCI_IOBASE + addr); \ + if (range) \ + write##bw(value, PCI_IOBASE + addr); \ } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ - struct logic_pio_hwaddr *range = find_io_range(addr); \ size_t sz = sizeof(type); \ \ if (range && range->ops) \ @@ -230,10 +233,12 @@ void logic_out##bw(type value, unsigned long addr) \ \ void logic_ins##bw(unsigned long addr, void *buf, unsigned int cnt) \ { \ + struct logic_pio_hwaddr *range = find_io_range(addr); \ + \ if (addr < MMIO_UPPER_LIMIT) { \ - reads##bw(PCI_IOBASE + addr, buf, cnt); \ + if (range) \ + reads##bw(PCI_IOBASE + addr, buf, cnt); \ } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ - struct logic_pio_hwaddr *range = find_io_range(addr); \ size_t sz = sizeof(type); \ \ if (range && range->ops) \ @@ -242,16 +247,17 @@ void logic_ins##bw(unsigned long addr, void *buf, unsigned int cnt) \ else \ WARN_ON_ONCE(1); \ } \ - \ } \ \ void logic_outs##bw(unsigned long addr, const void *buf, \ unsigned int cnt) \ { \ + struct logic_pio_hwaddr *range = find_io_range(addr); \ + \ if (addr < MMIO_UPPER_LIMIT) { \ - writes##bw(PCI_IOBASE + addr, buf, cnt); \ + if (range) \ + writes##bw(PCI_IOBASE + addr, buf, cnt); \ } else if (addr >= MMIO_UPPER_LIMIT && addr < IO_SPACE_LIMIT) { \ - struct logic_pio_hwaddr *range = find_io_range(addr); \ size_t sz = sizeof(type); \ \ if (range && range->ops) \ @@ -269,28 +275,44 @@ type logic_in##bw(unsigned long addr) \ { \ type ret = (type)~0; \ \ - if (addr < MMIO_UPPER_LIMIT) \ - ret = read##bw(PCI_IOBASE + addr); \ + if (addr < MMIO_UPPER_LIMIT) { \ + struct logic_pio_hwaddr *range = find_io_range(addr); \ + \ + if (range) \ + ret = read##bw(PCI_IOBASE + addr); \ + } \ return ret; \ } \ \ -void logic_out##bw(type value, unsigned long addr) \ +void logic_out##bw(type val, unsigned long addr) \ { \ - if (addr < MMIO_UPPER_LIMIT) \ - write##bw(value, PCI_IOBASE + addr); \ + if (addr < MMIO_UPPER_LIMIT) { \ + struct logic_pio_hwaddr *range = find_io_range(addr); \ + \ + if (range) \ + write##bw(val, PCI_IOBASE + addr); \ + } \ } \ \ void logic_ins##bw(unsigned long addr, void *buf, unsigned int cnt) \ { \ - if (addr < MMIO_UPPER_LIMIT) \ - reads##bw(PCI_IOBASE + addr, buf, cnt); \ + if (addr < MMIO_UPPER_LIMIT) { \ + struct logic_pio_hwaddr *range = find_io_range(addr); \ + \ + if (range) \ + reads##bw(PCI_IOBASE + addr, buf, cnt); \ + } \ } \ \ void logic_outs##bw(unsigned long addr, const void *buf, \ unsigned int cnt) \ { \ - if (addr < MMIO_UPPER_LIMIT) \ - writes##bw(PCI_IOBASE + addr, buf, cnt); \ + if (addr < MMIO_UPPER_LIMIT) { \ + struct logic_pio_hwaddr *range = find_io_range(addr); \ + \ + if (range) \ + writes##bw(PCI_IOBASE + addr, buf, cnt); \ + } \ } #endif /* CONFIG_INDIRECT_PIO */ From patchwork Tue Jun 11 14:12:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: John Garry X-Patchwork-Id: 166461 Delivered-To: patch@linaro.org Received: by 2002:a92:4782:0:0:0:0:0 with SMTP id e2csp2420556ilk; Tue, 11 Jun 2019 07:14:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqz27VWFJxJonRqcJqJ9axG41Npw/LMC5Z7mgJaJ+0kh1Zb1NnQlYI18IGhWYbHo5rB852/O X-Received: by 2002:a65:5688:: with SMTP id v8mr20713496pgs.138.1560262467076; Tue, 11 Jun 2019 07:14:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1560262467; cv=none; d=google.com; s=arc-20160816; b=yRWI3Y9WcIC8eaWTJN229C4HMs2ckqPuHTrpFDzr6OZ3T60F0PBi3A80pf03v8qGU3 CKmWMjuEl8Jx6eBobcPSsd0Q/k18owxuDHOGKo7Eu59xWjqES1H2pUO+V0O7cHfnOL9e QuLVSmwNn6gfo6lJJEqYiIA/KNNrWNxk5SeGzUhDthqd8Id7AWhnDZ7uF90Kan07f1R4 DBkhVY8ccX6btUmkRXFccD9/tNCqgn95MJuw8I7TU025hc716YUJ48UWt0Qbp9MObXCB 4PXHAz7+4BDPx7IOgp6sGCPzWfOQ4rAoCbA5Uf9PFb3YJ4mo1kHOUiGrb3cLKacpdCtW 8nEg== ARC-Message-Signature: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id f32si2572436pje.70.2019.06.11.07.14.26; Tue, 11 Jun 2019 07:14:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; spf=pass (google.com: best guess record for domain of linux-kernel-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2403762AbfFKOOW (ORCPT + 30 others); Tue, 11 Jun 2019 10:14:22 -0400 Received: from szxga07-in.huawei.com ([45.249.212.35]:48806 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S2390181AbfFKOOU (ORCPT ); Tue, 11 Jun 2019 10:14:20 -0400 Received: from DGGEMS401-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 648B6F9D4FA004DE7CD0; Tue, 11 Jun 2019 22:14:17 +0800 (CST) Received: from localhost.localdomain (10.67.212.75) by DGGEMS401-HUB.china.huawei.com (10.3.19.201) with Microsoft SMTP Server id 14.3.439.0; Tue, 11 Jun 2019 22:14:07 +0800 From: John Garry To: , , CC: , , , , , , , , , John Garry Subject: [PATCH v4 3/3] lib: logic_pio: Fix up a print Date: Tue, 11 Jun 2019 22:12:54 +0800 Message-ID: <1560262374-67875-4-git-send-email-john.garry@huawei.com> X-Mailer: git-send-email 2.8.1 In-Reply-To: <1560262374-67875-1-git-send-email-john.garry@huawei.com> References: <1560262374-67875-1-git-send-email-john.garry@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.67.212.75] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org For the print in logic_pio_trans_cpuaddr(), don't cast the value to unsigned long long, and just print the resource_size_t type directly. Signed-off-by: John Garry --- lib/logic_pio.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) -- 2.17.1 diff --git a/lib/logic_pio.c b/lib/logic_pio.c index 47d24f428908..030708ce7bb6 100644 --- a/lib/logic_pio.c +++ b/lib/logic_pio.c @@ -186,8 +186,7 @@ unsigned long logic_pio_trans_cpuaddr(resource_size_t addr) if (in_range(addr, range->hw_start, range->size)) return addr - range->hw_start + range->io_start; } - pr_err("addr %llx not registered in io_range_list\n", - (unsigned long long) addr); + pr_err("addr %pa not registered in io_range_list\n", &addr); return ~0UL; }