From patchwork Fri May 19 14:31:11 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 684018 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 37C48C77B7F for ; Fri, 19 May 2023 14:31:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232053AbjESObk (ORCPT ); Fri, 19 May 2023 10:31:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52108 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232065AbjESObi (ORCPT ); Fri, 19 May 2023 10:31:38 -0400 Received: from mail-pj1-x1036.google.com (mail-pj1-x1036.google.com [IPv6:2607:f8b0:4864:20::1036]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5E58613D for ; Fri, 19 May 2023 07:31:37 -0700 (PDT) Received: by mail-pj1-x1036.google.com with SMTP id 98e67ed59e1d1-25332b3915bso2672075a91.2 for ; Fri, 19 May 2023 07:31:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684506697; x=1687098697; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=5zLG4dTgi3xTplGTrfZB0o1fFz0ivS0ryK10HN6uoQ0=; b=qGdwPEmy69hz5bwluW7Fq1zj0cnJ763Juy1Q9I0nI60SqhiOMAI8IPYFfjjUoKmMh7 Z9rFHOxQmXWKEMJcqr9ebxI6WhpQLQxaMvFD6YkvQW1txWwTE+0341WLdr4r0AfmFlbp cCcsBAwjjNgAqRCKPBpIvyEMoZh666Jzw2ZPnL6epW++0h/lWQozK6G9CyBihIo6HK7s x7IM+fG1ck6w6IWX3LXHo/VTTEKXIYw7pR1AHukHHugbm5I04nkIkC9Goj/fqaS9nxuI 9eD6O0dt/eCA+q07GH2Nuaob+YogjGYjEjt0JXz90qDzXSG4dAtug95Hl/APgOpxoeFn 1pqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684506697; x=1687098697; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=5zLG4dTgi3xTplGTrfZB0o1fFz0ivS0ryK10HN6uoQ0=; b=R+0gknDiMo9G2QdwMIRneHM0Wxo/WvfUdxo+2+viMOq7keNgFBHt9NBAHGYjOg6boj sfRwbH/W/3UVDYUnJSBF4XZ7mOEdxI2cSa+EiuxqOXuqlBwNj9hlNliELJqMpNJgcNtN Rzed+44PddZoCHW1IbcaM5fAU4NLrhk3LBkixSA1nMnqcal9BWMDLo09kPgqH2O6vXxg LCxb8z1Zp+7MOrNGwE/mhvvYVHCJglewkBBVZ9nPHieksBSi6fhna7LAvTiGR8O1GNnd x54AxNisvBbBZjU/ob6Q+iDOchIo0rp37LxgVVeD+32J69SJsdLWU+y5DigW1hFjNxgX GdMA== X-Gm-Message-State: AC+VfDwHNl7qExTdDfD4Uuc7F9qER5fTteNpFrPqndIvD4fk6du5VvzM x7EwwioUyU+2QdPj57WrViKy X-Google-Smtp-Source: ACHHUZ7dxJ79BWs/7muqKSgLBnCVO7scQ7im2fPjzEq7ZYtBAxNGC3l855k3KgDIKAgSJ5QGWlmbjQ== X-Received: by 2002:a17:90b:3648:b0:253:927d:6a36 with SMTP id nh8-20020a17090b364800b00253927d6a36mr716888pjb.18.1684506696910; Fri, 19 May 2023 07:31:36 -0700 (PDT) Received: from localhost.localdomain ([117.202.184.13]) by smtp.gmail.com with ESMTPSA id 30-20020a17090a09a100b00250d908a771sm1634845pjo.50.2023.05.19.07.31.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 07:31:36 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam , Dmitry Baryshkov Subject: [PATCH v2 2/8] PCI: qcom: Disable write access to read only registers for IP v2.9.0 Date: Fri, 19 May 2023 20:01:11 +0530 Message-Id: <20230519143117.23875-3-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230519143117.23875-1-manivannan.sadhasivam@linaro.org> References: <20230519143117.23875-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org In the post init sequence of v2.9.0, write access to read only registers are not disabled after updating the registers. Fix it by disabling the access after register update. Fixes: 0cf7c2efe8ac ("PCI: qcom: Add IPQ60xx support") Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 01795ee7ce45..391a45d1e70a 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -1136,6 +1136,7 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) writel(0, pcie->parf + PARF_Q2A_FLUSH); dw_pcie_dbi_ro_wr_en(pci); + writel(PCIE_CAP_SLOT_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP); val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP); @@ -1145,6 +1146,8 @@ static int qcom_pcie_post_init_2_9_0(struct qcom_pcie *pcie) writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset + PCI_EXP_DEVCTL2); + dw_pcie_dbi_ro_wr_dis(pci); + for (i = 0; i < 256; i++) writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i)); From patchwork Fri May 19 14:31:13 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 684017 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44612C7EE26 for ; Fri, 19 May 2023 14:32:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232098AbjESOcB (ORCPT ); Fri, 19 May 2023 10:32:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52628 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231726AbjESOb6 (ORCPT ); Fri, 19 May 2023 10:31:58 -0400 Received: from mail-pg1-x529.google.com (mail-pg1-x529.google.com [IPv6:2607:f8b0:4864:20::529]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7A735E75 for ; Fri, 19 May 2023 07:31:46 -0700 (PDT) Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-517bdc9e81dso1793636a12.1 for ; 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But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's not set the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Tested-by: Sricharan Ramabadhran Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 8f448156eccc..64b6a8c6a99d 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -140,7 +140,6 @@ PCI_EXP_SLTCAP_AIP | \ PCI_EXP_SLTCAP_PIP | \ PCI_EXP_SLTCAP_HPS | \ - PCI_EXP_SLTCAP_HPC | \ PCI_EXP_SLTCAP_EIP | \ PCIE_CAP_SLOT_POWER_LIMIT_VAL | \ PCIE_CAP_SLOT_POWER_LIMIT_SCALE) From patchwork Fri May 19 14:31:15 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 684016 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 29D4CC77B7F for ; Fri, 19 May 2023 14:32:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232125AbjESOcU (ORCPT ); Fri, 19 May 2023 10:32:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52906 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232107AbjESOcP (ORCPT ); Fri, 19 May 2023 10:32:15 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 73E5010F4 for ; Fri, 19 May 2023 07:31:55 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id 98e67ed59e1d1-2537909d28cso777838a91.0 for ; Fri, 19 May 2023 07:31:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684506714; x=1687098714; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=dvVFJ4eRpjyBD7o1HP/7PTjD9zFytoFdbjvNe70Jf18=; b=AdxIfjDB8oHYMT8BNQcI8I8vVWjb1AfM/+816qqd/x0qvfPR2KXnBKApE6Q+FBrr0U r37dmu4filLwW+pM9i1TioIViH5fShG18gOY65UmdFI8igf//YL/9C1KoORjmUqINm0S zx4OCwg7YHS+5CRb7SBwRaT0VWuHBCYNJPPCn8TPhJcQTb3ERTAZnM2OOYUFp2jhW4j6 TbPljLSL6rU/vToH98Y7X5O5Aag/trWty75RKQYIpm8ip3B4ruUNdQdP8LKQoWWg3d1O 1BxEP/RIjvo8J1aKZgHfbTbZ7FbbZLggU5FHxT4928Y2qiBB4WtkENX2IBSi0MWHfzlS tl8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684506714; x=1687098714; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=dvVFJ4eRpjyBD7o1HP/7PTjD9zFytoFdbjvNe70Jf18=; b=OGygcyJ4I5xhSGrGm9a5CbKlHvBF4ZMbRdpQDJHJOChpZWbmhsm9TVtLNwYHTVp14m YNr8iYw9ZgSPVrVjrGRQ0rsCRj1wjdF+SANqps8Udm13W+k/OtT0FWdrJdTUXrowy9jA bdUyERfkHf4Qpsw1ZkP1U+5YOfPWQzPtCJtBFM/SCNpMZUQZXn+0xLRCm8UGdT+PHjrw PuBm4x3SGttvRW7quKlRehh4fZzUz4vWAPHcbOsi67cSIc/KpPKJe1z+Z0msUZSbhjiA qyuG7Bf6Ip5Cweoye7+oEaJ94wyBBjjuhyxch59t21fP6g87T060evW0cd1fK3WXAmna cLNw== X-Gm-Message-State: AC+VfDwKfuSiN+Zh0Tc93ZyI6zN1zGi9Qhg3nu4bgJIe4uxVsoBK/Tks f3lvjVpQUsuhXMH7DWmNyItD X-Google-Smtp-Source: ACHHUZ7E1a9GbFAcdbXSe8hjVHZf4mW3gGhaUwfI0CuwaigRcszwE7CIoDDzn8pXQ4cqXxoM4JJhHw== X-Received: by 2002:a17:90b:3d6:b0:24f:13ec:ecac with SMTP id go22-20020a17090b03d600b0024f13ececacmr2383045pjb.26.1684506714700; Fri, 19 May 2023 07:31:54 -0700 (PDT) Received: from localhost.localdomain ([117.202.184.13]) by smtp.gmail.com with ESMTPSA id 30-20020a17090a09a100b00250d908a771sm1634845pjo.50.2023.05.19.07.31.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 07:31:54 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 6/8] PCI: qcom: Use post init sequence of IP v2.3.2 for v2.4.0 Date: Fri, 19 May 2023 20:01:15 +0530 Message-Id: <20230519143117.23875-7-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230519143117.23875-1-manivannan.sadhasivam@linaro.org> References: <20230519143117.23875-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The post init sequence of IP v2.4.0 is same as v2.3.2. So let's reuse the v2.3.2 sequence which now also disables hotplug capability of the controller as it is not at all supported on any SoCs making use of this IP. Signed-off-by: Manivannan Sadhasivam Reviewed-by: Dmitry Baryshkov Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 30 +------------------------- 1 file changed, 1 insertion(+), 29 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 9c8dfd224e6e..e6db9e551752 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -703,34 +703,6 @@ static int qcom_pcie_init_2_4_0(struct qcom_pcie *pcie) return 0; } -static int qcom_pcie_post_init_2_4_0(struct qcom_pcie *pcie) -{ - u32 val; - - /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PARF_PHY_CTRL); - val &= ~PHY_TEST_PWR_DOWN; - writel(val, pcie->parf + PARF_PHY_CTRL); - - /* change DBI base address */ - writel(0, pcie->parf + PARF_DBI_BASE_ADDR); - - /* MAC PHY_POWERDOWN MUX DISABLE */ - val = readl(pcie->parf + PARF_SYS_CTRL); - val &= ~MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN; - writel(val, pcie->parf + PARF_SYS_CTRL); - - val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - val |= BYPASS; - writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL); - - val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - val |= EN; - writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2); - - return 0; -} - static int qcom_pcie_get_resources_2_3_3(struct qcom_pcie *pcie) { struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3; @@ -1276,7 +1248,7 @@ static const struct qcom_pcie_ops ops_2_3_2 = { static const struct qcom_pcie_ops ops_2_4_0 = { .get_resources = qcom_pcie_get_resources_2_4_0, .init = qcom_pcie_init_2_4_0, - .post_init = qcom_pcie_post_init_2_4_0, + .post_init = qcom_pcie_post_init_2_3_2, .deinit = qcom_pcie_deinit_2_4_0, .ltssm_enable = qcom_pcie_2_3_2_ltssm_enable, }; From patchwork Fri May 19 14:31:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Manivannan Sadhasivam X-Patchwork-Id: 684015 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86B0EC77B7F for ; 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Fri, 19 May 2023 07:32:03 -0700 (PDT) Received: from localhost.localdomain ([117.202.184.13]) by smtp.gmail.com with ESMTPSA id 30-20020a17090a09a100b00250d908a771sm1634845pjo.50.2023.05.19.07.31.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 May 2023 07:32:03 -0700 (PDT) From: Manivannan Sadhasivam To: lpieralisi@kernel.org, kw@linux.com, bhelgaas@google.com Cc: robh@kernel.org, andersson@kernel.org, konrad.dybcio@linaro.org, linux-pci@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, steev@kali.org, quic_srichara@quicinc.com, dmitry.baryshkov@linaro.org, Manivannan Sadhasivam Subject: [PATCH v2 8/8] PCI: qcom: Do not advertise hotplug capability for IP v2.1.0 Date: Fri, 19 May 2023 20:01:17 +0530 Message-Id: <20230519143117.23875-9-manivannan.sadhasivam@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230519143117.23875-1-manivannan.sadhasivam@linaro.org> References: <20230519143117.23875-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org SoCs making use of Qcom PCIe controller IP v2.1.0 do not support hotplug functionality. But the hotplug capability bit is set by default in the hardware. This causes the kernel PCI core to register hotplug service for the controller and send hotplug commands to it. But those commands will timeout generating messages as below during boot and suspend/resume. [ 5.782159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2020 msec ago) [ 5.810161] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x03c0 (issued 2048 msec ago) [ 7.838162] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2020 msec ago) [ 7.870159] pcieport 0001:00:00.0: pciehp: Timeout on hotplug command 0x07c0 (issued 2052 msec ago) This not only spams the console output but also induces a delay of a couple of seconds. To fix this issue, let's clear the HPC bit in PCI_EXP_SLTCAP register as a part of the post init sequence to not advertise the hotplug capability for the controller. Signed-off-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 612266fb849a..7a87a47eb7ed 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -438,6 +438,8 @@ static int qcom_pcie_post_init_2_1_0(struct qcom_pcie *pcie) writel(CFG_BRIDGE_SB_INIT, pci->dbi_base + AXI_MSTR_RESP_COMP_CTRL1); + qcom_pcie_clear_hpc(pcie->pci); + return 0; }