From patchwork Thu May 18 11:37:57 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 683518 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9A07C7EE24 for ; Thu, 18 May 2023 11:40:51 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231414AbjERLku (ORCPT ); Thu, 18 May 2023 07:40:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36418 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230416AbjERLkl (ORCPT ); Thu, 18 May 2023 07:40:41 -0400 Received: from mail-wr1-x429.google.com (mail-wr1-x429.google.com [IPv6:2a00:1450:4864:20::429]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF4A61FE8 for ; Thu, 18 May 2023 04:40:17 -0700 (PDT) Received: by mail-wr1-x429.google.com with SMTP id ffacd0b85a97d-30949241c65so485369f8f.1 for ; Thu, 18 May 2023 04:40:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684409994; x=1687001994; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HG4Vbyr7PlG0lpY1RSxwlZMOHt+XOR7/ovgh8gARZlM=; b=kbczseXt+Cf+wUhPfg3lOvHXPHqqYE7Mh28Vz0DG3Tus2Fb0O+v8jSSfk+sOsXfJej yFsMiR9F7FxX/XYGxM4urkPI0/lSKkx1ogJoX/ZhscTnCYQue3lPgolwI0KZ20oL5QUX XWn4zTIG5bKgqf67r94YkjPGJmgiyOlu4LYYiGUjSoTCUICGLzyxRRi9tHT4E2Gu8MWC gLEW6MZFNeeusp28Fca11GDy+1QJC2RvJ4JmpebUHRoXeILJscP8flYNw/+i4Ne/kFAZ y7aMlICfq5PLz8ul8AnbZst/iPbLSy7wAID9g1T00xAXXWI4OssILrA0Fjl2YQg7GJXi PUkQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684409994; x=1687001994; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HG4Vbyr7PlG0lpY1RSxwlZMOHt+XOR7/ovgh8gARZlM=; b=iuz9lIxXfRcv7Q6wYKozoFSEkmbSTdCKguq3/43gvUs7gidMPPtCtYJXLJfSADqIfn Brin9Uo80US3NTqdjJEH/KIFWNXejdr6aOusaAXNxSYWxCI0DKbY/1Qj7cix7pdhMWH6 bgC9jQ1uJhIf9wHL2kXSHIKqHQhds1SX9rDh0Gd7ZKNBgKoYt2P+ST2KLfDa+mZu5YGN 3rGd3ZZsO/IcmhOB4csVi9+KIC77luMHUgw8bB9+7EQ5l17RvCGaAETaLC6x2EuFp5Zj STxcpJRFnh/8D1cv3ISKV+szjdTf4/iTeWn3m8UBXGJbPAtc7jSqR83L+F8AJXbI9ou8 Je7w== X-Gm-Message-State: AC+VfDxIecUlUhDMARxE75TPlx6ERV6HhD6T4IBGvWK4MHg9Qe/F3vC9 EEe5Jx82guBpbqX77T6di2e3Mg== X-Google-Smtp-Source: ACHHUZ45vjuEaH9D5GBYXWDkM1nucUH5ctXYjl87CMZOxDISAypwtYW5WXGFDuw5yYrlwsiHTzA7Eg== X-Received: by 2002:adf:f484:0:b0:306:3ec9:99c5 with SMTP id l4-20020adff484000000b003063ec999c5mr1398646wro.9.1684409994340; Thu, 18 May 2023 04:39:54 -0700 (PDT) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id f14-20020a5d568e000000b003047d5b8817sm1897135wrv.80.2023.05.18.04.39.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 04:39:53 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 2/5] dt-bindings: clock: Add YAML schemas for LPASS AUDIOCC and reset on SC8280XP Date: Thu, 18 May 2023 12:37:57 +0100 Message-Id: <20230518113800.339158-3-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> References: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The LPASS(Low Power Audio Subsystem) Audio clock provider provides reset controller support when is driven by the Q6DSP. This patch adds support for those resets and adds IDs for clients to request the reset. Signed-off-by: Srinivas Kandagatla --- .../bindings/clock/qcom,sc8280xp-lpasscc.yaml | 11 +++++++++++ include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h | 5 +++++ 2 files changed, 16 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml index 7c30614a0af9..394833819ba3 100644 --- a/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,sc8280xp-lpasscc.yaml @@ -22,6 +22,7 @@ properties: compatible: enum: - qcom,sc8280xp-lpasscc + - qcom,sc8280xp-lpassaudiocc '#reset-cells': const: 1 @@ -45,6 +46,16 @@ required: additionalProperties: false examples: + - | + #include + lpass_audiocc: clock-controller@3300000 { + compatible = "qcom,sc8280xp-lpassaudiocc"; + reg = <0x32a9000 0x1000>; + #reset-cells = <1>; + #clock-cells = <1>; + qcom,adsp-pil-mode; + }; + - | #include lpasscc: clock-controller@3900000 { diff --git a/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h b/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h index df800ea2741c..d190d57fc81a 100644 --- a/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h +++ b/include/dt-bindings/clock/qcom,lpasscc-sc8280xp.h @@ -6,6 +6,11 @@ #ifndef _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H #define _DT_BINDINGS_CLK_QCOM_LPASSCC_SC8280XP_H +/* LPASS AUDIO CC CSR */ +#define LPASS_AUDIO_SWR_RX_CGCR 0 +#define LPASS_AUDIO_SWR_WSA_CGCR 1 +#define LPASS_AUDIO_SWR_WSA2_CGCR 2 + /* LPASS TCSR */ #define LPASS_AUDIO_SWR_TX_CGCR 0 From patchwork Thu May 18 11:37:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas Kandagatla X-Patchwork-Id: 683517 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B52BCC7EE2C for ; Thu, 18 May 2023 11:40:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231407AbjERLkw (ORCPT ); Thu, 18 May 2023 07:40:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36422 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231410AbjERLku (ORCPT ); Thu, 18 May 2023 07:40:50 -0400 Received: from mail-wr1-x430.google.com (mail-wr1-x430.google.com [IPv6:2a00:1450:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 49E8A1FD2 for ; Thu, 18 May 2023 04:40:20 -0700 (PDT) Received: by mail-wr1-x430.google.com with SMTP id ffacd0b85a97d-3078c092056so1278726f8f.1 for ; Thu, 18 May 2023 04:40:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684409997; x=1687001997; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=w+NnmS4Y3N2+zWv4AXvVWEIhI6GRLW/Tqx1d8cSKZH0=; b=WgmcYd3c2c6AmlCrESXGoTOnB4d/DjLyAxklZQY3IlX6lsIPNn9B8cYkfuSa/SKIj4 zLrhmGGzX/x++nUUWvv8gFHW1cLmJikKbJffcn/hSMa5GOJ5YXOW78CjVVWl+OKOHFSe Ko2sUmtsolRJIiLptuFsMxn/87vmOMYtIVo9VudQMJTAllWLLsHV9/8MDqhMxaFTzWKV dYVQvogf0/W7aDP38KKsH3dZH66xxx1hcO+FEuWQB6faRP0YnydpqGmcS/RJoY6Cb4sZ bJXLs8IcZBbliLdNkTxfDmGrd1A0HOihgl/GskeUcmecsE1hDzsBfgHrs4eQSqMQ30Tm Royg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684409997; x=1687001997; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=w+NnmS4Y3N2+zWv4AXvVWEIhI6GRLW/Tqx1d8cSKZH0=; b=lu4rPnz2C7aUqPT3kBK9zo0TVCn17AXGvg7QHrkV/gE4fcDqGP41s272xz4R0YkJK8 5aKDxIPwmcK8sIi3m/d8UYBR2n2wXQY6QFyz+pGp3g2O9Dm3hl1qcYnKYFltzNYNw1bC yJfaGPg3sXChMkbNIew+dR+TL0gfaXjgAW29+mKL30pZAPseLXyITqXl5JGMkW5cGWNY 58ShN5L2sCOWWIMGrim8D6g0vG+npDsXDdO0SaVQlq8LAjlZdHI2KVEyaG0FhtitICDN N+nSnu+XasU/tfUby99Sh+5LZpSneV9WQ7zmuJyIYE7gYmKZ4newmiwOlMmz8bevpCXJ iuTA== X-Gm-Message-State: AC+VfDxSo01wT5r+hyoiIcvCwl/NNu3ATmtM3DTLq0yIGVUG96uBL+QR Tbp2p2Feh9WWMLuJ7Uw42IXs9A== X-Google-Smtp-Source: ACHHUZ4xc23L4sP/TfxuHDTrwImaj5xkH98OAx2YSlJWBzyYAHAXNTvdKHWzQ+9tUgRkhCphmGYYHw== X-Received: by 2002:a5d:6d50:0:b0:309:475c:c90e with SMTP id k16-20020a5d6d50000000b00309475cc90emr1637260wri.37.1684409996910; Thu, 18 May 2023 04:39:56 -0700 (PDT) Received: from localhost.localdomain ([5.133.47.210]) by smtp.gmail.com with ESMTPSA id f14-20020a5d568e000000b003047d5b8817sm1897135wrv.80.2023.05.18.04.39.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 18 May 2023 04:39:56 -0700 (PDT) From: Srinivas Kandagatla To: andersson@kernel.org, robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org Cc: johan+linaro@kernel.org, agross@kernel.org, konrad.dybcio@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Srinivas Kandagatla Subject: [PATCH 4/5] clk: qcom: Add lpass audio clock controller driver for SC8280XP Date: Thu, 18 May 2023 12:37:59 +0100 Message-Id: <20230518113800.339158-5-srinivas.kandagatla@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> References: <20230518113800.339158-1-srinivas.kandagatla@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for the lpass audio clock controller found on SC8280XP based devices. This would allow lpass peripheral loader drivers to control the clocks and bring the subsystems out of reset. Currently this patch only supports resets as the Q6DSP is in control of LPASS IP which manages most of the clocks via Q6PRM service on GPR rpmsg channel. Signed-off-by: Srinivas Kandagatla --- drivers/clk/qcom/lpasscc-sc8280xp.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/qcom/lpasscc-sc8280xp.c b/drivers/clk/qcom/lpasscc-sc8280xp.c index 118320f8ee40..e221ae2d40ae 100644 --- a/drivers/clk/qcom/lpasscc-sc8280xp.c +++ b/drivers/clk/qcom/lpasscc-sc8280xp.c @@ -13,6 +13,26 @@ #include "common.h" #include "reset.h" +static const struct qcom_reset_map lpass_audio_csr_sc8280xp_resets[] = { + [LPASS_AUDIO_SWR_RX_CGCR] = { 0xa0, 1 }, + [LPASS_AUDIO_SWR_WSA_CGCR] = { 0xb0, 1 }, + [LPASS_AUDIO_SWR_WSA2_CGCR] = { 0xd8, 1 }, +}; + +static struct regmap_config lpass_audio_csr_sc8280xp_regmap_config = { + .reg_bits = 32, + .reg_stride = 4, + .val_bits = 32, + .name = "lpass-audio-csr", + .max_register = 0x1000, +}; + +static const struct qcom_cc_desc lpass_audio_csr_reset_sc8280xp_desc = { + .config = &lpass_audio_csr_sc8280xp_regmap_config, + .resets = lpass_audio_csr_sc8280xp_resets, + .num_resets = ARRAY_SIZE(lpass_audio_csr_sc8280xp_resets), +}; + static const struct qcom_reset_map lpass_tcsr_sc8280xp_resets[] = { [LPASS_AUDIO_SWR_TX_CGCR] = { 0xc010, 1 }, }; @@ -33,6 +53,9 @@ static const struct qcom_cc_desc lpass_tcsr_reset_sc8280xp_desc = { static const struct of_device_id lpasscc_sc8280xp_match_table[] = { { + .compatible = "qcom,sc8280xp-lpassaudiocc", + .data = &lpass_audio_csr_reset_sc8280xp_desc, + }, { .compatible = "qcom,sc8280xp-lpasscc", .data = &lpass_tcsr_reset_sc8280xp_desc, },