From patchwork Tue May 16 08:52:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dario Binacchi X-Patchwork-Id: 682722 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DD084C77B75 for ; Tue, 16 May 2023 08:52:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231282AbjEPIwy (ORCPT ); Tue, 16 May 2023 04:52:54 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:35318 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231750AbjEPIwm (ORCPT ); Tue, 16 May 2023 04:52:42 -0400 Received: from mail-qk1-x736.google.com (mail-qk1-x736.google.com [IPv6:2607:f8b0:4864:20::736]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B8B9E4C0A for ; Tue, 16 May 2023 01:52:28 -0700 (PDT) Received: by mail-qk1-x736.google.com with SMTP id af79cd13be357-7577ef2fa31so179230185a.0 for ; Tue, 16 May 2023 01:52:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; t=1684227148; x=1686819148; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=3Fsp/r/3X/nR5Dw9Y1Zsp/W7/PyEi0YNOAlMQBXhdvU=; b=IpHvYlsdGHRVrxdSldGKJOZaCDHvYa3054Jl2mOcEZkIz44x3oKuYk+VAZ+abkVCHZ ryThXyKnU22y2lO87uWBgHjsmA7Y4yXjB1rq8PBl1o688QRwuYjGDJhG83VlUfZpCZxG 1X3Wv34o5BGtgOQW3TLfRUXLewQFbYKu23RfA= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684227148; x=1686819148; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=3Fsp/r/3X/nR5Dw9Y1Zsp/W7/PyEi0YNOAlMQBXhdvU=; b=OBsM++VlTt/uKXfdVzFFdnMuASie57D9NTTGlBKtiw1Wdi2kYlV9BNiyZdkIwgT+vc HlBdSqiJPRhDnsgpXkONQYBzsrQVR/mNdg4m8cmkU4OihZu4U5CDS4XnDi3qGZT5Jj8z tmgNDczHUQKWu9goHwAcAvxjspQFMqrsZRHkTADUkokPdF3H0QRVtqNj/WRbQzoL4JQq E10Y/daRGnHzb7lx2T9je3vyBQZQhv03oBQ5NFKNI8kiCCzqWSlPFVQZZPHCzfPQcn/i XHN+EBoG6aYIujRz7Xf21uqdswTEQiXO6YbwOtm/QAUqALrqJj7PLVKksCa0uTE9DM79 9a2g== X-Gm-Message-State: AC+VfDyxfGhxYZe0YYHgJHEbVjX4a5LcbeC2nQgyQL/w9lPU9pDvF40/ lQ4wbT3Z7vgqUtKVCwiJmcqmsQ== X-Google-Smtp-Source: ACHHUZ58ENGBVYW2227e7XYFPh3fQ4T1J9FrMj5V0IlG55RxHnBgxuqmrqQC6uWuWy8Rx9ld0qpIlA== X-Received: by 2002:a05:6214:29c7:b0:56e:c066:3cd2 with SMTP id gh7-20020a05621429c700b0056ec0663cd2mr58463378qvb.2.1684227147882; Tue, 16 May 2023 01:52:27 -0700 (PDT) Received: from dario-ThinkPad-T14s-Gen-2i.pdxnet.pdxeng.ch (mob-5-90-62-17.net.vodafone.it. [5.90.62.17]) by smtp.gmail.com with ESMTPSA id d10-20020a0ce44a000000b005ef54657ea0sm5480337qvm.126.2023.05.16.01.52.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 01:52:27 -0700 (PDT) From: Dario Binacchi To: linux-kernel@vger.kernel.org Cc: Dario Binacchi , Alexandre Torgue , Conor Dooley , Krzysztof Kozlowski , Maxime Coquelin , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH] ARM: dts: stm32: use RCC macro for CRC node on stm32f746 Date: Tue, 16 May 2023 10:52:19 +0200 Message-Id: <20230516085219.3797677-1-dario.binacchi@amarulasolutions.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The patch replaces the number 12 with the appropriate numerical constant already defined in the file stm32f7-rcc.h. Signed-off-by: Dario Binacchi --- arch/arm/boot/dts/stm32f746.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32f746.dtsi b/arch/arm/boot/dts/stm32f746.dtsi index dc868e6da40e..e3564b74a779 100644 --- a/arch/arm/boot/dts/stm32f746.dtsi +++ b/arch/arm/boot/dts/stm32f746.dtsi @@ -515,7 +515,7 @@ pwrcfg: power-config@40007000 { crc: crc@40023000 { compatible = "st,stm32f7-crc"; reg = <0x40023000 0x400>; - clocks = <&rcc 0 12>; + clocks = <&rcc 0 STM32F7_AHB1_CLOCK(CRC)>; status = "disabled"; };