From patchwork Tue May 16 10:44:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Alex_Benn=C3=A9e?= X-Patchwork-Id: 682353 Delivered-To: patch@linaro.org Received: by 2002:adf:fd8f:0:0:0:0:0 with SMTP id d15csp261741wrr; Tue, 16 May 2023 03:44:47 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6x0MBCYkIs/Rt8327MYJnUJ2xredAyhRbiAHt3QIMHjXsHkP3OS8ZyqB6FVMi6RFXl8tcM X-Received: by 2002:a05:6214:5083:b0:61b:6a44:5f03 with SMTP id kk3-20020a056214508300b0061b6a445f03mr56928577qvb.33.1684233887802; Tue, 16 May 2023 03:44:47 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1684233887; cv=none; d=google.com; s=arc-20160816; b=x9rWaukYVpsaoFeBtAjUyina0TmWwwn34tmSBLFEefAdRGj6t4n+3wrc4QIm38yD4e 1Ecx7muDnT4V1w+fXyx0AURq/AQ9EEDGlEM4+V5hvhFzNduFFKVl1hwyyfQhC6+b9XzI KWMEmwoFacnF4KHjexrToPLS7tDw6Jy5HPELQve/Wdn35/QOJFG9xHa8wGyVDCzdcF5c kFdYHbvqOeXUoCAlSeGnceErJRdMdHwX7vohKEDm24fB6ukIT/N3P+wA7PIuBX7K1iuP /AD+ZfampI5GuTKs53J2BFVamMTQA6kOxNvMMF/6y+RUu0ePJMjni0fthXuWPOuxP+JY DmPQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:message-id:date:subject:cc:to:from:dkim-signature; bh=lXWfMZ/av4U9Bkl4i4+asgu1kTL2cD21X4pX4BS7V0k=; b=zipQnwL96fI/pJHOQS3UwJR+i2jNWzV4AgaLT41Q1dauxlfxStkRcsvIsEjtYt1JRG pUb8MSzEiToOkMrI0Lmn+DCvsh3oVurQGbNyuf0tbuik7Bq2zWop5yTdp9oCn8p75Asb zBtL7uRfO4D6tVoOUuNn0yW04p3O8c/QXGQmMkiN97mm2BrWsqbaevp2wa8Q8WVR4HRF vNfAH+s7a3Ul15useI6lZ5UqiSpc9QdtUbo6bYR26Egu3rSd92fntSj5rmZWdL6+WCOG L4A+UZ+s5nOeZuG4ES9h1O6OAbv1aEiOgkgR41RsLlNqHFXRlbR/81LU9nCx/QcQV6Pe 7L/w== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZEsOC5Y9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. [209.51.188.17]) by mx.google.com with ESMTPS id gv4-20020a056214262400b005f166fc7a7esi11431982qvb.471.2023.05.16.03.44.47 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Tue, 16 May 2023 03:44:47 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=ZEsOC5Y9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pysAU-0003Ke-5D; Tue, 16 May 2023 06:44:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pysAQ-0003JJ-68 for qemu-devel@nongnu.org; Tue, 16 May 2023 06:44:31 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pysAO-0004gd-GT for qemu-devel@nongnu.org; Tue, 16 May 2023 06:44:29 -0400 Received: by mail-wm1-x32d.google.com with SMTP id 5b1f17b1804b1-3f4249b7badso99130225e9.3 for ; Tue, 16 May 2023 03:44:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1684233867; x=1686825867; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=lXWfMZ/av4U9Bkl4i4+asgu1kTL2cD21X4pX4BS7V0k=; b=ZEsOC5Y9VDlQZrt8InJdRitnAxU24LUNYOF7MwrWMIPEqyM+5rGIWJb9eeO+sewUBP RfIYGVidjhUulyaqrnD3K/DitOegi5CRcl5Y49dmvP1maZpXAewuaKJcIeVgzcmfOLwf RSaTZ2IJnyQacrsEgb9CF9DP1m7vJdTk8RQgzEAsa5j9OMZM1XnydSxntY/Hp2jg5QwG UDNFca5CmXYGi3THGldFZACWLHbHmMjmNRpJhcceeaacYW5cxTFwwql4M7AYQaE8sTeM UBAbIgHsODAxjC71IrKEQOQ+IeShFKrpkfqQPW3M/v3oMYBqi2r1EabBcSWkdKBL5qen NMXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1684233867; x=1686825867; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=lXWfMZ/av4U9Bkl4i4+asgu1kTL2cD21X4pX4BS7V0k=; b=Li5WGvYq/er3fKzm++f+AL6J+IabKm4QAcnfFh/QW6DVMMIV4bUJB8fOTrKWGHeWEB 2K3Ca+LOqfskCZu7K7pxH//Z6/txg8JNlWe6UnDS2YKlblZGFxVVjs3ZmBINrd6M+OTH p1Z2AV24jlzAwGiL7vet/M6cWqyvl7trVF7B8EA/EFlTX/jp93mqJSEjYHaheHsnLI0+ nmyOvD+bbs2b6oZeanfORRP1KptViCbnyw4ubbBkIVY6Coz+Rk8NNDU58EGW+3GUqDPd NkmfmoAqaYkOVY3u+oTK6phXAGllXl+LbVubQonZfXLBqFVemPIS6z3kvULJ7++xGIlG Hqrg== X-Gm-Message-State: AC+VfDzv9/nCl2caYDMmh+q+vjvw09MD90bsIuPdI+USm0XUwmWaLfZz SyveBXCxyNoDYIwyt7zSqCcRRezIw245ix+XOZm5Bw== X-Received: by 2002:a7b:cb90:0:b0:3f4:f8f9:bce7 with SMTP id m16-20020a7bcb90000000b003f4f8f9bce7mr8560399wmi.32.1684233866907; Tue, 16 May 2023 03:44:26 -0700 (PDT) Received: from zen.linaroharston ([85.9.250.243]) by smtp.gmail.com with ESMTPSA id z21-20020a1c4c15000000b003f508115b25sm1947019wmf.4.2023.05.16.03.44.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 16 May 2023 03:44:26 -0700 (PDT) Received: from zen.lan (localhost [127.0.0.1]) by zen.linaroharston (Postfix) with ESMTP id D3D691FFBB; Tue, 16 May 2023 11:44:25 +0100 (BST) From: =?utf-8?q?Alex_Benn=C3=A9e?= To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?utf-8?q?Alex_Benn=C3=A9e?= , Anders Roxell , Evgeny Iakovlev , Peter Maydell Subject: [RFC PATCH] target/arm: add RAZ/WI handling for DBGDTR[TX|RX] Date: Tue, 16 May 2023 11:44:20 +0100 Message-Id: <20230516104420.407912-1-alex.bennee@linaro.org> X-Mailer: git-send-email 2.39.2 MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=alex.bennee@linaro.org; helo=mail-wm1-x32d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org The commit b3aa2f2128 (target/arm: provide stubs for more external debug registers) was added to handle HyperV's unconditional usage of Debug Communications Channel. It turns out that Linux will similarly break if you enable CONFIG_HVC_DCC "ARM JTAG DCC console". Extend the registers we RAZ/WI set to avoid this. Cc: Anders Roxell Cc: Evgeny Iakovlev Signed-off-by: Alex Bennée Reviewed-by: Richard Henderson --- target/arm/debug_helper.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index dfc8b2a1a5..d41cc643b1 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -949,8 +949,10 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .access = PL0_R, .accessfn = access_tdcc, .type = ARM_CP_CONST, .resetvalue = 0 }, /* - * OSDTRRX_EL1/OSDTRTX_EL1 are used for save and restore of DBGDTRRX_EL0. - * It is a component of the Debug Communications Channel, which is not implemented. + * These registers belong to the Debug Communications Channel, + * which is not implemented. However we implement RAZ/WI behaviour + * with trapping to prevent spurious SIGILLs if the guest OS does + * access them as the support cannot be probed for. */ { .name = "OSDTRRX_EL1", .state = ARM_CP_STATE_BOTH, .cp = 14, .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 2, @@ -960,6 +962,11 @@ static const ARMCPRegInfo debug_cp_reginfo[] = { .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2, .access = PL1_RW, .accessfn = access_tdcc, .type = ARM_CP_CONST, .resetvalue = 0 }, + /* DBGDTRTX_EL0/DBGDTRRX_EL0 depend on direction */ + { .name = "DBGDTR_EL0", .state = ARM_CP_STATE_BOTH, .cp = 14, + .opc0 = 2, .opc1 = 3, .crn = 0, .crm = 5, .opc2 = 0, + .access = PL0_RW, .accessfn = access_tdcc, + .type = ARM_CP_CONST, .resetvalue = 0 }, /* * OSECCR_EL1 provides a mechanism for an operating system * to access the contents of EDECCR. EDECCR is not implemented though,