From patchwork Fri May 12 00:32:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 681397 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6885BC7EE2A for ; Fri, 12 May 2023 00:32:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239637AbjELAch (ORCPT ); Thu, 11 May 2023 20:32:37 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43334 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239620AbjELAcf (ORCPT ); Thu, 11 May 2023 20:32:35 -0400 Received: from mail-lf1-x12d.google.com (mail-lf1-x12d.google.com [IPv6:2a00:1450:4864:20::12d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3CD1859DC for ; Thu, 11 May 2023 17:32:34 -0700 (PDT) Received: by mail-lf1-x12d.google.com with SMTP id 2adb3069b0e04-4f1fe1208a4so7580244e87.2 for ; Thu, 11 May 2023 17:32:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683851552; x=1686443552; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RzC/S26FfX2KBobwpdwOfCvN/amobbf96cFrDJ/wC6A=; b=fkMyWui9qjhtPN3UucqAj0YDgghgrr7ix+K6WBtwGUceg+JTjgwZf0kFsEUDhQTmB+ slvZ0dv8xZEOhDXZvZggMIDjv7ECm7yozeC17rIBrcTeFcZX/taGr122d3qJNVcsYEli oWnvmn/tgmko30sV5mlCWFfp7Nqi7wvm7SSBHaGUlSfL2YZGDyZSsDK8LIrYY2r0aI+v y1NEZr9Cdfu35HCjOBEHoyAO8Tfx/q6L0PwOqsza8z7NV4hpvxNo3XZofrm83nHQOgT7 uTMgvMOaKUCyJxC9DtBLEQ7x9v3NmoWJ6Ak0a0VNCysLFdSscxEnEne6RRI9Nhm7/Kim /AZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683851552; x=1686443552; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RzC/S26FfX2KBobwpdwOfCvN/amobbf96cFrDJ/wC6A=; b=KiX51FssySMkcJRXTF+sFVibNk98Le0eNBHFGLKSdcjR21r0sBWprf4yiSIf+e1giZ rdTzP7/S/n+/vQJyCiw58FPxkkz7KE7Ah6//M+Zb0Oyer9UtOX301GWdvzJJLj4psWyu jtHbCa8BueAwMxFEEh0l5CrOwrX5g5Ev4U1IBF38I0n28Z3ukLUmjhcNGnWUHd5kVFZi zqd20KJ/asuvJCLJoM82yGewV7d1nNIRM6lbHmCpvl5TiSxuf9qrSc+gmmkxn0JiZ2hG Psmk6fKK0MxIqIROP2hFgEjd33g5PpbIsKf3OEDvB2yyntfbkLryxkaoh5WMx+D0Vpp3 7rAg== X-Gm-Message-State: AC+VfDwGnM2yiZDhHT1HXBpZdD8gALSKBQtby8anHgo9IByFA6aI5p40 nuchk82gdLZtOien+0Zn8/VmJQ== X-Google-Smtp-Source: ACHHUZ6s7Y0KFS2o3h0R8qGGin1sTFHn0NyW1jVuQeQQDAHY9SEThMUg+YfbmkchsoShgGIEG3R20g== X-Received: by 2002:ac2:4a75:0:b0:4f1:444e:6c5a with SMTP id q21-20020ac24a75000000b004f1444e6c5amr3023901lfp.8.1683851552416; Thu, 11 May 2023 17:32:32 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id i7-20020a056512006700b004f13cd61ebbsm1282708lfo.175.2023.05.11.17.32.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 17:32:32 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v2 01/10] dt-bindings: clock: qcom,lcc.yaml: describe clocks for lcc,qcom-mdm9615 Date: Fri, 12 May 2023 03:32:21 +0300 Message-Id: <20230512003230.3043284-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230512003230.3043284-1-dmitry.baryshkov@linaro.org> References: <20230512003230.3043284-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Describe parent clocks used by the LCC on the MDM9615 platform. It is the list as the one for msm8960/apq8064, with only difference being pxo/cxo replacement. Acked-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../devicetree/bindings/clock/qcom,lcc.yaml | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/Documentation/devicetree/bindings/clock/qcom,lcc.yaml b/Documentation/devicetree/bindings/clock/qcom,lcc.yaml index 8c783823e93c..55985e562a34 100644 --- a/Documentation/devicetree/bindings/clock/qcom,lcc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,lcc.yaml @@ -76,6 +76,40 @@ allOf: - clocks - clock-names + - if: + properties: + compatible: + contains: + enum: + - qcom,lcc-mdm9615 + then: + properties: + clocks: + items: + - description: Board CXO source + - description: PLL 4 Vote clock + - description: MI2S codec clock + - description: Mic I2S codec clock + - description: Mic I2S spare clock + - description: Speaker I2S codec clock + - description: Speaker I2S spare clock + - description: PCM codec clock + + clock-names: + items: + - const: cxo + - const: pll4_vote + - const: mi2s_codec_clk + - const: codec_i2s_mic_codec_clk + - const: spare_i2s_mic_codec_clk + - const: codec_i2s_spkr_codec_clk + - const: spare_i2s_spkr_codec_clk + - const: pcm_codec_clk + + required: + - clocks + - clock-names + examples: - | clock-controller@28000000 { From patchwork Fri May 12 00:32:23 2023 Content-Type: text/plain; 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Split the qcom,gcc-mdm9615 to the separate schema file. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Dmitry Baryshkov --- .../bindings/clock/qcom,gcc-mdm9615.yaml | 48 +++++++++++++++++++ .../bindings/clock/qcom,gcc-other.yaml | 3 -- 2 files changed, 48 insertions(+), 3 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml new file mode 100644 index 000000000000..bc9786f2c1d5 --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-mdm9615.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: GPL-2.0-only +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc-mdm9615.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller on MDM9615 + +maintainers: + - Stephen Boyd + - Taniya Das + +description: | + Qualcomm global clock control module provides the clocks, resets and power + domains on MDM9615. + + See also:: + include/dt-bindings/clock/qcom,gcc-mdm9615.h + include/dt-bindings/reset/qcom,gcc-mdm9615.h + +allOf: + - $ref: qcom,gcc.yaml# + +properties: + compatible: + const: qcom,gcc-mdm9615 + + clocks: + maxItems: 2 + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + clock-controller@900000 { + compatible = "qcom,gcc-mdm9615"; + reg = <0x00900000 0x4000>; + #power-domain-cells = <1>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&cxo_board>, <&lcc PLL4>; + clock-names = "cxo", "pll4"; + }; +... diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml index ae01e7749534..b6e260755a21 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-other.yaml @@ -19,8 +19,6 @@ description: | include/dt-bindings/reset/qcom,gcc-ipq6018.h include/dt-bindings/clock/qcom,gcc-msm8953.h include/dt-bindings/clock/qcom,gcc-mdm9607.h - include/dt-bindings/clock/qcom,gcc-mdm9615.h - include/dt-bindings/reset/qcom,gcc-mdm9615.h allOf: - $ref: qcom,gcc.yaml# @@ -31,7 +29,6 @@ properties: - qcom,gcc-ipq6018 - qcom,gcc-mdm9607 - qcom,gcc-msm8953 - - qcom,gcc-mdm9615 required: - compatible From patchwork Fri May 12 00:32:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 681395 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0D6C6C7EE23 for ; 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Thu, 11 May 2023 17:32:36 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id i7-20020a056512006700b004f13cd61ebbsm1282708lfo.175.2023.05.11.17.32.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 17:32:35 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, stable@kernel.org, Neil Armstrong Subject: [PATCH v2 06/10] clk: qcom: gcc-mdm9615: use proper parent for pll0_vote clock Date: Fri, 12 May 2023 03:32:26 +0300 Message-Id: <20230512003230.3043284-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230512003230.3043284-1-dmitry.baryshkov@linaro.org> References: <20230512003230.3043284-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The pll0_vote clock definitely should have pll0 as a parent (instead of pll8). Fixes: 7792a8d6713c ("clk: mdm9615: Add support for MDM9615 Clock Controllers") Cc: stable@kernel.org Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-mdm9615.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index fb5c1244fb97..2f921891008d 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -58,7 +58,7 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_names = (const char *[]){ "pll0" }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, From patchwork Fri May 12 00:32:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 681394 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C51CDC7EE30 for ; Fri, 12 May 2023 00:32:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239640AbjELAco (ORCPT ); Thu, 11 May 2023 20:32:44 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43612 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239666AbjELAcn (ORCPT ); Thu, 11 May 2023 20:32:43 -0400 Received: from mail-lj1-x230.google.com (mail-lj1-x230.google.com [IPv6:2a00:1450:4864:20::230]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C234F72A4 for ; Thu, 11 May 2023 17:32:38 -0700 (PDT) Received: by mail-lj1-x230.google.com with SMTP id 38308e7fff4ca-2ac8d9399d5so82758521fa.1 for ; Thu, 11 May 2023 17:32:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683851557; x=1686443557; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=6wokvLB4E/PYGVb196XdxZfYyHsIhHMceF+n+PMLHuw=; b=q0pxiuw68YZ6ghTXXkQy9fCnQqiw2tsSR+ZJTYk8lBWLqc+PRYYq2WbmQBG7gRufeL xcwhHHaTPvDTuIDliqPwtn/PyMkc729kwwhEPh6UNN3Ua4GifKPVEk5wM10THqBRNbwO CtGxKmKq4Bgs7VWLGqA22qUntcX8/fTPgEhbyLwU0cLt3tRYSBAPc3UhKmVU0bZmwQun 2SK0VcjKPx4OXBdm/1RPXV7VTN2fIzjhbhUtPv5WBPV4VJHoyu9A7IElhnCRWpdZQBWl 9PU2muqoIr4alOt+i6BFt2SKIDdLyaXu9DW5tT9RhESjQAXNwhyy8fve3Dbq5DpOK6Hy 7V/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683851557; x=1686443557; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=6wokvLB4E/PYGVb196XdxZfYyHsIhHMceF+n+PMLHuw=; b=YlXI6odzQ9hm3uj7KW4qAiDXL/B2Rw2aFf9v3xNUn3FMVcLyw/gq4pS2dnEmxK2tLi oNx/QFL98Gr1S3whUuUPcgpUqH2EwgcM/fIYpVS5K1YKWgWHwBgL9J3SOYwuCWKI2YKN 13KvEGyHtsC3RZT21W6hjCKO81phZaAUP95h5kgT4dH1BZwTbrQ9FMX0f7aXdHCe851c hkpCb3ATseJSDN0Ws6fq8JGNSRl8EXqHCM9imjADPKuLv3SNs5oihzWSPDQlNTSMUpP/ nIvNzvQm7mLvK4f2v6gaZo6WZv0X0CYsLOPmBd2usjZlIiIy6wrvn53ygidW1jsg9mZ1 yb4A== X-Gm-Message-State: AC+VfDxAAYQfgdu9PMh8dOLWMlwzMoT7TnhtebbOjdpaXl8m+etpH/0Q kFFBXFSYcdPGS2gY50tDQitdMQ== X-Google-Smtp-Source: ACHHUZ7T+zyWnF+29jQ0myLshY6aytaXKJBd6vYtw8LzLVeOJvIT/2OppfksG4B0qYOPbhuC8osjQw== X-Received: by 2002:a19:ac01:0:b0:4e8:77a:f894 with SMTP id g1-20020a19ac01000000b004e8077af894mr3136202lfc.25.1683851556953; Thu, 11 May 2023 17:32:36 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id i7-20020a056512006700b004f13cd61ebbsm1282708lfo.175.2023.05.11.17.32.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 17:32:36 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong Subject: [PATCH v2 07/10] clk: qcom: gcc-mdm9615: use parent_hws/_data instead of parent_names Date: Fri, 12 May 2023 03:32:27 +0300 Message-Id: <20230512003230.3043284-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230512003230.3043284-1-dmitry.baryshkov@linaro.org> References: <20230512003230.3043284-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert the clock driver to specify parent data rather than parent names, to actually bind using 'clock-names' specified in the DTS rather than global clock names. Use parent_hws where possible to refer parent clocks directly, skipping the lookup. Note, the system names for xo clocks were changed from "cxo" to "cxo_board" to follow the example of other platforms. This switches the clocks to use DT-provided "cxo_board" clock instead of manually registered "cxo" clock and allows us to drop the cxo clock. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- drivers/clk/qcom/gcc-mdm9615.c | 206 ++++++++++++++++++++------------- 1 file changed, 124 insertions(+), 82 deletions(-) diff --git a/drivers/clk/qcom/gcc-mdm9615.c b/drivers/clk/qcom/gcc-mdm9615.c index 2f921891008d..458c18b639db 100644 --- a/drivers/clk/qcom/gcc-mdm9615.c +++ b/drivers/clk/qcom/gcc-mdm9615.c @@ -37,6 +37,25 @@ static struct clk_fixed_factor cxo = { }, }; +enum { + DT_CXO, + DT_PLL4, +}; + +enum { + P_CXO, + P_PLL8, + P_PLL14, +}; + +static const struct parent_map gcc_cxo_map[] = { + { P_CXO, 0 }, +}; + +static const struct clk_parent_data gcc_cxo[] = { + { .index = DT_CXO, .name = "cxo_board" }, +}; + static struct clk_pll pll0 = { .l_reg = 0x30c4, .m_reg = 0x30c8, @@ -47,8 +66,8 @@ static struct clk_pll pll0 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll0", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, + .parent_data = gcc_cxo, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_pll_ops, }, }; @@ -58,7 +77,9 @@ static struct clk_regmap pll0_vote = { .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ .name = "pll0_vote", - .parent_names = (const char *[]){ "pll0" }, + .parent_hws = (const struct clk_hw*[]) { + &pll0.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -69,7 +90,9 @@ static struct clk_regmap pll4_vote = { .enable_mask = BIT(4), .hw.init = &(struct clk_init_data){ .name = "pll4_vote", - .parent_names = (const char *[]){ "pll4" }, + .parent_data = &(const struct clk_parent_data) { + .index = DT_PLL4, .name = "pll4", + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -85,8 +108,8 @@ static struct clk_pll pll8 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll8", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, + .parent_data = gcc_cxo, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_pll_ops, }, }; @@ -96,7 +119,9 @@ static struct clk_regmap pll8_vote = { .enable_mask = BIT(8), .hw.init = &(struct clk_init_data){ .name = "pll8_vote", - .parent_names = (const char *[]){ "pll8" }, + .parent_hws = (const struct clk_hw*[]) { + &pll8.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, @@ -112,8 +137,8 @@ static struct clk_pll pll14 = { .status_bit = 16, .clkr.hw.init = &(struct clk_init_data){ .name = "pll14", - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, + .parent_data = gcc_cxo, + .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_pll_ops, }, }; @@ -123,26 +148,22 @@ static struct clk_regmap pll14_vote = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "pll14_vote", - .parent_names = (const char *[]){ "pll14" }, + .parent_hws = (const struct clk_hw*[]) { + &pll14.clkr.hw, + }, .num_parents = 1, .ops = &clk_pll_vote_ops, }, }; -enum { - P_CXO, - P_PLL8, - P_PLL14, -}; - static const struct parent_map gcc_cxo_pll8_map[] = { { P_CXO, 0 }, { P_PLL8, 3 } }; -static const char * const gcc_cxo_pll8[] = { - "cxo", - "pll8_vote", +static const struct clk_parent_data gcc_cxo_pll8[] = { + { .index = DT_CXO, .name = "cxo_board" }, + { .hw = &pll8_vote.hw }, }; static const struct parent_map gcc_cxo_pll14_map[] = { @@ -150,17 +171,9 @@ static const struct parent_map gcc_cxo_pll14_map[] = { { P_PLL14, 4 } }; -static const char * const gcc_cxo_pll14[] = { - "cxo", - "pll14_vote", -}; - -static const struct parent_map gcc_cxo_map[] = { - { P_CXO, 0 }, -}; - -static const char * const gcc_cxo[] = { - "cxo", +static const struct clk_parent_data gcc_cxo_pll14[] = { + { .index = DT_CXO, .name = "cxo_board" }, + { .hw = &pll14_vote.hw }, }; static struct freq_tbl clk_tbl_gsbi_uart[] = { @@ -206,7 +219,7 @@ static struct clk_rcg gsbi1_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -222,8 +235,8 @@ static struct clk_branch gsbi1_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_uart_clk", - .parent_names = (const char *[]){ - "gsbi1_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi1_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -257,7 +270,7 @@ static struct clk_rcg gsbi2_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -273,8 +286,8 @@ static struct clk_branch gsbi2_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_uart_clk", - .parent_names = (const char *[]){ - "gsbi2_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi2_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -308,7 +321,7 @@ static struct clk_rcg gsbi3_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi3_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -324,8 +337,8 @@ static struct clk_branch gsbi3_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi3_uart_clk", - .parent_names = (const char *[]){ - "gsbi3_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi3_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -359,7 +372,7 @@ static struct clk_rcg gsbi4_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -375,8 +388,8 @@ static struct clk_branch gsbi4_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_uart_clk", - .parent_names = (const char *[]){ - "gsbi4_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi4_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -410,7 +423,7 @@ static struct clk_rcg gsbi5_uart_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -426,8 +439,8 @@ static struct clk_branch gsbi5_uart_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_uart_clk", - .parent_names = (const char *[]){ - "gsbi5_uart_src", + .parent_hws = (const struct clk_hw*[]) { + &gsbi5_uart_src.clkr.hw, }, .num_parents = 1, .ops = &clk_branch_ops, @@ -473,7 +486,7 @@ static struct clk_rcg gsbi1_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -489,7 +502,9 @@ static struct clk_branch gsbi1_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi1_qup_clk", - .parent_names = (const char *[]){ "gsbi1_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi1_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -522,7 +537,7 @@ static struct clk_rcg gsbi2_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -538,7 +553,9 @@ static struct clk_branch gsbi2_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi2_qup_clk", - .parent_names = (const char *[]){ "gsbi2_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi2_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -571,7 +588,7 @@ static struct clk_rcg gsbi3_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi3_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -587,7 +604,9 @@ static struct clk_branch gsbi3_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi3_qup_clk", - .parent_names = (const char *[]){ "gsbi3_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi3_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -620,7 +639,7 @@ static struct clk_rcg gsbi4_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -636,7 +655,9 @@ static struct clk_branch gsbi4_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi4_qup_clk", - .parent_names = (const char *[]){ "gsbi4_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi4_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -669,7 +690,7 @@ static struct clk_rcg gsbi5_qup_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -685,7 +706,9 @@ static struct clk_branch gsbi5_qup_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gsbi5_qup_clk", - .parent_names = (const char *[]){ "gsbi5_qup_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gsbi5_qup_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -724,7 +747,7 @@ static struct clk_rcg gp0_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp0_src", - .parent_names = gcc_cxo, + .parent_data = gcc_cxo, .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_PARENT_GATE, @@ -740,7 +763,9 @@ static struct clk_branch gp0_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp0_clk", - .parent_names = (const char *[]){ "gp0_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gp0_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -773,7 +798,7 @@ static struct clk_rcg gp1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp1_src", - .parent_names = gcc_cxo, + .parent_data = gcc_cxo, .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -789,7 +814,9 @@ static struct clk_branch gp1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp1_clk", - .parent_names = (const char *[]){ "gp1_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gp1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -822,7 +849,7 @@ static struct clk_rcg gp2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "gp2_src", - .parent_names = gcc_cxo, + .parent_data = gcc_cxo, .num_parents = ARRAY_SIZE(gcc_cxo), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -838,7 +865,9 @@ static struct clk_branch gp2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "gp2_clk", - .parent_names = (const char *[]){ "gp2_src" }, + .parent_hws = (const struct clk_hw*[]) { + &gp2_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -874,7 +903,7 @@ static struct clk_rcg prng_src = { .clkr = { .hw.init = &(struct clk_init_data){ .name = "prng_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, @@ -890,7 +919,9 @@ static struct clk_branch prng_clk = { .enable_mask = BIT(10), .hw.init = &(struct clk_init_data){ .name = "prng_clk", - .parent_names = (const char *[]){ "prng_src" }, + .parent_hws = (const struct clk_hw*[]) { + &prng_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, }, @@ -936,7 +967,7 @@ static struct clk_rcg sdc1_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc1_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, @@ -951,7 +982,9 @@ static struct clk_branch sdc1_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc1_clk", - .parent_names = (const char *[]){ "sdc1_src" }, + .parent_hws = (const struct clk_hw*[]) { + &sdc1_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -984,7 +1017,7 @@ static struct clk_rcg sdc2_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "sdc2_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, }, @@ -999,7 +1032,9 @@ static struct clk_branch sdc2_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "sdc2_clk", - .parent_names = (const char *[]){ "sdc2_src" }, + .parent_hws = (const struct clk_hw*[]) { + &sdc2_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1037,7 +1072,7 @@ static struct clk_rcg usb_hs1_xcvr_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1053,7 +1088,9 @@ static struct clk_branch usb_hs1_xcvr_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_xcvr_clk", - .parent_names = (const char *[]){ "usb_hs1_xcvr_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hs1_xcvr_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1086,7 +1123,7 @@ static struct clk_rcg usb_hsic_xcvr_fs_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hsic_xcvr_fs_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1102,8 +1139,9 @@ static struct clk_branch usb_hsic_xcvr_fs_clk = { .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ .name = "usb_hsic_xcvr_fs_clk", - .parent_names = - (const char *[]){ "usb_hsic_xcvr_fs_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hsic_xcvr_fs_src.clkr.hw, + }, .num_parents = 1, .ops = &clk_branch_ops, .flags = CLK_SET_RATE_PARENT, @@ -1141,7 +1179,7 @@ static struct clk_rcg usb_hs1_system_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hs1_system_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1156,8 +1194,9 @@ static struct clk_branch usb_hs1_system_clk = { .enable_reg = 0x36a4, .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ - .parent_names = - (const char *[]){ "usb_hs1_system_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hs1_system_src.clkr.hw, + }, .num_parents = 1, .name = "usb_hs1_system_clk", .ops = &clk_branch_ops, @@ -1196,7 +1235,7 @@ static struct clk_rcg usb_hsic_system_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hsic_system_src", - .parent_names = gcc_cxo_pll8, + .parent_data = gcc_cxo_pll8, .num_parents = ARRAY_SIZE(gcc_cxo_pll8), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1211,8 +1250,9 @@ static struct clk_branch usb_hsic_system_clk = { .enable_reg = 0x2b58, .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ - .parent_names = - (const char *[]){ "usb_hsic_system_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hsic_system_src.clkr.hw, + }, .num_parents = 1, .name = "usb_hsic_system_clk", .ops = &clk_branch_ops, @@ -1251,7 +1291,7 @@ static struct clk_rcg usb_hsic_hsic_src = { .enable_mask = BIT(11), .hw.init = &(struct clk_init_data){ .name = "usb_hsic_hsic_src", - .parent_names = gcc_cxo_pll14, + .parent_data = gcc_cxo_pll14, .num_parents = ARRAY_SIZE(gcc_cxo_pll14), .ops = &clk_rcg_ops, .flags = CLK_SET_RATE_GATE, @@ -1265,7 +1305,9 @@ static struct clk_branch usb_hsic_hsic_clk = { .enable_reg = 0x2b50, .enable_mask = BIT(9), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "usb_hsic_hsic_src" }, + .parent_hws = (const struct clk_hw*[]) { + &usb_hsic_hsic_src.clkr.hw, + }, .num_parents = 1, .name = "usb_hsic_hsic_clk", .ops = &clk_branch_ops, @@ -1281,8 +1323,8 @@ static struct clk_branch usb_hsic_hsio_cal_clk = { .enable_reg = 0x2b48, .enable_mask = BIT(0), .hw.init = &(struct clk_init_data){ - .parent_names = (const char *[]){ "cxo" }, - .num_parents = 1, + .parent_data = gcc_cxo, + .num_parents = ARRAY_SIZE(gcc_cxo), .name = "usb_hsic_hsio_cal_clk", .ops = &clk_branch_ops, }, From patchwork Fri May 12 00:32:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 681393 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 568CFC7EE26 for ; Fri, 12 May 2023 00:32:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239689AbjELAcq (ORCPT ); Thu, 11 May 2023 20:32:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43646 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239662AbjELAco (ORCPT ); Thu, 11 May 2023 20:32:44 -0400 Received: from mail-lf1-x134.google.com (mail-lf1-x134.google.com [IPv6:2a00:1450:4864:20::134]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7FCE86A48 for ; Thu, 11 May 2023 17:32:39 -0700 (PDT) Received: by mail-lf1-x134.google.com with SMTP id 2adb3069b0e04-4eed764a10cso10421189e87.0 for ; Thu, 11 May 2023 17:32:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683851559; x=1686443559; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=UhWJCvsiOM+PbnYgsNzdrZ31BrHJ3YrqzSWfh68CWBg=; b=oOICufZb/myAzXdjpGcjdkexRD/RJ1hRY4YbUWRzEMTKb4kSvExw32iKAcypLd5Z0F qvCwoszG9WDS2/Sdq0lbfvAmnyHrURe/3xCvpDUQSAV0Iuwbm92EL1qpHshPJIZDoKcX /jrMTQy7ek5A5pK+N5+pC74JV9en3XqpTZR0GO9Nm5S88CrGwbSlKdA1UUI/PR0xMuKw yKGq99PmBGwwdORg+0fE+63msegSXhZ4Buu3Rg7i2ar4EKrGtLRMkBGLk9oYI0/IhZR9 qJLhyFv2AFH8HqD4/GBejXs9aRMFZEopWVOZGH/BkmyOmRk7R8doCthrupAYd4zvYl4d oA0A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683851559; x=1686443559; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=UhWJCvsiOM+PbnYgsNzdrZ31BrHJ3YrqzSWfh68CWBg=; b=WDaaioohFQ0fs+bHNvIXRfAYkEsVN7KenUNXj6YnMxCgm6HK0JVZxO1xamUsfczLF4 tOKIy0fwtfu/ftuTx3+nzK4WfFn7c8NglQ6tVjEpipdLTxITUToQzPlay9VZocTeCm8g E1G2BrEngml2As69tak/yDYW/mBC6ih6CWS/VM/VJHN79GlYFU9aT8wR/sDbU1NPPcy8 1rHt+nsb+zVLaoo5Nx6Cvc5X1JZ9UGNanhqE61rFKMkzHRW0sYoKqHSAg9dW2xUuvbtj /ewoV3TPfy+p2zYAJC6kY+8pCV7y6YA7+AMkS8/kh9vmN1ukMuUuUfTMfFR9ouH4yfnC ucgw== X-Gm-Message-State: AC+VfDyVT5YK+7r49Mfa7NJ1tyAM/i56ocW5LK+MsRyLF/9u9B/w07xI TyIyoofGP5ZQdA5wVDRrVV6iAA== X-Google-Smtp-Source: ACHHUZ7i+WdERWxL6xNwlrYNpnpFYdyBYvMlgqFqW6qoDXPmWogyM+3W3y6F+wboGLBqDn5SwAL8gQ== X-Received: by 2002:ac2:511e:0:b0:4eb:c4e:bd87 with SMTP id q30-20020ac2511e000000b004eb0c4ebd87mr3211134lfb.58.1683851558945; Thu, 11 May 2023 17:32:38 -0700 (PDT) Received: from umbar.unikie.fi ([192.130.178.91]) by smtp.gmail.com with ESMTPSA id i7-20020a056512006700b004f13cd61ebbsm1282708lfo.175.2023.05.11.17.32.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 11 May 2023 17:32:38 -0700 (PDT) From: Dmitry Baryshkov To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, Neil Armstrong Subject: [PATCH v2 10/10] ARM: dts: qcom-mdm9615: specify gcc clocks Date: Fri, 12 May 2023 03:32:30 +0300 Message-Id: <20230512003230.3043284-11-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230512003230.3043284-1-dmitry.baryshkov@linaro.org> References: <20230512003230.3043284-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Fully specify the clocks used by the GCC on the mdm9615 platform. Reviewed-by: Neil Armstrong Signed-off-by: Dmitry Baryshkov --- arch/arm/boot/dts/qcom-mdm9615.dtsi | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm/boot/dts/qcom-mdm9615.dtsi b/arch/arm/boot/dts/qcom-mdm9615.dtsi index 556abe90cf5b..fc4f52f9e9f7 100644 --- a/arch/arm/boot/dts/qcom-mdm9615.dtsi +++ b/arch/arm/boot/dts/qcom-mdm9615.dtsi @@ -10,6 +10,7 @@ #include #include +#include #include #include #include @@ -106,6 +107,8 @@ gcc: clock-controller@900000 { #power-domain-cells = <1>; #reset-cells = <1>; reg = <0x900000 0x4000>; + clocks = <&cxo_board>, + <&lcc PLL4>; }; lcc: clock-controller@28000000 {