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Thu, 11 May 2023 06:21:15 -0700 Received: from rnnvmail204.nvidia.com (10.129.68.6) by rnnvmail204.nvidia.com (10.129.68.6) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.37; Thu, 11 May 2023 06:21:15 -0700 Received: from 44189d9-lcedt.nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.6) with Microsoft SMTP Server id 15.2.986.37 via Frontend Transport; Thu, 11 May 2023 06:21:12 -0700 From: Peter De Schrijver To: Peter De Schrijver , Thierry Reding , Jonathan Hunter CC: Jassi Brar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Joe Perches , , , , , "Thierry Reding" Subject: [PATCH v4 1/6] dt-bindings: mailbox: tegra: Document Tegra264 HSP Date: Thu, 11 May 2023 16:20:44 +0300 Message-ID: <20230511132048.1122075-2-pdeschrijver@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511132048.1122075-1-pdeschrijver@nvidia.com> References: <20230511132048.1122075-1-pdeschrijver@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT059:EE_|DM4PR12MB5277:EE_ X-MS-Office365-Filtering-Correlation-Id: b20d041e-59c0-4710-6e8e-08db5222a174 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2023 13:21:29.2622 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b20d041e-59c0-4710-6e8e-08db5222a174 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT059.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5277 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add the compatible string for the HSP block found on the Tegra264 SoC. The HSP block in Tegra264 is not register compatible with the one in Tegra194 or Tegra234 hence there is no fallback compatibility string. Acked-by: Krzysztof Kozlowski Acked-by: Thierry Reding Signed-off-by: Peter De Schrijver --- .../devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml index a3e87516d637..2d14fc948999 100644 --- a/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml +++ b/Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.yaml @@ -66,6 +66,7 @@ properties: oneOf: - const: nvidia,tegra186-hsp - const: nvidia,tegra194-hsp + - const: nvidia,tegra264-hsp - items: - const: nvidia,tegra234-hsp - const: nvidia,tegra194-hsp From patchwork Thu May 11 13:20:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Peter De Schrijver X-Patchwork-Id: 681423 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 02A97C7EE23 for ; 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Thu, 11 May 2023 06:21:40 -0700 From: Peter De Schrijver To: Peter De Schrijver , , CC: , , , , , , Subject: [PATCH v4 4/6] dt-bindings: Add support for DRAM MRQ GSCs Date: Thu, 11 May 2023 16:20:49 +0300 Message-ID: <20230511132048.1122075-5-pdeschrijver@nvidia.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230511132048.1122075-1-pdeschrijver@nvidia.com> References: <20230511132048.1122075-1-pdeschrijver@nvidia.com> MIME-Version: 1.0 X-NVConfidentiality: public X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DM6NAM11FT058:EE_|MW3PR12MB4473:EE_ X-MS-Office365-Filtering-Correlation-Id: 3aab27a9-5eb5-4a26-0d5a-08db5222b1c6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: n2Nd3yjYapLeojixZTnaAcQhI1/cyt28hWQWCLlBOLTc0cdQ5Ljf/53j3k0DxgbgvsFtVHoajfjL8RYt5rhe3uqGnyCo5qkSduRINGPTq2gPk1AZ6kxz1GfP9uzUQLXUytW4iss4AvaAe4EojUUFcEawJbJtUn5XhiuTDbh1sdWW0E5GObOoBaR09axjJh3kY/xYdXoaoaiDuuu/+VhMVQXfXMopzey+6S2G2lVyk/EGqf3n1bPfQrox/9PxuZqBohcG5kmKF8BKLPXDE66lMDfmHDfY7FPoQ5sO/S+0mpI/t3Whz535twH8TJMp0bkFls+9k8KVRSM2/eqiGTJRWQAhroDdVXj5yqKSTstZXKvXJdLWRmlW5/YQs7b5CjfWZD6Xk6vR+InOzoTHx+ukNDHk6vw8P5z83W2qbY8c4u6bVmR+8ye4Hz5T565J7YmCPcmScDEiN6CJHuBJQpKwUX+JqZLQp6w6JPtMxi5YXJww47QEMo4lmAyBIZ/3RMvVK2+zX4ltEvqZgtphmQVri31SLe/a0wP1GEK2qdxr/g+7vdWGXTOpqGUJtwmKG2/c0q5BQ23kn+f5o01opsS+jU8Li8GiQZYWB3cuGMj68wtiLfKRLSNg2NAzkIqbbAKuqD6HBazXZBIKbKJ0xJ6bvm5nhzwoO17XXS1No9jXAwDBgh35rWF7gFEHuZNc3sdy6KTdKwPhH2IWxYy/ndtXT4jKF+v6cHlWz9veZTFcjxnyb5Q4x5ESHO0N+9iWzHcwwZVQW5lC+7CCeP0TrnI7j5c6VJScx1UVIb/qIFPiytj0cZWeFpbXIBqYK1u20q4H X-Forefront-Antispam-Report: CIP:216.228.117.161; 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Co-developed-by: Stefan Kristiansson Signed-off-by: Stefan Kristiansson Signed-off-by: Peter De Schrijver Reviewed-by: Conor Dooley --- .../nvidia,tegra264-bpmp-shmem.yaml | 47 +++++++++++++++++++ 1 file changed, 47 insertions(+) create mode 100644 Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml diff --git a/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml new file mode 100644 index 000000000000..4087459c01db --- /dev/null +++ b/Documentation/devicetree/bindings/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reserved-memory/nvidia,tegra264-bpmp-shmem.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Tegra CPU-NS - BPMP IPC reserved memory + +maintainers: + - Peter De Schrijver + +description: | + Define a memory region used for communication between CPU-NS and BPMP. + Typically this node is created by the bootloader as the physical address + has to be known to both CPU-NS and BPMP for correct IPC operation. + The memory region is defined using a child node under /reserved-memory. + The sub-node is named shmem@
. + +allOf: + - $ref: reserved-memory.yaml + +properties: + compatible: + const: nvidia,tegra264-bpmp-shmem + + reg: + description: The physical address and size of the shared SDRAM region + +unevaluatedProperties: false + +required: + - compatible + - reg + - no-map + +examples: + - | + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + dram_cpu_bpmp_mail: shmem@f1be0000 { + compatible = "nvidia,tegra264-bpmp-shmem"; + reg = <0x0 0xf1be0000 0x0 0x2000>; + no-map; + }; + }; +... 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DIR:OUT; SFP:1101; X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 May 2023 13:22:05.9494 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 424d933b-8e5e-420a-1087-08db5222b750 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a; Ip=[216.228.117.160]; Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DM6NAM11FT008.eop-nam11.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BL3PR12MB6548 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add memory-region property to the tegra186-bpmp binding to support DRAM MRQ GSCs. Co-developed-by: Stefan Kristiansson Signed-off-by: Stefan Kristiansson Signed-off-by: Peter De Schrijver --- .../firmware/nvidia,tegra186-bpmp.yaml | 37 +++++++++++++++++-- 1 file changed, 34 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml index 833c07f1685c..f3e02c9d090d 100644 --- a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml @@ -57,8 +57,11 @@ description: | "#address-cells" or "#size-cells" property. The shared memory area for the IPC TX and RX between CPU and BPMP are - predefined and work on top of sysram, which is an SRAM inside the - chip. See ".../sram/sram.yaml" for the bindings. + predefined and work on top of either sysram, which is an SRAM inside the + chip, or in normal SDRAM. + See ".../sram/sram.yaml" for the bindings for the SRAM case. + See "../reserved-memory/nvidia,tegra264-bpmp-shmem.yaml" for bindings for + the SDRAM case. properties: compatible: @@ -81,6 +84,11 @@ properties: minItems: 2 maxItems: 2 + memory-region: + description: phandle to reserved memory region used for IPC between + CPU-NS and BPMP. + maxItems: 1 + "#clock-cells": const: 1 @@ -115,10 +123,15 @@ properties: additionalProperties: false +oneOf: + - required: + - memory-region + - required: + - shmem + required: - compatible - mboxes - - shmem - "#clock-cells" - "#power-domain-cells" - "#reset-cells" @@ -184,3 +197,21 @@ examples: #thermal-sensor-cells = <1>; }; }; + + - | + #include + + bpmp { + compatible = "nvidia,tegra186-bpmp"; + interconnects = <&mc TEGRA186_MEMORY_CLIENT_BPMPR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPW &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAR &emc>, + <&mc TEGRA186_MEMORY_CLIENT_BPMPDMAW &emc>; + interconnect-names = "read", "write", "dma-mem", "dma-write"; + mboxes = <&hsp_top1 TEGRA_HSP_MBOX_TYPE_DB + TEGRA_HSP_DB_MASTER_BPMP>; + memory-region = <&dram_cpu_bpmp_mail>; + #clock-cells = <1>; + #power-domain-cells = <1>; + #reset-cells = <1>; + };