From patchwork Tue May 9 22:06:47 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 680598 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BD8D6C7EE23 for ; Tue, 9 May 2023 22:07:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236000AbjEIWHR (ORCPT ); Tue, 9 May 2023 18:07:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235535AbjEIWHP (ORCPT ); Tue, 9 May 2023 18:07:15 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E982C449C for ; Tue, 9 May 2023 15:07:12 -0700 (PDT) Received: from pps.filterd (m0279871.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 349LtiSq019388; Tue, 9 May 2023 22:07:06 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; h=from : date : subject : mime-version : content-type : content-transfer-encoding : message-id : references : in-reply-to : to : cc; s=qcppdkim1; bh=i+ycqDkIhQ+poeNyZiOh84lY9hOlRMVjI908m7BtgZM=; b=PqQ08ECUCXM5JFcQNQiMOIrrp/20PcZmn4ckmPNUOposDZoVEL0mI4PUnvwiTvYj+elJ +kTu1gZik06wlzXHfxdEU6Q2FTs0Dn1K5MxL5GYEdfsXdmM8gdwF41GKWyqZVohFfiEB UK+p8y0fHj/wh9VIMuth8MJF3wFy1ELXeG36GHl6HNXtUPSpQEPpJAyuZSAXeTznqO8V XCH7zy1XwuO7fOCvSs6Z/odpTM3NEpRJobdry6KImtQvITEQX/ydtVmHNbwk7Y19hDip /3a3TrGLy88L8ECYCkMKrHcAbZHqPphl5G3dfGjRLCaalWdmgQGJlBE/DSlDEIqsTAMV Zg== Received: from nasanppmta01.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 3qf785awuw-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 09 May 2023 22:07:05 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 349M747t028191 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 May 2023 22:07:04 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 15:07:04 -0700 From: Jessica Zhang Date: Tue, 9 May 2023 15:06:47 -0700 Subject: [PATCH v7 1/8] drm/display/dsc: Add flatness and initial scale value calculations MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v7-1-df48a2c54421@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683670024; l=1209; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=X1P2dRr1XjWxM2mEJq0Khyu3/P9/NnHWAmw6Bg9zkIU=; b=nw+fV2iHIKtM7UuUuxdRziGsmgSthZvpUreRMJjfSKFhs2IJ/bK7dKCy4rcivTD46orJKqInI vHq9wco/VkIDRvFPZJGqV3yXkc4HMR1C8P3expRgX5mWVlqLovO979B X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: Wvwbeen87OeGc73105BadCzmRlTOtC7o X-Proofpoint-GUID: Wvwbeen87OeGc73105BadCzmRlTOtC7o X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_14,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 phishscore=0 bulkscore=0 adultscore=0 priorityscore=1501 mlxlogscore=999 lowpriorityscore=0 malwarescore=0 mlxscore=0 impostorscore=0 clxscore=1015 spamscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090180 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Add helpers to calculate det_thresh_flatness and initial_scale_value as these calculations are defined within the DSC spec. Signed-off-by: Dmitry Baryshkov Signed-off-by: Jessica Zhang Reviewed-by: Marijn Suijten --- include/drm/display/drm_dsc_helper.h | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h index 0bb0c3afd740..422135a33d65 100644 --- a/include/drm/display/drm_dsc_helper.h +++ b/include/drm/display/drm_dsc_helper.h @@ -25,5 +25,16 @@ void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind); int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); +static inline void drm_dsc_set_initial_scale_value(struct drm_dsc_config *dsc) +{ + dsc->initial_scale_value = 8 * dsc->rc_model_size / + (dsc->rc_model_size - dsc->initial_offset); +} + +static inline int drm_dsc_calculate_flatness_det_thresh(struct drm_dsc_config *dsc) +{ + return 2 << (dsc->bits_per_component - 8); +} + #endif /* _DRM_DSC_HELPER_H_ */ From patchwork Tue May 9 22:06:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 680250 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B654AC7EE23 for ; Tue, 9 May 2023 22:07:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235081AbjEIWHV (ORCPT ); Tue, 9 May 2023 18:07:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234757AbjEIWHQ (ORCPT ); Tue, 9 May 2023 18:07:16 -0400 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8817646A2 for ; Tue, 9 May 2023 15:07:13 -0700 (PDT) Received: from pps.filterd (m0279865.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 349LSQjX013595; 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Tue, 9 May 2023 22:07:05 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 15:07:04 -0700 From: Jessica Zhang Date: Tue, 9 May 2023 15:06:48 -0700 Subject: [PATCH v7 2/8] drm/display/dsc: add helper to set semi-const parameters MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v7-2-df48a2c54421@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683670024; l=2616; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=vpqYM+/fP6kF/+TIF4Ds141h6njAEMMJ6yc7HHnoGas=; b=QNoA+Ewo5xyogieT7Vo5YrDFG4J+B1JNuFbH8sNl1uCs7pNlGmZHOWucNlrF5jydxEqSmpyr/ 4+OcPLKMWb3AZFKoWqXK68t3usphh7rcc6iRY9NfcPr0EvPXS9w9Xyu X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: UYcxzOGx7kmwx9snpDU_5sQwJruwJ96w X-Proofpoint-GUID: UYcxzOGx7kmwx9snpDU_5sQwJruwJ96w X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_14,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxlogscore=999 phishscore=0 spamscore=0 suspectscore=0 clxscore=1015 impostorscore=0 bulkscore=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 malwarescore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090180 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Dmitry Baryshkov Add a helper setting config values which are typically constant across operating modes (table E-4 of the standard) and mux_word_size (which is a const according to 3.5.2). Signed-off-by: Dmitry Baryshkov Signed-off-by: Jessica Zhang Reviewed-by: Marijn Suijten --- drivers/gpu/drm/display/drm_dsc_helper.c | 22 ++++++++++++++++++++++ include/drm/display/drm_dsc_helper.h | 1 + 2 files changed, 23 insertions(+) diff --git a/drivers/gpu/drm/display/drm_dsc_helper.c b/drivers/gpu/drm/display/drm_dsc_helper.c index 65e810a54257..b9c4e10ced41 100644 --- a/drivers/gpu/drm/display/drm_dsc_helper.c +++ b/drivers/gpu/drm/display/drm_dsc_helper.c @@ -270,6 +270,28 @@ void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload, } EXPORT_SYMBOL(drm_dsc_pps_payload_pack); +/** + * drm_dsc_set_const_params() - Set DSC parameters considered typically + * constant across operation modes + * + * @vdsc_cfg: + * DSC Configuration data partially filled by driver + */ +void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg) +{ + if (!vdsc_cfg->rc_model_size) + vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; + vdsc_cfg->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST; + vdsc_cfg->rc_tgt_offset_high = DSC_RC_TGT_OFFSET_HI_CONST; + vdsc_cfg->rc_tgt_offset_low = DSC_RC_TGT_OFFSET_LO_CONST; + + if (vdsc_cfg->bits_per_component <= 10) + vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; + else + vdsc_cfg->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; +} +EXPORT_SYMBOL(drm_dsc_set_const_params); + /* From DSC_v1.11 spec, rc_parameter_Set syntax element typically constant */ static const u16 drm_dsc_rc_buf_thresh[] = { 896, 1792, 2688, 3584, 4480, 5376, 6272, 6720, 7168, 7616, diff --git a/include/drm/display/drm_dsc_helper.h b/include/drm/display/drm_dsc_helper.h index 422135a33d65..bfa7f3acafcb 100644 --- a/include/drm/display/drm_dsc_helper.h +++ b/include/drm/display/drm_dsc_helper.h @@ -21,6 +21,7 @@ void drm_dsc_dp_pps_header_init(struct dp_sdp_header *pps_header); int drm_dsc_dp_rc_buffer_size(u8 rc_buffer_block_size, u8 rc_buffer_size); void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_sdp, const struct drm_dsc_config *dsc_cfg); +void drm_dsc_set_const_params(struct drm_dsc_config *vdsc_cfg); void drm_dsc_set_rc_buf_thresh(struct drm_dsc_config *vdsc_cfg); int drm_dsc_setup_rc_params(struct drm_dsc_config *vdsc_cfg, enum drm_dsc_params_kind kind); int drm_dsc_compute_rc_parameters(struct drm_dsc_config *vdsc_cfg); From patchwork Tue May 9 22:06:49 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 680596 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2E947C77B7C for ; Tue, 9 May 2023 22:07:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235697AbjEIWHV (ORCPT ); Tue, 9 May 2023 18:07:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51132 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235789AbjEIWHQ (ORCPT ); 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Tue, 09 May 2023 22:07:06 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA01.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 349M75bh028201 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 May 2023 22:07:05 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 15:07:05 -0700 From: Jessica Zhang Date: Tue, 9 May 2023 15:06:49 -0700 Subject: [PATCH v7 3/8] drm/msm/dsi: use DRM DSC helpers for DSC setup MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v7-3-df48a2c54421@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683670024; l=3480; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=KqpQapa0Gh5Z1++V/iVMGw9qB4lbgoEXu6JSvzDdD/4=; b=tREo3TerxLiy3UmdVWaV2tlzAMeykzPGvBoUjY6zPtHVb+rMA2K0T4wdouj0EHRNUrG/pjCMN bV154pvtOYzAkC0R07HS08Hgic7J2UNsaU5do2/2scpS0GpIkQIzQ9t X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: slKWZXU1SkehkOhecGRWoodVPFftpIO7 X-Proofpoint-ORIG-GUID: slKWZXU1SkehkOhecGRWoodVPFftpIO7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_14,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 priorityscore=1501 mlxscore=0 mlxlogscore=999 bulkscore=0 lowpriorityscore=0 malwarescore=0 clxscore=1015 impostorscore=0 adultscore=0 phishscore=0 suspectscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090180 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org From: Dmitry Baryshkov Use new DRM DSC helpers to setup DSI DSC configuration. The initial_scale_value needs to be adjusted according to the standard, but this is a separate change. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/dsi/dsi_host.c | 61 +++++--------------------------------- 1 file changed, 8 insertions(+), 53 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 961689a255c4..74d38f90398a 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -1731,28 +1731,9 @@ static int dsi_host_parse_lane_data(struct msm_dsi_host *msm_host, return -EINVAL; } -static u32 dsi_dsc_rc_buf_thresh[DSC_NUM_BUF_RANGES - 1] = { - 0x0e, 0x1c, 0x2a, 0x38, 0x46, 0x54, 0x62, - 0x69, 0x70, 0x77, 0x79, 0x7b, 0x7d, 0x7e -}; - -/* only 8bpc, 8bpp added */ -static char min_qp[DSC_NUM_BUF_RANGES] = { - 0, 0, 1, 1, 3, 3, 3, 3, 3, 3, 5, 5, 5, 7, 13 -}; - -static char max_qp[DSC_NUM_BUF_RANGES] = { - 4, 4, 5, 6, 7, 7, 7, 8, 9, 10, 11, 12, 13, 13, 15 -}; - -static char bpg_offset[DSC_NUM_BUF_RANGES] = { - 2, 0, 0, -2, -4, -6, -8, -8, -8, -10, -10, -12, -12, -12, -12 -}; - static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc_config *dsc) { - int i; - u16 bpp = dsc->bits_per_pixel >> 4; + int ret; if (dsc->bits_per_pixel & 0xf) { DRM_DEV_ERROR(&msm_host->pdev->dev, "DSI does not support fractional bits_per_pixel\n"); @@ -1764,49 +1745,23 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc return -EOPNOTSUPP; } - dsc->rc_model_size = 8192; - dsc->first_line_bpg_offset = 12; - dsc->rc_edge_factor = 6; - dsc->rc_tgt_offset_high = 3; - dsc->rc_tgt_offset_low = 3; dsc->simple_422 = 0; dsc->convert_rgb = 1; dsc->vbr_enable = 0; - /* handle only bpp = bpc = 8 */ - for (i = 0; i < DSC_NUM_BUF_RANGES - 1 ; i++) - dsc->rc_buf_thresh[i] = dsi_dsc_rc_buf_thresh[i]; + drm_dsc_set_const_params(dsc); + drm_dsc_set_rc_buf_thresh(dsc); - for (i = 0; i < DSC_NUM_BUF_RANGES; i++) { - dsc->rc_range_params[i].range_min_qp = min_qp[i]; - dsc->rc_range_params[i].range_max_qp = max_qp[i]; - /* - * Range BPG Offset contains two's-complement signed values that fill - * 8 bits, yet the registers and DCS PPS field are only 6 bits wide. - */ - dsc->rc_range_params[i].range_bpg_offset = bpg_offset[i] & DSC_RANGE_BPG_OFFSET_MASK; + /* handle only bpp = bpc = 8, pre-SCR panels */ + ret = drm_dsc_setup_rc_params(dsc, DRM_DSC_1_1_PRE_SCR); + if (ret) { + DRM_DEV_ERROR(&msm_host->pdev->dev, "could not find DSC RC parameters\n"); + return ret; } - dsc->initial_offset = 6144; /* Not bpp 12 */ - if (bpp != 8) - dsc->initial_offset = 2048; /* bpp = 12 */ - - if (dsc->bits_per_component <= 10) - dsc->mux_word_size = DSC_MUX_WORD_SIZE_8_10_BPC; - else - dsc->mux_word_size = DSC_MUX_WORD_SIZE_12_BPC; - - dsc->initial_xmit_delay = 512; dsc->initial_scale_value = 32; - dsc->first_line_bpg_offset = 12; dsc->line_buf_depth = dsc->bits_per_component + 1; - /* bpc 8 */ - dsc->flatness_min_qp = 3; - dsc->flatness_max_qp = 12; - dsc->rc_quant_incr_limit0 = 11; - dsc->rc_quant_incr_limit1 = 11; - return drm_dsc_compute_rc_parameters(dsc); } From patchwork Tue May 9 22:06:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 680252 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8802BC7EE2E for ; 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Tue, 9 May 2023 15:07:05 -0700 From: Jessica Zhang Date: Tue, 9 May 2023 15:06:50 -0700 Subject: [PATCH v7 4/8] drm/msm: Add MSM-specific DSC helper methods MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v7-4-df48a2c54421@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683670024; l=4322; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=LjpRl9BBvVaGeoCbBqLQVNYdI1AAL46fkeej5bCyeOw=; b=1iVngOj6w+2qY4VSf6BwmJWP31EOM9WVoCUiy/AVFnISuQgFiCmTFnAea0Pji/oGSNZikxsKT nPG0A4QQjibAPWZpoMVa/Kp53+6gBd5HshklkMM5zpo+zTLXYBQmBz0 X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: 0aR9tz0Sk1RmBUg9LtQBbhYldft8oD5t X-Proofpoint-ORIG-GUID: 0aR9tz0Sk1RmBUg9LtQBbhYldft8oD5t X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_14,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 malwarescore=0 suspectscore=0 adultscore=0 mlxlogscore=526 lowpriorityscore=0 phishscore=0 impostorscore=0 spamscore=0 clxscore=1015 bulkscore=0 priorityscore=1501 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090180 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Introduce MSM-specific DSC helper methods, as some calculations are common between DP and DSC. Reviewed-by: Dmitry Baryshkov Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/Makefile | 1 + drivers/gpu/drm/msm/msm_dsc_helper.c | 26 ++++++++++++++ drivers/gpu/drm/msm/msm_dsc_helper.h | 69 ++++++++++++++++++++++++++++++++++++ 3 files changed, 96 insertions(+) diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index 7274c41228ed..b814fc80e2d5 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -94,6 +94,7 @@ msm-y += \ msm_atomic_tracepoints.o \ msm_debugfs.o \ msm_drv.o \ + msm_dsc_helper.o \ msm_fb.o \ msm_fence.o \ msm_gem.o \ diff --git a/drivers/gpu/drm/msm/msm_dsc_helper.c b/drivers/gpu/drm/msm/msm_dsc_helper.c new file mode 100644 index 000000000000..29feb3e3b5a4 --- /dev/null +++ b/drivers/gpu/drm/msm/msm_dsc_helper.c @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved + */ + +#include +#include + +#include "msm_dsc_helper.h" + +s64 msm_dsc_get_bytes_per_soft_slice(struct drm_dsc_config *dsc) +{ + return drm_fixp_from_fraction(dsc->slice_width * msm_dsc_get_bpp_int(dsc), 8); +} + +u32 msm_dsc_get_bytes_per_intf(struct drm_dsc_config *dsc, int intf_width) +{ + u32 bytes_per_soft_slice; + s64 bytes_per_soft_slice_fp; + int slice_per_intf = msm_dsc_get_slice_per_intf(dsc, intf_width); + + bytes_per_soft_slice_fp = msm_dsc_get_bytes_per_soft_slice(dsc); + bytes_per_soft_slice = drm_fixp2int_ceil(bytes_per_soft_slice_fp); + + return bytes_per_soft_slice * slice_per_intf; +} diff --git a/drivers/gpu/drm/msm/msm_dsc_helper.h b/drivers/gpu/drm/msm/msm_dsc_helper.h new file mode 100644 index 000000000000..38f3651d0b79 --- /dev/null +++ b/drivers/gpu/drm/msm/msm_dsc_helper.h @@ -0,0 +1,69 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2023 Qualcomm Innovation Center, Inc. All rights reserved + */ + +#ifndef MSM_DSC_HELPER_H_ +#define MSM_DSC_HELPER_H_ + +#include +#include +#include + +/* + * Helper methods for MSM specific DSC calculations that are common between timing engine, + * DSI, and DP. + */ + +/** + * msm_dsc_get_bpp_int - get bits per pixel integer value + * @dsc: Pointer to drm dsc config struct + * Returns: BPP integer value + */ +static inline int msm_dsc_get_bpp_int(struct drm_dsc_config *dsc) +{ + WARN_ON_ONCE(dsc->bits_per_pixel & 0xf); + return dsc->bits_per_pixel >> 4; +} + +/** + * msm_dsc_get_slice_per_intf - get number of slices per interface + * @dsc: Pointer to drm dsc config struct + * @intf_width: interface width + * Returns: Integer representing the slice per interface + */ +static inline int msm_dsc_get_slice_per_intf(struct drm_dsc_config *dsc, int intf_width) +{ + return DIV_ROUND_UP(intf_width, dsc->slice_width); +} + +/** + * msm_dsc_get_bytes_per_line - Calculate bytes per line + * @dsc: Pointer to drm dsc config struct + * Returns: Integer value representing pclk per interface + * + * Note: This value will then be passed along to DSI and DP for some more + * calculations. This is because DSI and DP divide the pclk_per_intf value + * by different values depending on if widebus is enabled. + */ +static inline int msm_dsc_get_bytes_per_line(struct drm_dsc_config *dsc) +{ + return DIV_ROUND_UP(dsc->slice_width * dsc->slice_count * msm_dsc_get_bpp_int(dsc), 8); +} + +/** + * msm_dsc_get_bytes_per_soft_slice - get size of each soft slice for dsc + * @dsc: Pointer to drm dsc config struct + * Returns: s31.32 fixed point value representing bytes per soft slice + */ +s64 msm_dsc_get_bytes_per_soft_slice(struct drm_dsc_config *dsc); + +/** + * msm_dsc_get_bytes_per_intf - get total bytes per interface + * @dsc: Pointer to drm dsc config struct + * @intf_width: interface width + * Returns: u32 value representing bytes per interface + */ +u32 msm_dsc_get_bytes_per_intf(struct drm_dsc_config *dsc, int intf_width); + +#endif /* MSM_DSC_HELPER_H_ */ From patchwork Tue May 9 22:06:51 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 680254 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 86746C7EE26 for ; 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Tue, 9 May 2023 15:07:05 -0700 From: Jessica Zhang Date: Tue, 9 May 2023 15:06:51 -0700 Subject: [PATCH v7 5/8] drm/msm/dpu: Use DRM DSC helper for det_thresh_flatness MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v7-5-df48a2c54421@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683670024; l=1426; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=br5LvAp4/2HAZOqgHTP/2qMYu0f3UwcBBShc5n91vak=; b=G2v3T91OL91GFFh0QC5KfQRsM0KNQiF4y68PaR07f1CHKB19n6F/GGid6P0I4vP63G7qxtDWs itj5RiNtBUjCDsMvRkN4KZvmXTAiYDv/B8ykBeA2M/hGW40L5jpLyVC X-Developer-Key: i=quic_jesszhan@quicinc.com; a=ed25519; pk=gAUCgHZ6wTJOzQa3U0GfeCDH7iZLlqIEPo4rrjfDpWE= X-Originating-IP: [10.80.80.8] X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nasanex01b.na.qualcomm.com (10.46.141.250) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-ORIG-GUID: T2sNrK-SIAOja4AOpe-d2bwZnUy5gDj7 X-Proofpoint-GUID: T2sNrK-SIAOja4AOpe-d2bwZnUy5gDj7 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-05-09_14,2023-05-05_01,2023-02-09_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 adultscore=0 lowpriorityscore=0 spamscore=0 impostorscore=0 malwarescore=0 suspectscore=0 mlxlogscore=758 mlxscore=0 clxscore=1015 bulkscore=0 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2304280000 definitions=main-2305090180 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The current dpu_hw_dsc calculation for det_thresh_flatness does not match the downstream calculation or the DSC spec. Use the DRM DSC helper for det_thresh_flatness to match downstream implementation and the DSC spec. Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC") Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index 4e1396575e6a..1e11c0fb0545 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -3,6 +3,8 @@ * Copyright (c) 2020-2022, Linaro Limited */ +#include + #include "dpu_kms.h" #include "dpu_hw_catalog.h" #include "dpu_hwio.h" @@ -102,7 +104,7 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, data |= dsc->final_offset; DPU_REG_WRITE(c, DSC_DSC_OFFSET, data); - det_thresh_flatness = 7 + 2 * (dsc->bits_per_component - 8); + det_thresh_flatness = drm_dsc_calculate_flatness_det_thresh(dsc); data = det_thresh_flatness << 10; data |= dsc->flatness_max_qp << 5; data |= dsc->flatness_min_qp; From patchwork Tue May 9 22:06:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 680253 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 569FEC77B7C for ; Tue, 9 May 2023 22:07:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234609AbjEIWHR (ORCPT ); Tue, 9 May 2023 18:07:17 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51122 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230086AbjEIWHP (ORCPT ); Tue, 9 May 2023 18:07:15 -0400 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E94934498 for ; Tue, 9 May 2023 15:07:12 -0700 (PDT) Received: from pps.filterd (m0279873.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 349M6Vma001748; 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Fixes: c110cfd1753e ("drm/msm/disp/dpu1: Add support for DSC") Reviewed-by: Dmitry Baryshkov Reviewed-by: Marijn Suijten Signed-off-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c index 1e11c0fb0545..ddaec05151cd 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c @@ -56,9 +56,10 @@ static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc, if (is_cmd_mode) initial_lines += 1; - slice_last_group_size = 3 - (dsc->slice_width % 3); + slice_last_group_size = (dsc->slice_width + 2) % 3; + data = (initial_lines << 20); - data |= ((slice_last_group_size - 1) << 18); + data |= (slice_last_group_size << 18); /* bpp is 6.4 format, 4 LSBs bits are for fractional part */ data |= (dsc->bits_per_pixel << 8); data |= (dsc->block_pred_enable << 7); From patchwork Tue May 9 22:06:53 2023 Content-Type: text/plain; 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Tue, 9 May 2023 22:07:06 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 15:07:06 -0700 From: Jessica Zhang Date: Tue, 9 May 2023 15:06:53 -0700 Subject: [PATCH v7 7/8] drm/msm/dsi: Use MSM and DRM DSC helper methods MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v7-7-df48a2c54421@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; a=ed25519-sha256; t=1683670024; l=1800; i=quic_jesszhan@quicinc.com; s=20230329; h=from:subject:message-id; bh=+5QwXauqFQHhUPyfb+IAcqZqIt1aa1YNNVtj5JtkFtY=; b=/F6QDWoJaMy3Sun059vQaELAbeVKiieMbprxht93Ty7e5eVW/Z3BHegbiRnQLF0R5wvCbKFzz 3v9C3UEGWeKBvPZaARjLc6T2jl9Lt50IhBJ7hC0OUUaXDbSujzUi6Ab X-Developer-Key: i=quic_jesszhan@quicinc.com; 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Signed-off-by: Jessica Zhang Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/dsi/dsi_host.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 74d38f90398a..508577c596ff 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -28,6 +28,7 @@ #include "dsi.xml.h" #include "sfpb.xml.h" #include "dsi_cfg.h" +#include "msm_dsc_helper.h" #include "msm_kms.h" #include "msm_gem.h" #include "phy/dsi_phy.h" @@ -848,7 +849,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod /* first calculate dsc parameters and then program * compress mode registers */ - slice_per_intf = DIV_ROUND_UP(hdisplay, dsc->slice_width); + slice_per_intf = msm_dsc_get_slice_per_intf(dsc, hdisplay); /* * If slice_count is greater than slice_per_intf @@ -858,7 +859,7 @@ static void dsi_update_dsc_timing(struct msm_dsi_host *msm_host, bool is_cmd_mod if (dsc->slice_count > slice_per_intf) dsc->slice_count = 1; - total_bytes_per_intf = dsc->slice_chunk_size * slice_per_intf; + total_bytes_per_intf = msm_dsc_get_bytes_per_intf(dsc, hdisplay); eol_byte_num = total_bytes_per_intf % 3; pkt_per_line = slice_per_intf / dsc->slice_count; @@ -1759,7 +1760,7 @@ static int dsi_populate_dsc_params(struct msm_dsi_host *msm_host, struct drm_dsc return ret; } - dsc->initial_scale_value = 32; + drm_dsc_set_initial_scale_value(dsc); dsc->line_buf_depth = dsc->bits_per_component + 1; return drm_dsc_compute_rc_parameters(dsc); From patchwork Tue May 9 22:06:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jessica Zhang X-Patchwork-Id: 680251 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 22E65C7EE26 for ; Tue, 9 May 2023 22:07:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235123AbjEIWHU (ORCPT ); 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Tue, 09 May 2023 22:07:07 +0000 Received: from nasanex01b.na.qualcomm.com (nasanex01b.na.qualcomm.com [10.46.141.250]) by NASANPPMTA04.qualcomm.com (8.17.1.5/8.17.1.5) with ESMTPS id 349M77Hf027574 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 9 May 2023 22:07:07 GMT Received: from jesszhan-linux.qualcomm.com (10.80.80.8) by nasanex01b.na.qualcomm.com (10.46.141.250) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.986.42; Tue, 9 May 2023 15:07:06 -0700 From: Jessica Zhang Date: Tue, 9 May 2023 15:06:54 -0700 Subject: [PATCH v7 8/8] drm/msm/dsi: update hdisplay calculation for dsi_timing_setup MIME-Version: 1.0 Message-ID: <20230329-rfc-msm-dsc-helper-v7-8-df48a2c54421@quicinc.com> References: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> In-Reply-To: <20230329-rfc-msm-dsc-helper-v7-0-df48a2c54421@quicinc.com> To: CC: Marijn Suijten , Konrad Dybcio , Daniel Vetter , Rob Clark , Abhinav Kumar , "Dmitry Baryshkov" , Sean Paul , , , "Jessica Zhang" X-Mailer: b4 0.13-dev-bfdf5 X-Developer-Signature: v=1; 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Thus, use MSM DSC helper to calculate hdisplay for dsi_timing_setup instead of directly using mode->hdisplay. Reviewed-by: Dmitry Baryshkov Signed-off-by: Jessica Zhang Reviewed-by: Marijn Suijten --- drivers/gpu/drm/msm/dsi/dsi_host.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/dsi_host.c index 508577c596ff..d60403372514 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -952,7 +952,7 @@ static void dsi_timing_setup(struct msm_dsi_host *msm_host, bool is_bonded_dsi) * pulse width same */ h_total -= hdisplay; - hdisplay /= 3; + hdisplay = msm_dsc_get_bytes_per_line(msm_host->dsc) / 3; h_total += hdisplay; ha_end = ha_start + hdisplay; }