From patchwork Mon May 8 14:28:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 679998 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 476ACC7EE22 for ; Mon, 8 May 2023 14:29:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233946AbjEHO3e (ORCPT ); Mon, 8 May 2023 10:29:34 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36776 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234557AbjEHO32 (ORCPT ); Mon, 8 May 2023 10:29:28 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3514B49F0 for ; Mon, 8 May 2023 07:29:10 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-64359d9c531so3371269b3a.3 for ; Mon, 08 May 2023 07:29:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556149; x=1686148149; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=m1nY2tFDgGEcA5BPTW/qPM4ksEcua9dIFA1MwwOUg+w=; b=Y4KeKeEH2HyNjQj1MvzsAagGgVRUdpfCpDFHN+2mKM/yIL5V4lC3/r8BWTBVPv8mr8 crG2m3zs5hnPIFNLt92hug/24EbFLZl8MHqF6s0UAd9n57VO1wIMukU5t9t3dDPg2PRO sO9zoJNKGTBkOC3klDG6HaL02odtnyoCMZY6HzIpeP2+t3qrT/fC9nsHjjuQ7NCuBZj+ aq2dtuWODDaoxaCpgUoNZGGP1z628C7yRSBp+4ZUOT0oExNHPCeb8h1cRwyar7P0p+2V wseYx1vo0wkd9RoXyot8Efac9RcekQ3hmC2u3e4HorVZQmu9AI0obr74p9qEtJZc0r2+ fkMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556149; x=1686148149; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=m1nY2tFDgGEcA5BPTW/qPM4ksEcua9dIFA1MwwOUg+w=; b=f7Vu2GmTMtqMivVLJvzRyl/PeIPBAN9DU82rfTdvtHYL76c6Tg8HsySRLQEF86ZFp7 DsbJOkV+O4TNDjSinUAd/8iKUE0DlFipWpxjoGXyrv9dtGlnVaE9V1opaUNVS0Qaa4So aIpFNL7mxWNjyPEkG+5tT3k2yQzLunVDSdXrTeoLvBx/cQ0+m+qZA6YsIXjqQuTVTzfZ k77gWm+qbiML6uuFTFFMdx92hKYTkxjVjhEv1Yg8stgk6hRr7dCH6Kz0/iggFXt8Ecc6 uK79nKR64pX01Dj3ALulA42dUjYPe/C90Auq56H+hLWrkZrUIi/+PSL9XTwJhOrBFJ3V z5bA== X-Gm-Message-State: AC+VfDzQrPaeQx/v+9E9GrIJJHZ87hPuRcr4cpy+O7Hte5+bem+NSpu0 X1gek+QYQB332HNXH4dg5vwOyw== X-Google-Smtp-Source: ACHHUZ7gDrZ3JRghPX//cMrvwquC37PoOqjAFZxHaVQQxUAxuCDyhmWrefaoupApJJIMGX/LlXhLUA== X-Received: by 2002:a05:6a00:1503:b0:643:96e:666b with SMTP id q3-20020a056a00150300b00643096e666bmr13783594pfu.34.1683556149506; Mon, 08 May 2023 07:29:09 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:09 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 02/11] of/irq: Set FWNODE_FLAG_BEST_EFFORT for the interrupt controller DT nodes Date: Mon, 8 May 2023 19:58:33 +0530 Message-Id: <20230508142842.854564-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The RISC-V APLIC interrupt controller driver is a regular platform driver so we need to ensure that it is probed as soon as possible. To achieve this, we mark the interrupt controller device nodes with FWNODE_FLAG_BEST_EFFORT (just like console DT node). Fixes: 8f486cab263c ("driver core: fw_devlink: Allow firmware to mark devices as best effort") Signed-off-by: Anup Patel --- drivers/of/irq.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/of/irq.c b/drivers/of/irq.c index 174900072c18..94e1d9245cff 100644 --- a/drivers/of/irq.c +++ b/drivers/of/irq.c @@ -535,6 +535,16 @@ void __init of_irq_init(const struct of_device_id *matches) INIT_LIST_HEAD(&intc_desc_list); INIT_LIST_HEAD(&intc_parent_list); + /* + * We need interrupt controller platform drivers to work as soon + * as possible so mark the interrupt controller device nodes with + * FWNODE_FLAG_BEST_EFFORT so that fw_delink knows not to delay + * the probe of the interrupt controller device for suppliers + * without drivers. + */ + for_each_node_with_property(np, "interrupt-controller") + np->fwnode.flags |= FWNODE_FLAG_BEST_EFFORT; + for_each_matching_node_and_match(np, matches, &match) { if (!of_property_read_bool(np, "interrupt-controller") || !of_device_is_available(np)) From patchwork Mon May 8 14:28:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 679997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AE73CC7EE22 for ; Mon, 8 May 2023 14:29:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234493AbjEHO3z (ORCPT ); Mon, 8 May 2023 10:29:55 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36774 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234604AbjEHO3h (ORCPT ); Mon, 8 May 2023 10:29:37 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DEE5C7ABF for ; Mon, 8 May 2023 07:29:19 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-643465067d1so3408979b3a.0 for ; Mon, 08 May 2023 07:29:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556159; x=1686148159; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=N59rxkdYZA75SdcQLdoupuBl4MQdly/YxY4hY1fh15A=; b=UQaJc5hgt0zxDb26qFqMa3zhzlc20Btk/7b3pmoyfGVMwuQff0ihQFCpFbr2FLVL+d KM72UcUFTXoxZJaiLbBjX2wq3EEsoQIhxCe2kCzSKDJ8XA07NcfhYewApVvumbXgr/l6 Wdjg62Veayj8efnEif0ynVpiK1rRXTGoitkljHvIGo8OhxjcDL+bxVQSeegZ9k2leDA4 Sy13dFYuDO0CDwwZsAzsts9iPyDX0cnxCOGDfQC1Co4Ff91SHwWUd4Ajms+REbJYZm90 qN879ANhf9KsNTOKQTv9S4iD+xeYJcSJVMq6u9KnCKqrKWYR3jLQY8JaphntOgxbKtml m+Vw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556159; x=1686148159; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N59rxkdYZA75SdcQLdoupuBl4MQdly/YxY4hY1fh15A=; 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Signed-off-by: Anup Patel Reviewed-by: Conor Dooley Acked-by: Krzysztof Kozlowski --- .../interrupt-controller/riscv,imsics.yaml | 172 ++++++++++++++++++ 1 file changed, 172 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml new file mode 100644 index 000000000000..b2e70fc44dd0 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,imsics.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,imsics.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Incoming MSI Controller (IMSIC) + +maintainers: + - Anup Patel + +description: | + The RISC-V advanced interrupt architecture (AIA) defines a per-CPU incoming + MSI controller (IMSIC) for handling MSIs in a RISC-V platform. The RISC-V + AIA specification can be found at https://github.com/riscv/riscv-aia. + + The IMSIC is a per-CPU (or per-HART) device with separate interrupt file + for each privilege level (machine or supervisor). The configuration of + a IMSIC interrupt file is done using AIA CSRs and it also has a 4KB MMIO + space to receive MSIs from devices. Each IMSIC interrupt file supports a + fixed number of interrupt identities (to distinguish MSIs from devices) + which is same for given privilege level across CPUs (or HARTs). + + The device tree of a RISC-V platform will have one IMSIC device tree node + for each privilege level (machine or supervisor) which collectively describe + IMSIC interrupt files at that privilege level across CPUs (or HARTs). + + The arrangement of IMSIC interrupt files in MMIO space of a RISC-V platform + follows a particular scheme defined by the RISC-V AIA specification. A IMSIC + group is a set of IMSIC interrupt files co-located in MMIO space and we can + have multiple IMSIC groups (i.e. clusters, sockets, chiplets, etc) in a + RISC-V platform. The MSI target address of a IMSIC interrupt file at given + privilege level (machine or supervisor) encodes group index, HART index, + and guest index (shown below). + + XLEN-1 > (HART Index MSB) 12 0 + | | | | + ------------------------------------------------------------- + |xxxxxx|Group Index|xxxxxxxxxxx|HART Index|Guest Index| 0 | + ------------------------------------------------------------- + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + - $ref: /schemas/interrupt-controller/msi-controller.yaml# + +properties: + compatible: + items: + - enum: + - qemu,imsics + - const: riscv,imsics + + reg: + minItems: 1 + maxItems: 16384 + description: + Base address of each IMSIC group. + + interrupt-controller: true + + "#interrupt-cells": + const: 0 + + msi-controller: true + + "#msi-cells": + const: 0 + + interrupts-extended: + minItems: 1 + maxItems: 16384 + description: + This property represents the set of CPUs (or HARTs) for which given + device tree node describes the IMSIC interrupt files. Each node pointed + to should be a riscv,cpu-intc node, which has a riscv node (i.e. RISC-V + HART) as parent. + + riscv,num-ids: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 63 + maximum: 2047 + description: + Number of interrupt identities supported by IMSIC interrupt file. + + riscv,num-guest-ids: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 63 + maximum: 2047 + description: + Number of interrupt identities are supported by IMSIC guest interrupt + file. When not specified it is assumed to be same as specified by the + riscv,num-ids property. + + riscv,guest-index-bits: + minimum: 0 + maximum: 7 + default: 0 + description: + Number of guest index bits in the MSI target address. + + riscv,hart-index-bits: + minimum: 0 + maximum: 15 + description: + Number of HART index bits in the MSI target address. When not + specified it is calculated based on the interrupts-extended property. + + riscv,group-index-bits: + minimum: 0 + maximum: 7 + default: 0 + description: + Number of group index bits in the MSI target address. + + riscv,group-index-shift: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 55 + default: 24 + description: + The least significant bit position of the group index bits in the + MSI target address. + +required: + - compatible + - reg + - interrupt-controller + - msi-controller + - "#msi-cells" + - interrupts-extended + - riscv,num-ids + +unevaluatedProperties: false + +examples: + - | + // Example 1 (Machine-level IMSIC files with just one group): + + interrupt-controller@24000000 { + compatible = "qemu,imsics", "riscv,imsics"; + interrupts-extended = <&cpu1_intc 11>, + <&cpu2_intc 11>, + <&cpu3_intc 11>, + <&cpu4_intc 11>; + reg = <0x28000000 0x4000>; + interrupt-controller; + #interrupt-cells = <0>; + msi-controller; + #msi-cells = <0>; + riscv,num-ids = <127>; + }; + + - | + // Example 2 (Supervisor-level IMSIC files with two groups): + + interrupt-controller@28000000 { + compatible = "qemu,imsics", "riscv,imsics"; + interrupts-extended = <&cpu1_intc 9>, + <&cpu2_intc 9>, + <&cpu3_intc 9>, + <&cpu4_intc 9>; + reg = <0x28000000 0x2000>, /* Group0 IMSICs */ + <0x29000000 0x2000>; /* Group1 IMSICs */ + interrupt-controller; + #interrupt-cells = <0>; + msi-controller; + #msi-cells = <0>; + riscv,num-ids = <127>; + riscv,group-index-bits = <1>; + riscv,group-index-shift = <24>; + }; +... From patchwork Mon May 8 14:28:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 679996 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 440B1C77B7F for ; Mon, 8 May 2023 14:30:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234935AbjEHOaL (ORCPT ); Mon, 8 May 2023 10:30:11 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37270 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234909AbjEHO3x (ORCPT ); Mon, 8 May 2023 10:29:53 -0400 Received: from mail-pf1-x436.google.com (mail-pf1-x436.google.com [IPv6:2607:f8b0:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 21E2C7AA4 for ; Mon, 8 May 2023 07:29:30 -0700 (PDT) Received: by mail-pf1-x436.google.com with SMTP id d2e1a72fcca58-64359d9c531so3371480b3a.3 for ; Mon, 08 May 2023 07:29:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556169; x=1686148169; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=WZx8pVyFJqTIpr4BnDr/88VmIIeD0a98LNl1bXs4aCI=; b=dTnj8jF9WIu+jQo5yru3eJjRqiAEHZBZJ/aJ7cgeYj1zF9lv1xflSCfcl+LSKqGaIV jfZ1+t1HwtTt4GwgZN4XIOqbWYNhXDuQf/JKZTk9qPDhdLmaU8lezhkQeblu/H1yu1E1 Cv1IzlK841t90PK+K6bgn9E61JdlrFKX+7uMjSs2uLq/7V3lN2WDOAc3v3Pzwoyzqp7f QnN2moOnjD+ijPu/4+Rjz6CoJ+FC/Gg6vZ2w9ps1LXA1H50BzOFIWUUp2TeV+G3C3cjD w+2EcfAuNkf2HweC4ChcYrYIR7rD9bHgJBlMPvEf31IwarO+gcTz/fKSUPbeyqTAuUBL 2ttA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556169; x=1686148169; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WZx8pVyFJqTIpr4BnDr/88VmIIeD0a98LNl1bXs4aCI=; b=AXzS6sWjNHzjcS0Srg4VAh+gC/ETivmA1nSDYKWfjUb4i/hS90WRtUeUuxRqe+hhZF aVX567pNVFZX4oC4Bnd+/BsIG+iDeDL+1cmTv5TFwEGtb/IVyf4AryYvTqPiuzCBNraA XkxJy1XbWxbePLS7Vz5O3WL9q9yQNRvvf1Prxai7Yq6RtBXcGnLY9RU7zRwsB6Ph+oh2 T0wLGzcx957UIaVafW2Q5/y48nkUlY/jH8BnCNaBzNJCDJJktCS2mNg1LpLXFmmLp9vW auwg7s1ecw3sDh9vht44Kfzr8oiBerSapOL8kYAbN9yEAIJRjRLxSQjm5E/UfIoVx7kT k2+Q== X-Gm-Message-State: AC+VfDx3Y3oplr4Py8Y0EuElc2GtsUnAWGq2LT6z6W6eUjHo4yUw9NpQ rtweORqYYqURn47+sAc8fdp2yg== X-Google-Smtp-Source: ACHHUZ7uHyXdoGyRXbKaY6kklyMIWJI3o768YEmZqRcW81svn5/B1xtVVAkqcXoSxAkeEozUbYGp2A== X-Received: by 2002:a05:6a21:339c:b0:100:2c5c:8e69 with SMTP id yy28-20020a056a21339c00b001002c5c8e69mr5992538pzb.49.1683556168895; Mon, 08 May 2023 07:29:28 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:28 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 06/11] irqchip/riscv-imsic: Add support for PCI MSI irqdomain Date: Mon, 8 May 2023 19:58:37 +0530 Message-Id: <20230508142842.854564-7-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Linux PCI framework requires it's own dedicated MSI irqdomain so let us create PCI MSI irqdomain as child of the IMSIC base irqdomain. Signed-off-by: Anup Patel --- drivers/irqchip/Kconfig | 7 +++++ drivers/irqchip/irq-riscv-imsic.c | 49 +++++++++++++++++++++++++++++++ 2 files changed, 56 insertions(+) diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig index 8ef18be5f37b..d700980372ef 100644 --- a/drivers/irqchip/Kconfig +++ b/drivers/irqchip/Kconfig @@ -550,6 +550,13 @@ config RISCV_IMSIC select IRQ_DOMAIN_HIERARCHY select GENERIC_MSI_IRQ +config RISCV_IMSIC_PCI + bool + depends on RISCV_IMSIC + depends on PCI + depends on PCI_MSI + default RISCV_IMSIC + config EXYNOS_IRQ_COMBINER bool "Samsung Exynos IRQ combiner support" if COMPILE_TEST depends on (ARCH_EXYNOS && ARM) || COMPILE_TEST diff --git a/drivers/irqchip/irq-riscv-imsic.c b/drivers/irqchip/irq-riscv-imsic.c index 971fad638c9f..30247c84a6b0 100644 --- a/drivers/irqchip/irq-riscv-imsic.c +++ b/drivers/irqchip/irq-riscv-imsic.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -81,6 +82,7 @@ struct imsic_priv { /* IRQ domains */ struct irq_domain *base_domain; + struct irq_domain *pci_domain; struct irq_domain *plat_domain; }; @@ -547,6 +549,39 @@ static const struct irq_domain_ops imsic_base_domain_ops = { .free = imsic_irq_domain_free, }; +#ifdef CONFIG_RISCV_IMSIC_PCI + +static void imsic_pci_mask_irq(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void imsic_pci_unmask_irq(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + +static struct irq_chip imsic_pci_irq_chip = { + .name = "RISC-V IMSIC-PCI", + .irq_mask = imsic_pci_mask_irq, + .irq_unmask = imsic_pci_unmask_irq, + .irq_eoi = irq_chip_eoi_parent, +}; + +static struct msi_domain_ops imsic_pci_domain_ops = { +}; + +static struct msi_domain_info imsic_pci_domain_info = { + .flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_PCI_MSIX | MSI_FLAG_MULTI_PCI_MSI), + .ops = &imsic_pci_domain_ops, + .chip = &imsic_pci_irq_chip, +}; + +#endif + static struct irq_chip imsic_plat_irq_chip = { .name = "RISC-V IMSIC-PLAT", }; @@ -571,12 +606,26 @@ static int __init imsic_irq_domains_init(struct fwnode_handle *fwnode) } irq_domain_update_bus_token(imsic->base_domain, DOMAIN_BUS_NEXUS); +#ifdef CONFIG_RISCV_IMSIC_PCI + /* Create PCI MSI domain */ + imsic->pci_domain = pci_msi_create_irq_domain(fwnode, + &imsic_pci_domain_info, + imsic->base_domain); + if (!imsic->pci_domain) { + pr_err("Failed to create IMSIC PCI domain\n"); + irq_domain_remove(imsic->base_domain); + return -ENOMEM; + } +#endif + /* Create Platform MSI domain */ imsic->plat_domain = platform_msi_create_irq_domain(fwnode, &imsic_plat_domain_info, imsic->base_domain); if (!imsic->plat_domain) { pr_err("Failed to create IMSIC platform domain\n"); + if (imsic->pci_domain) + irq_domain_remove(imsic->pci_domain); irq_domain_remove(imsic->base_domain); return -ENOMEM; } From patchwork Mon May 8 14:28:39 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 679995 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 513F1C77B7F for ; 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Mon, 08 May 2023 07:29:39 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:38 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 08/11] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Date: Mon, 8 May 2023 19:58:39 +0530 Message-Id: <20230508142842.854564-9-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org We add DT bindings document for RISC-V advanced platform level interrupt controller (APLIC) defined by the RISC-V advanced interrupt architecture (AIA) specification. Signed-off-by: Anup Patel --- .../interrupt-controller/riscv,aplic.yaml | 162 ++++++++++++++++++ 1 file changed, 162 insertions(+) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml new file mode 100644 index 000000000000..b47a7987b774 --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml @@ -0,0 +1,162 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RISC-V Advanced Platform Level Interrupt Controller (APLIC) + +maintainers: + - Anup Patel + +description: + The RISC-V advanced interrupt architecture (AIA) defines an advanced + platform level interrupt controller (APLIC) for handling wired interrupts + in a RISC-V platform. The RISC-V AIA specification can be found at + https://github.com/riscv/riscv-aia. + + The RISC-V APLIC is implemented as hierarchical APLIC domains where all + interrupt sources connect to the root domain which can further delegate + interrupts to child domains. There is one device tree node for each APLIC + domain. + +allOf: + - $ref: /schemas/interrupt-controller.yaml# + +properties: + compatible: + items: + - enum: + - qemu,aplic + - const: riscv,aplic + + reg: + maxItems: 1 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + interrupts-extended: + minItems: 1 + maxItems: 16384 + description: + Given APLIC domain directly injects external interrupts to a set of + RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc + node, which has a riscv node (i.e. RISC-V HART) as parent. + + msi-parent: + description: + Given APLIC domain forwards wired interrupts as MSIs to a AIA incoming + message signaled interrupt controller (IMSIC). If both "msi-parent" and + "interrupts-extended" properties are present then it means the APLIC + domain supports both MSI mode and Direct mode in HW. In this case, the + APLIC driver has to choose between MSI mode or Direct mode. + + riscv,num-sources: + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + maximum: 1023 + description: + Specifies the number of wired interrupt sources supported by this + APLIC domain. + + riscv,children: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 1024 + items: + maxItems: 1 + description: + A list of child APLIC domains for the given APLIC domain. Each child + APLIC domain is assigned a child index in increasing order, with the + first child APLIC domain assigned child index 0. The APLIC domain child + index is used by firmware to delegate interrupts from the given APLIC + domain to a particular child APLIC domain. + + riscv,delegate: + $ref: /schemas/types.yaml#/definitions/phandle-array + minItems: 1 + maxItems: 1024 + items: + items: + - description: child APLIC domain phandle + - description: first interrupt number of this APLIC domain (inclusive) + - description: last interrupt number of this APLIC domain (inclusive) + description: + A interrupt delegation list where each entry is a triple consisting of + child APLIC domain phandle, first interrupt number of this APLIC domain, + and last interrupt number of this APLIC domain. Firmware must configure + interrupt delegation registers based on interrupt delegation list. + +required: + - compatible + - reg + - interrupt-controller + - "#interrupt-cells" + - riscv,num-sources + +unevaluatedProperties: false + +examples: + - | + // Example 1 (APLIC domains directly injecting interrupt to HARTs): + + interrupt-controller@c000000 { + compatible = "qemu,aplic", "riscv,aplic"; + interrupts-extended = <&cpu1_intc 11>, + <&cpu2_intc 11>, + <&cpu3_intc 11>, + <&cpu4_intc 11>; + reg = <0xc000000 0x4080>; + interrupt-controller; + #interrupt-cells = <2>; + riscv,num-sources = <63>; + riscv,children = <&aplic1>, <&aplic2>; + riscv,delegate = <&aplic1 1 63>; + }; + + aplic1: interrupt-controller@d000000 { + compatible = "qemu,aplic", "riscv,aplic"; + interrupts-extended = <&cpu1_intc 9>, + <&cpu2_intc 9>; + reg = <0xd000000 0x4080>; + interrupt-controller; + #interrupt-cells = <2>; + riscv,num-sources = <63>; + }; + + aplic2: interrupt-controller@e000000 { + compatible = "qemu,aplic", "riscv,aplic"; + interrupts-extended = <&cpu3_intc 9>, + <&cpu4_intc 9>; + reg = <0xe000000 0x4080>; + interrupt-controller; + #interrupt-cells = <2>; + riscv,num-sources = <63>; + }; + + - | + // Example 2 (APLIC domains forwarding interrupts as MSIs): + + interrupt-controller@c000000 { + compatible = "qemu,aplic", "riscv,aplic"; + msi-parent = <&imsic_mlevel>; + reg = <0xc000000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + riscv,num-sources = <63>; + riscv,children = <&aplic3>; + riscv,delegate = <&aplic3 1 63>; + }; + + aplic3: interrupt-controller@d000000 { + compatible = "qemu,aplic", "riscv,aplic"; + msi-parent = <&imsic_slevel>; + reg = <0xd000000 0x4000>; + interrupt-controller; + #interrupt-cells = <2>; + riscv,num-sources = <63>; + }; +... From patchwork Mon May 8 14:28:41 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Anup Patel X-Patchwork-Id: 679994 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 96F9AC7EE22 for ; Mon, 8 May 2023 14:30:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234920AbjEHOap (ORCPT ); Mon, 8 May 2023 10:30:45 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37252 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234901AbjEHOaM (ORCPT ); Mon, 8 May 2023 10:30:12 -0400 Received: from mail-pf1-x42d.google.com (mail-pf1-x42d.google.com [IPv6:2607:f8b0:4864:20::42d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4F7AB5BA7 for ; Mon, 8 May 2023 07:29:49 -0700 (PDT) Received: by mail-pf1-x42d.google.com with SMTP id d2e1a72fcca58-64388cf3263so3208111b3a.3 for ; Mon, 08 May 2023 07:29:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683556189; x=1686148189; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=ib+AURYSmjIxuoqk+PR8Eg/Z3fYq7w+OW68J7DC1sRs=; b=lhf0yTrL5foE3dgkCXYnbKFaPVDfELgWh9Qfu/YV+eeRXTgmNBLamrISJGm/kf8awb /Q+x7COPipzhN8O060faYDbfE9mfR23SP9HjXYhGusmHffrOHXqsmpI1CeuvtIza3iJb D2HJTugPooWWFNeSmHWphhPLl9HTV5glDX0ktJXkQfOxo9GqBoI+XQwkhqqVu2fbXa++ 7IVbVAbG5rwHmJWxdfwxWkg8E8AvJFCGWiFL1GD/XfG5ng5yS3gQtpftU4y0mQXFcrjF WuX4XDgTcmDX0aYWje38GHBLesDKvbasYOydQcOSSX1etOg97JceszynFQC+Wv6vzJdq tXiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683556189; x=1686148189; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=ib+AURYSmjIxuoqk+PR8Eg/Z3fYq7w+OW68J7DC1sRs=; b=isP2QjzqDjgLkYzigTNykr7TGSsRrUJnKHh896XR0fzAetQniyhDgvMEcqhVH8alrF KkQ4/DDnVHDLJ02Bng/fH5DgDAteUGtnIns2EhGuzPFVPQlO1956uH/n3K4rlU2nJFRr ovxqODfXf82k8W76PRTQYfeEwidBQvfFtnZgAY4cBn/UMiLShP9SE5CCsdiy2y99NK/i +Z5MLc1mT6qdNydVqSEy7czFSQ9GghGb0Hi4rWVm5dlVBe2O9AXO8POJqkn0dK0Q7cHS gtr64BJ7JBY/3+w0Q6POk0p8lsOTNECeOhLz1FCVYU3Is3aN5uMzx/YaHaFB9YDVnplq ANmA== X-Gm-Message-State: AC+VfDyhscTUXIrL9zRMollKMi1tHvJOGfKFRuSZCuky/hxvIqKxfXEr DrXzYQ3BDaQHLLP4hDobBlqrug9kYZYmDd00svg= X-Google-Smtp-Source: ACHHUZ70ix2zTrDE9s+rnkB6ZVqKqawiFZ9UB6Fb2s+oNTDZtIBezM4K/5LRvwmXZR9QE5qBhwN0HA== X-Received: by 2002:a05:6a00:b8a:b0:646:663a:9d60 with SMTP id g10-20020a056a000b8a00b00646663a9d60mr2975346pfj.10.1683556188702; Mon, 08 May 2023 07:29:48 -0700 (PDT) Received: from anup-ubuntu-vm.localdomain ([171.76.84.206]) by smtp.gmail.com with ESMTPSA id k3-20020aa790c3000000b0063d46ec5777sm6082pfk.158.2023.05.08.07.29.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 07:29:48 -0700 (PDT) From: Anup Patel To: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Robin Murphy , Joerg Roedel , Will Deacon , Frank Rowand Cc: Atish Patra , Andrew Jones , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, iommu@lists.linux.dev, Anup Patel Subject: [PATCH v3 10/11] RISC-V: Select APLIC and IMSIC drivers Date: Mon, 8 May 2023 19:58:41 +0530 Message-Id: <20230508142842.854564-11-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508142842.854564-1-apatel@ventanamicro.com> References: <20230508142842.854564-1-apatel@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The QEMU virt machine supports AIA emulation and we also have quite a few RISC-V platforms with AIA support under development so let us select APLIC and IMSIC drivers for all RISC-V platforms. Signed-off-by: Anup Patel --- arch/riscv/Kconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 491ecd7d2336..1bc2c7659b7d 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -135,6 +135,8 @@ config RISCV select PCI_DOMAINS_GENERIC if PCI select PCI_MSI if PCI select RISCV_ALTERNATIVE if !XIP_KERNEL + select RISCV_APLIC + select RISCV_IMSIC select RISCV_INTC select RISCV_TIMER if RISCV_SBI select SIFIVE_PLIC