From patchwork Mon May 8 11:52:17 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 679977 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 21483C77B7F for ; Mon, 8 May 2023 11:53:17 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233053AbjEHLxP (ORCPT ); Mon, 8 May 2023 07:53:15 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55790 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234060AbjEHLxG (ORCPT ); Mon, 8 May 2023 07:53:06 -0400 Received: from mail-pl1-x62d.google.com (mail-pl1-x62d.google.com [IPv6:2607:f8b0:4864:20::62d]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8E0189EF7 for ; Mon, 8 May 2023 04:53:03 -0700 (PDT) Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-1aaef97652fso29727775ad.0 for ; Mon, 08 May 2023 04:53:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546783; x=1686138783; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=rfepdXJdsq6ohX2AkAAGDRO8NQz+5w0XQmMbJfl5w48=; b=hWuy+ZiUw1JYUSFzt1E/M+vNy0IUQxsPk5lOKUyv1zV9wOWRmYghioaQiBULlwHm9s jgnGlauoLdXVPoAMoxq4MadMMtFM/J5XWiJ9NMXuPt4LI8V/fO1wX4KQedMz02XonrpK 2bKULo+edMjXoVmEnOJdNrGtOaG6T6fhzIJUjWfnqw8QNcENZyq4HHdpt54CoYg1Mk4i 2xOHuUtc8rMwNFDQWtei/1baL+hX/1cAkLd71vAoyeotWh6p04MycEDBN2sWpxJBT6QD d9zQ+HamS9r+B/LNFexRnGBokTG0UOkQpIbnT55w877Iq/XlSSM5alf3zJLvARbSSt8U ngsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546783; x=1686138783; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rfepdXJdsq6ohX2AkAAGDRO8NQz+5w0XQmMbJfl5w48=; b=fYJRJ6eK6lAnssmXhOAYWZmfT7inHlEh+69bn2h3+BGffilzGLfAGORg0AjspfhrUl o0xrXipom2yOuJTOepuRABqAU/dP2JyDON2gEQKZSxMmLhEmRvvrz2ItOwWeuSTf9/d3 RCOC6oqNVneLz1bmiw4+LkDMAo57Pfsdgy9zvGO3swrcEJADuTMNDOEkSLkKaJgswgTn 7tOwqBvtePKOuZzBaSVygN8FJ6XSyTZSE7U2saeOXqYVQ0BNqKrtfDmp7X5sLqs98VlI NhUWUuE76PoZeUyBMWU3PT0iFZfduM8IEQKv/41a8U5+mJ5nPILqkYt+vdF6i4Wb4vPk JOZg== X-Gm-Message-State: AC+VfDxk4obUFXczRtGCkfKgvagd5lT8velcgXm3A94XgN7klUZ0BbkZ d3duv206OSBO8Ae+i7/gL8wCWQ== X-Google-Smtp-Source: ACHHUZ6E5oSS35ppin16Fc2D/CJweZplodceAaOSb9zbK0yJSsiHXmdseC+7l9W8CGis6yGw0B7fxg== X-Received: by 2002:a17:902:ceca:b0:1a6:5fa2:3293 with SMTP id d10-20020a170902ceca00b001a65fa23293mr12096226plg.56.1683546783045; Mon, 08 May 2023 04:53:03 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.52.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:53:02 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Jisheng Zhang , Anup Patel , Atish Patra Subject: [PATCH V5 01/21] riscv: move sbi_init() earlier before jump_label_init() Date: Mon, 8 May 2023 17:22:17 +0530 Message-Id: <20230508115237.216337-2-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org From: Jisheng Zhang We call jump_label_init() in setup_arch() is to use static key mechanism earlier, but riscv jump label relies on the sbi functions, If we enable static key before sbi_init(), the code path looks like: static_branch_enable() .. arch_jump_label_transform() patch_text_nosync() flush_icache_range() flush_icache_all() sbi_remote_fence_i() for CONFIG_RISCV_SBI case __sbi_rfence() Since sbi isn't initialized, so NULL deference! Here is a typical panic log: [ 0.000000] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 [ 0.000000] Oops [#1] [ 0.000000] Modules linked in: [ 0.000000] CPU: 0 PID: 0 Comm: swapper Not tainted 5.18.0-rc7+ #79 [ 0.000000] Hardware name: riscv-virtio,qemu (DT) [ 0.000000] epc : 0x0 [ 0.000000] ra : sbi_remote_fence_i+0x1e/0x26 [ 0.000000] epc : 0000000000000000 ra : ffffffff80005826 sp : ffffffff80c03d50 [ 0.000000] gp : ffffffff80ca6178 tp : ffffffff80c0ad80 t0 : 6200000000000000 [ 0.000000] t1 : 0000000000000000 t2 : 62203a6b746e6972 s0 : ffffffff80c03d60 [ 0.000000] s1 : ffffffff80001af6 a0 : 0000000000000000 a1 : 0000000000000000 [ 0.000000] a2 : 0000000000000000 a3 : 0000000000000000 a4 : 0000000000000000 [ 0.000000] a5 : 0000000000000000 a6 : 0000000000000000 a7 : 0000000000080200 [ 0.000000] s2 : ffffffff808b3e48 s3 : ffffffff808bf698 s4 : ffffffff80cb2818 [ 0.000000] s5 : 0000000000000001 s6 : ffffffff80c9c345 s7 : ffffffff80895aa0 [ 0.000000] s8 : 0000000000000001 s9 : 000000000000007f s10: 0000000000000000 [ 0.000000] s11: 0000000000000000 t3 : ffffffff80824d08 t4 : 0000000000000022 [ 0.000000] t5 : 000000000000003d t6 : 0000000000000000 [ 0.000000] status: 0000000000000100 badaddr: 0000000000000000 cause: 000000000000000c [ 0.000000] ---[ end trace 0000000000000000 ]--- [ 0.000000] Kernel panic - not syncing: Attempted to kill the idle task! [ 0.000000] ---[ end Kernel panic - not syncing: Attempted to kill the idle task! ]--- Fix this issue by moving sbi_init() earlier before jump_label_init() Signed-off-by: Jisheng Zhang Reviewed-by: Anup Patel Reviewed-by: Atish Patra --- arch/riscv/kernel/setup.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 36b026057503..9fb839074e16 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -270,6 +270,7 @@ void __init setup_arch(char **cmdline_p) *cmdline_p = boot_command_line; early_ioremap_setup(); + sbi_init(); jump_label_init(); parse_early_param(); @@ -283,7 +284,6 @@ void __init setup_arch(char **cmdline_p) misc_mem_init(); init_resources(); - sbi_init(); #ifdef CONFIG_KASAN kasan_init(); From patchwork Mon May 8 11:52:18 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 680297 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9C629C77B75 for ; Mon, 8 May 2023 11:53:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236423AbjEHLxa (ORCPT ); Mon, 8 May 2023 07:53:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56316 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232840AbjEHLx0 (ORCPT ); Mon, 8 May 2023 07:53:26 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 38FEC40914 for ; Mon, 8 May 2023 04:53:12 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1ab14cb3aaeso30471555ad.2 for ; Mon, 08 May 2023 04:53:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546791; x=1686138791; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=+3BRBVSL8Q8oMs51cYTt5mS52il5fOg1fDJihGv43qY=; b=ES80Pxi/On81xqzn466VvCtk334hOGfLr3xn3NTzV4apgRB6RhbwKVZIBTo1IalSBU lVcmcysxZ/p/60nF3RQX8UI1koHmb+gb7F5LJZjEVSoVIGSHNIZ9O+CQQqq/ou8vs896 PsjSxFkz+JnUtxrFW3Jc29Ds2qTuysCBuEk2ac+MWgL1rEcleqYXwdECBvL5XAcvB/Wu hGnV8U+fIXsSHGY1953OB4LCCRDAP4Dd+fG/2c0eFv5FtPnxQujLOUpF86J7i47XEM3m 1YKonECds2h4NnmW4jdkgHVQz2gvVlcClU0sfnJgFqdQkSIDsEQpi42essJJz1Rx3DXZ MKXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546791; x=1686138791; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+3BRBVSL8Q8oMs51cYTt5mS52il5fOg1fDJihGv43qY=; b=AIRiSuIDDxCKbkmlGM1EJZDmewmOrSYmThMyOgFjV0Kh2DkoM7SWrwVynlzrZOjKN9 EriFvX+N2AzPfSE9s2S09uhlClsCfMZSacYM7Pi0gIWz7k6iaSHgrjSQW6uP7bSa3yRB O7R4kByiv/6o49nfEqyFBw62qKGdVNl80j8pBKnH19c7DzSO1JwKcuCH2lbV3Z5iEyp5 Qq8vuD0xhrZpMDn9WQ8OCydJhiMKWyOwqZoWKTAq1auT8i5ah5lROETttX1zzHGvrrxw /iHkFsbUqi+2Q7t9T21qns7W1KduEJBxGxnI23JRh26yPcUWwCa0418CqE6BgjAVn92o SmHA== X-Gm-Message-State: AC+VfDzdYxS8LtaUb5lW9p8g1+1GBRLzOF1X5rZ/rUsE9ZKgo2g+rIkd Ku+6STNpY5vlICiSILj4oC+pWQ== X-Google-Smtp-Source: ACHHUZ53NJaW+sZlrm12uD3x0j9cg0hxSH1iCIdCk/a3op4cRVXeGuLCDkrlAFFwOkN/WoP8UHY5Cg== X-Received: by 2002:a17:903:2312:b0:1ac:656f:a697 with SMTP id d18-20020a170903231200b001ac656fa697mr6858328plh.21.1683546791698; Mon, 08 May 2023 04:53:11 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.53.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:53:11 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L Subject: [PATCH V5 02/21] platform/surface: Disable for RISC-V Date: Mon, 8 May 2023 17:22:18 +0530 Message-Id: <20230508115237.216337-3-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in allmodconfig build. However, RISC-V doesn't support sub-word atomics which is used by this driver. Due to this, the build fails with below error. In function ‘ssh_seq_next’, inlined from ‘ssam_request_write_data’ at drivers/platform/surface/aggregator/controller.c:1483:8: ././include/linux/compiler_types.h:399:45: error: call to ‘__compiletime_assert_335’ declared with attribute error: BUILD_BUG failed 399 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^ ./include/linux/compiler.h:78:45: note: in definition of macro ‘unlikely’ 78 | # define unlikely(x) __builtin_expect(!!(x), 0) | ^ ././include/linux/compiler_types.h:387:9: note: in expansion of macro ‘__compiletime_assert’ 387 | __compiletime_assert(condition, msg, prefix, suffix) | ^~~~~~~~~~~~~~~~~~~~ ././include/linux/compiler_types.h:399:9: note: in expansion of macro ‘_compiletime_assert’ 399 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) | ^~~~~~~~~~~~~~~~~~~ ./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’ 39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg) | ^~~~~~~~~~~~~~~~~~ ./include/linux/build_bug.h:59:21: note: in expansion of macro ‘BUILD_BUG_ON_MSG’ 59 | #define BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed") | ^~~~~~~~~~~~~~~~ ./arch/riscv/include/asm/cmpxchg.h:335:17: note: in expansion of macro ‘BUILD_BUG’ 335 | BUILD_BUG(); \ | ^~~~~~~~~ ./arch/riscv/include/asm/cmpxchg.h:344:30: note: in expansion of macro ‘__cmpxchg’ 344 | (__typeof__(*(ptr))) __cmpxchg((ptr), \ | ^~~~~~~~~ ./include/linux/atomic/atomic-instrumented.h:1916:9: note: in expansion of macro ‘arch_cmpxchg’ 1916 | arch_cmpxchg(__ai_ptr, __VA_ARGS__); \ | ^~~~~~~~~~~~ drivers/platform/surface/aggregator/controller.c:61:32: note: in expansion of macro ‘cmpxchg’ 61 | while (unlikely((ret = cmpxchg(&c->value, old, new)) != old)) { | ^~~~~~~ There is currently no plan to support this driver for RISC-V. So, disable this driver for RISC-V even when ACPI is enabled for now. Signed-off-by: Sunil V L Acked-by: Maximilian Luz --- drivers/platform/surface/aggregator/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/platform/surface/aggregator/Kconfig b/drivers/platform/surface/aggregator/Kconfig index c114f9dd5fe1..88afc38ffdc5 100644 --- a/drivers/platform/surface/aggregator/Kconfig +++ b/drivers/platform/surface/aggregator/Kconfig @@ -4,7 +4,7 @@ menuconfig SURFACE_AGGREGATOR tristate "Microsoft Surface System Aggregator Module Subsystem and Drivers" depends on SERIAL_DEV_BUS - depends on ACPI + depends on ACPI && !RISCV select CRC_CCITT help The Surface System Aggregator Module (Surface SAM or SSAM) is an From patchwork Mon May 8 11:52:19 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 679976 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B74DBC77B75 for ; Mon, 8 May 2023 11:53:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236427AbjEHLxv (ORCPT ); Mon, 8 May 2023 07:53:51 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55830 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236432AbjEHLxa (ORCPT ); Mon, 8 May 2023 07:53:30 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 05622429C8 for ; Mon, 8 May 2023 04:53:20 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1aaf706768cso33123005ad.0 for ; Mon, 08 May 2023 04:53:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546800; x=1686138800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=qd6PQ1vE/SZdiXRk2V4YVd/9ukw5PfEy62nQ6sf0Uk0=; b=Wj+BdFY08go+Klnkl9ikMjatb5QJpTO2cewG54fs1b3lW77HcXNjgQTN2vzRD/j8ke U3yyKNS6ssEcggGMDfAXgwZPVb+FBmqfOr+Em+1ArsfHhZf2wSJZfgC6VkUq+JwWgyLn g+RLMWOOtmon/m7EVa2DCP+ETl1ECCK4M3nMIjFho7LKvb2yNVDCezwfPiVlDcs9QJCj 8LW7073DSm3mdChDFXxsHRRaDLUKp6u28cqpHj2tCtL9vO7xzRypFejOqMQyJUAGg7RB COx5W+bUevsvQur/1Cp+1+YUYxa7JkuqnS6OOhyy6oxt/zn2DyhnlYWkHpifR+QPUO6n siaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546800; x=1686138800; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qd6PQ1vE/SZdiXRk2V4YVd/9ukw5PfEy62nQ6sf0Uk0=; b=Me/f2xEZrqb2r4E1+f/aQCK0Iq3ONGAQ1bdv+Cy+ziAtxkUbg/jh/CnsazXbEwFUrP kUjp7dKI95w0fas/GSxHoCUb2HM9ri5jdzbXwV79VY/c5IK0vb/5AqvoTh9aC4aufLqz xXtQYug6GhhoRZ+Pm4FFz11MwjYnfq4UgqPbPRCGnGy8+OT1GFOOxM18q9asLiMx5agB Ssqk9dXWO7WadjUXEgeDioapBJxxh2OnKLRv7S1CILNuK/u5krxN+VnsAvESw8V3GD6J ruoJLrTw1VCbCg/uep2ZCHmNrv6L65TL+Y+WpbLTFNrFfhnXBlQPfJuvbgFwaniTLfrN iJ0g== X-Gm-Message-State: AC+VfDwiTLWEAADF2xJwHAp6AXmhbMXIV5cytOCoN3T/OTKtZM+phWyA LnzfR6I5Ne7pVX03p8YrlNpuRw== X-Google-Smtp-Source: ACHHUZ44JOKf09v8SpLqQAPymUJYFxrBhM0oK44TrPeFKd+o5n6tK/8ozBu8m8cH4Q+O9X7/qncP4w== X-Received: by 2002:a17:903:1252:b0:1aa:f0a7:933 with SMTP id u18-20020a170903125200b001aaf0a70933mr12699535plh.25.1683546800261; Mon, 08 May 2023 04:53:20 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.53.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:53:19 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L Subject: [PATCH V5 03/21] crypto: hisilicon/qm: Fix to enable build with RISC-V clang Date: Mon, 8 May 2023 17:22:19 +0530 Message-Id: <20230508115237.216337-4-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org With CONFIG_ACPI enabled for RISC-V, this driver gets enabled in allmodconfig build. However, build fails with clang and below error is seen. drivers/crypto/hisilicon/qm.c:627:10: error: invalid output constraint '+Q' in asm "+Q" (*((char __iomem *)fun_base)) ^ This is expected error with clang due to the way it is designed. To fix this issue, move arm64 assembly code under #if. Link: https://github.com/ClangBuiltLinux/linux/issues/999 Signed-off-by: Nathan Chancellor [sunilvl@ventanamicro.com: Moved tmp0 and tmp1 into the #if] Signed-off-by: Sunil V L --- drivers/crypto/hisilicon/qm.c | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/drivers/crypto/hisilicon/qm.c b/drivers/crypto/hisilicon/qm.c index ad0c042b5e66..2eaeaac2e246 100644 --- a/drivers/crypto/hisilicon/qm.c +++ b/drivers/crypto/hisilicon/qm.c @@ -610,13 +610,9 @@ EXPORT_SYMBOL_GPL(hisi_qm_wait_mb_ready); static void qm_mb_write(struct hisi_qm *qm, const void *src) { void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE; - unsigned long tmp0 = 0, tmp1 = 0; - if (!IS_ENABLED(CONFIG_ARM64)) { - memcpy_toio(fun_base, src, 16); - dma_wmb(); - return; - } +#if IS_ENABLED(CONFIG_ARM64) + unsigned long tmp0 = 0, tmp1 = 0; asm volatile("ldp %0, %1, %3\n" "stp %0, %1, %2\n" @@ -626,6 +622,11 @@ static void qm_mb_write(struct hisi_qm *qm, const void *src) "+Q" (*((char __iomem *)fun_base)) : "Q" (*((char *)src)) : "memory"); +#else + memcpy_toio(fun_base, src, 16); + dma_wmb(); +#endif + } static int qm_mb_nolock(struct hisi_qm *qm, struct qm_mailbox *mailbox) From patchwork Mon May 8 11:52:20 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 680296 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D6AFDC77B75 for ; Mon, 8 May 2023 11:54:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229464AbjEHLyF (ORCPT ); Mon, 8 May 2023 07:54:05 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56292 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234579AbjEHLxh (ORCPT ); Mon, 8 May 2023 07:53:37 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id EEE33272D for ; Mon, 8 May 2023 04:53:28 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1aaec6f189cso29517095ad.3 for ; Mon, 08 May 2023 04:53:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546808; x=1686138808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=1wcGbfhUP5NrwGCYl7Q1yL0FMzRdJBr1PIlnUSkktJs=; b=fBHUfS8fWSAOqlwT6Q08NJnR0u3M9PyiSxhBSIcvPa/yshAYWNpI0o9m3i1+avJke7 UpdOLZb8RloM1SZR7kh5kmhzwoaBrLsvxZoeqYVZqqF396fb/4BhWwd23qb9VCpaKumw +uzkOQJbxs7oZeo9NsWhaHt5YsTFd1D2MQy8quk+pYQZ9V1E+g372HhAHRdQNMKrPpL/ Y2eneBn1k8hN2tTm1lHK/RgQHMRZvomTuBl9iOkHafRg69ncMDwy+Yu/SoJirdME89sk +YabmC7IczGRfgKnOXQXtodoUNlYgFuPjduPauQRgsg6YGZbopdDa3L+DuoJF7LnTN5O CPQg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546808; x=1686138808; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=1wcGbfhUP5NrwGCYl7Q1yL0FMzRdJBr1PIlnUSkktJs=; b=HMj/a8EWQ1JCOJWh9C0LqHh2zrZix+Ss5H2WXXILGvCxa0IyLCu80qpURdXHghJKVy ig9P6MLDeO3bdpB+N/3nvv+Nv5yE13M5ZjfNaWWcwdu2W2yYkek5dNqRQ+6ffZnmVRCo Cg2hcEBo/A1kuVTU8o69LcuNcnFsKIFvgM2igBAt+r+xWu95QPeUTl+6tXvcRto8fnRQ A0I9GX0zFuWu6UjLQOsmnhUuVRXfSTDOr3RrC0/7nZIY3fRm35xP4+ATU53x/cj7zDQA YHMXskg4Em1ZHAOqlCVkzFXXNFIh5maJ96PdHAQv/3oqkk/hKi/nOR1Bc0EwJAN2+Rmz Vtpg== X-Gm-Message-State: AC+VfDxol2zOvjfEsc+dTE+BHjx+mgPpjwfOrG4bsLlqqLU5PSXtNF4n e+8MAk64IewtDgoWHan1rNEglA== X-Google-Smtp-Source: ACHHUZ4YPZPXYK0bFQvCKyd/gnSncEBJ6qVKzMyJ4dAbIZymuHBA+fio0dFknn2dgtRYb5PHf8ADKA== X-Received: by 2002:a17:902:b405:b0:1a5:a1b:bbd8 with SMTP id x5-20020a170902b40500b001a50a1bbbd8mr9546124plr.45.1683546808426; Mon, 08 May 2023 04:53:28 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.53.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:53:28 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones Subject: [PATCH V5 04/21] ACPI: tables: Print RINTC information when MADT is parsed Date: Mon, 8 May 2023 17:22:20 +0530 Message-Id: <20230508115237.216337-5-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org When MADT is parsed, print RINTC information as below: ACPI: RISC-V INTC (acpi_uid[0x0000] hart_id[0x0] enabled) ACPI: RISC-V INTC (acpi_uid[0x0001] hart_id[0x1] enabled) ... ACPI: RISC-V INTC (acpi_uid[0x000f] hart_id[0xf] enabled) This debug information will be very helpful during bring up. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones --- drivers/acpi/tables.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/acpi/tables.c b/drivers/acpi/tables.c index 7b4680da57d7..8ab0a82b4da4 100644 --- a/drivers/acpi/tables.c +++ b/drivers/acpi/tables.c @@ -220,6 +220,16 @@ void acpi_table_print_madt_entry(struct acpi_subtable_header *header) } break; + case ACPI_MADT_TYPE_RINTC: + { + struct acpi_madt_rintc *p = (struct acpi_madt_rintc *)header; + + pr_debug("RISC-V INTC (acpi_uid[0x%04x] hart_id[0x%llx] %s)\n", + p->uid, p->hart_id, + (p->flags & ACPI_MADT_ENABLED) ? "enabled" : "disabled"); + } + break; + default: pr_warn("Found unsupported MADT entry (type = 0x%x)\n", header->type); From patchwork Mon May 8 11:52:21 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 679975 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DCDA0C77B73 for ; Mon, 8 May 2023 11:54:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236451AbjEHLy0 (ORCPT ); Mon, 8 May 2023 07:54:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56386 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236454AbjEHLxs (ORCPT ); Mon, 8 May 2023 07:53:48 -0400 Received: from mail-pl1-x632.google.com (mail-pl1-x632.google.com [IPv6:2607:f8b0:4864:20::632]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 12D0840334 for ; Mon, 8 May 2023 04:53:36 -0700 (PDT) Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-1ab13da70a3so43455565ad.1 for ; Mon, 08 May 2023 04:53:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546816; x=1686138816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=g9sxg5LZ/1sJSiDItv56ESM72UWoohRRXZed1vK0StQ=; b=LI6hJFWMPnsAo7nIAUuNh8he07mq1qgBALuGpR9EPgsWn0RuQgqraPJfQDVda1IPzP dxfRnz2+Y1bBoCiW6MOE7juSAhHpWJ5eHqBpRXu6YmP8VojcJM4EoeZQlUqk7qVboH0r A+Q9G5B1hyxCv4ivTDFstBhRFjJb8+NWDTdCrbOGDjkl0MIJm5n95AroRQ88lMxfgPqT JrBnULZUv/fWaGdmODxR/f+VFKjEDxTExcbSfGxpMgB1dt+zxESFqt+Wjv/vLG4AQVAS 35iYEQdCAIV6RHM2AkPKMrGfP5t56Mm4wvj4UplcEL3D8qytkfAH0uRNjcFGeSquvRNo SSAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546816; x=1686138816; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=g9sxg5LZ/1sJSiDItv56ESM72UWoohRRXZed1vK0StQ=; b=LxCfA+erRaRJHtoeVA2Cl2Djbm3u8tPRiSJHkhLzNQbWePClGDhymX7bwrvIONLWti YL+tYgQfZbUv+2xlheB/i/XLI/EotzXQCdYh7cYGNGMoYH6YGCQA54gbZxHgOHta6mhT POEI3NY4CxF8qDTZZz/+raBPug4FBbB1SXcrduXLiLqYR99Qia2ntAWvLguUOVlXhX5y NS1dTtuYrXKkSqItC78Pm9ZDWTnsqP1TuvB1VgLecE1Sxooku03X0QgkrF7zfIP+zyi3 Dhn8ThwJdHWWEjkDUkKbtG9TEBIv2JlybbrSw+icViBaQYeLtyCMjfuY/U6g8BPkhbDA 4W2g== X-Gm-Message-State: AC+VfDwjbTsg9TMDGXyw5wNwS9vnJpqUgeFiNGv0z5MiU4TO3qSZ8dsq 2/VIRLHgGVabWCkYm7WD3POiKA== X-Google-Smtp-Source: ACHHUZ52W6P99fGjx1H1aTdF1PS++Nk8GKk+bQ6gsyNGyvgDs6xJ01TMTUEtUHiG/54yN9c7UrsPkQ== X-Received: by 2002:a17:902:b085:b0:1aa:fdab:24a5 with SMTP id p5-20020a170902b08500b001aafdab24a5mr9199631plr.10.1683546816386; Mon, 08 May 2023 04:53:36 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.53.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:53:36 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V5 05/21] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Date: Mon, 8 May 2023 17:22:21 +0530 Message-Id: <20230508115237.216337-6-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Without this, if the tables are larger than 4K, acpi_map() will fail. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki --- drivers/acpi/osl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/acpi/osl.c b/drivers/acpi/osl.c index 3269a888fb7a..f725813d0cce 100644 --- a/drivers/acpi/osl.c +++ b/drivers/acpi/osl.c @@ -276,7 +276,7 @@ acpi_map_lookup_virt(void __iomem *virt, acpi_size size) return NULL; } -#if defined(CONFIG_IA64) || defined(CONFIG_ARM64) +#if defined(CONFIG_IA64) || defined(CONFIG_ARM64) || defined(CONFIG_RISCV) /* ioremap will take care of cache attributes */ #define should_use_kmap(pfn) 0 #else From patchwork Mon May 8 11:52:22 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 680295 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26C20C77B75 for ; Mon, 8 May 2023 11:54:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236466AbjEHLyr (ORCPT ); Mon, 8 May 2023 07:54:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56356 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236376AbjEHLyR (ORCPT ); Mon, 8 May 2023 07:54:17 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6D38F43690 for ; Mon, 8 May 2023 04:53:45 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1ab1ce53ca6so31164375ad.0 for ; Mon, 08 May 2023 04:53:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546824; x=1686138824; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=hXB6eSvEhnIAtMiQWlMtfWUjRdd7V8Gch2IVA+HK6fk=; b=ebWTZvVaQDx6X+9UsK2RbHTnW183k6BKTsOF+bCMFgqFtgeBzsyP/w5qy7tOKROuUC ZxTuvZiMQiB+Ua4SXOBNs+t7uI0Ats9RXLgJVMycPsYyF2eIPW3Gh+M9ye96yAMc0RH1 Mtb+794zmhSFBW/GwJSgBFFZzeQ4b2k2P98Dpl5wOc3MxFTYa2gck9ClbsPUhl//ERS2 IWbrVH8Qmq/UF93MEUcUH8RTYSDW0HAjPAZ+t1IaTrcEVR+jx0vficJZuWZHxA7vJzkg Wu3R3iYhGAmBuvaYLY5b/vwtSTaUxwNpNSnCci0i3v1xoRxXfuTlZ4HVqPLs9tkO4dGH MRKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546825; x=1686138825; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hXB6eSvEhnIAtMiQWlMtfWUjRdd7V8Gch2IVA+HK6fk=; b=aRXiSPx/i+wDKv6Wg5rw1T2QRFhodjjGp3yLZparPc2Gc+Jw/zXWKkDJr/Ur+1kg6g dqiSJvvWY4RwB+MHQNWV//HRJGns1ZFxrmP3hJ7Cw5DilZb/Xt+he0RxFs+akf1y7YRy GN4mO8SjsIwJJ2u/WCGYNN9qEleY+0PeyOsMmFMzzme0qWYf0BlBTonGYZHuV0dWFqLx DfHPMXsHxPawDClsoR3jGuNBVGEZxvw3gY827ZdM+aX2j5OgSpA6W8342b5YVCXuegW8 87NSbA16E6OTqaD5+d5S3E2tDblYrdhgbSLl7kKLf08jlBbQLCjt1yOz/NTbtAKPmS3X 2pGw== X-Gm-Message-State: AC+VfDzPrSrbzim+p7ayI/UZDk+W2JoPCKOTohxgCnU/hMKnKYhYjPrZ UqDkRJ8jMNthRJGFAl3cCTIvaQ== X-Google-Smtp-Source: ACHHUZ4PU3YdcmwoLuH4jvs9+bfUcLvXabdC5Eg1na9dV0OJsAf5GJnzwnVXrkvmBEUvHMCJo+05+Q== X-Received: by 2002:a17:902:c40b:b0:1aa:fd48:f5e2 with SMTP id k11-20020a170902c40b00b001aafd48f5e2mr13592838plk.32.1683546824698; Mon, 08 May 2023 04:53:44 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.53.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:53:44 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley , Palmer Dabbelt Subject: [PATCH V5 06/21] RISC-V: Add support to build the ACPI core Date: Mon, 8 May 2023 17:22:22 +0530 Message-Id: <20230508115237.216337-7-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Enable ACPI core for RISC-V after adding architecture-specific interfaces and header files required to build the ACPI core. 1) Couple of header files are required unconditionally by the ACPI core. Add empty acenv.h and cpu.h header files. 2) If CONFIG_PCI is enabled, a few PCI related interfaces need to be provided by the architecture. Define dummy interfaces for now so that build succeeds. Actual implementation will be added when PCI support is added for ACPI along with external interrupt controller support. 3) A few globals and memory mapping related functions specific to the architecture need to be provided. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley Reviewed-by: Palmer Dabbelt --- arch/riscv/Kconfig | 5 +++ arch/riscv/include/asm/acenv.h | 11 +++++ arch/riscv/include/asm/acpi.h | 61 ++++++++++++++++++++++++++ arch/riscv/include/asm/cpu.h | 8 ++++ arch/riscv/kernel/Makefile | 1 + arch/riscv/kernel/acpi.c | 80 ++++++++++++++++++++++++++++++++++ 6 files changed, 166 insertions(+) create mode 100644 arch/riscv/include/asm/acenv.h create mode 100644 arch/riscv/include/asm/acpi.h create mode 100644 arch/riscv/include/asm/cpu.h create mode 100644 arch/riscv/kernel/acpi.c diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 348c0fa1fc8c..491ecd7d2336 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -12,6 +12,8 @@ config 32BIT config RISCV def_bool y + select ACPI_GENERIC_GSI if ACPI + select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ARCH_DMA_DEFAULT_COHERENT select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION select ARCH_ENABLE_SPLIT_PMD_PTLOCK if PGTABLE_LEVELS > 2 @@ -707,6 +709,7 @@ config EFI depends on OF && !XIP_KERNEL depends on MMU default y + select ARCH_SUPPORTS_ACPI if 64BIT select EFI_GENERIC_STUB select EFI_PARAMS_FROM_FDT select EFI_RUNTIME_WRAPPERS @@ -816,3 +819,5 @@ source "drivers/cpufreq/Kconfig" endmenu # "CPU Power Management" source "arch/riscv/kvm/Kconfig" + +source "drivers/acpi/Kconfig" diff --git a/arch/riscv/include/asm/acenv.h b/arch/riscv/include/asm/acenv.h new file mode 100644 index 000000000000..43ae2e32c779 --- /dev/null +++ b/arch/riscv/include/asm/acenv.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * RISC-V specific ACPICA environments and implementation + */ + +#ifndef _ASM_ACENV_H +#define _ASM_ACENV_H + +/* This header is required unconditionally by the ACPI core */ + +#endif /* _ASM_ACENV_H */ diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h new file mode 100644 index 000000000000..bcade255bd6e --- /dev/null +++ b/arch/riscv/include/asm/acpi.h @@ -0,0 +1,61 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2013-2014, Linaro Ltd. + * Author: Al Stone + * Author: Graeme Gregory + * Author: Hanjun Guo + * + * Copyright (C) 2021-2023, Ventana Micro Systems Inc. + * Author: Sunil V L + */ + +#ifndef _ASM_ACPI_H +#define _ASM_ACPI_H + +/* Basic configuration for ACPI */ +#ifdef CONFIG_ACPI + +/* ACPI table mapping after acpi_permanent_mmap is set */ +void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); +#define acpi_os_ioremap acpi_os_ioremap + +#define acpi_strict 1 /* No out-of-spec workarounds on RISC-V */ +extern int acpi_disabled; +extern int acpi_noirq; +extern int acpi_pci_disabled; + +static inline void disable_acpi(void) +{ + acpi_disabled = 1; + acpi_pci_disabled = 1; + acpi_noirq = 1; +} + +static inline void enable_acpi(void) +{ + acpi_disabled = 0; + acpi_pci_disabled = 0; + acpi_noirq = 0; +} + +/* + * The ACPI processor driver for ACPI core code needs this macro + * to find out whether this cpu was already mapped (mapping from CPU hardware + * ID to CPU logical ID) or not. + */ +#define cpu_physical_id(cpu) cpuid_to_hartid_map(cpu) + +/* + * Since MADT must provide at least one RINTC structure, the + * CPU will be always available in MADT on RISC-V. + */ +static inline bool acpi_has_cpu_in_madt(void) +{ + return true; +} + +static inline void arch_fix_phys_package_id(int num, u32 slot) { } + +#endif /* CONFIG_ACPI */ + +#endif /*_ASM_ACPI_H*/ diff --git a/arch/riscv/include/asm/cpu.h b/arch/riscv/include/asm/cpu.h new file mode 100644 index 000000000000..28d45a6678ce --- /dev/null +++ b/arch/riscv/include/asm/cpu.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ASM_CPU_H +#define _ASM_CPU_H + +/* This header is required unconditionally by the ACPI core */ + +#endif /* _ASM_CPU_H */ diff --git a/arch/riscv/kernel/Makefile b/arch/riscv/kernel/Makefile index fbdccc21418a..ed5fcd90036e 100644 --- a/arch/riscv/kernel/Makefile +++ b/arch/riscv/kernel/Makefile @@ -92,3 +92,4 @@ obj-$(CONFIG_COMPAT) += compat_signal.o obj-$(CONFIG_COMPAT) += compat_vdso/ obj-$(CONFIG_64BIT) += pi/ +obj-$(CONFIG_ACPI) += acpi.o diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c new file mode 100644 index 000000000000..81d448c41714 --- /dev/null +++ b/arch/riscv/kernel/acpi.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * RISC-V Specific Low-Level ACPI Boot Support + * + * Copyright (C) 2013-2014, Linaro Ltd. + * Author: Al Stone + * Author: Graeme Gregory + * Author: Hanjun Guo + * Author: Tomasz Nowicki + * Author: Naresh Bhat + * + * Copyright (C) 2021-2023, Ventana Micro Systems Inc. + * Author: Sunil V L + */ + +#include +#include +#include + +int acpi_noirq = 1; /* skip ACPI IRQ initialization */ +int acpi_disabled = 1; +EXPORT_SYMBOL(acpi_disabled); + +int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */ +EXPORT_SYMBOL(acpi_pci_disabled); + +/* + * __acpi_map_table() will be called before paging_init(), so early_ioremap() + * or early_memremap() should be called here to for ACPI table mapping. + */ +void __init __iomem *__acpi_map_table(unsigned long phys, unsigned long size) +{ + if (!size) + return NULL; + + return early_memremap(phys, size); +} + +void __init __acpi_unmap_table(void __iomem *map, unsigned long size) +{ + if (!map || !size) + return; + + early_memunmap(map, size); +} + +void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size) +{ + return memremap(phys, size, MEMREMAP_WB); +} + +#ifdef CONFIG_PCI + +/* + * These interfaces are defined just to enable building ACPI core. + * TODO: Update it with actual implementation when external interrupt + * controller support is added in RISC-V ACPI. + */ +int raw_pci_read(unsigned int domain, unsigned int bus, unsigned int devfn, + int reg, int len, u32 *val) +{ + return PCIBIOS_DEVICE_NOT_FOUND; +} + +int raw_pci_write(unsigned int domain, unsigned int bus, unsigned int devfn, + int reg, int len, u32 val) +{ + return PCIBIOS_DEVICE_NOT_FOUND; +} + +int acpi_pci_bus_find_domain_nr(struct pci_bus *bus) +{ + return -1; +} + +struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root) +{ + return NULL; +} +#endif /* CONFIG_PCI */ From patchwork Mon May 8 11:52:23 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 679974 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 46E55C7EE23 for ; Mon, 8 May 2023 11:55:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232562AbjEHLzU (ORCPT ); Mon, 8 May 2023 07:55:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57110 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236422AbjEHLyj (ORCPT ); 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Wysocki" , Andrew Jones Subject: [PATCH V5 07/21] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Date: Mon, 8 May 2023 17:22:23 +0530 Message-Id: <20230508115237.216337-8-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org processor_core needs arch-specific functions to map the ACPI ID to the physical ID. In RISC-V platforms, hartid is the physical id and RINTC structure in MADT provides this mapping. Add arch-specific function to get this mapping from RINTC. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones --- arch/riscv/include/asm/acpi.h | 3 +++ drivers/acpi/processor_core.c | 29 +++++++++++++++++++++++++++++ 2 files changed, 32 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index bcade255bd6e..9be52b6ffae1 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -15,6 +15,9 @@ /* Basic configuration for ACPI */ #ifdef CONFIG_ACPI +typedef u64 phys_cpuid_t; +#define PHYS_CPUID_INVALID INVALID_HARTID + /* ACPI table mapping after acpi_permanent_mmap is set */ void *acpi_os_ioremap(acpi_physical_address phys, acpi_size size); #define acpi_os_ioremap acpi_os_ioremap diff --git a/drivers/acpi/processor_core.c b/drivers/acpi/processor_core.c index 2ac48cda5b20..d6606a9f2da6 100644 --- a/drivers/acpi/processor_core.c +++ b/drivers/acpi/processor_core.c @@ -106,6 +106,32 @@ static int map_gicc_mpidr(struct acpi_subtable_header *entry, return -EINVAL; } +/* + * Retrieve the RISC-V hartid for the processor + */ +static int map_rintc_hartid(struct acpi_subtable_header *entry, + int device_declaration, u32 acpi_id, + phys_cpuid_t *hartid) +{ + struct acpi_madt_rintc *rintc = + container_of(entry, struct acpi_madt_rintc, header); + + if (!(rintc->flags & ACPI_MADT_ENABLED)) + return -ENODEV; + + /* device_declaration means Device object in DSDT, in the + * RISC-V, logical processors are required to + * have a Processor Device object in the DSDT, so we should + * check device_declaration here + */ + if (device_declaration && rintc->uid == acpi_id) { + *hartid = rintc->hart_id; + return 0; + } + + return -EINVAL; +} + static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt, int type, u32 acpi_id) { @@ -136,6 +162,9 @@ static phys_cpuid_t map_madt_entry(struct acpi_table_madt *madt, } else if (header->type == ACPI_MADT_TYPE_GENERIC_INTERRUPT) { if (!map_gicc_mpidr(header, type, acpi_id, &phys_id)) break; + } else if (header->type == ACPI_MADT_TYPE_RINTC) { + if (!map_rintc_hartid(header, type, acpi_id, &phys_id)) + break; } entry += header->length; } From patchwork Mon May 8 11:52:24 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 680294 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4DC77C7EE30 for ; Mon, 8 May 2023 11:55:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234189AbjEHLzW (ORCPT ); Mon, 8 May 2023 07:55:22 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236441AbjEHLyp (ORCPT ); Mon, 8 May 2023 07:54:45 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6313C4418F for ; Mon, 8 May 2023 04:54:01 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1aafa41116fso29543275ad.1 for ; Mon, 08 May 2023 04:54:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546841; x=1686138841; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=d2h3vevkYkVu6ki2VA7HPdPz/xuNcH/E20UC4Fi6w3o=; b=ZZntHeSbVEpN02Cc+DEk3iz4bVfHnuRM7WXQFLS0RRgrCwNBHq8sayu889D7P++r3l 1gAWSEh9mwMM1kV8cZ4wLRQO6IgX4yBBIXJiz9RrSkfYghpY3CmVSdAcHA9dEq3URnX/ QpFe+mOoaH7nAoQtsuoqkZzYKMeL3KF7pKgtxQiTauaupMtTSAz+NKn1LgASFO5wXbUi EcqgjxB7hqnvV7G1mrA8dhh2WIDT5/evRVQiT1GKkkpgK3LN02qAuAAKd90NpRQ113F1 OffZEST/D6geWJCn+4z4IOeEejiohuTr/piTkuJSkGofxieZm2iKwTRYMQijgLtpweAr cTKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546841; x=1686138841; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=d2h3vevkYkVu6ki2VA7HPdPz/xuNcH/E20UC4Fi6w3o=; b=EPt8rRRfbKFYPKuru12+ebFKk4D9iqbuZtJEleiHXsv71S1xvHtq7IYMJ+TjigTPI+ rc2yIgJEVKIcJIUOuNDj/pA1W3V/VO5zmijYRhzVfZi76rUvFDiGteOjSZ3diydmKsVn H4oQ69Iz75aW4OPmwLXuN5OZvM8R1j3JFDYqibuGqjPFgL6TbixiXco9vr+RJjnjGQY8 cPqpejPbvKM7vluO6LbXS9+YyR1rKd0toXanv19bMBb6CsoT04ddYckm/dITMHvEMakL Vttq9Cdxp/urE2JK7c5C1F/aElzcI2YqSX6yEHW83P07Rg0qzTeF0dRrBzgao1Ouo7i3 uyng== X-Gm-Message-State: AC+VfDwlbdS7BCG1T7H2ooql8jkYUC4rr4vCG4NFgClSWF5PevH84pjK PBh4esY5AdcUZ8boJS8uxnQmnFpZUUXxEwkKAZQ= X-Google-Smtp-Source: ACHHUZ69ugSarTSAMXC6f5oL9jNd6KuCehtnlrYptJAQTMRmfWkWaZ+k5Pb6dtDwggIXeWsz/yggPg== X-Received: by 2002:a17:902:e74c:b0:1aa:cddd:57f2 with SMTP id p12-20020a170902e74c00b001aacddd57f2mr12752642plf.25.1683546840856; Mon, 08 May 2023 04:54:00 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.53.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:00 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V5 08/21] RISC-V: ACPI: Cache and retrieve the RINTC structure Date: Mon, 8 May 2023 17:22:24 +0530 Message-Id: <20230508115237.216337-9-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org RINTC structures in the MADT provide mapping between the hartid and the CPU. This is required many times even at run time like cpuinfo. So, instead of parsing the ACPI table every time, cache the RINTC structures and provide a function to get the correct RINTC structure for a given cpu. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki --- arch/riscv/include/asm/acpi.h | 10 ++++++++ arch/riscv/kernel/acpi.c | 45 +++++++++++++++++++++++++++++++++++ arch/riscv/kernel/setup.c | 4 ++++ 3 files changed, 59 insertions(+) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 9be52b6ffae1..6519529c8bdf 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -59,6 +59,16 @@ static inline bool acpi_has_cpu_in_madt(void) static inline void arch_fix_phys_package_id(int num, u32 slot) { } +void acpi_init_rintc_map(void); +struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu); +u32 get_acpi_id_for_cpu(int cpu); +#else +static inline void acpi_init_rintc_map(void) { } +static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) +{ + return NULL; +} + #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 81d448c41714..89e142611c84 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -24,6 +24,51 @@ EXPORT_SYMBOL(acpi_disabled); int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */ EXPORT_SYMBOL(acpi_pci_disabled); +static struct acpi_madt_rintc cpu_madt_rintc[NR_CPUS]; + +static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) +{ + struct acpi_madt_rintc *rintc = (struct acpi_madt_rintc *)header; + int cpuid; + + if (!(rintc->flags & ACPI_MADT_ENABLED)) + return 0; + + cpuid = riscv_hartid_to_cpuid(rintc->hart_id); + /* + * When CONFIG_SMP is disabled, mapping won't be created for + * all cpus. + * CPUs more than num_possible_cpus, will be ignored. + */ + if (cpuid >= 0 && cpuid < num_possible_cpus()) + cpu_madt_rintc[cpuid] = *rintc; + + return 0; +} + +/* + * Instead of parsing (and freeing) the ACPI table, cache + * the RINTC structures since they are frequently used + * like in cpuinfo. + */ +void __init acpi_init_rintc_map(void) +{ + if (acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_madt_rintc, 0) <= 0) { + pr_err("No valid RINTC entries exist\n"); + BUG(); + } +} + +struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) +{ + return &cpu_madt_rintc[cpu]; +} + +u32 get_acpi_id_for_cpu(int cpu) +{ + return acpi_cpu_get_madt_rintc(cpu)->uid; +} + /* * __acpi_map_table() will be called before paging_init(), so early_ioremap() * or early_memremap() should be called here to for ACPI table mapping. diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index 9fb839074e16..a44c7fcde12f 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -21,6 +21,7 @@ #include #include +#include #include #include #include @@ -293,6 +294,9 @@ void __init setup_arch(char **cmdline_p) setup_smp(); #endif + if (!acpi_disabled) + acpi_init_rintc_map(); + riscv_init_cbo_blocksizes(); riscv_fill_hwcap(); apply_boot_alternatives(); From patchwork Mon May 8 11:52:25 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 679973 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D87B8C7EE31 for ; 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.54.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:09 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Palmer Dabbelt Subject: [PATCH V5 09/21] drivers/acpi: RISC-V: Add RHCT related code Date: Mon, 8 May 2023 17:22:25 +0530 Message-Id: <20230508115237.216337-10-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org RHCT is a new table defined for RISC-V to communicate the features of the CPU to the OS. Create a new architecture folder in drivers/acpi and add RHCT parsing code. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Palmer Dabbelt --- arch/riscv/include/asm/acpi.h | 8 ++++ drivers/acpi/Makefile | 2 + drivers/acpi/riscv/Makefile | 2 + drivers/acpi/riscv/rhct.c | 83 +++++++++++++++++++++++++++++++++++ 4 files changed, 95 insertions(+) create mode 100644 drivers/acpi/riscv/Makefile create mode 100644 drivers/acpi/riscv/rhct.c diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 6519529c8bdf..39471759bec1 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -62,6 +62,8 @@ static inline void arch_fix_phys_package_id(int num, u32 slot) { } void acpi_init_rintc_map(void); struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu); u32 get_acpi_id_for_cpu(int cpu); +int acpi_get_riscv_isa(struct acpi_table_header *table, + unsigned int cpu, const char **isa); #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) @@ -69,6 +71,12 @@ static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) return NULL; } +static inline int acpi_get_riscv_isa(struct acpi_table_header *table, + unsigned int cpu, const char **isa) +{ + return -EINVAL; +} + #endif /* CONFIG_ACPI */ #endif /*_ASM_ACPI_H*/ diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile index feb36c0b9446..3fc5a0d54f6e 100644 --- a/drivers/acpi/Makefile +++ b/drivers/acpi/Makefile @@ -131,3 +131,5 @@ obj-y += dptf/ obj-$(CONFIG_ARM64) += arm64/ obj-$(CONFIG_ACPI_VIOT) += viot.o + +obj-$(CONFIG_RISCV) += riscv/ diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile new file mode 100644 index 000000000000..8b3b126e0b94 --- /dev/null +++ b/drivers/acpi/riscv/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +obj-y += rhct.o diff --git a/drivers/acpi/riscv/rhct.c b/drivers/acpi/riscv/rhct.c new file mode 100644 index 000000000000..b280b3e9c7d9 --- /dev/null +++ b/drivers/acpi/riscv/rhct.c @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2022-2023, Ventana Micro Systems Inc + * Author: Sunil V L + * + */ + +#define pr_fmt(fmt) "ACPI: RHCT: " fmt + +#include + +static struct acpi_table_header *acpi_get_rhct(void) +{ + static struct acpi_table_header *rhct; + acpi_status status; + + /* + * RHCT will be used at runtime on every CPU, so we + * don't need to call acpi_put_table() to release the table mapping. + */ + if (!rhct) { + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); + if (ACPI_FAILURE(status)) { + pr_warn_once("No RHCT table found\n"); + return NULL; + } + } + + return rhct; +} + +/* + * During early boot, the caller should call acpi_get_table() and pass its pointer to + * these functions(and free up later). At run time, since this table can be used + * multiple times, NULL may be passed in order to use the cached table. + */ +int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa) +{ + struct acpi_rhct_node_header *node, *ref_node, *end; + u32 size_hdr = sizeof(struct acpi_rhct_node_header); + u32 size_hartinfo = sizeof(struct acpi_rhct_hart_info); + struct acpi_rhct_hart_info *hart_info; + struct acpi_rhct_isa_string *isa_node; + struct acpi_table_rhct *rhct; + u32 *hart_info_node_offset; + u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu); + + BUG_ON(acpi_disabled); + + if (!table) { + rhct = (struct acpi_table_rhct *)acpi_get_rhct(); + if (!rhct) + return -ENOENT; + } else { + rhct = (struct acpi_table_rhct *)table; + } + + end = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->header.length); + + for (node = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->node_offset); + node < end; + node = ACPI_ADD_PTR(struct acpi_rhct_node_header, node, node->length)) { + if (node->type == ACPI_RHCT_NODE_TYPE_HART_INFO) { + hart_info = ACPI_ADD_PTR(struct acpi_rhct_hart_info, node, size_hdr); + hart_info_node_offset = ACPI_ADD_PTR(u32, hart_info, size_hartinfo); + if (acpi_cpu_id != hart_info->uid) + continue; + + for (int i = 0; i < hart_info->num_offsets; i++) { + ref_node = ACPI_ADD_PTR(struct acpi_rhct_node_header, + rhct, hart_info_node_offset[i]); + if (ref_node->type == ACPI_RHCT_NODE_TYPE_ISA_STRING) { + isa_node = ACPI_ADD_PTR(struct acpi_rhct_isa_string, + ref_node, size_hdr); + *isa = isa_node->isa; + return 0; + } + } + } + } + + return -1; +} From patchwork Mon May 8 11:52:26 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 680293 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DAC97C77B75 for ; Mon, 8 May 2023 11:56:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235033AbjEHL4D (ORCPT ); Mon, 8 May 2023 07:56:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57134 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236529AbjEHLzF (ORCPT ); Mon, 8 May 2023 07:55:05 -0400 Received: from mail-pl1-x62e.google.com (mail-pl1-x62e.google.com [IPv6:2607:f8b0:4864:20::62e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7928741555 for ; Mon, 8 May 2023 04:54:19 -0700 (PDT) Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-1aaf21bb427so31037355ad.1 for ; Mon, 08 May 2023 04:54:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546858; x=1686138858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yNB5noEZPasx/OngqcP7wy15OXtx85aYSDWecQ1qX3I=; b=bdUOpEXd7GBDCNnXUsvG3ckYwryUiZjYQOSav9QR4GUG/8ayaYYTDJbjXmtRT0zXHg +eV9YbxhRW91B0jQB9sWuZdtdciKI6upjJ8I4udwA4rx3uxaZH3/cHQQIYX/BwmUfzpq NsqTsFR3sE7Sw5k7La5uhu2K1GfIJvVKlyUsE9CInG6jxddpYqF2680jb/sf33vgVttu fcjUSpTZANBOqnqT1fW/y+mY7OP8uyDjndoX8ITOfZTo5j6GWdLzl5yLKDZo9yepSUTZ j7MCN0w4HtF1A7pQPYPkQoqB1NHg8jHylF85r+oebUh2luVMl3g79mLXG0a54WpOSPgX TqFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546858; x=1686138858; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yNB5noEZPasx/OngqcP7wy15OXtx85aYSDWecQ1qX3I=; b=T42o5OvV9Ec4FA3meRdJfYrp9oMgvupw2FkTiBIvJ6oIDpE58wRD4hvsRqNv0g1ZCu vRRfTapa7FYXBb42ja8reQMiOXREJ0cLCq6+NpFCwRmlKZZ4HilG6+6u/DgL2c+yeu6H sBoZ7sFqHMByqxylIm4N2pDun7igu5ZlqGl5ZPhz/VuyYUzUTfPhg4OO6cSTDdPlj7Q1 auJ6DslYs0DhK8gbK237vv/AMCESRsz/UaOfTHivqBCHP5lpmPA9WVmGcCz7ZP04R1LC GXJWxeHtvymlayCgVdWak8b8//eX2eCQNaTSoqvw8GHa9RgbvdzWMARRz6wvE9fesQJf 0lyQ== X-Gm-Message-State: AC+VfDzlQj1r+3+Z2OGUc3p/x752H3GpzpjzKL8KWxfopjCQQEmOHvNp V2zMWf1FxeSvXF/1KgNZEMIFRQ== X-Google-Smtp-Source: ACHHUZ5TYA+zQ+rNZLCdLbZt13LOcV1erZfJUbyqxcsnGU9IG5qaZ/PIek5MVqznsb13nf9WEs/MHw== X-Received: by 2002:a17:902:c40b:b0:1aa:fd48:f5e2 with SMTP id k11-20020a170902c40b00b001aafd48f5e2mr13594721plk.32.1683546858666; Mon, 08 May 2023 04:54:18 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:18 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Conor Dooley , Andrew Jones , Palmer Dabbelt Subject: [PATCH V5 10/21] RISC-V: smpboot: Create wrapper setup_smp() Date: Mon, 8 May 2023 17:22:26 +0530 Message-Id: <20230508115237.216337-11-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org setup_smp() currently assumes DT-based platforms. To enable ACPI, first make this a wrapper function and move existing code to a separate DT-specific function. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones Reviewed-by: Palmer Dabbelt --- arch/riscv/kernel/smpboot.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index 445a4efee267..a2e66126b733 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -70,7 +70,7 @@ void __init smp_prepare_cpus(unsigned int max_cpus) } } -void __init setup_smp(void) +static void __init of_parse_and_init_cpus(void) { struct device_node *dn; unsigned long hart; @@ -116,6 +116,11 @@ void __init setup_smp(void) } } +void __init setup_smp(void) +{ + of_parse_and_init_cpus(); +} + static int start_secondary_cpu(int cpu, struct task_struct *tidle) { if (cpu_ops[cpu]->cpu_start) From patchwork Mon May 8 11:52:27 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 679972 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C4BE0C77B7F for ; Mon, 8 May 2023 11:56:16 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236373AbjEHL4O (ORCPT ); Mon, 8 May 2023 07:56:14 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236564AbjEHLzN (ORCPT ); Mon, 8 May 2023 07:55:13 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id C2C6CA5E4 for ; Mon, 8 May 2023 04:54:28 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1aaef97652fso29739355ad.0 for ; Mon, 08 May 2023 04:54:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546867; x=1686138867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xPSUnhfUj53RcidJeP5kL6gGwZHEmDmCHUal6KZm638=; b=B89bgCvRmGEMAUxP/QGsfNQm2gjwxDg+QrprfVD8J+SUcbDL0JuefH8yg3QbKPSusP 8rH/5FTe8ecRIqNzZRrZVua1E97KFmKTWvsf05A6XAiAhMWHWulc88M5zsYV9fPB6BS/ MG1FdVheDOnn8ZrtyfRM2iqXy2fuTrATFp+FIVtPvWglUNAhf60NlY4E0EgKpwIVymAG 22Z/iJxvTrTLUL6IMkcXxeYFv6Sm+2OuG3qF25Rr4SJJxf68+Ai+1zi6h4/KC4tNa7G2 WrEHfPZyxjuUyQJiZAjQ56tNOS0EUPhcyh8ipbTdoOLoQSzzpNN6x9F1W2Hpj6hP3F0Z eKaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546867; x=1686138867; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xPSUnhfUj53RcidJeP5kL6gGwZHEmDmCHUal6KZm638=; b=IMf7k45oPBj1ppTL+qIM64zPr4a3Xx1P3SPDu4Mxmcf5IByPMlE5AjEEXwqhHiHhhi 2A7+ENOGcD+y9Cf6tnpLbzwxVDqn8ACtM0wjtdM4e8vV2BbozY2fQA2WjOeTpa+Ot9oH itE5R0s3bFfny/qMNU7A/O4IbdThND9wA1AjrY4V9cZyIuYs9fvZfTyfaBSaECOKLsYC mBhf8U20XQpTF7YqrpowWEH4z37WE2+dVP0Kvg0xygcHU5HB4bAKTdEXgIziNdDhOv5A X4hWLYTNXreRBElaxHnQ9+Cco87iyqxDNQVblUkp32AgkRCUX2tjrymtGpjDQI9uzrpA RE3g== X-Gm-Message-State: AC+VfDyynnIgSntVsTx7zIwm90uX8oq3pK094mb5g3+ihywTcvQ1SzYp SoZUn6FXQdrb0hIYf9sw9od22VVGNBJwZfaJmNo= X-Google-Smtp-Source: ACHHUZ6Gz6YRt/rRbsWfX8rM4EyT+3FO881Otsm/ltvRREx1WVjAZpVesBHDJ+4NomT8Orb6vkyrsA== X-Received: by 2002:a17:902:f547:b0:1ab:bfb:4b6e with SMTP id h7-20020a170902f54700b001ab0bfb4b6emr13666475plf.31.1683546866800; Mon, 08 May 2023 04:54:26 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.54.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:26 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Conor Dooley , Andrew Jones Subject: [PATCH V5 11/21] RISC-V: smpboot: Add ACPI support in setup_smp() Date: Mon, 8 May 2023 17:22:27 +0530 Message-Id: <20230508115237.216337-12-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Enable SMP boot on ACPI based platforms by using the RINTC structures in the MADT table. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/include/asm/acpi.h | 2 + arch/riscv/kernel/smpboot.c | 72 ++++++++++++++++++++++++++++++++++- 2 files changed, 73 insertions(+), 1 deletion(-) diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h index 39471759bec1..f71ce21ff684 100644 --- a/arch/riscv/include/asm/acpi.h +++ b/arch/riscv/include/asm/acpi.h @@ -64,6 +64,8 @@ struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu); u32 get_acpi_id_for_cpu(int cpu); int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa); + +static inline int acpi_numa_get_nid(unsigned int cpu) { return NUMA_NO_NODE; } #else static inline void acpi_init_rintc_map(void) { } static inline struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu) diff --git a/arch/riscv/kernel/smpboot.c b/arch/riscv/kernel/smpboot.c index a2e66126b733..67bc5ef3e8b2 100644 --- a/arch/riscv/kernel/smpboot.c +++ b/arch/riscv/kernel/smpboot.c @@ -8,6 +8,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -70,6 +71,72 @@ void __init smp_prepare_cpus(unsigned int max_cpus) } } +#ifdef CONFIG_ACPI +static unsigned int cpu_count = 1; + +static int __init acpi_parse_rintc(union acpi_subtable_headers *header, const unsigned long end) +{ + unsigned long hart; + static bool found_boot_cpu; + struct acpi_madt_rintc *processor = (struct acpi_madt_rintc *)header; + + /* + * Each RINTC structure in MADT will have a flag. If ACPI_MADT_ENABLED + * bit in the flag is not enabled, it means OS should not try to enable + * the cpu to which RINTC belongs. + */ + if (!(processor->flags & ACPI_MADT_ENABLED)) + return 0; + + if (BAD_MADT_ENTRY(processor, end)) + return -EINVAL; + + acpi_table_print_madt_entry(&header->common); + + hart = processor->hart_id; + if (hart == INVALID_HARTID) { + pr_warn("Invalid hartid\n"); + return 0; + } + + if (hart == cpuid_to_hartid_map(0)) { + BUG_ON(found_boot_cpu); + found_boot_cpu = true; + early_map_cpu_to_node(0, acpi_numa_get_nid(cpu_count)); + return 0; + } + + if (cpu_count >= NR_CPUS) { + pr_warn("NR_CPUS is too small for the number of ACPI tables.\n"); + return 0; + } + + cpuid_to_hartid_map(cpu_count) = hart; + early_map_cpu_to_node(cpu_count, acpi_numa_get_nid(cpu_count)); + cpu_count++; + + return 0; +} + +static void __init acpi_parse_and_init_cpus(void) +{ + int cpuid; + + cpu_set_ops(0); + + acpi_table_parse_madt(ACPI_MADT_TYPE_RINTC, acpi_parse_rintc, 0); + + for (cpuid = 1; cpuid < nr_cpu_ids; cpuid++) { + if (cpuid_to_hartid_map(cpuid) != INVALID_HARTID) { + cpu_set_ops(cpuid); + set_cpu_possible(cpuid, true); + } + } +} +#else +#define acpi_parse_and_init_cpus(...) do { } while (0) +#endif + static void __init of_parse_and_init_cpus(void) { struct device_node *dn; @@ -118,7 +185,10 @@ static void __init of_parse_and_init_cpus(void) void __init setup_smp(void) { - of_parse_and_init_cpus(); + if (acpi_disabled) + of_parse_and_init_cpus(); + else + acpi_parse_and_init_cpus(); } static int start_secondary_cpu(int cpu, struct task_struct *tidle) From patchwork Mon May 8 11:52:28 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 680292 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B7350C77B73 for ; Mon, 8 May 2023 11:56:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236437AbjEHL43 (ORCPT ); Mon, 8 May 2023 07:56:29 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236586AbjEHLzQ (ORCPT ); Mon, 8 May 2023 07:55:16 -0400 Received: from mail-pl1-x629.google.com (mail-pl1-x629.google.com [IPv6:2607:f8b0:4864:20::629]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8B1CD44BEB for ; Mon, 8 May 2023 04:54:35 -0700 (PDT) Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-1aaea43def7so29597515ad.2 for ; Mon, 08 May 2023 04:54:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546875; x=1686138875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=/XDEVfXqS4FP0KdGTx6jL5yfIe6/oO8gDCIQfJ1eWZE=; b=NcufZwwvsj6/Boyj1pZX9SDoMFX3Dm2oty/qRNBJOjRjuNJFqKfLDuz7KnZhPMErND hzMLFmmVo206PCVp9d7A+QuEFdVAvPQsbM/vMN5sifyGfmgdxW3gVzHHSWPvKPArOvik YIAfNdCYYluT2mdY/5ynJqUWZ6Juz4WRIwj6Ip9TdigxU8k/hWnFJqi14QGEMNF80tah vQYIR/at9zkw9K58cy2JXFTG0ONm0RMZMBw0iyqx5FimbSkg7TOJEWNpDfjK345YX5Ji 3dFtlaLRzMTCuxo+IZaZKoQXFtXhTHUQyNbLjYPc2TgTkRFaX+pOViv/azy0VTr/QdHk snAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546875; x=1686138875; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/XDEVfXqS4FP0KdGTx6jL5yfIe6/oO8gDCIQfJ1eWZE=; b=VWkT464KkTXTGCUtqmREkmTNaLeSI1pYOdsfvl1qq96bZ4cIO5kyId579Xm/dWLqjo uRGOMctTFPOiJs1k2C74ALEf320ssR5dC+o1RggjkkVGhYg8WlO65tuSdunVa2qkpyrr 8cFfxgo5KbxfEN6RqEJBqVJIWypA2I5SBB0aI2IovvtiriONelBkiRdhYhRjPxYeFEOs 2R0dYHph+dTaL+CIJh0Eak3H2bzINwGPuSjypGE6pqGA6Uyfgk4f1MTyJIKktNbVvXWH 5ehemUrSwST7pCDwfWJewIvFfmDUFvjLND1thPqfYzL7SszM3qi3chEdITk+Cg8HatiY nV4w== X-Gm-Message-State: AC+VfDxVOeWoS1ztgkMjSrSh+8w0CRKkOS3K3hZR0vmoYBglX/AENzBM clChEJBQttTOf31pNUpMFfIg6w== X-Google-Smtp-Source: ACHHUZ5hMTFJTQPYhgpNKN39ORLnHJpWwdogloO8Lwo1VmnXnF01HpatA+Awvt6a3JK3sbEX6Ku1xg== X-Received: by 2002:a17:903:2308:b0:19d:778:ff5 with SMTP id d8-20020a170903230800b0019d07780ff5mr13151647plh.15.1683546874762; Mon, 08 May 2023 04:54:34 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.54.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:34 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , Conor Dooley , Andrew Jones Subject: [PATCH V5 12/21] RISC-V: only iterate over possible CPUs in ISA string parser Date: Mon, 8 May 2023 17:22:28 +0530 Message-Id: <20230508115237.216337-13-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org During boot we call riscv_of_processor_hartid() for each hart that we add to the possible cpus list. Repeating the call again here is not required, if we iterate over the list of possible CPUs, rather than the list of all CPUs. The call to of_property_read_string() for "riscv,isa" cannot fail either, as it has previously succeeded in riscv_of_processor_hartid(), but leaving in the error checking makes the operation of the loop more obvious & provides leeway for future refactoring of riscv_of_processor_hartid(). Signed-off-by: Sunil V L Co-developed-by: Conor Dooley Signed-off-by: Conor Dooley Reviewed-by: Andrew Jones --- arch/riscv/kernel/cpufeature.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index b1d6b7e4b829..c607db2c842c 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -99,7 +100,7 @@ void __init riscv_fill_hwcap(void) char print_str[NUM_ALPHA_EXTS + 1]; int i, j, rc; unsigned long isa2hwcap[26] = {0}; - unsigned long hartid; + unsigned int cpu; isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; isa2hwcap['m' - 'a'] = COMPAT_HWCAP_ISA_M; @@ -112,16 +113,20 @@ void __init riscv_fill_hwcap(void) bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); - for_each_of_cpu_node(node) { + for_each_possible_cpu(cpu) { unsigned long this_hwcap = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; - rc = riscv_of_processor_hartid(node, &hartid); - if (rc < 0) + node = of_cpu_device_node_get(cpu); + if (!node) { + pr_warn("Unable to find cpu node\n"); continue; + } - if (of_property_read_string(node, "riscv,isa", &isa)) { + rc = of_property_read_string(node, "riscv,isa", &isa); + of_node_put(node); + if (rc) { pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); continue; } From patchwork Mon May 8 11:52:29 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 679971 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC2A5C7EE23 for ; Mon, 8 May 2023 11:56:48 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236460AbjEHL4q (ORCPT ); Mon, 8 May 2023 07:56:46 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56322 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233575AbjEHLzt (ORCPT ); Mon, 8 May 2023 07:55:49 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id DAA90431D8 for ; Mon, 8 May 2023 04:54:43 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1aaef97652fso29742595ad.0 for ; Mon, 08 May 2023 04:54:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546883; x=1686138883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=fWBNL8Yoxn6F5OA39mGQO+nKX7WWRbncPVBB9F2/Cag=; b=UTsXWuWmC1/7OSeoOkGn1KtYJ4R67wvdM1zq1WLN+1ByrSweQv67hbCW21chigqyUL RoLkjnU29qDA2eL1AmAYAKdZpKeOZFV2drbpvALpFYEos5q8DrWTc0KulaF49nmXAtxs T58TcPDImDQi7FarA7t1zpdQnq/s2chlB7/U1Ayte6Xky8oFb9z5l0IvWzkCp6PyAHpp XgNZKJkSZRvGaQCsPymV7tY68VEyhsqUsUTEJBSQF+t9coEokHQ2Ccp5AkD76Zz/V7Sq KoBHjvURG9QFm9hHkIcJ1XRk3wsGHhH2zQejXHjZKWxe/9ZDXgLZYHTgrRBDnFn+tXBS 4Fcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546883; x=1686138883; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=fWBNL8Yoxn6F5OA39mGQO+nKX7WWRbncPVBB9F2/Cag=; b=PRGwWqYIRE7akNjKmUHlcJXVjgFHD88hU+Z0ZxLfihN458qvlIz03SX2kEJQTLueeq jHxXhggL/YYvW4BkK9nNtgRWZq8BUC0Hg74hOl2TiXN3r6qeTtQWWg8nC3SGS8PM5eeO f6B8LtE+JSgBVmnth3H6LeJ2oTd+vZmFJl0guuK6BBct/mBNnFxZ0Ow3sCaSYbhghGxR b3cfZs8B+ktP099z+KgU+91Ti52d55ndTiCxKHcqQQxH4cGGS90L6DDrZ7RKmgBUN/x/ yjRzN0/ude+2hTmdquKC9OFu6lIerIOjDmqXhcq9dlsNOnwixFqiOmaT39u5pl87DYmp yAUw== X-Gm-Message-State: AC+VfDzjJ1sC9BJ0MWIE9V4IgYKkGnYQ8AY4obMkfK3cg+n3KH9OL2ri LRyPdaJrtq5Pmtr0EtpcvksEmA== X-Google-Smtp-Source: ACHHUZ5fapwQi2xeO87i4COCX6B1jL+21dW5efwIR1o/iBifUL/k3oeJ8FMjBSZShytx/bDfbkIfDQ== X-Received: by 2002:a17:902:aa47:b0:1a9:9c5d:9fac with SMTP id c7-20020a170902aa4700b001a99c5d9facmr8993592plr.33.1683546883069; Mon, 08 May 2023 04:54:43 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.54.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:42 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 13/21] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Date: Mon, 8 May 2023 17:22:29 +0530 Message-Id: <20230508115237.216337-14-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On ACPI based systems, the information about the hart like ISA is provided by the RISC-V Hart Capabilities Table (RHCT). Enable filling up hwcap structure based on the information in RHCT. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/cpufeature.c | 41 +++++++++++++++++++++++++--------- 1 file changed, 31 insertions(+), 10 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index c607db2c842c..6ba8e20c5346 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -6,6 +6,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -13,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -100,6 +102,8 @@ void __init riscv_fill_hwcap(void) char print_str[NUM_ALPHA_EXTS + 1]; int i, j, rc; unsigned long isa2hwcap[26] = {0}; + struct acpi_table_header *rhct; + acpi_status status; unsigned int cpu; isa2hwcap['i' - 'a'] = COMPAT_HWCAP_ISA_I; @@ -113,22 +117,36 @@ void __init riscv_fill_hwcap(void) bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX); + if (!acpi_disabled) { + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct); + if (ACPI_FAILURE(status)) + return; + } + for_each_possible_cpu(cpu) { unsigned long this_hwcap = 0; DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX); const char *temp; - node = of_cpu_device_node_get(cpu); - if (!node) { - pr_warn("Unable to find cpu node\n"); - continue; - } + if (acpi_disabled) { + node = of_cpu_device_node_get(cpu); + if (!node) { + pr_warn("Unable to find cpu node\n"); + continue; + } - rc = of_property_read_string(node, "riscv,isa", &isa); - of_node_put(node); - if (rc) { - pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); - continue; + rc = of_property_read_string(node, "riscv,isa", &isa); + of_node_put(node); + if (rc) { + pr_warn("Unable to find \"riscv,isa\" devicetree entry\n"); + continue; + } + } else { + rc = acpi_get_riscv_isa(rhct, cpu, &isa); + if (rc < 0) { + pr_warn("Unable to get ISA for the hart - %d\n", cpu); + continue; + } } temp = isa; @@ -265,6 +283,9 @@ void __init riscv_fill_hwcap(void) bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX); } + if (!acpi_disabled && rhct) + acpi_put_table((struct acpi_table_header *)rhct); + /* We don't support systems with F but without D, so mask those out * here. */ if ((elf_hwcap & COMPAT_HWCAP_ISA_F) && !(elf_hwcap & COMPAT_HWCAP_ISA_D)) { From patchwork Mon May 8 11:52:30 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 680291 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id AAFA0C77B73 for ; Mon, 8 May 2023 11:57:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233569AbjEHL5D (ORCPT ); Mon, 8 May 2023 07:57:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56762 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236370AbjEHL4O (ORCPT ); Mon, 8 May 2023 07:56:14 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0B8511C0F3 for ; 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.54.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:51 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 14/21] RISC-V: cpu: Enable cpuinfo for ACPI systems Date: Mon, 8 May 2023 17:22:30 +0530 Message-Id: <20230508115237.216337-15-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On ACPI based platforms, few details like ISA need to be read from the ACPI table. Enable cpuinfo on ACPI based systems. ACPI has nothing similar to DT compatible property for each CPU. Hence, cpuinfo will not print "uarch". Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/cpu.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index c96aa56cf1c7..5de6fb703cc2 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -3,10 +3,12 @@ * Copyright (C) 2012 Regents of the University of California */ +#include #include #include #include #include +#include #include #include #include @@ -283,23 +285,35 @@ static void c_stop(struct seq_file *m, void *v) static int c_show(struct seq_file *m, void *v) { unsigned long cpu_id = (unsigned long)v - 1; - struct device_node *node = of_get_cpu_node(cpu_id, NULL); struct riscv_cpuinfo *ci = per_cpu_ptr(&riscv_cpuinfo, cpu_id); + struct device_node *node; const char *compat, *isa; seq_printf(m, "processor\t: %lu\n", cpu_id); seq_printf(m, "hart\t\t: %lu\n", cpuid_to_hartid_map(cpu_id)); - if (!of_property_read_string(node, "riscv,isa", &isa)) - print_isa(m, isa); - print_mmu(m); - if (!of_property_read_string(node, "compatible", &compat) - && strcmp(compat, "riscv")) - seq_printf(m, "uarch\t\t: %s\n", compat); + + if (acpi_disabled) { + node = of_get_cpu_node(cpu_id, NULL); + if (!of_property_read_string(node, "riscv,isa", &isa)) + print_isa(m, isa); + + print_mmu(m); + if (!of_property_read_string(node, "compatible", &compat) && + strcmp(compat, "riscv")) + seq_printf(m, "uarch\t\t: %s\n", compat); + + of_node_put(node); + } else { + if (!acpi_get_riscv_isa(NULL, cpu_id, &isa)) + print_isa(m, isa); + + print_mmu(m); + } + seq_printf(m, "mvendorid\t: 0x%lx\n", ci->mvendorid); seq_printf(m, "marchid\t\t: 0x%lx\n", ci->marchid); seq_printf(m, "mimpid\t\t: 0x%lx\n", ci->mimpid); seq_puts(m, "\n"); - of_node_put(node); return 0; } From patchwork Mon May 8 11:52:31 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 679970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 30E32C77B73 for ; Mon, 8 May 2023 11:57:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233575AbjEHL5Y (ORCPT ); Mon, 8 May 2023 07:57:24 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56290 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234291AbjEHL4r (ORCPT ); Mon, 8 May 2023 07:56:47 -0400 Received: from mail-pl1-x634.google.com (mail-pl1-x634.google.com [IPv6:2607:f8b0:4864:20::634]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0DDD65B9A for ; Mon, 8 May 2023 04:55:07 -0700 (PDT) Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-1a50cb65c92so30389515ad.0 for ; Mon, 08 May 2023 04:55:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546900; x=1686138900; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=GSuTggFYj3JSbFizfFEsySbatkGCHwC0oNgPzvEucIg=; b=OwnBVNyw27EdkLus1jTOuwbndB2EL2oVzQ7k7WqNfE23/8qlo+tk8UFosj4+DGtIEM we9+O1U8hj7m0aWDcbRQxN5ACgyeeG2VJSTA+BGXf0Lc91Yu3v8w6YkG0P9tVDrl1Pjb M/Jj9HtGkwPWIa+gtgQXauU7tRECTZ4MSLSX7eV6SQDAJy5Q22e88y0ohlQ2w+9nI9vm 4cLX6IAHT9CSG0m6PilY/qusyz8K+wT4LRCKXTzhosGOyZItkPHdE81/RAXq3F3cHu9l MrD0rX8pil+aPxPPGWzdKtYQEVz9zLmR7W/XzVVJNkvN4gGzVcNn/RllSUoQVTVxW2HZ pP5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546900; x=1686138900; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GSuTggFYj3JSbFizfFEsySbatkGCHwC0oNgPzvEucIg=; b=PyHLujaUyIygDrjFnwpMXSBzSYjkW9Z7TsYn1bg56EMbMOVdCH0H7eRRJBiSZuPeEw RnqkPfBIRzWwSQl+OuoO0VcWAo7hZ7NC1rypm05FbfI1wqSSAVlihwahv8w1zyRjpDPE 5hR00n4j4ZC8O/8ffCerSDvRR8UNoB53uWJ8oRJnTl/cFXs7HtuDcUPTaAD0ZvB2O9oY LguGjchWY1XkQ7XHsSdY8M5DubeE6pYMSDwUWR5lXnEhx/YKn4V/3w8bV8X+EEVLGPle s+esU5miZarusb3KNc5wZZcjGCBYDKTW1DcL6+N4BQ84c5VMvk6TBJn24tODLqyYlYS6 9V5A== X-Gm-Message-State: AC+VfDzHkOIY/KuXLmWK3eSn6Qi+ar/VAYGp96otIX0b15vVrEv5YZ8a SocE3T87rKFLBF/Kc/tncqT5lg== X-Google-Smtp-Source: ACHHUZ74VlINKqqw1M1Nzm9Knvlkg1O1yI8Vgz31f0P7xgzVEMnDcYaHW6CpqAaMkpJZUju498eICg== X-Received: by 2002:a17:902:eccc:b0:1a6:6b85:7b4a with SMTP id a12-20020a170902eccc00b001a66b857b4amr12146859plh.18.1683546899877; Mon, 08 May 2023 04:54:59 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.54.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:54:59 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 15/21] irqchip/riscv-intc: Add ACPI support Date: Mon, 8 May 2023 17:22:31 +0530 Message-Id: <20230508115237.216337-16-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add support for initializing the RISC-V INTC driver on ACPI platforms. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- drivers/irqchip/irq-riscv-intc.c | 70 +++++++++++++++++++++++++------- 1 file changed, 55 insertions(+), 15 deletions(-) diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c index f229e3e66387..4adeee1bc391 100644 --- a/drivers/irqchip/irq-riscv-intc.c +++ b/drivers/irqchip/irq-riscv-intc.c @@ -6,6 +6,7 @@ */ #define pr_fmt(fmt) "riscv-intc: " fmt +#include #include #include #include @@ -112,6 +113,30 @@ static struct fwnode_handle *riscv_intc_hwnode(void) return intc_domain->fwnode; } +static int __init riscv_intc_init_common(struct fwnode_handle *fn) +{ + int rc; + + intc_domain = irq_domain_create_linear(fn, BITS_PER_LONG, + &riscv_intc_domain_ops, NULL); + if (!intc_domain) { + pr_err("unable to add IRQ domain\n"); + return -ENXIO; + } + + rc = set_handle_irq(&riscv_intc_irq); + if (rc) { + pr_err("failed to set irq handler\n"); + return rc; + } + + riscv_set_intc_hwnode_fn(riscv_intc_hwnode); + + pr_info("%d local interrupts mapped\n", BITS_PER_LONG); + + return 0; +} + static int __init riscv_intc_init(struct device_node *node, struct device_node *parent) { @@ -133,24 +158,39 @@ static int __init riscv_intc_init(struct device_node *node, if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) return 0; - intc_domain = irq_domain_add_linear(node, BITS_PER_LONG, - &riscv_intc_domain_ops, NULL); - if (!intc_domain) { - pr_err("unable to add IRQ domain\n"); - return -ENXIO; - } + return riscv_intc_init_common(of_node_to_fwnode(node)); +} - rc = set_handle_irq(&riscv_intc_irq); - if (rc) { - pr_err("failed to set irq handler\n"); - return rc; - } +IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); - riscv_set_intc_hwnode_fn(riscv_intc_hwnode); +#ifdef CONFIG_ACPI - pr_info("%d local interrupts mapped\n", BITS_PER_LONG); +static int __init riscv_intc_acpi_init(union acpi_subtable_headers *header, + const unsigned long end) +{ + struct fwnode_handle *fn; + struct acpi_madt_rintc *rintc; - return 0; + rintc = (struct acpi_madt_rintc *)header; + + /* + * The ACPI MADT will have one INTC for each CPU (or HART) + * so riscv_intc_acpi_init() function will be called once + * for each INTC. We only do INTC initialization + * for the INTC belonging to the boot CPU (or boot HART). + */ + if (riscv_hartid_to_cpuid(rintc->hart_id) != smp_processor_id()) + return 0; + + fn = irq_domain_alloc_named_fwnode("RISCV-INTC"); + if (!fn) { + pr_err("unable to allocate INTC FW node\n"); + return -ENOMEM; + } + + return riscv_intc_init_common(fn); } -IRQCHIP_DECLARE(riscv, "riscv,cpu-intc", riscv_intc_init); +IRQCHIP_ACPI_DECLARE(riscv_intc, ACPI_MADT_TYPE_RINTC, NULL, + ACPI_MADT_RINTC_VERSION_V1, riscv_intc_acpi_init); +#endif From patchwork Mon May 8 11:52:32 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 680290 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B85E6C77B75 for ; Mon, 8 May 2023 11:57:39 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234973AbjEHL5i (ORCPT ); Mon, 8 May 2023 07:57:38 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56670 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234736AbjEHL5B (ORCPT ); Mon, 8 May 2023 07:57:01 -0400 Received: from mail-pl1-x62c.google.com (mail-pl1-x62c.google.com [IPv6:2607:f8b0:4864:20::62c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id ABAEB46409 for ; Mon, 8 May 2023 04:55:11 -0700 (PDT) Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-1aaebed5bd6so30379655ad.1 for ; Mon, 08 May 2023 04:55:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546907; x=1686138907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=IS1GWILYl7Q6QsdApEh939z6h09NwhOHpvU6XTgdfRk=; b=eJP89kRror/WxWaBzogTWwKQS/PyObvkTktOyW2ST1w6dYrfbIM25CrRJEoriiGQPv jBw7v2p3iubHma3A00VZI1GxTututaNq3cEMEB+VpqfPtLgUM9ldNDYuerBTRWKmM7HO Lceb3PA1kqCbvSCD9bENVg7C0g0Thk/GkHZNcEGymFu7CY4aWIYRjmikxQwgnKx9rwzO tSjzRzpNulsyDBmv+tYYCYByckjjCpnnnyHxJGnbxutWrWtqV71BjhaIl0FcKjMZ539i O/gtCtD7xMfoH2ESqmBOdrXjxLrTeJUIMhCeYnp5nlw9g4GL5wD79puJaehSyrvk/xSt K2Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546907; x=1686138907; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IS1GWILYl7Q6QsdApEh939z6h09NwhOHpvU6XTgdfRk=; b=NFBRQhYl33cMkS+0pcOgyipkFM01JFr2Ogg2MV9RfVePLA/rCFEWiKEmHRn6jYdm+f Z4m2W2CCXt7Mhu5FGsrtKRxt9J3KcKFRfwTHh/NSoRUaedBTYiBskbFUr3SxQ8WYa5AP itxHRwOzyF/LUQeD8hKTWyhtBOW+DFVduj1b4gELhrrL3Br0YWvZO60F+XgBEDZzOKoe X8ms2Qz98M04rXeKWCmVNQEgYGge/Y8MwYxpAC1nz6iznpqn7eD0WYGrqVYdmPhxw74P fBwEkqfv2FzQLdMBC941xtm0+M6peBlhrvI1//S58Q4ltoda6WKQNnvq/QciOzRoj2dV AwRg== X-Gm-Message-State: AC+VfDyOfqSMDl9ddV3TR1wrKStsM+zDkujdTUCV85p9PNwaqNBfoqut GiOLqB27ihs7YCo3xxqmw2KCeg== X-Google-Smtp-Source: ACHHUZ6//ba6VErYOIFC/lD2lq4dOAV7ar+pg4EF30qL8CJ9coxtnjfAekRLC5ouqlPwgJX2ME/5RA== X-Received: by 2002:a17:903:2344:b0:1ac:6a6f:2dc3 with SMTP id c4-20020a170903234400b001ac6a6f2dc3mr5426436plh.20.1683546907481; Mon, 08 May 2023 04:55:07 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.55.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:55:07 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , Anup Patel , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 16/21] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Date: Mon, 8 May 2023 17:22:32 +0530 Message-Id: <20230508115237.216337-17-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Refactor the timer init function such that few things can be shared by both DT and ACPI based platforms. Co-developed-by: Anup Patel Signed-off-by: Anup Patel Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- drivers/clocksource/timer-riscv.c | 81 +++++++++++++++---------------- 1 file changed, 40 insertions(+), 41 deletions(-) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index 5f0f10c7e222..cecc4662293b 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -124,61 +124,28 @@ static irqreturn_t riscv_timer_interrupt(int irq, void *dev_id) return IRQ_HANDLED; } -static int __init riscv_timer_init_dt(struct device_node *n) +static int __init riscv_timer_init_common(void) { - int cpuid, error; - unsigned long hartid; - struct device_node *child; + int error; struct irq_domain *domain; + struct fwnode_handle *intc_fwnode = riscv_get_intc_hwnode(); - error = riscv_of_processor_hartid(n, &hartid); - if (error < 0) { - pr_warn("Not valid hartid for node [%pOF] error = [%lu]\n", - n, hartid); - return error; - } - - cpuid = riscv_hartid_to_cpuid(hartid); - if (cpuid < 0) { - pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); - return cpuid; - } - - if (cpuid != smp_processor_id()) - return 0; - - child = of_find_compatible_node(NULL, NULL, "riscv,timer"); - if (child) { - riscv_timer_cannot_wake_cpu = of_property_read_bool(child, - "riscv,timer-cannot-wake-cpu"); - of_node_put(child); - } - - domain = NULL; - child = of_get_compatible_child(n, "riscv,cpu-intc"); - if (!child) { - pr_err("Failed to find INTC node [%pOF]\n", n); - return -ENODEV; - } - domain = irq_find_host(child); - of_node_put(child); + domain = irq_find_matching_fwnode(intc_fwnode, DOMAIN_BUS_ANY); if (!domain) { - pr_err("Failed to find IRQ domain for node [%pOF]\n", n); + pr_err("Failed to find irq_domain for INTC node [%pfwP]\n", + intc_fwnode); return -ENODEV; } riscv_clock_event_irq = irq_create_mapping(domain, RV_IRQ_TIMER); if (!riscv_clock_event_irq) { - pr_err("Failed to map timer interrupt for node [%pOF]\n", n); + pr_err("Failed to map timer interrupt for node [%pfwP]\n", intc_fwnode); return -ENODEV; } - pr_info("%s: Registering clocksource cpuid [%d] hartid [%lu]\n", - __func__, cpuid, hartid); error = clocksource_register_hz(&riscv_clocksource, riscv_timebase); if (error) { - pr_err("RISCV timer register failed [%d] for cpu = [%d]\n", - error, cpuid); + pr_err("RISCV timer registration failed [%d]\n", error); return error; } @@ -207,4 +174,36 @@ static int __init riscv_timer_init_dt(struct device_node *n) return error; } +static int __init riscv_timer_init_dt(struct device_node *n) +{ + int cpuid, error; + unsigned long hartid; + struct device_node *child; + + error = riscv_of_processor_hartid(n, &hartid); + if (error < 0) { + pr_warn("Invalid hartid for node [%pOF] error = [%lu]\n", + n, hartid); + return error; + } + + cpuid = riscv_hartid_to_cpuid(hartid); + if (cpuid < 0) { + pr_warn("Invalid cpuid for hartid [%lu]\n", hartid); + return cpuid; + } + + if (cpuid != smp_processor_id()) + return 0; + + child = of_find_compatible_node(NULL, NULL, "riscv,timer"); + if (child) { + riscv_timer_cannot_wake_cpu = of_property_read_bool(child, + "riscv,timer-cannot-wake-cpu"); + of_node_put(child); + } + + return riscv_timer_init_common(); +} + TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); From patchwork Mon May 8 11:52:33 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 679969 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3BE7C7EE23 for ; Mon, 8 May 2023 11:57:54 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236008AbjEHL5w (ORCPT ); Mon, 8 May 2023 07:57:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56384 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236366AbjEHL5S (ORCPT ); Mon, 8 May 2023 07:57:18 -0400 Received: from mail-pl1-x630.google.com (mail-pl1-x630.google.com [IPv6:2607:f8b0:4864:20::630]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 539BB4419E for ; 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([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.55.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:55:14 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 17/21] clocksource/timer-riscv: Add ACPI support Date: Mon, 8 May 2023 17:22:33 +0530 Message-Id: <20230508115237.216337-18-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Initialize the timer driver based on RHCT table on ACPI based platforms. Currently, ACPI doesn't support a flag to indicate that the timer interrupt can wake up the cpu irrespective of its power state. It will be added in future update. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- drivers/clocksource/timer-riscv.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c index cecc4662293b..da3071b387eb 100644 --- a/drivers/clocksource/timer-riscv.c +++ b/drivers/clocksource/timer-riscv.c @@ -10,6 +10,7 @@ #define pr_fmt(fmt) "riscv-timer: " fmt +#include #include #include #include @@ -207,3 +208,13 @@ static int __init riscv_timer_init_dt(struct device_node *n) } TIMER_OF_DECLARE(riscv_timer, "riscv", riscv_timer_init_dt); + +#ifdef CONFIG_ACPI +static int __init riscv_timer_acpi_init(struct acpi_table_header *table) +{ + return riscv_timer_init_common(); +} + +TIMER_ACPI_DECLARE(aclint_mtimer, ACPI_SIG_RHCT, riscv_timer_acpi_init); + +#endif From patchwork Mon May 8 11:52:34 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 680289 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2B888C77B75 for ; Mon, 8 May 2023 11:58:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233483AbjEHL6K (ORCPT ); Mon, 8 May 2023 07:58:10 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234094AbjEHL5e (ORCPT ); Mon, 8 May 2023 07:57:34 -0400 Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 55BA54641E for ; Mon, 8 May 2023 04:55:25 -0700 (PDT) Received: by mail-pf1-x434.google.com with SMTP id d2e1a72fcca58-64115e652eeso33927756b3a.0 for ; Mon, 08 May 2023 04:55:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546924; x=1686138924; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=yRIRI8aArNgE1fextAvbnFu2fBTu5X0gP4d56RcrLtU=; b=dPMbOuJszGZR9AahCXbvkNUwii+U9QMTSbyX/g4rgl2Q6FpYBFAPcbDw395JVWTi3S E6urCy+MpwA2mwwR1jCyAvffT1l31W8/LPIcJGeeFTD5aLYHDEquT54qiJ2PiGwewAK/ 7/al2D5PTVEakeiZsNEdWqALf2XkQL0K7k9aFb+4iJxePbBgZXZVkfp8vW4aBTIcs+SD +bz/l9nW3Yjj7WFv+zwFHYEfdt26tbRHLOQXJbw4w/Xh1zaR7Z1ODfJ0Z4leFb0BXw7C UqtjGgxhDIEAThPM+W99EdZymdIczjmy/IDVSEpiG7tDS91x79zJImn26Sq77ax+bOHo zOIA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546924; x=1686138924; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=yRIRI8aArNgE1fextAvbnFu2fBTu5X0gP4d56RcrLtU=; b=BL58L/SI+lxouHybwIMCOSo5X7ty08O+Nc7r7C2m5mP6u1p+ar1K0VGkmP9NpjZTwm Ao50uKqWrGXvtcjvf9dM4WGSfwtqY3q46nYQpWNoNkFjbRzMbkGerDWQ8GscNIUox4n6 T5UGlUyYHqW/jkumQx/2J3H6gu0w7gwNi8g6XBJxzNBtVgF0yVXqsd5cMGc35TuJiGP1 aldt6jslYBYB0e7+JAldsBrW1+JOn0rK5JgU13iih5ibSyK5GZDmm1Nwqkyi0+QYPxv/ GdEfx+1F6a2P8Q2MUui3fG5OGN5LUC65z5RJghfVbyh7ADkAVszGNisETuN2WQsOWmDS phIg== X-Gm-Message-State: AC+VfDw9P4MW0yj1hJaSK3HrQDYkaKLHD+cPD7TH+PIwCZAfJGnao20P 2Lo5hacVYquKhse3uGnVSwcOAg== X-Google-Smtp-Source: ACHHUZ6789eMhEedD+DjgP1qLrd+M1OvHlv3gMG5XLhQSR4jt23EMajfCnuU+TlGtnZrH0ieEuaCGA== X-Received: by 2002:a17:902:e550:b0:1a6:e564:6044 with SMTP id n16-20020a170902e55000b001a6e5646044mr12627890plf.7.1683546924015; Mon, 08 May 2023 04:55:24 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.55.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:55:23 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 18/21] RISC-V: time.c: Add ACPI support for time_init() Date: Mon, 8 May 2023 17:22:34 +0530 Message-Id: <20230508115237.216337-19-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org On ACPI based platforms, timer related information is available in RHCT. Add ACPI based probe support to the timer initialization. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/kernel/time.c | 25 +++++++++++++++++++------ 1 file changed, 19 insertions(+), 6 deletions(-) diff --git a/arch/riscv/kernel/time.c b/arch/riscv/kernel/time.c index babaf3b48ba8..23641e82a9df 100644 --- a/arch/riscv/kernel/time.c +++ b/arch/riscv/kernel/time.c @@ -4,6 +4,7 @@ * Copyright (C) 2017 SiFive */ +#include #include #include #include @@ -18,17 +19,29 @@ EXPORT_SYMBOL_GPL(riscv_timebase); void __init time_init(void) { struct device_node *cpu; + struct acpi_table_rhct *rhct; + acpi_status status; u32 prop; - cpu = of_find_node_by_path("/cpus"); - if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop)) - panic(KERN_WARNING "RISC-V system with no 'timebase-frequency' in DTS\n"); - of_node_put(cpu); - riscv_timebase = prop; + if (acpi_disabled) { + cpu = of_find_node_by_path("/cpus"); + if (!cpu || of_property_read_u32(cpu, "timebase-frequency", &prop)) + panic("RISC-V system with no 'timebase-frequency' in DTS\n"); + + of_node_put(cpu); + riscv_timebase = prop; + of_clk_init(NULL); + } else { + status = acpi_get_table(ACPI_SIG_RHCT, 0, (struct acpi_table_header **)&rhct); + if (ACPI_FAILURE(status)) + panic("RISC-V ACPI system with no RHCT table\n"); + + riscv_timebase = rhct->time_base_freq; + acpi_put_table((struct acpi_table_header *)rhct); + } lpj_fine = riscv_timebase / HZ; - of_clk_init(NULL); timer_probe(); tick_setup_hrtimer_broadcast(); From patchwork Mon May 8 11:52:35 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 679968 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE3FCC7EE23 for ; Mon, 8 May 2023 11:58:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234090AbjEHL6V (ORCPT ); Mon, 8 May 2023 07:58:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56800 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233140AbjEHL5p (ORCPT ); Mon, 8 May 2023 07:57:45 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E5DF8473C3 for ; Mon, 8 May 2023 04:55:33 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1a50cb65c92so30394265ad.0 for ; Mon, 08 May 2023 04:55:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546933; x=1686138933; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=AKIAPMXrXfzkk8IX1ewOX27TBpicUwrq64VdyI20DAw=; b=KpgNJW0kX+Z9Wh6YbIvm+WvnaRcQpsLdZVg6avNrhWbmHJqQq3JK8lHR9rYyL6R4yt WkgJRqi3N8sMKuoXuEZOJTn6/ObWFDVNXf4lzDXX3HFu1cbJiR8NsI64zyjkCquA5WQj b1r0AqTwhdfn8wWoWDeIz4mUtDbnkowHWK1+RBRutlIT2OEpP4MSi57BYhtfhLCNooqJ VYhJOr8PYqpluzQAk1jrzZHteLtOzdpR2+Dt9qbePCgNDMSgUQcNgs3KqytEoo8U6Pe9 XN2/dekVn2I3WMG2LAzZblSzmku6j6LY6D+8zPaWghquK9oXxgo63cTgY9rDGF/GDEWL jcFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546933; x=1686138933; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=AKIAPMXrXfzkk8IX1ewOX27TBpicUwrq64VdyI20DAw=; b=LdMG++ecDN3FNhGgjzaaFhepJN4tbljEJE4wYIDPE8IpWY11iXlx0ZKFhdqLKTLmQo 8Sr4id17r+hjf/2d2CLC1a0NZ3ihAPDPDSqF2ZaWWQVPhqQo3Idr+jB/2zR6fGqwRzmD Buw+PlhdxO/R3xgbD/6Yyr/E6x01/GH2fXR26OsQtOMn9nM8GL7PPKaI/b3XzkDwQEqi pcZvXwjUc5KXXn55GH6PSZ7vSIKAaRqNxgTeb7r7WHxrYmMJShL54esGFFJvA0Rz/cnu LMwkANNjX7oz5oCYZlQp9yIfQ8MizIw9CrwrucML/qPm0SzfHQOOyfZbYoRUfnxdiAFz m+BA== X-Gm-Message-State: AC+VfDzvayqONMXwvkDI8KGirn0IAqakmRK25KVfL/j9J/4Ci4zC7x9e 7cdRvOOIZfNjZnqYVJ1/vG9yBA== X-Google-Smtp-Source: ACHHUZ7NAIOrHplYZkCxTdW1wLJXPNPUzm6zz0o6Ibgq4lD55UWL7tyxIaH+bDt+zorb8yD6L84S/g== X-Received: by 2002:a17:903:1110:b0:1aa:ff41:31a7 with SMTP id n16-20020a170903111000b001aaff4131a7mr13029996plh.13.1683546932740; Mon, 08 May 2023 04:55:32 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.55.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:55:32 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 19/21] RISC-V: Add ACPI initialization in setup_arch() Date: Mon, 8 May 2023 17:22:35 +0530 Message-Id: <20230508115237.216337-20-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Initialize the ACPI core for RISC-V during boot. ACPI tables and interpreter are initialized based on the information passed from the firmware and the value of the kernel parameter 'acpi'. With ACPI support added for RISC-V, the kernel parameter 'acpi' is also supported on RISC-V. Hence, update the documentation. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Acked-by: Conor Dooley --- .../admin-guide/kernel-parameters.txt | 8 +- arch/riscv/kernel/acpi.c | 125 ++++++++++++++++++ arch/riscv/kernel/setup.c | 5 + 3 files changed, 134 insertions(+), 4 deletions(-) diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 9e5bab29685f..d910fba25f2c 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -1,17 +1,17 @@ - acpi= [HW,ACPI,X86,ARM64] + acpi= [HW,ACPI,X86,ARM64,RISCV64] Advanced Configuration and Power Interface Format: { force | on | off | strict | noirq | rsdt | copy_dsdt } force -- enable ACPI if default was off - on -- enable ACPI but allow fallback to DT [arm64] + on -- enable ACPI but allow fallback to DT [arm64,riscv64] off -- disable ACPI if default was on noirq -- do not use ACPI for IRQ routing strict -- Be less tolerant of platforms that are not strictly ACPI specification compliant. rsdt -- prefer RSDT over (default) XSDT copy_dsdt -- copy DSDT to memory - For ARM64, ONLY "acpi=off", "acpi=on" or "acpi=force" - are available + For ARM64 and RISCV64, ONLY "acpi=off", "acpi=on" or + "acpi=force" are available See also Documentation/power/runtime_pm.rst, pci=noacpi diff --git a/arch/riscv/kernel/acpi.c b/arch/riscv/kernel/acpi.c index 89e142611c84..93f643f8d763 100644 --- a/arch/riscv/kernel/acpi.c +++ b/arch/riscv/kernel/acpi.c @@ -16,6 +16,7 @@ #include #include #include +#include int acpi_noirq = 1; /* skip ACPI IRQ initialization */ int acpi_disabled = 1; @@ -25,6 +26,130 @@ int acpi_pci_disabled = 1; /* skip ACPI PCI scan and IRQ initialization */ EXPORT_SYMBOL(acpi_pci_disabled); static struct acpi_madt_rintc cpu_madt_rintc[NR_CPUS]; +static bool param_acpi_off __initdata; +static bool param_acpi_on __initdata; +static bool param_acpi_force __initdata; + +static int __init parse_acpi(char *arg) +{ + if (!arg) + return -EINVAL; + + /* "acpi=off" disables both ACPI table parsing and interpreter */ + if (strcmp(arg, "off") == 0) + param_acpi_off = true; + else if (strcmp(arg, "on") == 0) /* prefer ACPI over DT */ + param_acpi_on = true; + else if (strcmp(arg, "force") == 0) /* force ACPI to be enabled */ + param_acpi_force = true; + else + return -EINVAL; /* Core will print when we return error */ + + return 0; +} +early_param("acpi", parse_acpi); + +/* + * acpi_fadt_sanity_check() - Check FADT presence and carry out sanity + * checks on it + * + * Return 0 on success, <0 on failure + */ +static int __init acpi_fadt_sanity_check(void) +{ + struct acpi_table_header *table; + struct acpi_table_fadt *fadt; + acpi_status status; + int ret = 0; + + /* + * FADT is required on riscv; retrieve it to check its presence + * and carry out revision and ACPI HW reduced compliancy tests + */ + status = acpi_get_table(ACPI_SIG_FADT, 0, &table); + if (ACPI_FAILURE(status)) { + const char *msg = acpi_format_exception(status); + + pr_err("Failed to get FADT table, %s\n", msg); + return -ENODEV; + } + + fadt = (struct acpi_table_fadt *)table; + + /* + * The revision in the table header is the FADT's Major revision. The + * FADT also has a minor revision, which is stored in the FADT itself. + * + * TODO: Currently, we check for 6.5 as the minimum version to check + * for HW_REDUCED flag. However, once RISC-V updates are released in + * the ACPI spec, we need to update this check for exact minor revision + */ + if (table->revision < 6 || (table->revision == 6 && fadt->minor_revision < 5)) + pr_err(FW_BUG "Unsupported FADT revision %d.%d, should be 6.5+\n", + table->revision, fadt->minor_revision); + + if (!(fadt->flags & ACPI_FADT_HW_REDUCED)) { + pr_err("FADT not ACPI hardware reduced compliant\n"); + ret = -EINVAL; + } + + /* + * acpi_get_table() creates FADT table mapping that + * should be released after parsing and before resuming boot + */ + acpi_put_table(table); + return ret; +} + +/* + * acpi_boot_table_init() called from setup_arch(), always. + * 1. find RSDP and get its address, and then find XSDT + * 2. extract all tables and checksums them all + * 3. check ACPI FADT HW reduced flag + * + * We can parse ACPI boot-time tables such as MADT after + * this function is called. + * + * On return ACPI is enabled if either: + * + * - ACPI tables are initialized and sanity checks passed + * - acpi=force was passed in the command line and ACPI was not disabled + * explicitly through acpi=off command line parameter + * + * ACPI is disabled on function return otherwise + */ +void __init acpi_boot_table_init(void) +{ + /* + * Enable ACPI instead of device tree unless + * - ACPI has been disabled explicitly (acpi=off), or + * - firmware has not populated ACPI ptr in EFI system table + * and ACPI has not been [force] enabled (acpi=on|force) + */ + if (param_acpi_off || + (!param_acpi_on && !param_acpi_force && + efi.acpi20 == EFI_INVALID_TABLE_ADDR)) + return; + + /* + * ACPI is disabled at this point. Enable it in order to parse + * the ACPI tables and carry out sanity checks + */ + enable_acpi(); + + /* + * If ACPI tables are initialized and FADT sanity checks passed, + * leave ACPI enabled and carry on booting; otherwise disable ACPI + * on initialization error. + * If acpi=force was passed on the command line it forces ACPI + * to be enabled even if its initialization failed. + */ + if (acpi_table_init() || acpi_fadt_sanity_check()) { + pr_err("Failed to init ACPI tables\n"); + if (!param_acpi_force) + disable_acpi(); + } +} static int acpi_parse_madt_rintc(union acpi_subtable_headers *header, const unsigned long end) { diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c index a44c7fcde12f..2ab4cdaa2e68 100644 --- a/arch/riscv/kernel/setup.c +++ b/arch/riscv/kernel/setup.c @@ -8,6 +8,7 @@ * Nick Kossifidis */ +#include #include #include #include @@ -277,6 +278,10 @@ void __init setup_arch(char **cmdline_p) efi_init(); paging_init(); + + /* Parse the ACPI tables for possible boot-time configuration */ + acpi_boot_table_init(); + #if IS_ENABLED(CONFIG_BUILTIN_DTB) unflatten_and_copy_device_tree(); #else From patchwork Mon May 8 11:52:36 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 680288 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id BFB42C77B7F for ; Mon, 8 May 2023 11:58:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234087AbjEHL6n (ORCPT ); Mon, 8 May 2023 07:58:43 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56412 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232887AbjEHL6F (ORCPT ); Mon, 8 May 2023 07:58:05 -0400 Received: from mail-pl1-x62f.google.com (mail-pl1-x62f.google.com [IPv6:2607:f8b0:4864:20::62f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 06E5F473F9 for ; Mon, 8 May 2023 04:55:44 -0700 (PDT) Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-1aaebed5bd6so30384915ad.1 for ; Mon, 08 May 2023 04:55:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546941; x=1686138941; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=38k1Pzb7K1cfn0j2an7l+ypiTAB8VfWPvQzIb1c40CU=; b=PChmFsn3jZ8YIN6et/HE2FT9KTKcn+85yUyr9DAN37WxMFW8+DniecytVJXMB+E4Yt cwg8NffeENFCvkKnaWixs6tUyDd3Pe6n2aLn4UIePpKETvgDRw/tKZj+YWWWcT4mL8PX tYib/TSvHrN7Ey/NaA2sBIl3ZhsF/OALW01VQPmUVWr5lFOnvHHzhr8ONcBU4wdYDXUM 2glikRs238NvoLM/xUbz0Xj6aUVZA+JwoGLMj1OClPKRSjyvFoYHdvDFP9z9Wm3UBUso nG8WFplmCxjrRVNpFWVJOLFxXe7WeRsIP9yzHVTVBjY97ncMG5iq4wNUkEILfoLw9j50 tEaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546941; x=1686138941; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=38k1Pzb7K1cfn0j2an7l+ypiTAB8VfWPvQzIb1c40CU=; b=TspC2VjOeEq2xCprnd3sNrGEGv9GCM4XddCPUcfyXR8MycrasSZycmYiUC69h0NqoF mOA3RIJqAYxElDP1gqL4QUcGQ2l0pXA1KJV62RCwrTdW4drxM1LQ7RwyJCBAxfpErcM0 azFPWhJRURIX2aBHHdQCxp+/DTI8jdbMV7N96XSwP1vPwFxtCZFFprw/BDM5vPdiRqeI kHr0KEXZMSfuHlnu7nTP5cKYzQX76CqVs7pSD+uoc4q3xPUmajzlPMrfCTA8DX7M4KGC fQSxic6GXAauQ/ZxS4dKK8Tp/rwwfTXgN5RDt9rXIlblfl9Qmpq3QanwQgY399n85xFT IW6w== X-Gm-Message-State: AC+VfDxcOCjr7XPOOMid02gIKl5l8AodqDtXCJQUS0w69CMGuouJ5GKt KeAqZDdr1OL6LTGW3p1kKXnyBw== X-Google-Smtp-Source: ACHHUZ6zMo1/GVdCMuvw4uqUNbB5el8P538gaRe9zZQmHaDTlvRjtiHbiNIa2a1kNbjX1A6CxKl+VA== X-Received: by 2002:a17:902:8c96:b0:1a9:631b:7d68 with SMTP id t22-20020a1709028c9600b001a9631b7d68mr8947702plo.8.1683546941248; Mon, 08 May 2023 04:55:41 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.55.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:55:40 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" , Andrew Jones , Conor Dooley Subject: [PATCH V5 20/21] RISC-V: Enable ACPI in defconfig Date: Mon, 8 May 2023 17:22:36 +0530 Message-Id: <20230508115237.216337-21-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org Add support to build ACPI subsystem in defconfig. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki Reviewed-by: Andrew Jones Reviewed-by: Conor Dooley --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index d98d6e90b2b8..d3d1fbf2dd5f 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -37,6 +37,7 @@ CONFIG_PM=y CONFIG_CPU_IDLE=y CONFIG_VIRTUALIZATION=y CONFIG_KVM=m +CONFIG_ACPI=y CONFIG_JUMP_LABEL=y CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y From patchwork Mon May 8 11:52:37 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sunil V L X-Patchwork-Id: 679967 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 506F3C77B75 for ; Mon, 8 May 2023 11:58:55 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234329AbjEHL6x (ORCPT ); Mon, 8 May 2023 07:58:53 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56340 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234334AbjEHL6J (ORCPT ); Mon, 8 May 2023 07:58:09 -0400 Received: from mail-pl1-x62b.google.com (mail-pl1-x62b.google.com [IPv6:2607:f8b0:4864:20::62b]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1C2F044BC2 for ; Mon, 8 May 2023 04:55:50 -0700 (PDT) Received: by mail-pl1-x62b.google.com with SMTP id d9443c01a7336-1a516fb6523so41403335ad.3 for ; Mon, 08 May 2023 04:55:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; t=1683546949; x=1686138949; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=OXbI3HNo2LwXyvQs8qly8d1W6GTwS2nLVT7+MHc+VBo=; b=VJ05ByxAGU0vvx8FU1rjL6l0PIhYquRStC62VT+/S2jdFsLmaNzstWpoe/hp4v7/fY 9Ylc58Ec1X59MDBgEvRnZDYa2YK4has1nYcaIChEcUHpK9Rtzzs0lN8auNvjP/eS/mzF b/q8IeE+kqnv4kgmSGEDfxohLmsEDEAmTj4HLYxPf8Gjz4R36yz+fRDNLHDdLtDGxoAl 7mtfwXr9/djJaaG1DwPbd57mwyG5l4sdX1mA2Rl2byTeWWF1TsEdVB1cs1cR+R0R1EW9 +Ash7wiwJX0Utkc0AktTYUTxTmaoyjAeBGJFDxoAhquycttgz+y0oV4T4PsNDlPm/P57 2AwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683546949; x=1686138949; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OXbI3HNo2LwXyvQs8qly8d1W6GTwS2nLVT7+MHc+VBo=; b=a673mDdsZUbmUX6/uP+Auhj9kaAnwdNWnwCsrj09mL+CgNTsbQkdFAZ33kXaF8erud sOPup7wXZXNcFxtif8HITIijjlRN5XfMkC3adVUVY7vCDj1d4b82XTM326FV+Z0ZQQeE Gzkm+01QiHIhr+/7u+W/vwfTzSkb7jrmyMuR4XIlmjpy5YvHSA9gW8XN1Gvr9FAS/Lgy sP/WbvNSNB45RSz06DmmTEgOPCyBHjoGXYSEf6nG/6/VKXD2dXr9juhSVV7SUQjrxWHS VoL2Oun57UKcj79tJmll/ZKwKi/jSiU6kSDkpp/6ISf4jC+fBeuNjVzWxM7G3EHqIarb 74xQ== X-Gm-Message-State: AC+VfDx3pCcerTxU3mHJO7gpYKic1D+I7Nk2PW0mJP1SsVSfsKETUzZL h0Z3HUh7Vt5jgbyBTIrcJdXt5w== X-Google-Smtp-Source: ACHHUZ4GEr9Y9j7DgnPzlC1fbWrO73mkCaN33oq08+WeT0xKd/++5k0KyC4CIRoSU1LTRnVvt3Uuyw== X-Received: by 2002:a17:902:b20a:b0:1ac:3e90:7c4 with SMTP id t10-20020a170902b20a00b001ac3e9007c4mr10016908plr.2.1683546948833; Mon, 08 May 2023 04:55:48 -0700 (PDT) Received: from sunil-laptop.. ([106.51.189.144]) by smtp.gmail.com with ESMTPSA id w9-20020a170902904900b001aaed524541sm7015149plz.227.2023.05.08.04.55.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 08 May 2023 04:55:48 -0700 (PDT) From: Sunil V L To: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org, linux-crypto@vger.kernel.org, platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev Cc: Jonathan Corbet , Paul Walmsley , Palmer Dabbelt , Albert Ou , "Rafael J . Wysocki" , Len Brown , Daniel Lezcano , Thomas Gleixner , Weili Qian , Zhou Wang , Herbert Xu , "David S . Miller" , Marc Zyngier , Maximilian Luz , Hans de Goede , Mark Gross , Nathan Chancellor , Nick Desaulniers , Tom Rix , Sunil V L , "Rafael J . Wysocki" Subject: [PATCH V5 21/21] MAINTAINERS: Add entry for drivers/acpi/riscv Date: Mon, 8 May 2023 17:22:37 +0530 Message-Id: <20230508115237.216337-22-sunilvl@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230508115237.216337-1-sunilvl@ventanamicro.com> References: <20230508115237.216337-1-sunilvl@ventanamicro.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-crypto@vger.kernel.org ACPI defines few RISC-V specific tables which need parsing code added in drivers/acpi/riscv. Add maintainer entries for this newly created folder. Signed-off-by: Sunil V L Acked-by: Rafael J. Wysocki --- MAINTAINERS | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 7e0b87d5aa2e..083ba321fc7c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -406,6 +406,14 @@ L: linux-arm-kernel@lists.infradead.org (moderated for non-subscribers) S: Maintained F: drivers/acpi/arm64 +ACPI FOR RISC-V (ACPI/riscv) +M: Sunil V L +L: linux-acpi@vger.kernel.org +L: linux-riscv@lists.infradead.org +S: Maintained +F: arch/riscv/kernel/acpi.c +F: drivers/acpi/riscv + ACPI SERIAL MULTI INSTANTIATE DRIVER M: Hans de Goede L: platform-driver-x86@vger.kernel.org