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[209.51.188.17]) by mx.google.com with ESMTPS id n14si8167533qkg.165.2019.06.05.14.07.01 for (version=TLS1 cipher=AES128-SHA bits=128/128); Wed, 05 Jun 2019 14:07:01 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=OoIeqPmZ; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([127.0.0.1]:50045 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYd7d-0005Mv-CQ for patch@linaro.org; Wed, 05 Jun 2019 17:07:01 -0400 Received: from eggs.gnu.org ([209.51.188.92]:48058) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1hYcyB-0006A4-Lx for qemu-devel@nongnu.org; Wed, 05 Jun 2019 16:57:16 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1hYcyA-00087R-9p for qemu-devel@nongnu.org; Wed, 05 Jun 2019 16:57:15 -0400 Received: from mail-oi1-x243.google.com ([2607:f8b0:4864:20::243]:35086) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1hYcyA-00085J-5G for qemu-devel@nongnu.org; Wed, 05 Jun 2019 16:57:14 -0400 Received: by mail-oi1-x243.google.com with SMTP id y6so59282oix.2 for ; Wed, 05 Jun 2019 13:57:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=VGvFhyg+EUZksh+VTROd86GaO53VcnzMT3R6u6jPQAY=; b=OoIeqPmZjHB3rL9pqVkgC//djxrxRKMbvTLI/lNj/jUKtpVZU24+DJwHFfk8rkB9Et 7VZQU9GvIwyFNUNQPGcg/9eZOzeoBIBK983oq242StsYqiZ//A15cr/9Afk+f4rxa4XB lYxTPX/3mEyYWtPYY23n1eqvuhL/Gxnl7drwrlPsrThBz2/Cdt+0Gbo7+JcSMohL32uc KmQOxb9+xAszytdDLr+/TbaKY/r27in9EW5QvLNcH6YJrgzYcKWQbNS8BSXrhoLfzJog UvSZaazsPsbp/cpi5i+WyC49uDxok4v9bzoPw685T020BnOWZkmNao9ZCerC8zeR0alH 8yLw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=VGvFhyg+EUZksh+VTROd86GaO53VcnzMT3R6u6jPQAY=; b=da7zeKHRXv186AJGtKi31/l6LP6uxkKJAxU+xwy2HthsCANmrYOFySs0/jZE07WCrB OSAValXkCp/nsv3/2MXF/4KjWjsWH7VOfjmJt0YUqEhveuwErIR77dm+xW2dZlH4BSzX Ng+IUlmdASFRE9njkpwpE3loiiPC0k6KgJo30cfyKLpoC5+ICZcMhB43cgI07YAWRE3z bwmr1t+rM6m2ECQ/y+sF21WNucp/pczsg2p2Rd8Svfb2+pjZ/I35VmUss9TFKlM5U0CY oPi1U//eMYWYtTaFko7SlE+KSIeIRxSDbGqDu944ALjJJi0NWgvjcE3cJPW7zUwWIj2J zgvQ== X-Gm-Message-State: APjAAAWKTAXwM7DdoDm1lea6WWNIqOTnYVgf9v8Xb+JtAhBJQ3Vho9r1 lqQBFayInSGtsDcZQTyAlZ7ON43a9yulig== X-Received: by 2002:aca:ef43:: with SMTP id n64mr10168835oih.79.1559768233178; Wed, 05 Jun 2019 13:57:13 -0700 (PDT) Received: from localhost.localdomain (200-56-192-86-cable.cybercable.net.mx. [200.56.192.86]) by smtp.gmail.com with ESMTPSA id f5sm7414155otl.51.2019.06.05.13.57.11 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jun 2019 13:57:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jun 2019 15:57:01 -0500 Message-Id: <20190605205706.569-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190605205706.569-1-richard.henderson@linaro.org> References: <20190605205706.569-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::243 Subject: [Qemu-devel] [PATCH v6 1/6] linux-user/aarch64: Reset btype for syscalls and signals X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, Dave.Martin@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The value of btype for syscalls is CONSTRAINED UNPREDICTABLE, so we need to make sure that the value is 0 before clone, fork, or syscall return. The kernel sets btype for the signal handler as if for a call. Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 7 +++++++ linux-user/aarch64/signal.c | 10 ++++++++-- 2 files changed, 15 insertions(+), 2 deletions(-) -- 2.17.1 diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 2f2f63e3e8..1f68b13168 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -86,6 +86,13 @@ void cpu_loop(CPUARMState *env) switch (trapnr) { case EXCP_SWI: + /* + * The state of BTYPE on syscall entry is CONSTRAINED + * UNPREDICTABLE. The real kernel will need to tidy this up + * as well. Do this before syscalls so that the value is + * correct on return from syscall (especially clone & fork). + */ + env->btype = 0; ret = do_syscall(env, env->xregs[8], env->xregs[0], diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index f84a9cf28a..5605d404b3 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -506,10 +506,16 @@ static void target_setup_frame(int usig, struct target_sigaction *ka, + offsetof(struct target_rt_frame_record, tramp); } env->xregs[0] = usig; - env->xregs[31] = frame_addr; env->xregs[29] = frame_addr + fr_ofs; - env->pc = ka->_sa_handler; env->xregs[30] = return_addr; + env->xregs[31] = frame_addr; + env->pc = ka->_sa_handler; + + /* Invoke the signal handler as if by indirect call. */ + if (cpu_isar_feature(aa64_bti, arm_env_get_cpu(env))) { + env->btype = 2; + } + if (info) { tswap_siginfo(&frame->info, info); env->xregs[1] = frame_addr + offsetof(struct target_rt_sigframe, info); From patchwork Wed Jun 5 20:57:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 165934 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp7869832ili; Wed, 5 Jun 2019 14:14:52 -0700 (PDT) X-Google-Smtp-Source: APXvYqzZizUpvCdTUK5SYBD83l8mEMYYr5FLskk0savDQ9ANwc8MXjyGfw5VCybf1OnIQm3YF4KO X-Received: by 2002:ac8:1e15:: with SMTP id n21mr11206406qtl.20.1559769292253; Wed, 05 Jun 2019 14:14:52 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559769292; cv=none; d=google.com; s=arc-20160816; b=W2zuze1ADTMPKfHcULDYBakJm0PIkzeOpdtzgdAEDYACa3jnY4RPIUVZ5PelAWbyFi ictZG9QHBmYrvZ0klTR73uXMU44Xm6SFsffqNBcZnRUEmZBqM4tV3Afes13Nlw3Yfgnz QMloscpWqk3WcCtDe2RMQ74HTHkKqmLecsOKPnqsYOl70CXfRaSY9N0uACp0gu+WZoc/ OobLnD2gP/wLhshszLjOY8OQtRfX3vBQf+lcFQW4FdV1ZwfwMUdzsiDE/boTpI5bfyMD e2ahQHvHngY89V4vlDIeTdfpLz/lhD+6tlu3r9ai1ZdZ1TjkjsSFemG8Gkw6qbSEGoqO jEmw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=yjdMaLJKLWTE+OzLW+tTbL3wKIJtV8g2rfeZlQHS85U=; b=mAbtvLLhxFvHdRB9PUWYkbYzEFd+qg/O3fx2WlpvkgC332hX/YJvYZn4/rKZpad9nb cbikuc7T6KITkYwqXng2NRPyt00X32+GTvi4FD8G9KR+WSgqsPBDUlk+TroOQNFbkt7u 8Eh0GTirszGg/Q/lW5uT4PADPD16ltNm920Ack5U8gCO0JBSU7sYYW/LOzxszWCO4g1m FpwPpina+Bi8IxN3BIjsuOkN+FXgy2AiQk+A9XOBEw+QmgfeWk9nPjYS+lhCdxkNstyA 5bQHoo795FS1O4Hg1KlhA5vLaKCEft+fTySmqYpfRiieQehczmi0HoMJvpFrQDfO1hGd Z45Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=xRhC6ePo; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id f5sm7414155otl.51.2019.06.05.13.57.13 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jun 2019 13:57:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jun 2019 15:57:02 -0500 Message-Id: <20190605205706.569-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190605205706.569-1-richard.henderson@linaro.org> References: <20190605205706.569-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::242 Subject: [Qemu-devel] [PATCH v6 2/6] linux-user: Validate mmap/mprotect prot value X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, Dave.Martin@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" The kernel will return -EINVAL for bits set in the prot argument that are unknown or invalid. Previously we were simply cropping out the bits that we care about. Introduce validate_prot_to_pageflags to perform this check in a single place between the two syscalls. Differentiate between the target and host versions of prot. Compute the qemu internal page_flags value at the same time. Signed-off-by: Richard Henderson --- linux-user/mmap.c | 106 ++++++++++++++++++++++++++++++++-------------- 1 file changed, 75 insertions(+), 31 deletions(-) -- 2.17.1 diff --git a/linux-user/mmap.c b/linux-user/mmap.c index af41339d57..3117f57fd8 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -61,11 +61,38 @@ void mmap_fork_end(int child) pthread_mutex_unlock(&mmap_mutex); } +/* + * Validate target prot bitmask. + * Return the prot bitmask for the host in *HOST_PROT. + * Return 0 if the target prot bitmask is invalid, otherwise + * the internal qemu page_flags (which will include PAGE_VALID). + */ +static int validate_prot_to_pageflags(int *host_prot, int prot) +{ + int valid = PROT_READ | PROT_WRITE | PROT_EXEC | TARGET_PROT_SEM; + int page_flags = (prot & PAGE_BITS) | PAGE_VALID; + + /* + * For the host, we need not pass anything except read/write/exec. + * While PROT_SEM is allowed by all hosts, it is also ignored, so + * don't bother transforming guest bit to host bit. Any other + * target-specific prot bits will not be understood by the host + * and will need to be encoded into page_flags for qemu emulation. + * + * TODO: We do not actually have to map guest pages as executable, + * since they will not be directly executed by the host. We only + * need to remember exec within page_flags. + */ + *host_prot = prot & (PROT_READ | PROT_WRITE | PROT_EXEC); + + return prot & ~valid ? 0 : page_flags; +} + /* NOTE: all the constants are the HOST ones, but addresses are target. */ -int target_mprotect(abi_ulong start, abi_ulong len, int prot) +int target_mprotect(abi_ulong start, abi_ulong len, int target_prot) { abi_ulong end, host_start, host_end, addr; - int prot1, ret; + int prot1, ret, page_flags, host_prot; #ifdef DEBUG_MMAP printf("mprotect: start=0x" TARGET_ABI_FMT_lx @@ -75,56 +102,65 @@ int target_mprotect(abi_ulong start, abi_ulong len, int prot) prot & PROT_EXEC ? 'x' : '-'); #endif - if ((start & ~TARGET_PAGE_MASK) != 0) + if ((start & ~TARGET_PAGE_MASK) != 0) { return -TARGET_EINVAL; + } + page_flags = validate_prot_to_pageflags(&host_prot, target_prot); + if (!page_flags) { + return -TARGET_EINVAL; + } len = TARGET_PAGE_ALIGN(len); end = start + len; if (!guest_range_valid(start, len)) { return -TARGET_ENOMEM; } - prot &= PROT_READ | PROT_WRITE | PROT_EXEC; - if (len == 0) + if (len == 0) { return 0; + } mmap_lock(); host_start = start & qemu_host_page_mask; host_end = HOST_PAGE_ALIGN(end); if (start > host_start) { /* handle host page containing start */ - prot1 = prot; - for(addr = host_start; addr < start; addr += TARGET_PAGE_SIZE) { + prot1 = host_prot; + for (addr = host_start; addr < start; addr += TARGET_PAGE_SIZE) { prot1 |= page_get_flags(addr); } if (host_end == host_start + qemu_host_page_size) { - for(addr = end; addr < host_end; addr += TARGET_PAGE_SIZE) { + for (addr = end; addr < host_end; addr += TARGET_PAGE_SIZE) { prot1 |= page_get_flags(addr); } end = host_end; } - ret = mprotect(g2h(host_start), qemu_host_page_size, prot1 & PAGE_BITS); - if (ret != 0) + ret = mprotect(g2h(host_start), qemu_host_page_size, + prot1 & PAGE_BITS); + if (ret != 0) { goto error; + } host_start += qemu_host_page_size; } if (end < host_end) { - prot1 = prot; - for(addr = end; addr < host_end; addr += TARGET_PAGE_SIZE) { + prot1 = host_prot; + for (addr = end; addr < host_end; addr += TARGET_PAGE_SIZE) { prot1 |= page_get_flags(addr); } - ret = mprotect(g2h(host_end - qemu_host_page_size), qemu_host_page_size, - prot1 & PAGE_BITS); - if (ret != 0) + ret = mprotect(g2h(host_end - qemu_host_page_size), + qemu_host_page_size, prot1 & PAGE_BITS); + if (ret != 0) { goto error; + } host_end -= qemu_host_page_size; } /* handle the pages in the middle */ if (host_start < host_end) { - ret = mprotect(g2h(host_start), host_end - host_start, prot); - if (ret != 0) + ret = mprotect(g2h(host_start), host_end - host_start, host_prot); + if (ret != 0) { goto error; + } } - page_set_flags(start, start + len, prot | PAGE_VALID); + page_set_flags(start, start + len, page_flags); mmap_unlock(); return 0; error: @@ -364,10 +400,11 @@ abi_ulong mmap_find_vma(abi_ulong start, abi_ulong size, abi_ulong align) } /* NOTE: all the constants are the HOST ones */ -abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, +abi_long target_mmap(abi_ulong start, abi_ulong len, int target_prot, int flags, int fd, abi_ulong offset) { abi_ulong ret, end, real_start, real_end, retaddr, host_offset, host_len; + int page_flags, host_prot; mmap_lock(); #ifdef DEBUG_MMAP @@ -402,6 +439,12 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, goto fail; } + page_flags = validate_prot_to_pageflags(&host_prot, target_prot); + if (!page_flags) { + errno = EINVAL; + goto fail; + } + /* Also check for overflows... */ len = TARGET_PAGE_ALIGN(len); if (!len) { @@ -467,14 +510,15 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, /* Note: we prefer to control the mapping address. It is especially important if qemu_host_page_size > qemu_real_host_page_size */ - p = mmap(g2h(start), host_len, prot, + p = mmap(g2h(start), host_len, host_prot, flags | MAP_FIXED | MAP_ANONYMOUS, -1, 0); - if (p == MAP_FAILED) + if (p == MAP_FAILED) { goto fail; + } /* update start so that it points to the file position at 'offset' */ host_start = (unsigned long)p; if (!(flags & MAP_ANONYMOUS)) { - p = mmap(g2h(start), len, prot, + p = mmap(g2h(start), len, host_prot, flags | MAP_FIXED, fd, host_offset); if (p == MAP_FAILED) { munmap(g2h(start), host_len); @@ -508,19 +552,19 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, /* msync() won't work here, so we return an error if write is possible while it is a shared mapping */ if ((flags & MAP_TYPE) == MAP_SHARED && - (prot & PROT_WRITE)) { + (host_prot & PROT_WRITE)) { errno = EINVAL; goto fail; } - retaddr = target_mmap(start, len, prot | PROT_WRITE, + retaddr = target_mmap(start, len, target_prot | PROT_WRITE, MAP_FIXED | MAP_PRIVATE | MAP_ANONYMOUS, -1, 0); if (retaddr == -1) goto fail; if (pread(fd, g2h(start), len, offset) == -1) goto fail; - if (!(prot & PROT_WRITE)) { - ret = target_mprotect(start, len, prot); + if (!(host_prot & PROT_WRITE)) { + ret = target_mprotect(start, len, target_prot); assert(ret == 0); } goto the_end; @@ -531,13 +575,13 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, if (real_end == real_start + qemu_host_page_size) { /* one single host page */ ret = mmap_frag(real_start, start, end, - prot, flags, fd, offset); + host_prot, flags, fd, offset); if (ret == -1) goto fail; goto the_end1; } ret = mmap_frag(real_start, start, real_start + qemu_host_page_size, - prot, flags, fd, offset); + host_prot, flags, fd, offset); if (ret == -1) goto fail; real_start += qemu_host_page_size; @@ -546,7 +590,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, if (end < real_end) { ret = mmap_frag(real_end - qemu_host_page_size, real_end - qemu_host_page_size, end, - prot, flags, fd, + host_prot, flags, fd, offset + real_end - qemu_host_page_size - start); if (ret == -1) goto fail; @@ -562,13 +606,13 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int prot, else offset1 = offset + real_start - start; p = mmap(g2h(real_start), real_end - real_start, - prot, flags, fd, offset1); + host_prot, flags, fd, offset1); if (p == MAP_FAILED) goto fail; } } the_end1: - page_set_flags(start, start + len, prot | PAGE_VALID); + page_set_flags(start, start + len, page_flags); the_end: #ifdef DEBUG_MMAP printf("ret=0x" TARGET_ABI_FMT_lx "\n", start); From patchwork Wed Jun 5 20:57:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 165932 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp7864768ili; Wed, 5 Jun 2019 14:09:33 -0700 (PDT) X-Google-Smtp-Source: APXvYqw9kcDyUGvwZoiWzsqtYndA60Dx7/oahgxa3j1xylRzt/jtcIW684kCr1+b4mfTnk8qIoPp X-Received: by 2002:a37:4804:: with SMTP id v4mr36274092qka.330.1559768973594; Wed, 05 Jun 2019 14:09:33 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559768973; cv=none; d=google.com; s=arc-20160816; b=yMdNlaVvB15EO2ORnpx8ow06CBhievxWL9CUIZ3jYK5GXUtEkMOEG+3eMTN8epBDcQ TmmUVQKioQhg+ZqwIt4og6weZi/U/eWsHjSrnYEfmBkT4LH1YtFhv0Dhap5KdipWOWCC A+iQY2t8/0OCX/jqTcC59qEOwcUGTM3hhEV7b5dJQKZdtVEbtWg37GCDdIWaNCSyxhmp GZ3j/ZTuhyMUOx4WRp9pxXkjldA35dMtEmrud90nlmeQG4qOAwzXGjUxUJzo2cLp90x+ mDfPIcGH/HY+HqdacyejFXpgYjf3tafgoBrn+rxnEfzfCK/WEv7sl8uq9NYLU1LBtoWF rUbw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=ZCHRkKij7pQF0R23SJZo3xfE1Nbsenr9fc05DQb889w=; b=hJRUiSOXg0oS1Vypu0PQ++6gX1356Y9a/JxggSdBLXhjskjNY/H2q1AgFZ+IzM6uPt 1nrT3ij6efy/YxPMncAVWuEqfg+cHm4bbH21Yj0VTO1Zl5vsbJAsNrnWgQiiakQ5cujn lhXzQUgXHCAqn0E4ktGVnk2SM7zzLb7yGDqd6FgeaKGIvVdFoj5qWrP7uov5kxgOlWfW bv6bWdaSzirSD+WzCcxdIRD6xzaOZAKj3Z+yP/hNVEnR4PgeRwKlVCClzZK+6w8vJHZD 18+x8io80IN1Tz9Ws67JtFcv1HPz81yNHuI8GmX+DRaJiT7GX1YJxY2fBFkV0jXyzxVq XH4Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=EovjxdH3; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id f5sm7414155otl.51.2019.06.05.13.57.14 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jun 2019 13:57:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jun 2019 15:57:03 -0500 Message-Id: <20190605205706.569-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190605205706.569-1-richard.henderson@linaro.org> References: <20190605205706.569-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::342 Subject: [Qemu-devel] [PATCH v6 3/6] linux-user: Set PAGE_TARGET_1 for TARGET_PROT_BTI X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, Dave.Martin@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" Transform the prot bit to a qemu internal page bit, and save it in the page tables. Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 2 ++ linux-user/syscall_defs.h | 4 ++++ linux-user/mmap.c | 16 ++++++++++++++++ target/arm/translate-a64.c | 6 +++--- 4 files changed, 25 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index da07ce311f..e65530acae 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -249,6 +249,8 @@ extern intptr_t qemu_host_page_mask; /* FIXME: Code that sets/uses this is broken and needs to go away. */ #define PAGE_RESERVED 0x0020 #endif +/* Target-specific bits that will be used via page_get_flags(). */ +#define PAGE_TARGET_1 0x0080 #if defined(CONFIG_USER_ONLY) void page_dump(FILE *f); diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index 7f141f699c..9a8a14e81e 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -1097,6 +1097,10 @@ struct target_winsize { #define TARGET_PROT_SEM 0x08 #endif +#ifdef TARGET_AARCH64 +#define TARGET_PROT_BTI 0x10 +#endif + /* Common */ #define TARGET_MAP_SHARED 0x01 /* Share changes */ #define TARGET_MAP_PRIVATE 0x02 /* Changes are private */ diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 3117f57fd8..def64a41d5 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -85,6 +85,22 @@ static int validate_prot_to_pageflags(int *host_prot, int prot) */ *host_prot = prot & (PROT_READ | PROT_WRITE | PROT_EXEC); +#ifdef TARGET_AARCH64 + /* + * The PROT_BTI bit is only accepted if the cpu supports the feature. + * Since this is the unusual case, don't bother checking unless + * the bit has been requested. If set and valid, record the bit + * within QEMU's page_flags as PAGE_TARGET_1. + */ + if (prot & TARGET_PROT_BTI) { + ARMCPU *cpu = ARM_CPU(thread_cpu); + if (cpu_isar_feature(aa64_bti, cpu)) { + valid |= TARGET_PROT_BTI; + page_flags |= PAGE_TARGET_1; + } + } +#endif + return prot & ~valid ? 0 : page_flags; } diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 092f0df3c4..5043344eba 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14115,10 +14115,10 @@ static void disas_data_proc_simd_fp(DisasContext *s, uint32_t insn) */ static bool is_guarded_page(CPUARMState *env, DisasContext *s) { -#ifdef CONFIG_USER_ONLY - return false; /* FIXME */ -#else uint64_t addr = s->base.pc_first; +#ifdef CONFIG_USER_ONLY + return page_get_flags(addr) & PAGE_TARGET_1; +#else int mmu_idx = arm_to_core_mmu_idx(s->mmu_idx); unsigned int index = tlb_index(env, mmu_idx, addr); CPUTLBEntry *entry = tlb_entry(env, mmu_idx, addr); From patchwork Wed Jun 5 20:57:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 165926 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp7858941ili; Wed, 5 Jun 2019 14:03:53 -0700 (PDT) X-Google-Smtp-Source: APXvYqyVdxirpZYEFmJpsIe6dTGIWt2p8piiySYUqgVtXmR+saLZuWynNz0Y9lQr7VOTHdbgKkzS X-Received: by 2002:a0c:888a:: with SMTP id 10mr10704841qvn.0.1559768633119; Wed, 05 Jun 2019 14:03:53 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559768633; cv=none; d=google.com; s=arc-20160816; b=qsIbYSOuxP8d3KUcnCcChVM8AHbe6nd4sKPwJTkFSQVXJLAi3kuLXJDHH91uPCChCJ DDmAJT4mEFhSpiMpsgxfmKWV459wH7Hh5IgNPOPxoTZgdd6eRvIhjGgRrZZ1lzpgsZTx 12PLZE7h35BgxyCmhy2qPAd2DwoEl5e24r0XIGepqCKNKZYPoJJwlwIadixum5Wu6Ub0 S1R8afyp6j7sQAq5lpQb8HDAb8c7hL9n7O+H1TbrVATtuuKVkPbBROCQQHKmN68+sgfy RHL2UKbdJdf2LeY/Og5lVB+PRLsgMHSIoHNsZ1auO/rBc5tYqWB4JEkoDlCx3p+ZMOeO btvw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=D6qDvZ2yUvasBaOhuVQfPLH+R2qFXowjyUNz4x5+OYc=; b=jMm/s3I+YIc98iv9BfNjf+cnHf/xUasMfU7023BKlv2l+q4i59yR3ukBYBEAmLKNyU DyUF+azx06rv4UcRo3gVDXwRxTow1O5IThmlbRJQ7Pozac2Rj/Rx2Xg8AIvioUd5h+BU BnEKURj5MW/CrInoQQ23MAV+fZy3M5In6toGceQs+n15k8CDppzbmGGTLwPnnh6xVXo4 o2EHKbJf+VIjvPn+43DqNHkErVnyT33Fjt9JSDxjzQVw7PatjdNiPrZdtFFt94Wajynk h5YYtcHU3sYEF8U5SXrSn/Uzi68soePl+iSyGP7fxZZWLd5HMUQE5Ia2NnhZDejPUhBV 2/Ow== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b="J8pG3bM/"; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id f5sm7414155otl.51.2019.06.05.13.57.16 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jun 2019 13:57:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jun 2019 15:57:04 -0500 Message-Id: <20190605205706.569-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190605205706.569-1-richard.henderson@linaro.org> References: <20190605205706.569-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v6 4/6] include/elf: Add defines related to notes for GNU systems X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, Dave.Martin@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This is a collection of related defines for notes, copied from glibc's . We're not going to use all of these right away, but it seemed foolish to cherry-pick only the ones we need now. Signed-off-by: Richard Henderson --- include/elf.h | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+) -- 2.17.1 diff --git a/include/elf.h b/include/elf.h index ea7708a4ea..6f3eada36f 100644 --- a/include/elf.h +++ b/include/elf.h @@ -1650,6 +1650,54 @@ typedef struct elf64_shdr { #define NT_ARM_HW_WATCH 0x403 /* ARM hardware watchpoint registers */ #define NT_ARM_SYSTEM_CALL 0x404 /* ARM system call number */ +/* Defined note types for GNU systems. */ + +#define NT_GNU_ABI_TAG 1 /* ABI information */ +#define NT_GNU_HWCAP 2 /* Synthetic hwcap information */ +#define NT_GNU_BUILD_ID 3 /* Build ID */ +#define NT_GNU_GOLD_VERSION 4 /* Version of ld.gold */ +#define NT_GNU_PROPERTY_TYPE_0 5 /* Program property */ + +/* Values used in GNU .note.gnu.property notes (NT_GNU_PROPERTY_TYPE_0). */ + +#define GNU_PROPERTY_STACK_SIZE 1 +#define GNU_PROPERTY_NO_COPY_ON_PROTECTED 2 + +#define GNU_PROPERTY_LOPROC 0xc0000000 +#define GNU_PROPERTY_HIPROC 0xdfffffff +#define GNU_PROPERTY_LOUSER 0xe0000000 +#define GNU_PROPERTY_HIUSER 0xffffffff + +#define GNU_PROPERTY_X86_ISA_1_USED 0xc0000000 +#define GNU_PROPERTY_X86_ISA_1_NEEDED 0xc0000001 + +#define GNU_PROPERTY_X86_ISA_1_486 (1U << 0) +#define GNU_PROPERTY_X86_ISA_1_586 (1U << 1) +#define GNU_PROPERTY_X86_ISA_1_686 (1U << 2) +#define GNU_PROPERTY_X86_ISA_1_SSE (1U << 3) +#define GNU_PROPERTY_X86_ISA_1_SSE2 (1U << 4) +#define GNU_PROPERTY_X86_ISA_1_SSE3 (1U << 5) +#define GNU_PROPERTY_X86_ISA_1_SSSE3 (1U << 6) +#define GNU_PROPERTY_X86_ISA_1_SSE4_1 (1U << 7) +#define GNU_PROPERTY_X86_ISA_1_SSE4_2 (1U << 8) +#define GNU_PROPERTY_X86_ISA_1_AVX (1U << 9) +#define GNU_PROPERTY_X86_ISA_1_AVX2 (1U << 10) +#define GNU_PROPERTY_X86_ISA_1_AVX512F (1U << 11) +#define GNU_PROPERTY_X86_ISA_1_AVX512CD (1U << 12) +#define GNU_PROPERTY_X86_ISA_1_AVX512ER (1U << 13) +#define GNU_PROPERTY_X86_ISA_1_AVX512PF (1U << 14) +#define GNU_PROPERTY_X86_ISA_1_AVX512VL (1U << 15) +#define GNU_PROPERTY_X86_ISA_1_AVX512DQ (1U << 16) +#define GNU_PROPERTY_X86_ISA_1_AVX512BW (1U << 17) + +#define GNU_PROPERTY_X86_FEATURE_1_AND 0xc0000002 +#define GNU_PROPERTY_X86_FEATURE_1_IBT (1U << 0) +#define GNU_PROPERTY_X86_FEATURE_1_SHSTK (1U << 1) + +#define GNU_PROPERTY_AARCH64_FEATURE_1_AND 0xc0000000 +#define GNU_PROPERTY_AARCH64_FEATURE_1_BTI (1u << 0) +#define GNU_PROPERTY_AARCH64_FEATURE_1_PAC (1u << 1) + /* * Physical entry point into the kernel. * From patchwork Wed Jun 5 20:57:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 165927 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp7861767ili; Wed, 5 Jun 2019 14:06:38 -0700 (PDT) X-Google-Smtp-Source: APXvYqwVuyk9C/TA2RIXMzh4inFMMSj0GwLJYIla8/QxEnsK+CxT6gB8sqDm7caEh7AJTlPU4H97 X-Received: by 2002:a0c:b59c:: with SMTP id g28mr34871976qve.171.1559768797547; Wed, 05 Jun 2019 14:06:37 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559768797; cv=none; d=google.com; s=arc-20160816; b=pXAGd5VLdxQFH/ajAMfQMymIMmWyeJutfGnvhvdmvDKsEL/H6McQdiinJ2dJufFPc/ eRmA/4MRNqG8JkcuCSo/xmh8LHtD9k+rnkKgdRk3famq4Qs1CVI+GmkI5EjPTq+fme7a i4PhGb3D1dvpsT0eU00mD3Jkw8l/bYz5PgWo6U/+95VSUbipIiHyO6qynX3FWfK21Ztw KZaBMUtd+Ab2C/JTIJ120DFqZtIC/K4/FWC9fsohBjmtmJ0VInLH3yxJmqVMbohXvSyN QI1DSZf78MPUOi3Kzp66TtXGRgLfVosHNL8dbec/j1NWVXiCxPWbWh0UkQEtUkomC1n8 JH/Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=jLJZRLTAFOL7hrqtZKjJ5DWxzgzN1ppLIoLLfp8TQiM=; b=pYTDkRyMnMJBmE3Cd5nVJv0Y1aUU3z5zDSidYolVOMXmgNjENOE7pPsdbxn936++yA kItC8Ta0EcugBl6+03msik7uouIZKukzF8ohi4QP6NOlT3xqVrALQOXAiZ/VTG/gpFe4 boOw14KCRlcO2OLctuMaYAAqB/EHiPNjWAuW1iFgsCFLuB5MB7Xnp3SvizpV0cG3Rmpb eBmznmcOhfR+Rqr2nOyCBF2M+WvETKhdI8O6dqivPpJR8jWp68KSVkL2F+7SnRv2OdnZ LPDnLyoN2uRZZhCD6nFA5bn5WbIkZ3dqAwi0yMXjc851L9ibZ6KvLvDQn2YnMBXhmkCP DZlw== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=nHI2qAKF; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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X-Received-From: 2607:f8b0:4864:20::341 Subject: [Qemu-devel] [PATCH v6 5/6] linux-user: Parse NT_GNU_PROPERTY_TYPE_0 notes X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, Dave.Martin@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" For aarch64, this includes the GNU_PROPERTY_AARCH64_FEATURE_1_BTI bit, which indicates that the image should be mapped with guarded pages. Signed-off-by: Richard Henderson --- linux-user/elfload.c | 83 +++++++++++++++++++++++++++++++++++++++----- 1 file changed, 75 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/linux-user/elfload.c b/linux-user/elfload.c index a57b7049dd..1a12c60a33 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2253,7 +2253,7 @@ static void load_elf_image(const char *image_name, int image_fd, struct elfhdr *ehdr = (struct elfhdr *)bprm_buf; struct elf_phdr *phdr; abi_ulong load_addr, load_bias, loaddr, hiaddr, error; - int i, retval; + int i, retval, prot_exec = PROT_EXEC; const char *errmsg; /* First of all, some simple consistency checks */ @@ -2288,17 +2288,78 @@ static void load_elf_image(const char *image_name, int image_fd, loaddr = -1, hiaddr = 0; info->alignment = 0; for (i = 0; i < ehdr->e_phnum; ++i) { - if (phdr[i].p_type == PT_LOAD) { - abi_ulong a = phdr[i].p_vaddr - phdr[i].p_offset; + struct elf_phdr *eppnt = phdr + i; + + if (eppnt->p_type == PT_LOAD) { + abi_ulong a = eppnt->p_vaddr - eppnt->p_offset; if (a < loaddr) { loaddr = a; } - a = phdr[i].p_vaddr + phdr[i].p_memsz; + a = eppnt->p_vaddr + eppnt->p_memsz; if (a > hiaddr) { hiaddr = a; } ++info->nsegs; - info->alignment |= phdr[i].p_align; + info->alignment |= eppnt->p_align; + } else if (eppnt->p_type == PT_NOTE) { +#ifdef TARGET_AARCH64 + /* + * Process NT_GNU_PROPERTY_TYPE_0. + * + * TODO: The only item that is AArch64 specific is the + * GNU_PROPERTY_AARCH64_FEATURE_1_AND processing at the end. + * If we were to ever process GNU_PROPERTY_X86_*, all of the + * code through checking the gnu0 magic number is sharable. + * But for now, since this *is* only used by AArch64, don't + * process the note elsewhere. + */ + const uint32_t gnu0_magic = const_le32('G' | 'N' << 8 | 'U' << 16); + uint32_t note[7]; + + /* + * The note contents are 7 words, but depending on LP64 vs ILP32 + * there may be an 8th padding word at the end. Check for and + * read the minimum size. Further checks below will validate + * that the sizes of everything involved are as we expect. + */ + if (eppnt->p_filesz < sizeof(note)) { + continue; + } + if (eppnt->p_offset + eppnt->p_filesz <= BPRM_BUF_SIZE) { + memcpy(note, bprm_buf + eppnt->p_offset, sizeof(note)); + } else { + retval = pread(image_fd, note, sizeof(note), eppnt->p_offset); + if (retval != sizeof(note)) { + goto exit_perror; + } + } +#ifdef BSWAP_NEEDED + for (i = 0; i < ARRAY_SIZE(note); ++i) { + bswap32s(note + i); + } +#endif + /* + * Check that this is a NT_GNU_PROPERTY_TYPE_0 note. + * Again, descsz includes padding. Full size validation + * awaits checking the final payload. + */ + if (note[0] != 4 || /* namesz */ + note[1] < 12 || /* descsz */ + note[2] != NT_GNU_PROPERTY_TYPE_0 || /* type */ + note[3] != gnu0_magic) { /* name */ + continue; + } + /* + * Check for the BTI feature. If present, this indicates + * that all the executable pages of the binary should be + * mapped with PROT_BTI, so that branch targets are enforced. + */ + if (note[4] == GNU_PROPERTY_AARCH64_FEATURE_1_AND && + note[5] == 4 && + (note[6] & GNU_PROPERTY_AARCH64_FEATURE_1_BTI)) { + prot_exec |= TARGET_PROT_BTI; + } +#endif /* TARGET_AARCH64 */ } } @@ -2358,9 +2419,15 @@ static void load_elf_image(const char *image_name, int image_fd, abi_ulong vaddr, vaddr_po, vaddr_ps, vaddr_ef, vaddr_em, vaddr_len; int elf_prot = 0; - if (eppnt->p_flags & PF_R) elf_prot = PROT_READ; - if (eppnt->p_flags & PF_W) elf_prot |= PROT_WRITE; - if (eppnt->p_flags & PF_X) elf_prot |= PROT_EXEC; + if (eppnt->p_flags & PF_R) { + elf_prot |= PROT_READ; + } + if (eppnt->p_flags & PF_W) { + elf_prot |= PROT_WRITE; + } + if (eppnt->p_flags & PF_X) { + elf_prot |= prot_exec; + } vaddr = load_bias + eppnt->p_vaddr; vaddr_po = TARGET_ELF_PAGEOFFSET(vaddr); From patchwork Wed Jun 5 20:57:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 165933 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp7866560ili; Wed, 5 Jun 2019 14:11:22 -0700 (PDT) X-Google-Smtp-Source: APXvYqwhiFsKrMhZ23kHyPziKkOqYyYxX4NSFkYaxBFFKm+Lg6ZrjZDtw7qGuW6AyULwZN0eb+Lk X-Received: by 2002:a0c:9357:: with SMTP id e23mr4039596qve.173.1559769082316; Wed, 05 Jun 2019 14:11:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559769082; cv=none; d=google.com; s=arc-20160816; b=Koh3aNO2T3tou/su+rH5zcv4z/86FpYalxwV4G2NFQwc/DupF5H35joZTSGsp8r1zv +8uCdwV192vormsPE4xFz/hFBkUd3QIx/dyNu9ZKmSOPqJf+gCPZS2Pi727PDVzO6x5r m156yFF+jw8OfAXZATjzr3Vm2L9B/otjKNgJp0+4m3mX5NFyUtblpJZH8bxpC2KkWF9t 8+BHsVt5tJ4I7zHUSwzCmp0zmBXH+FoXgEbcQdieTloRX2QrsG8aeaVSnGw9nU0zGaef 41jNG3srWf6S7iFqlnK9x4H8lJs/LfEH/UZXh9rs7ko5XoKNwUxKtwoqyjw9FOSrnt7o zScg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:cc:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:subject:references:in-reply-to :message-id:date:to:from:dkim-signature; bh=c6s3cz8Azngdshx9nMls9ehZ7rxdcfsNQPzwRD0wABs=; b=K/Xm2PtMKqtfdy6Vjzfy+WTE/5we1U93p6bwMSZCkpy7oLmAJNOo9BFbi1Ic4J73uP TaieEXb8Zxwz5LXBwqekw9qKderudSyE9FRRZxgZiPXsHW90EzldMqaRVoW1Do3yQ6eE FHXQFxQIQ6hCy0zXw/n4ss4J5LPhdf9volvjdwvtPz7nI/eJoy4ZonIMdrz3VzAFLNNM vngm9TCbrH2f+3R6ihl0q+h7q90vYjjO+moC+PZliWXtFIz82hZdcovp4RjUpPPf4+ko AQhkBLRhOkd0lVE/VIWCbC2gV8jbSnGYid2BEqX24jzfawWEIXicWV1QjFRc8M+SYn+C khNQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=fail header.i=@linaro.org header.s=google header.b=Pi3aTdqr; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=fail (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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[200.56.192.86]) by smtp.gmail.com with ESMTPSA id f5sm7414155otl.51.2019.06.05.13.57.20 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 05 Jun 2019 13:57:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Date: Wed, 5 Jun 2019 15:57:06 -0500 Message-Id: <20190605205706.569-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190605205706.569-1-richard.henderson@linaro.org> References: <20190605205706.569-1-richard.henderson@linaro.org> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::343 Subject: [Qemu-devel] [PATCH v6 6/6] tests/tcg/aarch64: Add bti smoke test X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, Dave.Martin@arm.com Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: "Qemu-devel" This will build with older toolchains, without the upstream support for -mbranch-protection. Such a toolchain will produce a warning in such cases, ld: warning: /tmp/ccyZt0kq.o: unsupported GNU_PROPERTY_TYPE (5) \ type: 0xc0000000 but the still places the note at the correct location in the binary for processing by the runtime loader. Signed-off-by: Richard Henderson --- tests/tcg/aarch64/bti-1.c | 77 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/bti-crt.inc.c | 69 +++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 3 ++ 3 files changed, 149 insertions(+) create mode 100644 tests/tcg/aarch64/bti-1.c create mode 100644 tests/tcg/aarch64/bti-crt.inc.c -- 2.17.1 diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c new file mode 100644 index 0000000000..2aee57ea7a --- /dev/null +++ b/tests/tcg/aarch64/bti-1.c @@ -0,0 +1,77 @@ +/* + * Branch target identification, basic notskip cases. + */ + +#include "bti-crt.inc.c" + +/* + * Work around lack of -mbranch-protection=standard in older toolchains. + * The signal handler is invoked by the kernel with PSTATE.BTYPE=2, which + * means that the handler must begin with a marker like BTI_C. + */ +asm("skip2_sigill1:\n\ + hint #34\n\ + b skip2_sigill2\n\ +.type skip2_sigill1,%function\n\ +.size skip2_sigill1,8"); + +extern void skip2_sigill1(int sig, siginfo_t *info, ucontext_t *uc) + __attribute__((visibility("hidden"))); + +static void __attribute__((used)) +skip2_sigill2(int sig, siginfo_t *info, ucontext_t *uc) +{ + uc->uc_mcontext.pc += 8; + uc->uc_mcontext.pstate = 1; +} + +#define NOP "nop" +#define BTI_N "hint #32" +#define BTI_C "hint #34" +#define BTI_J "hint #36" +#define BTI_JC "hint #38" + +#define BTYPE_1(DEST) \ + asm("mov %0,#1; adr x16, 1f; br x16; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x16") + +#define BTYPE_2(DEST) \ + asm("mov %0,#1; adr x16, 1f; blr x16; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x16", "x30") + +#define BTYPE_3(DEST) \ + asm("mov %0,#1; adr x15, 1f; br x15; 1: " DEST "; mov %0,#0" \ + : "=r"(skipped) : : "x15") + +#define TEST(WHICH, DEST, EXPECT) \ + do { WHICH(DEST); fail += skipped ^ EXPECT; } while (0) + + +int main() +{ + int fail = 0; + int skipped; + + /* Signal-like with SA_SIGINFO. */ + signal_info(SIGILL, skip2_sigill1); + + TEST(BTYPE_1, NOP, 1); + TEST(BTYPE_1, BTI_N, 1); + TEST(BTYPE_1, BTI_C, 0); + TEST(BTYPE_1, BTI_J, 0); + TEST(BTYPE_1, BTI_JC, 0); + + TEST(BTYPE_2, NOP, 1); + TEST(BTYPE_2, BTI_N, 1); + TEST(BTYPE_2, BTI_C, 0); + TEST(BTYPE_2, BTI_J, 1); + TEST(BTYPE_2, BTI_JC, 0); + + TEST(BTYPE_3, NOP, 1); + TEST(BTYPE_3, BTI_N, 1); + TEST(BTYPE_3, BTI_C, 1); + TEST(BTYPE_3, BTI_J, 0); + TEST(BTYPE_3, BTI_JC, 0); + + return fail; +} diff --git a/tests/tcg/aarch64/bti-crt.inc.c b/tests/tcg/aarch64/bti-crt.inc.c new file mode 100644 index 0000000000..bb363853de --- /dev/null +++ b/tests/tcg/aarch64/bti-crt.inc.c @@ -0,0 +1,69 @@ +/* + * Minimal user-environment for testing BTI. + * + * Normal libc is not built with BTI support enabled, and so could + * generate a BTI TRAP before ever reaching main. + */ + +#include +#include +#include +#include + +int main(void); + +void _start(void) +{ + exit(main()); +} + +void exit(int ret) +{ + register int x0 __asm__("x0") = ret; + register int x8 __asm__("x8") = __NR_exit; + + asm volatile("svc #0" : : "r"(x0), "r"(x8)); + __builtin_unreachable(); +} + +/* + * Irritatingly, the user API struct sigaction does not match the + * kernel API struct sigaction. So for simplicity, isolate the + * kernel ABI here, and make this act like signal. + */ +void signal_info(int sig, void (*fn)(int, siginfo_t *, ucontext_t *)) +{ + struct kernel_sigaction { + void (*handler)(int, siginfo_t *, ucontext_t *); + unsigned long flags; + unsigned long restorer; + unsigned long mask; + } sa = { fn, SA_SIGINFO, 0, 0 }; + + register int x0 __asm__("x0") = sig; + register void *x1 __asm__("x1") = &sa; + register void *x2 __asm__("x2") = 0; + register int x3 __asm__("x3") = sizeof(unsigned long); + register int x8 __asm__("x8") = __NR_rt_sigaction; + + asm volatile("svc #0" + : : "r"(x0), "r"(x1), "r"(x2), "r"(x3), "r"(x8) : "memory"); +} + +/* + * Create the PT_NOTE that will enable BTI in the page tables. + * This will be created by the compiler with -mbranch-protection=standard, + * but as of 2019-03-29, this is has not been committed to gcc mainline. + * This will probably be in GCC10. + */ +asm(".section .note.gnu.property,\"a\"\n\ + .align 3\n\ + .long 4\n\ + .long 16\n\ + .long 5\n\ + .string \"GNU\"\n\ + .long 0xc0000000\n\ + .long 4\n\ + .long 1\n\ + .align 3\n\ + .previous"); diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 2bb914975b..21da3bc37f 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -18,4 +18,7 @@ run-fcvt: fcvt AARCH64_TESTS += pauth-1 run-pauth-%: QEMU += -cpu max +AARCH64_TESTS += bti-1 +bti-1: LDFLAGS += -nostartfiles -nodefaultlibs -nostdlib + TESTS:=$(AARCH64_TESTS)