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[209.51.188.17]) by mx.google.com with ESMTPS id s15-20020ac85ccf000000b003f2309181eesi824774qta.389.2023.05.03.00.32.31 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 May 2023 00:32:31 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=JtNtM5mU; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pu6pC-0007VS-0V; Wed, 03 May 2023 03:22:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pu6oq-0006nC-4R for qemu-devel@nongnu.org; Wed, 03 May 2023 03:22:40 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pu6oj-0007Gw-24 for qemu-devel@nongnu.org; Wed, 03 May 2023 03:22:27 -0400 Received: by mail-wm1-x332.google.com with SMTP id 5b1f17b1804b1-3f19ab99540so46397395e9.2 for ; Wed, 03 May 2023 00:22:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683098543; x=1685690543; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=czFfn3mdhb3cc0K7eXA/dlkeA2fEfLq9sRo8IDRWWf8=; b=JtNtM5mU/Sx4s4CCdz34ODajSonIkcNUGY8EhUAksM0OX+y9BTiFv32nCtcHPeCWYW qqeixvAUYJWK+7W9v0KQQk916okscfAshKBzqMIp8row5ExnXjzKO2S1pCbXGPOfFp7h P69xs6o8lgtcoWDmVa7naZx63u2/m5d9nUab9sN+OjhbB7nFvM79OGpufdU6bipy2Ecw isXD+pId+JzLEtXfBzQOUkKSG8/+MbNjmPKEPAM4hB9nH3sxz00NsnH8zaQe1PDl24pH vhinJAG0w7/VFSylfkngvB1qziY1PsGQcH6ZVxQA6XI+1f8RFljXwQL3Ytz7zd+XYoy5 RR2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683098543; x=1685690543; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=czFfn3mdhb3cc0K7eXA/dlkeA2fEfLq9sRo8IDRWWf8=; b=VE6Um6XVeLsBQdKn8Z4/a9nLAlgPeQVCh16Srdj5RYqD0HhngcNq5PN9+maqFrF3i3 GZVNKV88ZKK4/HuShqQO46cQXbYNraPkASMiz+PtfNCQP17DXO0ig4iXqIjO+Sm8BWya m38tZGM7FJvwtQqmRPVxqYM21f3Co38utefK4P+8gEfDdMI9V1SSFI4IOHgicfqla0PD Kfby6jmIk4Wbo/8T8tTh3diN+mS2HNXRjauAZYlq4bvhEk524bnkKabIf9X9PDM8lrPa Ug7cQh/1B/+aSJ0k2qS4N/rzQQaA6ylGuYoX1bZFQW8gpdIGIZB2bVqXL+IxBEfBNUyb tG9w== X-Gm-Message-State: AC+VfDwJo9ZMVFh9B8Fb1H7bGBqEKAD3zEhqo/VPubSBDfrDqoQDidgO mDKnshrtN5HuOBKyDvQ13EDmx/8CMOtsStDW2XKPJQ== X-Received: by 2002:a05:600c:2183:b0:3f1:76d7:ae2b with SMTP id e3-20020a05600c218300b003f176d7ae2bmr14290163wme.13.1683098543097; Wed, 03 May 2023 00:22:23 -0700 (PDT) Received: from stoup.Home ([2a02:c7c:74db:8d00:c01d:9d74:b630:9087]) by smtp.gmail.com with ESMTPSA id t4-20020a7bc3c4000000b003f1745c7df3sm962789wmj.23.2023.05.03.00.22.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 May 2023 00:22:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ale@rev.ng, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com, anjo@rev.ng, Thomas Huth , Juan Quintela Subject: [PULL v2 01/12] softmmu: Tidy dirtylimit_dirty_ring_full_time Date: Wed, 3 May 2023 08:20:46 +0100 Message-Id: <20230503072221.1746802-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230503072221.1746802-1-richard.henderson@linaro.org> References: <20230503072221.1746802-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Drop inline marker: let compiler decide. Change return type to uint64_t: this matches the computation in the return statement and the local variable assignment in the caller. Rename local to dirty_ring_size_MB to fix typo. Simplify conversion to MiB via qemu_target_page_bits and right shift. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Thomas Huth Reviewed-by: Juan Quintela Signed-off-by: Richard Henderson --- softmmu/dirtylimit.c | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/softmmu/dirtylimit.c b/softmmu/dirtylimit.c index 82986c1499..71bf6dc7a4 100644 --- a/softmmu/dirtylimit.c +++ b/softmmu/dirtylimit.c @@ -232,18 +232,23 @@ bool dirtylimit_vcpu_index_valid(int cpu_index) cpu_index >= ms->smp.max_cpus); } -static inline int64_t dirtylimit_dirty_ring_full_time(uint64_t dirtyrate) +static uint64_t dirtylimit_dirty_ring_full_time(uint64_t dirtyrate) { static uint64_t max_dirtyrate; - uint32_t dirty_ring_size = kvm_dirty_ring_size(); - uint64_t dirty_ring_size_meory_MB = - dirty_ring_size * qemu_target_page_size() >> 20; + unsigned target_page_bits = qemu_target_page_bits(); + uint64_t dirty_ring_size_MB; + + /* So far, the largest (non-huge) page size is 64k, i.e. 16 bits. */ + assert(target_page_bits < 20); + + /* Convert ring size (pages) to MiB (2**20). */ + dirty_ring_size_MB = kvm_dirty_ring_size() >> (20 - target_page_bits); if (max_dirtyrate < dirtyrate) { max_dirtyrate = dirtyrate; } - return dirty_ring_size_meory_MB * 1000000 / max_dirtyrate; + return dirty_ring_size_MB * 1000000 / max_dirtyrate; } static inline bool dirtylimit_done(uint64_t quota, From patchwork Wed May 3 07:20:48 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 678681 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp910290wrs; Wed, 3 May 2023 00:28:17 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6iesTMNy4Ml1912bQs5kwTOFxJQpRD4Log+Ucb2qeY7aVrN6SSC/07lx+/41pzra9Mgnom X-Received: by 2002:a05:6214:5084:b0:61a:943c:11fd with SMTP id kk4-20020a056214508400b0061a943c11fdmr9372635qvb.4.1683098896688; Wed, 03 May 2023 00:28:16 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683098896; cv=none; d=google.com; s=arc-20160816; b=bU8u1nrGc2P4DHxE1mE75K7coYqGFFrYDuAf5PqHLEtLwQVtMDQnGx9FqW8KOk8CMw zkrMFtd8BeR8Q8QhYN+GPIG9ZHkCNgX3erOirf6XTFIJ+nazqmLw1TYrlEeSlafpUTnm 5+vHMP6DN2U3yzLVUCAm6ZqFN8jbRVpzXxm5KfGKAg95EOGxLsq4ElWUSOodr98DcBao 0bnlyQK6CSL9I/F2VEnuk3RRBNNA0M1litdppJQp7/bEK59N8VgY6ugzMHw4a6gefbjb jE2aGAkeTA2p8HOSI1sHjindvsvp7b+VfH1Ar3xs/i0usDUR0ZgKJUj4jhAMEb9PRyVX AKQg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=lK51qYTnNnXJZN0e/9Jj4Bv1cCHWx7/0IfdphjJpI60=; b=KlcXwEujIjbInHcBx21q4hv1FLVbOuAN+pt6MPS9rBFcCSgmMjoSZXu+UgSCzYRtGx COIqARPPe2UmYeYGGKKoWGCGE7Xo7zQAR2Qo6662Trgy7JuzPzlGiiUE36xbZaWYLpfy rbi75yLcwakkf7gtF4xD2SPtabX/s6JQO0S25XEJtDpfuDTwToMm0CnE53x74EWreR/B cW8kEuc2igpN/S9j7C6NAo3OLQ09CicN5oXX8TZJdvJxJrVLqtIyhd0vwRhl6VHV2opf AeQ0pLfeHRPi3io3qD1coKU8Co8atFMoeMbDUfZ7wd7wwI2az7S/2n3UKpYb4UBX8Ive A46Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=oh2uZrao; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Wed, 03 May 2023 00:22:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ale@rev.ng, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com, anjo@rev.ng, Weiwei Li , Junqiang Wang , LIU Zhiwei Subject: [PULL v2 02/12] accel/tcg: Uncache the host address for instruction fetch when tlb size < 1 Date: Wed, 3 May 2023 08:20:48 +0100 Message-Id: <20230503072221.1746802-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230503072221.1746802-1-richard.henderson@linaro.org> References: <20230503072221.1746802-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Weiwei Li When PMP entry overlap part of the page, we'll set the tlb_size to 1, which will make the address in tlb entry set with TLB_INVALID_MASK, and the next access will again go through tlb_fill.However, this way will not work in tb_gen_code() => get_page_addr_code_hostp(): the TLB host address will be cached, and the following instructions can use this host address directly which may lead to the bypass of PMP related check. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1542. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: LIU Zhiwei Reviewed-by: Richard Henderson Message-Id: <20230422130329.23555-6-liweiwei@iscas.ac.cn> --- accel/tcg/cputlb.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index e984a98dc4..efa0cb67c9 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1696,6 +1696,11 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState *env, target_ulong addr, if (p == NULL) { return -1; } + + if (full->lg_page_size < TARGET_PAGE_BITS) { + return -1; + } + if (hostp) { *hostp = p; } From patchwork Wed May 3 07:20:50 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 678672 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp909801wrs; Wed, 3 May 2023 00:26:45 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6673DwinXijwLS6+9JH1UOI6E/68k8rNxYWtfaTspbjm7H8gy0a4NPdgiFgVv1jxH43pHR X-Received: by 2002:a05:6214:f2a:b0:61b:3557:a699 with SMTP id iw10-20020a0562140f2a00b0061b3557a699mr8728744qvb.9.1683098805274; Wed, 03 May 2023 00:26:45 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683098805; cv=none; d=google.com; s=arc-20160816; b=VKC4E95+qNxc4Swy4YDvT6bt4/+k4BQTkMlu95EfpWqzo1sY1j0G9gC8aKfmDNHm0S EgXjR7mlOxwBgLGDdgUFYCqI7My4DNMNiCqDX5uegl+5AZOHdDNYFq0UNXSqXE+dib66 S54HEZ//K/pmY5C0oEp2lRSK/cAjHjcQNB1Rh2bjGSqWgjR/8aWLa+m4xTqPfG+xHnC6 lQq3xPVhXL1oVJdG8YMp1sTf3XyXm6/eN6ldrFGLI2xaGAmoVJIt0iGh6K6uaTNwRfZo yNOQaoKxZVYxtrmG05q9PT12vcQshP6Ycb5pvrmrNqTZoDH6GafBo72/y0htRr00wwiN sYaA== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=/U0Vyp8Amqznn7BNsR01h6DT7+XVVrY10qRvQ4sHEiE=; b=DxSs7rItTsi8IzHMXX4+QCAMFkGqiAX94GD3lZvs7Cvye6cYFe2mKgK2/rTbzIDdEl lfmrF2NGLzSPgttQKrI20CjFZlB05fII7ahpBRnoFO9c1tLZwFHTMvLjcTRE92xeGa/g UbWbMNmlfDmLSuB/lHfo0tRAHiJCTAjrpGWvP4NY6nINOI27VFLs7G8dS33GOSlk3hR1 uuCTIPx/RTfPWJ6e4yaT+48rEkxpZbbNfDTCqhiOn9T9c/c7HyefFBDK3Uq6uh9nORZz 6Z33Y8qdPEMHNl3aPDYrN/7FbWn3kYpMi9wZtXK7T6zLpo0+UTQoxar+kZCrx1+XVlZe MN0g== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=m3yMyZNS; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Adjust tcg_out_{ld,st}_helper_args to match. Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 26 +++++++++--------- accel/tcg/cputlb.c | 26 +++++++++--------- accel/tcg/user-exec.c | 26 +++++++++--------- tcg/tcg.c | 62 ++++++++++++++++++++++++++++++++---------- 4 files changed, 87 insertions(+), 53 deletions(-) diff --git a/include/tcg/tcg-ldst.h b/include/tcg/tcg-ldst.h index 7dd57013e9..6ccfe9131d 100644 --- a/include/tcg/tcg-ldst.h +++ b/include/tcg/tcg-ldst.h @@ -26,38 +26,38 @@ #define TCG_LDST_H /* Value zero-extended to tcg register size. */ -tcg_target_ulong helper_ldub_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_lduw_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_ldul_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); -uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, +uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); -Int128 helper_ld16_mmu(CPUArchState *env, target_ulong addr, +Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); /* Value sign-extended to tcg register size. */ -tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); -tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr); /* * Value extended to at least uint32_t, so that some ABIs do not require * zero-extension from uint8_t or uint16_t. */ -void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); -void helper_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); -void helper_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr); -void helper_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, +void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr); -void helper_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, +void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx oi, uintptr_t retaddr); #endif /* TCG_LDST_H */ diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index a77b439df8..b594401267 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -2357,7 +2357,7 @@ static uint8_t do_ld1_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, return do_ld_1(env, &l.page[0], l.mmu_idx, access_type, ra); } -tcg_target_ulong helper_ldub_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_8); @@ -2388,7 +2388,7 @@ static uint16_t do_ld2_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, return ret; } -tcg_target_ulong helper_lduw_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_16); @@ -2415,7 +2415,7 @@ static uint32_t do_ld4_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, return ret; } -tcg_target_ulong helper_ldul_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_32); @@ -2442,7 +2442,7 @@ static uint64_t do_ld8_mmu(CPUArchState *env, target_ulong addr, MemOpIdx oi, return ret; } -uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, +uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64); @@ -2454,19 +2454,19 @@ uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, * avoid this for 64-bit data, or for 32-bit data on 32-bit host. */ -tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { return (int8_t)helper_ldub_mmu(env, addr, oi, retaddr); } -tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { return (int16_t)helper_lduw_mmu(env, addr, oi, retaddr); } -tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t retaddr) { return (int32_t)helper_ldul_mmu(env, addr, oi, retaddr); @@ -2534,7 +2534,7 @@ static Int128 do_ld16_mmu(CPUArchState *env, target_ulong addr, return ret; } -Int128 helper_ld16_mmu(CPUArchState *env, target_ulong addr, +Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr, uint32_t oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_128); @@ -2842,7 +2842,7 @@ static void do_st_8(CPUArchState *env, MMULookupPageData *p, uint64_t val, } } -void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { MMULookupLocals l; @@ -2877,7 +2877,7 @@ static void do_st2_mmu(CPUArchState *env, target_ulong addr, uint16_t val, do_st_1(env, &l.page[1], b, l.mmu_idx, ra); } -void helper_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_16); @@ -2904,7 +2904,7 @@ static void do_st4_mmu(CPUArchState *env, target_ulong addr, uint32_t val, (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); } -void helper_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_32); @@ -2931,7 +2931,7 @@ static void do_st8_mmu(CPUArchState *env, target_ulong addr, uint64_t val, (void) do_st_leN(env, &l.page[1], val, l.mmu_idx, l.memop, ra); } -void helper_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, +void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_64); @@ -2999,7 +2999,7 @@ static void do_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, } } -void helper_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, +void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx oi, uintptr_t retaddr) { tcg_debug_assert((get_memop(oi) & MO_SIZE) == MO_128); diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 7b824dcde8..9a7afb6f78 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -920,13 +920,13 @@ static uint8_t do_ld1_mmu(CPUArchState *env, abi_ptr addr, return ret; } -tcg_target_ulong helper_ldub_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldub_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { return do_ld1_mmu(env, addr, get_memop(oi), ra); } -tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsb_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { return (int8_t)do_ld1_mmu(env, addr, get_memop(oi), ra); @@ -953,7 +953,7 @@ static uint16_t do_ld2_he_mmu(CPUArchState *env, abi_ptr addr, return ret; } -tcg_target_ulong helper_lduw_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_lduw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { MemOp mop = get_memop(oi); @@ -965,7 +965,7 @@ tcg_target_ulong helper_lduw_mmu(CPUArchState *env, target_ulong addr, return ret; } -tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsw_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { MemOp mop = get_memop(oi); @@ -1014,7 +1014,7 @@ static uint32_t do_ld4_he_mmu(CPUArchState *env, abi_ptr addr, return ret; } -tcg_target_ulong helper_ldul_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldul_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { MemOp mop = get_memop(oi); @@ -1026,7 +1026,7 @@ tcg_target_ulong helper_ldul_mmu(CPUArchState *env, target_ulong addr, return ret; } -tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, target_ulong addr, +tcg_target_ulong helper_ldsl_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { MemOp mop = get_memop(oi); @@ -1075,7 +1075,7 @@ static uint64_t do_ld8_he_mmu(CPUArchState *env, abi_ptr addr, return ret; } -uint64_t helper_ldq_mmu(CPUArchState *env, target_ulong addr, +uint64_t helper_ldq_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { MemOp mop = get_memop(oi); @@ -1124,7 +1124,7 @@ static Int128 do_ld16_he_mmu(CPUArchState *env, abi_ptr addr, return ret; } -Int128 helper_ld16_mmu(CPUArchState *env, target_ulong addr, +Int128 helper_ld16_mmu(CPUArchState *env, uint64_t addr, MemOpIdx oi, uintptr_t ra) { MemOp mop = get_memop(oi); @@ -1182,7 +1182,7 @@ static void do_st1_mmu(CPUArchState *env, abi_ptr addr, uint8_t val, clear_helper_retaddr(); } -void helper_stb_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stb_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { do_st1_mmu(env, addr, val, get_memop(oi), ra); @@ -1206,7 +1206,7 @@ static void do_st2_he_mmu(CPUArchState *env, abi_ptr addr, uint16_t val, clear_helper_retaddr(); } -void helper_stw_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stw_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { MemOp mop = get_memop(oi); @@ -1248,7 +1248,7 @@ static void do_st4_he_mmu(CPUArchState *env, abi_ptr addr, uint32_t val, clear_helper_retaddr(); } -void helper_stl_mmu(CPUArchState *env, target_ulong addr, uint32_t val, +void helper_stl_mmu(CPUArchState *env, uint64_t addr, uint32_t val, MemOpIdx oi, uintptr_t ra) { MemOp mop = get_memop(oi); @@ -1290,7 +1290,7 @@ static void do_st8_he_mmu(CPUArchState *env, abi_ptr addr, uint64_t val, clear_helper_retaddr(); } -void helper_stq_mmu(CPUArchState *env, target_ulong addr, uint64_t val, +void helper_stq_mmu(CPUArchState *env, uint64_t addr, uint64_t val, MemOpIdx oi, uintptr_t ra) { MemOp mop = get_memop(oi); @@ -1332,7 +1332,7 @@ static void do_st16_he_mmu(CPUArchState *env, abi_ptr addr, Int128 val, clear_helper_retaddr(); } -void helper_st16_mmu(CPUArchState *env, target_ulong addr, Int128 val, +void helper_st16_mmu(CPUArchState *env, uint64_t addr, Int128 val, MemOpIdx oi, uintptr_t ra) { MemOp mop = get_memop(oi); diff --git a/tcg/tcg.c b/tcg/tcg.c index a3b8c82073..685e555754 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -768,7 +768,7 @@ static TCGHelperInfo info_helper_ld32_mmu = { .flags = TCG_CALL_NO_WG, .typemask = dh_typemask(ttl, 0) /* return tcg_target_ulong */ | dh_typemask(env, 1) - | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 2) /* uint64_t addr */ | dh_typemask(i32, 3) /* unsigned oi */ | dh_typemask(ptr, 4) /* uintptr_t ra */ }; @@ -777,7 +777,7 @@ static TCGHelperInfo info_helper_ld64_mmu = { .flags = TCG_CALL_NO_WG, .typemask = dh_typemask(i64, 0) /* return uint64_t */ | dh_typemask(env, 1) - | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 2) /* uint64_t addr */ | dh_typemask(i32, 3) /* unsigned oi */ | dh_typemask(ptr, 4) /* uintptr_t ra */ }; @@ -786,7 +786,7 @@ static TCGHelperInfo info_helper_ld128_mmu = { .flags = TCG_CALL_NO_WG, .typemask = dh_typemask(i128, 0) /* return Int128 */ | dh_typemask(env, 1) - | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 2) /* uint64_t addr */ | dh_typemask(i32, 3) /* unsigned oi */ | dh_typemask(ptr, 4) /* uintptr_t ra */ }; @@ -795,7 +795,7 @@ static TCGHelperInfo info_helper_st32_mmu = { .flags = TCG_CALL_NO_WG, .typemask = dh_typemask(void, 0) | dh_typemask(env, 1) - | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 2) /* uint64_t addr */ | dh_typemask(i32, 3) /* uint32_t data */ | dh_typemask(i32, 4) /* unsigned oi */ | dh_typemask(ptr, 5) /* uintptr_t ra */ @@ -805,7 +805,7 @@ static TCGHelperInfo info_helper_st64_mmu = { .flags = TCG_CALL_NO_WG, .typemask = dh_typemask(void, 0) | dh_typemask(env, 1) - | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 2) /* uint64_t addr */ | dh_typemask(i64, 3) /* uint64_t data */ | dh_typemask(i32, 4) /* unsigned oi */ | dh_typemask(ptr, 5) /* uintptr_t ra */ @@ -815,7 +815,7 @@ static TCGHelperInfo info_helper_st128_mmu = { .flags = TCG_CALL_NO_WG, .typemask = dh_typemask(void, 0) | dh_typemask(env, 1) - | dh_typemask(tl, 2) /* target_ulong addr */ + | dh_typemask(i64, 2) /* uint64_t addr */ | dh_typemask(i128, 3) /* Int128 data */ | dh_typemask(i32, 4) /* unsigned oi */ | dh_typemask(ptr, 5) /* uintptr_t ra */ @@ -5456,11 +5456,26 @@ static void tcg_out_ld_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst, next_arg = 1; loc = &info->in[next_arg]; - nmov = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_TL, TCG_TYPE_TL, - ldst->addrlo_reg, ldst->addrhi_reg); - next_arg += nmov; + if (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 64) { + nmov = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, TCG_TYPE_TL, + ldst->addrlo_reg, ldst->addrhi_reg); + tcg_out_helper_load_slots(s, nmov, mov, parm); + next_arg += nmov; + } else { + /* + * 32-bit host with 32-bit guest: zero-extend the guest address + * to 64-bits for the helper by storing the low part, then + * load a zero for the high part. + */ + tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, + TCG_TYPE_I32, TCG_TYPE_I32, + ldst->addrlo_reg, -1); + tcg_out_helper_load_slots(s, 1, mov, parm); - tcg_out_helper_load_slots(s, nmov, mov, parm); + tcg_out_helper_load_imm(s, loc[!HOST_BIG_ENDIAN].arg_slot, + TCG_TYPE_I32, 0, parm); + next_arg += 2; + } switch (info->out_kind) { case TCG_CALL_RET_NORMAL: @@ -5614,10 +5629,24 @@ static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst, /* Handle addr argument. */ loc = &info->in[next_arg]; - n = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_TL, TCG_TYPE_TL, - ldst->addrlo_reg, ldst->addrhi_reg); - next_arg += n; - nmov += n; + if (TCG_TARGET_REG_BITS == 64 || TARGET_LONG_BITS == 64) { + n = tcg_out_helper_add_mov(mov, loc, TCG_TYPE_I64, TCG_TYPE_TL, + ldst->addrlo_reg, ldst->addrhi_reg); + next_arg += n; + nmov += n; + } else { + /* + * 32-bit host with 32-bit guest: zero-extend the guest address + * to 64-bits for the helper by storing the low part. Later, + * after we have processed the register inputs, we will load a + * zero for the high part. + */ + tcg_out_helper_add_mov(mov, loc + HOST_BIG_ENDIAN, + TCG_TYPE_I32, TCG_TYPE_I32, + ldst->addrlo_reg, -1); + next_arg += 2; + nmov += 1; + } /* Handle data argument. */ loc = &info->in[next_arg]; @@ -5662,6 +5691,11 @@ static void tcg_out_st_helper_args(TCGContext *s, const TCGLabelQemuLdst *ldst, g_assert_not_reached(); } + if (TCG_TARGET_REG_BITS == 32 && TARGET_LONG_BITS == 32) { + loc = &info->in[1 + !HOST_BIG_ENDIAN]; + tcg_out_helper_load_imm(s, loc->arg_slot, TCG_TYPE_I32, 0, parm); + } + tcg_out_helper_load_common_args(s, ldst, parm, info, next_arg); } From patchwork Wed May 3 07:20:52 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 678657 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp908652wrs; Wed, 3 May 2023 00:23:10 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ673aPgp1/9q8VsAKBXQ5xUY1UFka3QIM/aErUph/eYxDIvJzvDEl7lLXzNs2lz1XQGMHzC X-Received: by 2002:a05:6214:769:b0:5ab:a50b:e610 with SMTP id f9-20020a056214076900b005aba50be610mr8777143qvz.33.1683098589827; Wed, 03 May 2023 00:23:09 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683098589; cv=none; d=google.com; s=arc-20160816; b=PbQ04+Xk0W8hBTI23DxWasJk6pzA0wKI3h2fddF2lahPWQXkmjGR9RdpIjCl4w4+aN aXhOhbL2mR7X0ee89VcSCU2Mpy7hv/ZqQQLauzzutEc3dfkD9v7+yAulPDImWZe0gtCk Wf1TZ0byBGfC1SeYgJoWr553C8Zp+Gd/UJkmlbvtyYMv4SBWkiWjqTQhUx/ATYVgoYN/ Fi9xt0sDpsA+hIuEDplmKNkofIydVLy2vAPPZC7Ogermdf6OT9KlLSp9QInz1fWw/8DM UYBAr20g6hggjwJK4aJnHunhMMtdTeM6uiIinkyNup5Jg64tymWZDeJBPCiNh2RZxLqz Xsog== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=m4s47C7gmYdUlM0SIov8ZnFiPUvDgmGeRG+O+etXAiw=; b=0utOK6L3O/QAGj9W+oN8NunyLWJnfjFyAS0Nk6jrlopi/A2Kn/Jk+6xBwSGFTHWAAE xrhHrO5Svg0YViG7d7OzXUUYbyBInWSWr47HW3SqtsetNdzMFti6I//87bIydwPHViW8 180D0FtdVKhdMEmZmo+51ELN5FKDYXZ7DJDHBIWKOHt7STdNJdUdYTnFL/kkERkz141Y HhU/4dD77AirNyXiqslZOMHmkWT8Q4quRAIW2j7nS+JNWVKAhZ2WtIFYI3T0xS/Qrp00 z9BgGovmb6v4XyAavDfnpu4OW8mCeG/fzt6RfsUfVC4WSadmsaD3DpnB5kz2P3N7Iuf1 YO2Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=baj3BlHy; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Kiran Ostrolenk Reviewed-by: Richard Henderson Message-Id: <20230428144757.57530-11-lawrence.hunter@codethink.co.uk> Signed-off-by: Richard Henderson --- include/qemu/host-utils.h | 54 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 3ce62bf4a5..d3b4dce6a9 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -107,6 +107,36 @@ static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) } #endif +/** + * clz8 - count leading zeros in a 8-bit value. + * @val: The value to search + * + * Returns 8 if the value is zero. Note that the GCC builtin is + * undefined if the value is zero. + * + * Note that the GCC builtin will upcast its argument to an `unsigned int` + * so this function subtracts off the number of prepended zeroes. + */ +static inline int clz8(uint8_t val) +{ + return val ? __builtin_clz(val) - 24 : 8; +} + +/** + * clz16 - count leading zeros in a 16-bit value. + * @val: The value to search + * + * Returns 16 if the value is zero. Note that the GCC builtin is + * undefined if the value is zero. + * + * Note that the GCC builtin will upcast its argument to an `unsigned int` + * so this function subtracts off the number of prepended zeroes. + */ +static inline int clz16(uint16_t val) +{ + return val ? __builtin_clz(val) - 16 : 16; +} + /** * clz32 - count leading zeros in a 32-bit value. * @val: The value to search @@ -153,6 +183,30 @@ static inline int clo64(uint64_t val) return clz64(~val); } +/** + * ctz8 - count trailing zeros in a 8-bit value. + * @val: The value to search + * + * Returns 8 if the value is zero. Note that the GCC builtin is + * undefined if the value is zero. + */ +static inline int ctz8(uint8_t val) +{ + return val ? __builtin_ctz(val) : 8; +} + +/** + * ctz16 - count trailing zeros in a 16-bit value. + * @val: The value to search + * + * Returns 16 if the value is zero. Note that the GCC builtin is + * undefined if the value is zero. + */ +static inline int ctz16(uint16_t val) +{ + return val ? __builtin_ctz(val) : 16; +} + /** * ctz32 - count trailing zeros in a 32-bit value. * @val: The value to search From patchwork Wed May 3 07:20:54 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 678662 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp908957wrs; Wed, 3 May 2023 00:24:08 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4mlfWZMqjwnDJ0fG3w5+LRUzvRXlD5FBYevBWXqypTs1dfl2q1wKwiE6N4N+oONb/CZZgl X-Received: by 2002:a05:6214:258a:b0:56c:13cc:d21f with SMTP id fq10-20020a056214258a00b0056c13ccd21fmr9325080qvb.50.1683098648067; Wed, 03 May 2023 00:24:08 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683098648; cv=none; d=google.com; s=arc-20160816; b=MUlyyrK0Wn/4vEsTSi5mQfy/DE68gBS3vExceIqwaRSHPKBZx0f16azmjbETlABqrD 8MmWejwhN2UtEKef3dz07ohK8jOVxHbuzSpvVQzDPVEcCFOedL7mdiLexpt8PzPHMBMR k/3/2t418bO3rvsFgNfkOMsvCNIN1zWjI+CD82h06t8IlSrDXfSq5GcDtele1YYRvg3f MBPoQ1CgIrUoMkIxf4oi9eYo+RO5GlwsMHbVhnH5/PsSME3HXL5UsND44fgLgCFe213i w0TIH2sPXISlszyD5zM3NnmHs0CrtGao0DYTfJ8xrci59k8Hs1nigZGCRpeEFcFz2qLJ Ttuw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=Ee+/tZtVXx1HapVlpwz6x03LyQaqO+PtTzdE1w9ii1A=; b=H4tKsFVnsOvpYOj5FLvjpCA5OSgWi5qCNRCcvuoCPDy1qlyeU/OLwypGxkczKAaxid QzDWdV3ISHEsdtIflCyUMTAj3SKdC9EQ2yW+D7RbEojseERBvOwsXM1mk+v8NXyfIcuG ACT2iTH5kg7UhMd/KY0RFsTqeRMiYfKcHYoDKSkbf2qn+2evBZcDwFtS6T4JFM0fIVoP oSLni5qWm79TvVhAJ5JrsrRzzf5VVR1TooXxTiItWKvx5le5QupJf4PlI3p6Wi4l7TTf 0Y+ObWWGbKABs4MhkuxMt5X3dgtl2wlfLywnXCd/A2+w0Zn8o9Dx/m+1/+LRM2Oxpisi KZyA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=gpQ7EwwA; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Nazar Kazakov Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk> [rth: Split out of larger patch.] Signed-off-by: Richard Henderson --- accel/tcg/tcg-runtime.h | 1 + include/tcg/tcg-op-gvec.h | 2 ++ accel/tcg/tcg-runtime-gvec.c | 11 +++++++++++ tcg/tcg-op-gvec.c | 17 +++++++++++++++++ 4 files changed, 31 insertions(+) diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index e141a6ab24..b8e6421c8a 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -217,6 +217,7 @@ DEF_HELPER_FLAGS_4(gvec_nor, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eqv, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_ands, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) +DEF_HELPER_FLAGS_4(gvec_andcs, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(gvec_xors, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) DEF_HELPER_FLAGS_4(gvec_ors, TCG_CALL_NO_RWG, void, ptr, ptr, i64, i32) diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index 28cafbcc5c..6d58683171 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -330,6 +330,8 @@ void tcg_gen_gvec_ori(unsigned vece, uint32_t dofs, uint32_t aofs, void tcg_gen_gvec_ands(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_xors(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i64 c, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_ors(unsigned vece, uint32_t dofs, uint32_t aofs, diff --git a/accel/tcg/tcg-runtime-gvec.c b/accel/tcg/tcg-runtime-gvec.c index ac7d28c251..97399493d5 100644 --- a/accel/tcg/tcg-runtime-gvec.c +++ b/accel/tcg/tcg-runtime-gvec.c @@ -550,6 +550,17 @@ void HELPER(gvec_ands)(void *d, void *a, uint64_t b, uint32_t desc) clear_high(d, oprsz, desc); } +void HELPER(gvec_andcs)(void *d, void *a, uint64_t b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) & ~b; + } + clear_high(d, oprsz, desc); +} + void HELPER(gvec_xors)(void *d, void *a, uint64_t b, uint32_t desc) { intptr_t oprsz = simd_oprsz(desc); diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 047a832f44..9c14908a46 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -2761,6 +2761,23 @@ void tcg_gen_gvec_andi(unsigned vece, uint32_t dofs, uint32_t aofs, tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, tmp, &gop_ands); } +void tcg_gen_gvec_andcs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i64 c, uint32_t oprsz, uint32_t maxsz) +{ + static GVecGen2s g = { + .fni8 = tcg_gen_andc_i64, + .fniv = tcg_gen_andc_vec, + .fno = gen_helper_gvec_andcs, + .prefer_i64 = TCG_TARGET_REG_BITS == 64, + .vece = MO_64 + }; + + TCGv_i64 tmp = tcg_temp_ebb_new_i64(); + tcg_gen_dup_i64(vece, tmp, c); + tcg_gen_gvec_2s(dofs, aofs, oprsz, maxsz, c, &g); + tcg_temp_free_i64(tmp); +} + static const GVecGen2s gop_xors = { .fni8 = tcg_gen_xor_i64, .fniv = tcg_gen_xor_vec, From patchwork Wed May 3 07:20:56 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 678688 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp910459wrs; Wed, 3 May 2023 00:28:52 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4AqIIx377zHEUXy2eNCGPNqsJC0RsWwCSeqXxUgg2rHMjFsRaJ5UmsXk7YFLXnitJWrHvZ X-Received: by 2002:ac8:5a08:0:b0:3f2:421:4de5 with SMTP id n8-20020ac85a08000000b003f204214de5mr24846120qta.26.1683098931913; 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[209.51.188.17]) by mx.google.com with ESMTPS id f20-20020a05620a409400b0074e1dfce0c3si19434740qko.19.2023.05.03.00.28.51 for (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 03 May 2023 00:28:51 -0700 (PDT) Received-SPF: pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; Authentication-Results: mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=rzPHAiQc; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1pu6p6-0007DA-Hq; Wed, 03 May 2023 03:22:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1pu6ow-0006pZ-Lo for qemu-devel@nongnu.org; Wed, 03 May 2023 03:22:40 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1pu6oq-0007IV-IX for qemu-devel@nongnu.org; Wed, 03 May 2023 03:22:34 -0400 Received: by mail-wm1-x335.google.com with SMTP id 5b1f17b1804b1-3f173af665fso30096045e9.3 for ; Wed, 03 May 2023 00:22:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1683098550; x=1685690550; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=aGVAM5f/fVkyzn3zO3fNGB1yt+oMwQWHTxZuqdKZ/tI=; b=rzPHAiQcP4uS+qD9CpuRceNXGD3+laQ0rs2EUMv1KcPlHJenRiIeo51QhNp1q8Ijt5 c4xLQyLskfssYn6caSXi0rGmfVy+j/OuVGFBMes/HKEmJ/1IuBf5h746sn9imEI4dkiJ CSCXWN+dVmZiUEifWI1Ez1Z2Lr313NwJujqAdiCMOAyECk/CLgazvVTciGH4ZliTQ7NE 5YVPlnHEySuJ6BDL5R9owiweegWMD4PUpiKPtqZ95dk0k9draCwCN9hjyJ6qh82PB+ux XKyjXFJXUZiI6bq46O5buqfCYRMMyUCzVIwgoIPmDjA3IUnY6mo0pW6mEqZg7shDnk1Y RLqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1683098550; x=1685690550; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=aGVAM5f/fVkyzn3zO3fNGB1yt+oMwQWHTxZuqdKZ/tI=; b=Sj4Za8VPG5MeaVi1wFk8FeAAgJy7H2k3vZuSKx+FyXMmSbqOXu7zfw35JE9BOrGA66 ZMHbNhUJsXoWJ2gsUUPRisVN8r07zZutjHbqK+j9Ia00K0gLrcu5qSZJ8MdmKvDvfe7K Q09db3FoK2dUr5Zm3f13OL9Ry//LuOEU9Gh28arHLYF5LWrTOlzQkeL/4lA4XU34UPAC 1nmh1/RV9GMQJa9GzvBNLcqnWyFQEMP2Xckju36f2Bnn27g3sQO6hJ02kN5QOClG4SVr SQM5+vIxvuZoZVnt+bgwvyO7GxzpbnJXnzCYP3T1dsEhh0tShglgLnRTaHpV78ssC+vl jVxg== X-Gm-Message-State: AC+VfDxHRDTfSNIihj5KXbLxttWQp0kJ+LBIp7swDIW6IMKah4+gwtDm CsqdBQWQQy6W8XmrypyIuaJMvXScafoy5bdMNZPhAw== X-Received: by 2002:a05:600c:257:b0:3f0:5887:bea3 with SMTP id 23-20020a05600c025700b003f05887bea3mr14049789wmj.27.1683098550445; Wed, 03 May 2023 00:22:30 -0700 (PDT) Received: from stoup.Home ([2a02:c7c:74db:8d00:c01d:9d74:b630:9087]) by smtp.gmail.com with ESMTPSA id t4-20020a7bc3c4000000b003f1745c7df3sm962789wmj.23.2023.05.03.00.22.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 03 May 2023 00:22:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ale@rev.ng, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com, anjo@rev.ng, Nazar Kazakov Subject: [PULL v2 06/12] tcg: Add tcg_gen_gvec_rotrs Date: Wed, 3 May 2023 08:20:56 +0100 Message-Id: <20230503072221.1746802-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230503072221.1746802-1-richard.henderson@linaro.org> References: <20230503072221.1746802-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org From: Nazar Kazakov Add tcg expander and helper functions for rotate right vector with scalar operand. Signed-off-by: Nazar Kazakov Message-Id: <20230428144757.57530-10-lawrence.hunter@codethink.co.uk> [rth: Split out of larger patch; mask rotation count.] Signed-off-by: Richard Henderson --- include/tcg/tcg-op-gvec.h | 2 ++ tcg/tcg-op-gvec.c | 11 +++++++++++ 2 files changed, 13 insertions(+) diff --git a/include/tcg/tcg-op-gvec.h b/include/tcg/tcg-op-gvec.h index 6d58683171..a8183bfeab 100644 --- a/include/tcg/tcg-op-gvec.h +++ b/include/tcg/tcg-op-gvec.h @@ -371,6 +371,8 @@ void tcg_gen_gvec_sars(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); /* * Perform vector shift by vector element, modulo the element size. diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 9c14908a46..f51bcaa87b 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -3353,6 +3353,17 @@ void tcg_gen_gvec_rotls(unsigned vece, uint32_t dofs, uint32_t aofs, do_gvec_shifts(vece, dofs, aofs, shift, oprsz, maxsz, &g); } +void tcg_gen_gvec_rotrs(unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + TCGv_i32 tmp = tcg_temp_ebb_new_i32(); + + tcg_gen_neg_i32(tmp, shift); + tcg_gen_andi_i32(tmp, tmp, (8 << vece) - 1); + tcg_gen_gvec_rotls(vece, dofs, aofs, tmp, oprsz, maxsz); + tcg_temp_free_i32(tmp); +} + /* * Expand D = A << (B % element bits) * From patchwork Wed May 3 07:20:59 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 678682 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp910325wrs; Wed, 3 May 2023 00:28:22 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ73kCKjV8etkZYhE8oEeTmVTVt7oQ7k9qplwk/lN25SyFr/baR8Xs/IA6O6yz5emzg326j3 X-Received: by 2002:a05:6214:1241:b0:5a3:79cd:8ef7 with SMTP id r1-20020a056214124100b005a379cd8ef7mr7448864qvv.23.1683098902652; Wed, 03 May 2023 00:28:22 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683098902; cv=none; d=google.com; s=arc-20160816; b=MBnXKZ9Xdzp+gbASE+Y78Llz34AiCjJZon2V6+NYLPR87FIuRyzHnoPT3yAjnxdeIM Z1rAvkj960lBI43oWm9Ww9P80fEalIDfBV8uwxErzXTNwKKqflj5vUGbKdIhc6Kf6gqV EnGmzb0Yx9it8j+eLVfMRqF7SgKVHUv0LcaVmuNNruY4W6dx25af+lQL5eMBhHrp1aDY 8aHCMakZo/WiFe90HxlTz4cNRknmWGqlpvgtqvRgDYwuY4A+yKRpN/jnINyBVA+C90Ta 8t3jsEidXWIet/o56bGjj87lMxVTzk0YahTAnLgStBbWlnY2QnIWUpkXf2pPhxOA6Jby VHOw== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=wY72rBTCusrC/WPaiwfzmoq60/uULSGfuUcD5/U5TwY=; b=e4++jrOM59FJ2/EA3J5Q2u0Mm/2gjk3rIYhCLO4qPz9hUYUg6NOKo7TGYyj8dMdsH4 b2JaY3m2Rok/fMOomHbffpKhSZ+7rGrTYfKXdRAPblo5dZ0iZp4Cp6fSH5eh2K8P/E5E BefR2jw0+G5dl3Yc2MddQWtCy2juLwqHd4kT3hs7tKGkVpc/+1rUJyMPAEKRLCoyHr0Z lrHQJtnBA/aEZaMpcvo+dE+0L7xlMxo3Sxgk2UxqipDNi2fBz8J2joqii1Brm1wBk4Aj +lhT2Oj3z1HnRzDC0TRitcBALvbjdazoErMuRGjnoF7J3lHPGy8IxZYP4oZsJqD5A8GE g15Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=VVX2wPC9; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Wed, 03 May 2023 00:22:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: ale@rev.ng, philmd@linaro.org, marcel.apfelbaum@gmail.com, wangyanan55@huawei.com, anjo@rev.ng, =?utf-8?q?Alex_Benn=C3=A9e?= Subject: [PULL v2 07/12] qemu/int128: Re-shuffle Int128Alias members Date: Wed, 3 May 2023 08:20:59 +0100 Message-Id: <20230503072221.1746802-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230503072221.1746802-1-richard.henderson@linaro.org> References: <20230503072221.1746802-1-richard.henderson@linaro.org> MIME-Version: 1.0 Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+patch=linaro.org@nongnu.org Sender: qemu-devel-bounces+patch=linaro.org@nongnu.org Clang 14, with --enable-tcg-interpreter errors with include/qemu/int128.h:487:16: error: alignment of field 'i' (128 bits) does not match the alignment of the first field in transparent union; transparent_union attribute ignored [-Werror,-Wignored-attributes] __int128_t i; ^ include/qemu/int128.h:486:12: note: alignment of first field is 64 bits Int128 s; ^ 1 error generated. By placing the __uint128_t member first, this is avoided. Signed-off-by: Richard Henderson Reviewed-by: Alex Bennée Message-Id: <20230501204625.277361-1-richard.henderson@linaro.org> --- include/qemu/int128.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/qemu/int128.h b/include/qemu/int128.h index f62a46b48c..9e46cfaefc 100644 --- a/include/qemu/int128.h +++ b/include/qemu/int128.h @@ -483,9 +483,9 @@ static inline void bswap128s(Int128 *s) */ #ifdef CONFIG_INT128 typedef union { - Int128 s; - __int128_t i; __uint128_t u; + __int128_t i; + Int128 s; } Int128Alias __attribute__((transparent_union)); #else typedef Int128 Int128Alias; From patchwork Wed May 3 07:21:00 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 678675 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp909898wrs; Wed, 3 May 2023 00:27:00 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ4mQtSmwcA+FgRmgj0whDCnUmDmwQcaMBL1d+BL15JkCngxBL0ThiYNQYAOv5GyYEdiBw4K X-Received: by 2002:a05:6214:2629:b0:61b:17bd:c603 with SMTP id gv9-20020a056214262900b0061b17bdc603mr10209546qvb.9.1683098820542; Wed, 03 May 2023 00:27:00 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683098820; cv=none; d=google.com; s=arc-20160816; b=bEwfJvepWBMD9KxYOPARBL9rSHE5VDB0wSAGdOSLvlyCJcCILtS+byWU8TeFQ3Y91u b2McZPq4tGeBkE0Zw8YM8I9Syf6H6LtQbNrYvciMx960Y5gvkAvTLFcBz2PWDq8SQRiC yh/RhM0dmozzU0Z2VOyvLrYZ6hK+2Dyd66XKVH/PnARP8PQw3fktt9All/18U6DW7iB9 Ce0O5lWHq51fW/4qr5Chud3g/SrEoJu2xiRx4dCbPUbtjAxy58DAK3tV7/IsmF3ok8dG iF/3OzI+9o5KthX8CEXuJ3evpeRqcPdskBRzb7OC6m4qmcZmC3U4nB9E91sRDs++TM+1 Kb2w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=pPLvUEtS2r7DTVcycF0JmWSxgARIqH2mkH/yVD891tk=; b=u4QetoPMtUynvxWWYbjFz/3oPm+LX5uip2ldgBdwUexOXtPR1wxEJYRTE9UbgPH4J/ bKBPxtvwFvcuV+KgNTbEzllZ9B9nlZaBtlUcs38KF1uJZsO1n1sFKlq1lHGFooUkQmgM YqOLYS2Jeh5Cf0vv8zxoKxcJU+x2smIUynZx5qVDX6liid+SjAd7cn0UHJa/UoXmlLxA NLSIA0A6eK9wTJJW4+1k2qYQp4EA9IJyB6OVX6rgR5c8AlXMt6MwiauKOcoCYyI173xD 96sJyPW1awNrYzZna1iSqnvgD0xfm5P6qEfoMF4oYLDVeRP+gjvnjcUgMJ5HB8L1ib3k 7SmA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=S9E55tR7; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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Signed-off-by: Richard Henderson --- accel/tcg/plugin-gen.c | 41 ++++++++++++++++++----------------------- 1 file changed, 18 insertions(+), 23 deletions(-) diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index 04facd6305..55e892b684 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -92,27 +92,6 @@ void HELPER(plugin_vcpu_mem_cb)(unsigned int vcpu_index, void *userdata) { } -static void do_gen_mem_cb(TCGv vaddr, uint32_t info) -{ - TCGv_i32 cpu_index = tcg_temp_ebb_new_i32(); - TCGv_i32 meminfo = tcg_temp_ebb_new_i32(); - TCGv_i64 vaddr64 = tcg_temp_ebb_new_i64(); - TCGv_ptr udata = tcg_temp_ebb_new_ptr(); - - tcg_gen_movi_i32(meminfo, info); - tcg_gen_movi_ptr(udata, 0); - tcg_gen_ld_i32(cpu_index, cpu_env, - -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)); - tcg_gen_extu_tl_i64(vaddr64, vaddr); - - gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, vaddr64, udata); - - tcg_temp_free_ptr(udata); - tcg_temp_free_i64(vaddr64); - tcg_temp_free_i32(meminfo); - tcg_temp_free_i32(cpu_index); -} - static void gen_empty_udata_cb(void) { TCGv_i32 cpu_index = tcg_temp_ebb_new_i32(); @@ -145,9 +124,25 @@ static void gen_empty_inline_cb(void) tcg_temp_free_i64(val); } -static void gen_empty_mem_cb(TCGv addr, uint32_t info) +static void gen_empty_mem_cb(TCGv vaddr, uint32_t info) { - do_gen_mem_cb(addr, info); + TCGv_i32 cpu_index = tcg_temp_ebb_new_i32(); + TCGv_i32 meminfo = tcg_temp_ebb_new_i32(); + TCGv_i64 vaddr64 = tcg_temp_ebb_new_i64(); + TCGv_ptr udata = tcg_temp_ebb_new_ptr(); + + tcg_gen_movi_i32(meminfo, info); + tcg_gen_movi_ptr(udata, 0); + tcg_gen_ld_i32(cpu_index, cpu_env, + -offsetof(ArchCPU, env) + offsetof(CPUState, cpu_index)); + tcg_gen_extu_tl_i64(vaddr64, vaddr); + + gen_helper_plugin_vcpu_mem_cb(cpu_index, meminfo, vaddr64, udata); + + tcg_temp_free_ptr(udata); + tcg_temp_free_i64(vaddr64); + tcg_temp_free_i32(meminfo); + tcg_temp_free_i32(cpu_index); } /* From patchwork Wed May 3 07:21:03 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 678705 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp911747wrs; Wed, 3 May 2023 00:32:55 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6qg/NwO7H//pLSOph7z1+iOcwjXMBM9bbOV8Rk0VA8pt1jMscQvaAurkdc6wUqUy+Vi39h X-Received: by 2002:a05:622a:58c:b0:3f0:a1f7:6943 with SMTP id c12-20020a05622a058c00b003f0a1f76943mr27209342qtb.61.1683099175592; Wed, 03 May 2023 00:32:55 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1683099175; cv=none; d=google.com; s=arc-20160816; b=DYffsW4kHZXGToBe01TqZn2DIF/lzod0CFUxowGARUsdy31hz9mlCNmMwbkPiaf411 s4nJpv/62JhE4xW8aMAp3L3MNwIdgN7/XwDhQwIJgWecdMCZL5AdA1vAjbTh//ycl6xJ Vblv+7zyPuX9eDnVBISocr8+yICuQFzzwjLjd1I8koh/kwOeaDpJMW5Ev+X0c1JtH5F5 YaoHMPNjeHd6iDviQphsRHoQQpzMzg90HjFe92SlRmZB7D0TkV9ejqB0iAS9LQTfH8KN RHC/kkWCk4kYy70zRU9BxIf13hKGeT9w0F+CbSUFZqwpis8WyUsDYsPRe3foAV9+R+0T 1fzQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=sender:errors-to:list-subscribe:list-help:list-post:list-archive :list-unsubscribe:list-id:precedence:content-transfer-encoding :mime-version:references:in-reply-to:message-id:date:subject:cc:to :from:dkim-signature; bh=z8sjCuLtJ7QtevNycg+bE9LkfywEsd1zAt00dn10Z1Q=; b=jf954rBsGTr7u0VdBjLJSQ7uK9cl17FtXocXNNT9o77OYTvGsDPM6qCyuT/4tPh2FY 67y/q/rHziEJmCIafPDN8cD9sAWiJ0GWFDOeg3S9xorlCDYQzmMWO+OfT/mk+dLUHaO4 tnMbgTG9Icg0h9qkFd0wmvYORs49DBaP/fsM/akq5ftmlafitAp1WzATKS2FnZJrjGB5 GO9maBNylGdXFDwVtKdSiL+HQWkeGbaI8oiW1TU/nZ7Lr2SN5+vZJsENuv4u/auPYod4 h1adNUpe/kPFWV4jmb01L4oL+EtDP835XWeY9CQGGoywCzSO5wvnwFqJURDNdccUAKvm uybw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@linaro.org header.s=google header.b=i1TjvEcu; spf=pass (google.com: domain of qemu-devel-bounces+patch=linaro.org@nongnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom="qemu-devel-bounces+patch=linaro.org@nongnu.org"; dmarc=pass (p=NONE sp=NONE dis=NONE) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org. 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For now, only eliminate the copy for stores and 128-bit loads. Rename plugin_prep_mem_callbacks to plugin_maybe_preserve_addr, returning NULL if no copy is made. Signed-off-by: Richard Henderson --- tcg/tcg-op-ldst.c | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-) diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 17fe35b93c..cbd85f793c 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -114,7 +114,8 @@ static void tcg_gen_req_mo(TCGBar type) } } -static inline TCGv plugin_prep_mem_callbacks(TCGv vaddr) +/* Only required for loads, where value might overlap addr. */ +static TCGv plugin_maybe_preserve_addr(TCGv vaddr) { #ifdef CONFIG_PLUGIN if (tcg_ctx->plugin_insn != NULL) { @@ -124,17 +125,20 @@ static inline TCGv plugin_prep_mem_callbacks(TCGv vaddr) return temp; } #endif - return vaddr; + return NULL; } -static void plugin_gen_mem_callbacks(TCGv vaddr, MemOpIdx oi, - enum qemu_plugin_mem_rw rw) +static void +plugin_gen_mem_callbacks(TCGv copy_addr, TCGv orig_addr, MemOpIdx oi, + enum qemu_plugin_mem_rw rw) { #ifdef CONFIG_PLUGIN if (tcg_ctx->plugin_insn != NULL) { qemu_plugin_meminfo_t info = make_plugin_meminfo(oi, rw); - plugin_gen_empty_mem_callback(vaddr, info); - tcg_temp_free(vaddr); + plugin_gen_empty_mem_callback(copy_addr ? : orig_addr, info); + if (copy_addr) { + tcg_temp_free(copy_addr); + } } #endif } @@ -143,6 +147,7 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) { MemOp orig_memop; MemOpIdx oi; + TCGv copy_addr; tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); memop = tcg_canonicalize_memop(memop, 0, 0); @@ -157,9 +162,9 @@ void tcg_gen_qemu_ld_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) } } - addr = plugin_prep_mem_callbacks(addr); + copy_addr = plugin_maybe_preserve_addr(addr); gen_ldst_i32(INDEX_op_qemu_ld_i32, val, addr, memop, idx); - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); + plugin_gen_mem_callbacks(copy_addr, addr, oi, QEMU_PLUGIN_MEM_R); if ((orig_memop ^ memop) & MO_BSWAP) { switch (orig_memop & MO_SIZE) { @@ -202,13 +207,12 @@ void tcg_gen_qemu_st_i32(TCGv_i32 val, TCGv addr, TCGArg idx, MemOp memop) memop &= ~MO_BSWAP; } - addr = plugin_prep_mem_callbacks(addr); if (TCG_TARGET_HAS_qemu_st8_i32 && (memop & MO_SIZE) == MO_8) { gen_ldst_i32(INDEX_op_qemu_st8_i32, val, addr, memop, idx); } else { gen_ldst_i32(INDEX_op_qemu_st_i32, val, addr, memop, idx); } - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); + plugin_gen_mem_callbacks(NULL, addr, oi, QEMU_PLUGIN_MEM_W); if (swap) { tcg_temp_free_i32(swap); @@ -219,6 +223,7 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) { MemOp orig_memop; MemOpIdx oi; + TCGv copy_addr; if (TCG_TARGET_REG_BITS == 32 && (memop & MO_SIZE) < MO_64) { tcg_gen_qemu_ld_i32(TCGV_LOW(val), addr, idx, memop); @@ -243,9 +248,9 @@ void tcg_gen_qemu_ld_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) } } - addr = plugin_prep_mem_callbacks(addr); + copy_addr = plugin_maybe_preserve_addr(addr); gen_ldst_i64(INDEX_op_qemu_ld_i64, val, addr, memop, idx); - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); + plugin_gen_mem_callbacks(copy_addr, addr, oi, QEMU_PLUGIN_MEM_R); if ((orig_memop ^ memop) & MO_BSWAP) { int flags = (orig_memop & MO_SIGN @@ -300,9 +305,8 @@ void tcg_gen_qemu_st_i64(TCGv_i64 val, TCGv addr, TCGArg idx, MemOp memop) memop &= ~MO_BSWAP; } - addr = plugin_prep_mem_callbacks(addr); gen_ldst_i64(INDEX_op_qemu_st_i64, val, addr, memop, idx); - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); + plugin_gen_mem_callbacks(NULL, addr, oi, QEMU_PLUGIN_MEM_W); if (swap) { tcg_temp_free_i64(swap); @@ -430,7 +434,6 @@ void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memop) tcg_debug_assert((memop & MO_SIGN) == 0); tcg_gen_req_mo(TCG_MO_LD_LD | TCG_MO_ST_LD); - addr = plugin_prep_mem_callbacks(addr); /* TODO: For now, force 32-bit hosts to use the helper. */ if (TCG_TARGET_HAS_qemu_ldst_i128 && TCG_TARGET_REG_BITS == 64) { @@ -501,7 +504,7 @@ void tcg_gen_qemu_ld_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memop) maybe_free_addr64(a64); } - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_R); + plugin_gen_mem_callbacks(NULL, addr, oi, QEMU_PLUGIN_MEM_R); } void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memop) @@ -512,7 +515,6 @@ void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memop) tcg_debug_assert((memop & MO_SIGN) == 0); tcg_gen_req_mo(TCG_MO_ST_LD | TCG_MO_ST_ST); - addr = plugin_prep_mem_callbacks(addr); /* TODO: For now, force 32-bit hosts to use the helper. */ @@ -583,7 +585,7 @@ void tcg_gen_qemu_st_i128(TCGv_i128 val, TCGv addr, TCGArg idx, MemOp memop) maybe_free_addr64(a64); } - plugin_gen_mem_callbacks(addr, oi, QEMU_PLUGIN_MEM_W); + plugin_gen_mem_callbacks(NULL, addr, oi, QEMU_PLUGIN_MEM_W); } static void tcg_gen_ext_i32(TCGv_i32 ret, TCGv_i32 val, MemOp opc) From patchwork Wed May 3 07:21:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Richard Henderson X-Patchwork-Id: 678726 Delivered-To: patch@linaro.org Received: by 2002:a5d:4a41:0:0:0:0:0 with SMTP id v1csp913497wrs; Wed, 3 May 2023 00:38:42 -0700 (PDT) X-Google-Smtp-Source: ACHHUZ6GO4NZplVym4ze8nTG8CZi+AcAAbyF3qzN496iDRZbh5UFk8KXpW7tZNhs5XtS5ddeyMF0 X-Received: by 2002:a05:622a:150:b0:3ef:25ad:27fd with SMTP id v16-20020a05622a015000b003ef25ad27fdmr30394999qtw.1.1683099522250; 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This is already relied upon by comparisons. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 21c2fc9e98..0940788c6f 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -463,7 +463,9 @@ static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) static void tcg_out_exts_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg) { - tcg_out_ext32s(s, ret, arg); + if (ret != arg) { + tcg_out_ext32s(s, ret, arg); + } } static void tcg_out_extu_i32_i64(TCGContext *s, TCGReg ret, TCGReg arg)