From patchwork Sun Apr 30 20:57:02 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 678031 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9694BC77B7F for ; Sun, 30 Apr 2023 20:57:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230494AbjD3U5T (ORCPT ); Sun, 30 Apr 2023 16:57:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34154 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229688AbjD3U5S (ORCPT ); Sun, 30 Apr 2023 16:57:18 -0400 Received: from mail-lf1-x131.google.com (mail-lf1-x131.google.com [IPv6:2a00:1450:4864:20::131]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 6ECCCF5 for ; Sun, 30 Apr 2023 13:57:14 -0700 (PDT) Received: by mail-lf1-x131.google.com with SMTP id 2adb3069b0e04-4edc7cc6f46so2320964e87.1 for ; Sun, 30 Apr 2023 13:57:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682888233; x=1685480233; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=RMoajvygLpHN0tJCNypWoRhLDvyZjkn9k0Ux5UMBZj0=; b=nWldz1WKP5mFdBSBHfAEK085rVYocoobKjLZX4YQn1lsQ2cVYwlVPi3OKO5c9ALrSn EJ0nEgmZxKfsgPC6mg+801ga7hVtsy2bAAS4ITAoiGs1srM4zZKuCtV/CN4q23zQuAyL p7x84jGpcs+HEa19QOTm4TKdrpw7DOwgGRT0sI4/Hj3WDwxCzdstS68n+GjLfFTdDe0b +sCbAD4wu5PdRgNmQeiS86XwAv1VTX/RJW+625Tb13/WaoGiZXHPIDKW0rLoRGi3MJx2 kEd8tEGi2Uf6d6TPceIJ4GZgG5XIIpcpq/tmk/05V1hNl1OlmPwPsQyfOan/KH5G0xPU n7YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682888233; x=1685480233; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RMoajvygLpHN0tJCNypWoRhLDvyZjkn9k0Ux5UMBZj0=; b=IzGkB0D7ir4mTzi9RCCvEXrYodfOUjI1a5p/i1Hpc+fEGaWYvwBzDb4C6xD/Lpzn1n lh85llticpC4L1tPMBnuMwH6h+nl8rGDtbkPcXb2aBFtoT8JUID9eNhowfaTysrd5ztX cFzFONQPJhtAzuficqxtO6MAXDFw21UW2kxB+17mw1zFYMsTnqiMItk5YEstpOEKDonu ZBWD9NTWSE2l6Wf6NVGnBbjD0R0QbqveBf7ihyac7NMIPmaC/jcQpJRPi0E6nxdmOMpl jtpYIN7pJ5Sr3Gt3ddo9nXB6kZj1P+1oOitZ8wkPUn6/0YnlQetXzO2gbNygDcwJNGRl djgQ== X-Gm-Message-State: AC+VfDx+3sbZU/Tm32wbThxEl88C8mo5Q/lqm9VErxdDWy/mxiZfr5So C3bQbHpOj4SLtw3ztPwb1O/9Jg== X-Google-Smtp-Source: ACHHUZ5K3Ytg3QVRPnUnd31crBnmsRBI7qqbKV2zFwbBkzVp1eqvWcBAzLzZgc6iaS4hhfVt+wpr/Q== X-Received: by 2002:a05:6512:401:b0:4ec:85f6:5bf8 with SMTP id u1-20020a056512040100b004ec85f65bf8mr3647367lfk.8.1682888232695; Sun, 30 Apr 2023 13:57:12 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id x6-20020ac259c6000000b004db1a7e6decsm4332749lfn.205.2023.04.30.13.57.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Apr 2023 13:57:12 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 1/9] drm/msm/dpu: fix SSPP register definitions Date: Sun, 30 Apr 2023 23:57:02 +0300 Message-Id: <20230430205710.3188230-2-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> References: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Reorder SSPP register definitions to sort them in the ascending order. Move register bitfields after the register definitions. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 66 +++++++++++---------- 1 file changed, 34 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 6b68ec5c7a5a..1bf717290dab 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -26,45 +26,18 @@ #define SSPP_SRC_FORMAT 0x30 #define SSPP_SRC_UNPACK_PATTERN 0x34 #define SSPP_SRC_OP_MODE 0x38 - -/* SSPP_MULTIRECT*/ -#define SSPP_SRC_SIZE_REC1 0x16C -#define SSPP_SRC_XY_REC1 0x168 -#define SSPP_OUT_SIZE_REC1 0x160 -#define SSPP_OUT_XY_REC1 0x164 -#define SSPP_SRC_FORMAT_REC1 0x174 -#define SSPP_SRC_UNPACK_PATTERN_REC1 0x178 -#define SSPP_SRC_OP_MODE_REC1 0x17C -#define SSPP_MULTIRECT_OPMODE 0x170 -#define SSPP_SRC_CONSTANT_COLOR_REC1 0x180 -#define SSPP_EXCL_REC_SIZE_REC1 0x184 -#define SSPP_EXCL_REC_XY_REC1 0x188 - -#define MDSS_MDP_OP_DEINTERLACE BIT(22) -#define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23) -#define MDSS_MDP_OP_IGC_ROM_1 BIT(18) -#define MDSS_MDP_OP_IGC_ROM_0 BIT(17) -#define MDSS_MDP_OP_IGC_EN BIT(16) -#define MDSS_MDP_OP_FLIP_UD BIT(14) -#define MDSS_MDP_OP_FLIP_LR BIT(13) -#define MDSS_MDP_OP_BWC_EN BIT(0) -#define MDSS_MDP_OP_PE_OVERRIDE BIT(31) -#define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1) -#define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1) -#define MDSS_MDP_OP_BWC_Q_MED (2 << 1) - #define SSPP_SRC_CONSTANT_COLOR 0x3c #define SSPP_EXCL_REC_CTL 0x40 #define SSPP_UBWC_STATIC_CTRL 0x44 -#define SSPP_FETCH_CONFIG 0x048 +#define SSPP_FETCH_CONFIG 0x48 #define SSPP_DANGER_LUT 0x60 #define SSPP_SAFE_LUT 0x64 #define SSPP_CREQ_LUT 0x68 #define SSPP_QOS_CTRL 0x6C -#define SSPP_DECIMATION_CONFIG 0xB4 #define SSPP_SRC_ADDR_SW_STATUS 0x70 #define SSPP_CREQ_LUT_0 0x74 #define SSPP_CREQ_LUT_1 0x78 +#define SSPP_DECIMATION_CONFIG 0xB4 #define SSPP_SW_PIX_EXT_C0_LR 0x100 #define SSPP_SW_PIX_EXT_C0_TB 0x104 #define SSPP_SW_PIX_EXT_C0_REQ_PIXELS 0x108 @@ -81,11 +54,33 @@ #define SSPP_TRAFFIC_SHAPER_PREFILL 0x150 #define SSPP_TRAFFIC_SHAPER_REC1_PREFILL 0x154 #define SSPP_TRAFFIC_SHAPER_REC1 0x158 +#define SSPP_OUT_SIZE_REC1 0x160 +#define SSPP_OUT_XY_REC1 0x164 +#define SSPP_SRC_XY_REC1 0x168 +#define SSPP_SRC_SIZE_REC1 0x16C +#define SSPP_MULTIRECT_OPMODE 0x170 +#define SSPP_SRC_FORMAT_REC1 0x174 +#define SSPP_SRC_UNPACK_PATTERN_REC1 0x178 +#define SSPP_SRC_OP_MODE_REC1 0x17C +#define SSPP_SRC_CONSTANT_COLOR_REC1 0x180 +#define SSPP_EXCL_REC_SIZE_REC1 0x184 +#define SSPP_EXCL_REC_XY_REC1 0x188 #define SSPP_EXCL_REC_SIZE 0x1B4 #define SSPP_EXCL_REC_XY 0x1B8 -#define SSPP_VIG_OP_MODE 0x0 -#define SSPP_VIG_CSC_10_OP_MODE 0x0 -#define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF + +/* SSPP_SRC_OP_MODE & OP_MODE_REC1 */ +#define MDSS_MDP_OP_DEINTERLACE BIT(22) +#define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23) +#define MDSS_MDP_OP_IGC_ROM_1 BIT(18) +#define MDSS_MDP_OP_IGC_ROM_0 BIT(17) +#define MDSS_MDP_OP_IGC_EN BIT(16) +#define MDSS_MDP_OP_FLIP_UD BIT(14) +#define MDSS_MDP_OP_FLIP_LR BIT(13) +#define MDSS_MDP_OP_BWC_EN BIT(0) +#define MDSS_MDP_OP_PE_OVERRIDE BIT(31) +#define MDSS_MDP_OP_BWC_LOSSLESS (0 << 1) +#define MDSS_MDP_OP_BWC_Q_HIGH (1 << 1) +#define MDSS_MDP_OP_BWC_Q_MED (2 << 1) /* SSPP_QOS_CTRL */ #define SSPP_QOS_CTRL_VBLANK_EN BIT(16) @@ -96,6 +91,7 @@ #define SSPP_QOS_CTRL_CREQ_VBLANK_OFF 20 /* DPU_SSPP_SCALER_QSEED2 */ +#define SSPP_VIG_OP_MODE 0x0 #define SCALE_CONFIG 0x04 #define COMP0_3_PHASE_STEP_X 0x10 #define COMP0_3_PHASE_STEP_Y 0x14 @@ -107,6 +103,12 @@ #define COMP1_2_INIT_PHASE_Y 0x2C #define VIG_0_QSEED2_SHARP 0x30 +/* DPU_SSPP_CSC_10BIT space */ +#define SSPP_VIG_CSC_10_OP_MODE 0x0 + +/* SSPP_TRAFFIC_SHAPER and _REC1 */ +#define SSPP_TRAFFIC_SHAPER_BPC_MAX 0xFF + /* * Definitions for ViG op modes */ From patchwork Sun Apr 30 20:57:03 2023 Content-Type: text/plain; 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id x6-20020ac259c6000000b004db1a7e6decsm4332749lfn.205.2023.04.30.13.57.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Apr 2023 13:57:13 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 2/9] drm/msm/dpu: simplify CDP programming Date: Sun, 30 Apr 2023 23:57:03 +0300 Message-Id: <20230430205710.3188230-3-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> References: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Get rid of intermediatory configuration structure and defines. Pass the format and the enablement bit directly to the new helper. The WB_CDP_CNTL register ignores BIT(2), so we can write it for both SSPP and WB CDP settings. Signed-off-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 19 ++++------------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 17 ++++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 14 ++++--------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 21 +++++++++++++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 19 +++-------------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 19 ++++------------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 11 ++-------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 20 ++++-------------- 8 files changed, 46 insertions(+), 94 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index bac4aa807b4b..120141f1e5c5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -140,7 +140,6 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc, struct dpu_encoder_phys_wb *wb_enc = to_dpu_encoder_phys_wb(phys_enc); struct dpu_hw_wb *hw_wb; struct dpu_hw_wb_cfg *wb_cfg; - struct dpu_hw_cdp_cfg cdp_cfg; if (!phys_enc || !phys_enc->dpu_kms || !phys_enc->dpu_kms->catalog) { DPU_ERROR("invalid encoder\n"); @@ -162,20 +161,10 @@ static void dpu_encoder_phys_wb_setup_fb(struct dpu_encoder_phys *phys_enc, if (hw_wb->ops.setup_outformat) hw_wb->ops.setup_outformat(hw_wb, wb_cfg); - if (hw_wb->ops.setup_cdp) { - memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg)); - - cdp_cfg.enable = phys_enc->dpu_kms->catalog->perf->cdp_cfg - [DPU_PERF_CDP_USAGE_NRT].wr_enable; - cdp_cfg.ubwc_meta_enable = - DPU_FORMAT_IS_UBWC(wb_cfg->dest.format); - cdp_cfg.tile_amortize_enable = - DPU_FORMAT_IS_UBWC(wb_cfg->dest.format) || - DPU_FORMAT_IS_TILE(wb_cfg->dest.format); - cdp_cfg.preload_ahead = DPU_WB_CDP_PRELOAD_AHEAD_64; - - hw_wb->ops.setup_cdp(hw_wb, &cdp_cfg); - } + if (hw_wb->ops.setup_cdp) + hw_wb->ops.setup_cdp(hw_wb, wb_cfg->dest.format, + phys_enc->dpu_kms->catalog->perf->cdp_cfg + [DPU_PERF_CDP_USAGE_NRT].wr_enable); if (hw_wb->ops.setup_outaddress) hw_wb->ops.setup_outaddress(hw_wb, wb_cfg); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 1bf717290dab..731199030336 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -592,13 +592,13 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, } static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, - struct dpu_hw_cdp_cfg *cfg) + const struct dpu_format *fmt, + bool enable) { struct dpu_hw_sspp *ctx = pipe->sspp; - u32 cdp_cntl = 0; u32 cdp_cntl_offset = 0; - if (!ctx || !cfg) + if (!ctx) return; if (pipe->multirect_index == DPU_SSPP_RECT_SOLO || @@ -607,16 +607,7 @@ static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, else cdp_cntl_offset = SSPP_CDP_CNTL_REC1; - if (cfg->enable) - cdp_cntl |= BIT(0); - if (cfg->ubwc_meta_enable) - cdp_cntl |= BIT(1); - if (cfg->tile_amortize_enable) - cdp_cntl |= BIT(2); - if (cfg->preload_ahead == DPU_SSPP_CDP_PRELOAD_AHEAD_64) - cdp_cntl |= BIT(3); - - DPU_REG_WRITE(&ctx->hw, cdp_cntl_offset, cdp_cntl); + dpu_setup_cdp(&ctx->hw, cdp_cntl_offset, fmt, enable); } static void _setup_layer_ops(struct dpu_hw_sspp *c, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 7a8d11ba618d..86bf4b2cda77 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -177,14 +177,6 @@ struct dpu_hw_pipe_qos_cfg { bool danger_safe_en; }; -/** - * enum CDP preload ahead address size - */ -enum { - DPU_SSPP_CDP_PRELOAD_AHEAD_32, - DPU_SSPP_CDP_PRELOAD_AHEAD_64 -}; - /** * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration * @size: size to prefill in bytes, or zero to disable @@ -331,10 +323,12 @@ struct dpu_hw_sspp_ops { /** * setup_cdp - setup client driven prefetch * @pipe: Pointer to software pipe context - * @cfg: Pointer to cdp configuration + * @fmt: format used by the sw pipe + * @enable: whether the CDP should be enabled for this pipe */ void (*setup_cdp)(struct dpu_sw_pipe *pipe, - struct dpu_hw_cdp_cfg *cfg); + const struct dpu_format *fmt, + bool enable); }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c index 8062228eada6..95d20b9a3f2f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c @@ -494,3 +494,24 @@ int dpu_hw_collect_misr(struct dpu_hw_blk_reg_map *c, return 0; } + +#define CDP_ENABLE BIT(0) +#define CDP_UBWC_META_ENABLE BIT(1) +#define CDP_TILE_AMORTIZE_ENABLE BIT(2) +#define CDP_PRELOAD_AHEAD_64 BIT(3) + +void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset, + const struct dpu_format *fmt, bool enable) +{ + u32 cdp_cntl = CDP_PRELOAD_AHEAD_64; + + if (enable) + cdp_cntl |= CDP_ENABLE; + if (DPU_FORMAT_IS_UBWC(fmt)) + cdp_cntl |= CDP_UBWC_META_ENABLE; + if (DPU_FORMAT_IS_UBWC(fmt) || + DPU_FORMAT_IS_TILE(fmt)) + cdp_cntl |= CDP_TILE_AMORTIZE_ENABLE; + + DPU_REG_WRITE(c, offset, cdp_cntl); +} diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h index 27f4c39e35ab..dc6e3b795aef 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -305,22 +305,6 @@ struct dpu_drm_scaler_v2 { struct dpu_drm_de_v1 de; }; -/** - * struct dpu_hw_cdp_cfg : CDP configuration - * @enable: true to enable CDP - * @ubwc_meta_enable: true to enable ubwc metadata preload - * @tile_amortize_enable: true to enable amortization control for tile format - * @preload_ahead: number of request to preload ahead - * DPU_*_CDP_PRELOAD_AHEAD_32, - * DPU_*_CDP_PRELOAD_AHEAD_64 - */ -struct dpu_hw_cdp_cfg { - bool enable; - bool ubwc_meta_enable; - bool tile_amortize_enable; - u32 preload_ahead; -}; - u32 *dpu_hw_util_get_log_mask_ptr(void); void dpu_reg_write(struct dpu_hw_blk_reg_map *c, @@ -346,6 +330,9 @@ void dpu_hw_csc_setup(struct dpu_hw_blk_reg_map *c, u32 csc_reg_off, const struct dpu_csc_cfg *data, bool csc10); +void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset, + const struct dpu_format *fmt, bool enable); + u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, u32 total_fl); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c index 4834866d72fd..a6de4b82a188 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c @@ -164,24 +164,13 @@ static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx, } static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx, - struct dpu_hw_cdp_cfg *cfg) + const struct dpu_format *fmt, + bool enable) { - struct dpu_hw_blk_reg_map *c; - u32 cdp_cntl = 0; - - if (!ctx || !cfg) + if (!ctx) return; - c = &ctx->hw; - - if (cfg->enable) - cdp_cntl |= BIT(0); - if (cfg->ubwc_meta_enable) - cdp_cntl |= BIT(1); - if (cfg->preload_ahead == DPU_WB_CDP_PRELOAD_AHEAD_64) - cdp_cntl |= BIT(3); - - DPU_REG_WRITE(c, WB_CDP_CNTL, cdp_cntl); + dpu_setup_cdp(&ctx->hw, WB_CDP_CNTL, fmt, enable); } static void dpu_hw_wb_bind_pingpong_blk( diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h index e4f85409c624..ab3541856258 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h @@ -21,14 +21,6 @@ struct dpu_hw_wb_cfg { struct drm_rect crop; }; -/** - * enum CDP preload ahead address size - */ -enum { - DPU_WB_CDP_PRELOAD_AHEAD_32, - DPU_WB_CDP_PRELOAD_AHEAD_64 -}; - /** * struct dpu_hw_wb_qos_cfg : Writeback pipe QoS configuration * @danger_lut: LUT for generate danger level based on fill level @@ -67,7 +59,8 @@ struct dpu_hw_wb_ops { struct dpu_hw_wb_qos_cfg *cfg); void (*setup_cdp)(struct dpu_hw_wb *ctx, - struct dpu_hw_cdp_cfg *cfg); + const struct dpu_format *fmt, + bool enable); void (*bind_pingpong_blk)(struct dpu_hw_wb *ctx, bool enable, const enum dpu_pingpong pp); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 14b5cfe30611..43d9fbc0c687 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1115,22 +1115,10 @@ static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, /* update format */ pipe->sspp->ops.setup_format(pipe, fmt, src_flags); - if (pipe->sspp->ops.setup_cdp) { - struct dpu_hw_cdp_cfg cdp_cfg; - - memset(&cdp_cfg, 0, sizeof(struct dpu_hw_cdp_cfg)); - - cdp_cfg.enable = pdpu->catalog->perf->cdp_cfg - [DPU_PERF_CDP_USAGE_RT].rd_enable; - cdp_cfg.ubwc_meta_enable = - DPU_FORMAT_IS_UBWC(fmt); - cdp_cfg.tile_amortize_enable = - DPU_FORMAT_IS_UBWC(fmt) || - DPU_FORMAT_IS_TILE(fmt); - cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64; - - pipe->sspp->ops.setup_cdp(pipe, &cdp_cfg); - } + if (pipe->sspp->ops.setup_cdp) + pipe->sspp->ops.setup_cdp(pipe, fmt, + pdpu->catalog->perf->cdp_cfg + [DPU_PERF_CDP_USAGE_RT].rd_enable); } _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); From patchwork Sun Apr 30 20:57:04 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 678032 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7EA53C77B7C for ; Sun, 30 Apr 2023 20:57:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229688AbjD3U5U (ORCPT ); Sun, 30 Apr 2023 16:57:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34158 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230194AbjD3U5S (ORCPT ); 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id x6-20020ac259c6000000b004db1a7e6decsm4332749lfn.205.2023.04.30.13.57.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Apr 2023 13:57:13 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 3/9] drm/msm/dpu: fix the condition for (not) applying QoS to CURSOR SSPP Date: Sun, 30 Apr 2023 23:57:04 +0300 Message-Id: <20230430205710.3188230-4-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> References: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org The function dpu_plane_sspp_update_pipe() contains code to skip enabling the QoS and OT limitis for CURSOR pipes. However all DPU since sdm845 repurpose DMA SSPP for the cursor planes because they lack the real CURSOR SSPP. Fix the condition to actually check that the plane is CURSOR or not. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 43d9fbc0c687..36f6eb71fef8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1124,7 +1124,8 @@ static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); _dpu_plane_set_danger_lut(plane, pipe, fmt); - if (plane->type != DRM_PLANE_TYPE_CURSOR) { + if (pipe->sspp->idx == SSPP_CURSOR0 || + pipe->sspp->idx == SSPP_CURSOR1) { _dpu_plane_set_qos_ctrl(plane, pipe, true, DPU_PLANE_QOS_PANIC_CTRL); _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate); } From patchwork Sun Apr 30 20:57:05 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 678174 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 03D68C7EE24 for ; Sun, 30 Apr 2023 20:57:22 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229663AbjD3U5U (ORCPT ); Sun, 30 Apr 2023 16:57:20 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34160 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230347AbjD3U5T (ORCPT ); Sun, 30 Apr 2023 16:57:19 -0400 Received: from mail-lf1-x132.google.com (mail-lf1-x132.google.com [IPv6:2a00:1450:4864:20::132]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id AC2B412D for ; Sun, 30 Apr 2023 13:57:16 -0700 (PDT) Received: by mail-lf1-x132.google.com with SMTP id 2adb3069b0e04-4ec8148f73eso2260711e87.1 for ; Sun, 30 Apr 2023 13:57:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682888235; x=1685480235; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xxMIlhE+xo1ndRNL8TNhFy+W+mxe0zzz0yJ/CAW62w4=; b=VO/JrwDg94kbsUdw9EK5ccKxqJlrawqyw5q0ef5tpIPXaSNp03qXp3v7A1pxt9guPO vdg2hjQg5eTgKlvO6H8fviQRKIEdH47T6HUuje3MTVwcGMG141LyHmz1sJvWs31FNGQu vd4x4QeJKkiyYBAakjcorNnvPVhWfmeWxxW8UTH7V3CTtTeeiD+/VXdwQ2wOBa6Ay6Py ZYWmam5Zjrr0nIaaTkd4EyeRG6ltmA++AEMEXIIoDY7T1ZcPZgGVSW9rrlMP6e+ds8S9 2YJZ77tnboxxTXCl/cIzlFSj8R+mExhpVwv8KdZBa7xOfzHU6vkRryyXxRzBSaiqSVUX dxjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682888235; x=1685480235; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xxMIlhE+xo1ndRNL8TNhFy+W+mxe0zzz0yJ/CAW62w4=; b=MISnKREBvE+63xK3+Xvq1Ck864rYB4LPGj9ZUrQVKvyhgSKa0LwaHpf8bRMrHGzIQ3 vZQU5ViMI1XSEIajrrv/4Gfm9oIzly8YirJnOhkWZBFatLDG2uqpJ4V2bosebXuc44qo UPtDU+nGu6eYIHvo3e0r54sLD7YLucvB7gk8ii9n5fUWsassLz59ojn33s8Qm1ZEU6Rd 6JozKSA2If6b81f7ZC8wKv47apw+Bw1dpgsKR/s+Olt+o6nuCgBoPiuRd+hL6mpIp+em ivHpwXpKWPR+8LjdwjoOBCfjx/6BSdXr16W3bakmFOzsudrBN+nUbY/OWMrVUnPdkEg/ K3MA== X-Gm-Message-State: AC+VfDz5kKWfT6DaM/M/65clI4KxM8P+fHE5quiNvQgJDqoqSWcPmgcL xEduRZxYWrq0RvRjfkM7rWaBog== X-Google-Smtp-Source: ACHHUZ75oe2mpelzwjC1zNnI6eL3nDKdEoAQfJ145W+UsY93FRLEu3NU1KQH8EG2DWSdeE9Szy27OA== X-Received: by 2002:ac2:414c:0:b0:4eb:2e5c:e0a with SMTP id c12-20020ac2414c000000b004eb2e5c0e0amr3503756lfi.41.1682888234872; Sun, 30 Apr 2023 13:57:14 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id x6-20020ac259c6000000b004db1a7e6decsm4332749lfn.205.2023.04.30.13.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Apr 2023 13:57:14 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 4/9] drm/msm/dpu: rearrange QoS setting code Date: Sun, 30 Apr 2023 23:57:05 +0300 Message-Id: <20230430205710.3188230-5-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> References: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Slightly rearrainge code in dpu_plane_sspp_update_pipe() to group QoS/LUT related functions. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 36f6eb71fef8..4a5a58152fa8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -1079,10 +1079,10 @@ static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, pipe->sspp->ops.setup_sourceaddress(pipe, layout); } - _dpu_plane_set_qos_ctrl(plane, pipe, false, DPU_PLANE_QOS_PANIC_CTRL); - /* override for color fill */ if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { + _dpu_plane_set_qos_ctrl(plane, pipe, false, DPU_PLANE_QOS_PANIC_CTRL); + /* skip remaining processing on color fill */ return; } @@ -1123,12 +1123,14 @@ static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); _dpu_plane_set_danger_lut(plane, pipe, fmt); + _dpu_plane_set_qos_ctrl(plane, pipe, + pipe->sspp->idx != SSPP_CURSOR0 && + pipe->sspp->idx != SSPP_CURSOR1, + DPU_PLANE_QOS_PANIC_CTRL); if (pipe->sspp->idx == SSPP_CURSOR0 || - pipe->sspp->idx == SSPP_CURSOR1) { - _dpu_plane_set_qos_ctrl(plane, pipe, true, DPU_PLANE_QOS_PANIC_CTRL); + pipe->sspp->idx == SSPP_CURSOR1) _dpu_plane_set_ot_limit(plane, pipe, pipe_cfg, frame_rate); - } if (pstate->needs_qos_remap) _dpu_plane_set_qos_remap(plane, pipe); From patchwork Sun Apr 30 20:57:06 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 678173 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D4E83C77B73 for ; Sun, 30 Apr 2023 20:57:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230347AbjD3U5V (ORCPT ); Sun, 30 Apr 2023 16:57:21 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34170 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231150AbjD3U5T (ORCPT ); Sun, 30 Apr 2023 16:57:19 -0400 Received: from mail-lf1-x133.google.com (mail-lf1-x133.google.com [IPv6:2a00:1450:4864:20::133]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4FF7D12F for ; Sun, 30 Apr 2023 13:57:17 -0700 (PDT) Received: by mail-lf1-x133.google.com with SMTP id 2adb3069b0e04-4ec8148f73eso2260718e87.1 for ; Sun, 30 Apr 2023 13:57:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682888235; x=1685480235; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8IldrM6PVf7lolgGQLZs8CrARxItt7xmrIuooW70x7g=; b=LMg54sCY0oWs8jIE5/Nd8alwWe3DES37WCZeZtWgIxBcUd0ciQEuTxEf/i2Jkg5dac 6dV3DdmILMfE/pyOMetkK11uMyhCJQafT1qvRp5Id166EIyz+K5NchcMxURcL0GU0R8h Wxs249SE/SNr/1IpfS2iLwp+jf7Ts9/L0Fa/2M8erS4ETHzGZcAR8rgeyNZieMHoX5NG v0y2ADqnYwsX57AJqrPIP8LPlG+Un1XJfqilqn8VxsPLrMT5AyJ+cr8MQ548sugJ8FzU 2bgtY3giEh5Lcqk7Dm4WLLVfoG/cCDtCTBLXcHmw1bn5kmwvovi+1hhDxCdymi+UlY3u RxvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682888235; x=1685480235; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8IldrM6PVf7lolgGQLZs8CrARxItt7xmrIuooW70x7g=; b=N5po+GVp6Sh8Py7IJh4uR31aYnAFZP8Mf9oNma92L+mroycHc9qJfoIMMDnWbQdYnB rdTRZ3xjXTNSR/3e+e99WXCBIeUOIopGXvKeQ5dukfBBVVKP4v7u4aCNwBO79FxQV/d9 l/kUScf2PO+Z7koeljfAQyxy8cOhmjzbndkUwGrdlMMY6Bb0pWRQtHvy3JVe3ZX0KDit 9lxpMQkdsGGmELBdcEallDwzqiq7nQOv6dtFxd0LiGUrPxIvBXcgE5CNjDqkQGr6elD+ jqm1++9UpxiAja4KLZBv87E+jW9dXajwCI1TkaPq6Hgv+SbDimYpd+/pRwu9KO5Pm+N/ FCrw== X-Gm-Message-State: AC+VfDxMN4aX7BAz5VvWTJaPOXzU+s2l66xkEqhzW81JVwEI1VtbFHsd aZuGTa/GOQagLnLp6+zsTL0n8g== X-Google-Smtp-Source: ACHHUZ6vYTRMjLtpGWm54O6d5niNUnuG6bx/OWBjOHrFNPdFpFQHi0PxClS/XRQTCx/Ia5av9SMEuA== X-Received: by 2002:ac2:54ae:0:b0:4ed:d5ce:7df0 with SMTP id w14-20020ac254ae000000b004edd5ce7df0mr3292630lfk.7.1682888235585; Sun, 30 Apr 2023 13:57:15 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id x6-20020ac259c6000000b004db1a7e6decsm4332749lfn.205.2023.04.30.13.57.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Apr 2023 13:57:15 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 5/9] drm/msm/dpu: drop DPU_PLANE_QOS_VBLANK_CTRL Date: Sun, 30 Apr 2023 23:57:06 +0300 Message-Id: <20230430205710.3188230-6-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> References: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Drop support for DPU_PLANE_QOS_VBLANK_CTRL flag. It is not used both in upstream driver and in vendor SDE driver. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 4 ---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 8 -------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 10 ---------- 3 files changed, 22 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index b2831b45ac64..d47e7061a36b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -371,8 +371,6 @@ struct dpu_caps { /** * struct dpu_sspp_sub_blks : SSPP sub-blocks * common: Pointer to common configurations shared by sub blocks - * @creq_vblank: creq priority during vertical blanking - * @danger_vblank: danger priority during vertical blanking * @maxdwnscale: max downscale ratio supported(without DECIMATION) * @maxupscale: maxupscale ratio supported * @smart_dma_priority: hw priority of rect1 of multirect pipe @@ -387,8 +385,6 @@ struct dpu_caps { * @dpu_rotation_cfg: inline rotation configuration */ struct dpu_sspp_sub_blks { - u32 creq_vblank; - u32 danger_vblank; u32 maxdwnscale; u32 maxupscale; u32 smart_dma_priority; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 731199030336..b198def5534b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -697,14 +697,6 @@ int _dpu_hw_sspp_init_debugfs(struct dpu_hw_sspp *hw_pipe, struct dpu_kms *kms, 0400, debugfs_root, (u32 *) &cfg->clk_ctrl); - debugfs_create_x32("creq_vblank", - 0600, - debugfs_root, - (u32 *) &sblk->creq_vblank); - debugfs_create_x32("danger_vblank", - 0600, - debugfs_root, - (u32 *) &sblk->danger_vblank); return 0; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 4a5a58152fa8..d7ee4bdc752f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -73,13 +73,11 @@ static const uint32_t qcom_compressed_supported_formats[] = { /** * enum dpu_plane_qos - Different qos configurations for each pipe * - * @DPU_PLANE_QOS_VBLANK_CTRL: Setup VBLANK qos for the pipe. * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. * this configuration is mutually exclusive from VBLANK_CTRL. * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. */ enum dpu_plane_qos { - DPU_PLANE_QOS_VBLANK_CTRL = BIT(0), DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), DPU_PLANE_QOS_PANIC_CTRL = BIT(2), }; @@ -361,15 +359,7 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); - if (flags & DPU_PLANE_QOS_VBLANK_CTRL) { - pipe_qos_cfg.creq_vblank = pipe->sspp->cap->sblk->creq_vblank; - pipe_qos_cfg.danger_vblank = - pipe->sspp->cap->sblk->danger_vblank; - pipe_qos_cfg.vblank_en = enable; - } - if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) { - /* this feature overrules previous VBLANK_CTRL */ pipe_qos_cfg.vblank_en = false; pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ } From patchwork Sun Apr 30 20:57:07 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 678030 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 19073C77B7F for ; Sun, 30 Apr 2023 20:57:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231779AbjD3U5X (ORCPT ); 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id x6-20020ac259c6000000b004db1a7e6decsm4332749lfn.205.2023.04.30.13.57.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Apr 2023 13:57:15 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 6/9] drm/msm/dpu: simplify qos_ctrl handling Date: Sun, 30 Apr 2023 23:57:07 +0300 Message-Id: <20230430205710.3188230-7-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> References: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org After removal of DPU_PLANE_QOS_VBLANK_CTRL, several fields of struct dpu_hw_pipe_qos_cfg are fixed to false/0. Drop them from the structure (and drop the corresponding code from the functions). The DPU_PLANE_QOS_VBLANK_AMORTIZE flag is also removed, since it is now a NOP. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 10 ---------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 6 ------ drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 17 ++--------------- 3 files changed, 2 insertions(+), 31 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index b198def5534b..341e3a8fc927 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -575,16 +575,6 @@ static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, if (!ctx) return; - if (cfg->vblank_en) { - qos_ctrl |= ((cfg->creq_vblank & - SSPP_QOS_CTRL_CREQ_VBLANK_MASK) << - SSPP_QOS_CTRL_CREQ_VBLANK_OFF); - qos_ctrl |= ((cfg->danger_vblank & - SSPP_QOS_CTRL_DANGER_VBLANK_MASK) << - SSPP_QOS_CTRL_DANGER_VBLANK_OFF); - qos_ctrl |= SSPP_QOS_CTRL_VBLANK_EN; - } - if (cfg->danger_safe_en) qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 86bf4b2cda77..aaf6f41d546c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -165,15 +165,9 @@ struct dpu_sw_pipe_cfg { /** * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration - * @creq_vblank: creq value generated to vbif during vertical blanking - * @danger_vblank: danger value generated during vertical blanking - * @vblank_en: enable creq_vblank and danger_vblank during vblank * @danger_safe_en: enable danger safe generation */ struct dpu_hw_pipe_qos_cfg { - u32 creq_vblank; - u32 danger_vblank; - bool vblank_en; bool danger_safe_en; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index d7ee4bdc752f..f7656436f3f1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -73,12 +73,9 @@ static const uint32_t qcom_compressed_supported_formats[] = { /** * enum dpu_plane_qos - Different qos configurations for each pipe * - * @DPU_PLANE_QOS_VBLANK_AMORTIZE: Enables Amortization within pipe. - * this configuration is mutually exclusive from VBLANK_CTRL. * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. */ enum dpu_plane_qos { - DPU_PLANE_QOS_VBLANK_AMORTIZE = BIT(1), DPU_PLANE_QOS_PANIC_CTRL = BIT(2), }; @@ -359,25 +356,15 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); - if (flags & DPU_PLANE_QOS_VBLANK_AMORTIZE) { - pipe_qos_cfg.vblank_en = false; - pipe_qos_cfg.creq_vblank = 0; /* clear vblank bits */ - } - if (flags & DPU_PLANE_QOS_PANIC_CTRL) pipe_qos_cfg.danger_safe_en = enable; - if (!pdpu->is_rt_pipe) { - pipe_qos_cfg.vblank_en = false; + if (!pdpu->is_rt_pipe) pipe_qos_cfg.danger_safe_en = false; - } - DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d vb:%d pri[0x%x, 0x%x] is_rt:%d\n", + DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", pdpu->pipe - SSPP_VIG0, pipe_qos_cfg.danger_safe_en, - pipe_qos_cfg.vblank_en, - pipe_qos_cfg.creq_vblank, - pipe_qos_cfg.danger_vblank, pdpu->is_rt_pipe); pipe->sspp->ops.setup_qos_ctrl(pipe->sspp, From patchwork Sun Apr 30 20:57:08 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 678171 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2FD4CC77B7C for ; Sun, 30 Apr 2023 20:57:25 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231814AbjD3U5Y (ORCPT ); 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id x6-20020ac259c6000000b004db1a7e6decsm4332749lfn.205.2023.04.30.13.57.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Apr 2023 13:57:16 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 7/9] drm/msm/dpu: drop DPU_PLANE_QOS_PANIC_CTRL Date: Sun, 30 Apr 2023 23:57:08 +0300 Message-Id: <20230430205710.3188230-8-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> References: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org This flag is always passed to _dpu_plane_set_qos_ctrl(), so drop it and remove corresponding conditions from the mentioned function. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 27 +++++++---------------- 1 file changed, 8 insertions(+), 19 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index f7656436f3f1..22273d0baf59 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -70,15 +70,6 @@ static const uint32_t qcom_compressed_supported_formats[] = { DRM_FORMAT_P010, }; -/** - * enum dpu_plane_qos - Different qos configurations for each pipe - * - * @DPU_PLANE_QOS_PANIC_CTRL: Setup panic for the pipe. - */ -enum dpu_plane_qos { - DPU_PLANE_QOS_PANIC_CTRL = BIT(2), -}; - /* * struct dpu_plane - local dpu plane structure * @aspace: address space pointer @@ -349,15 +340,14 @@ static void _dpu_plane_set_danger_lut(struct drm_plane *plane, */ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, struct dpu_sw_pipe *pipe, - bool enable, u32 flags) + bool enable) { struct dpu_plane *pdpu = to_dpu_plane(plane); struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); - if (flags & DPU_PLANE_QOS_PANIC_CTRL) - pipe_qos_cfg.danger_safe_en = enable; + pipe_qos_cfg.danger_safe_en = enable; if (!pdpu->is_rt_pipe) pipe_qos_cfg.danger_safe_en = false; @@ -1058,7 +1048,7 @@ static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, /* override for color fill */ if (pdpu->color_fill & DPU_PLANE_COLOR_FILL_FLAG) { - _dpu_plane_set_qos_ctrl(plane, pipe, false, DPU_PLANE_QOS_PANIC_CTRL); + _dpu_plane_set_qos_ctrl(plane, pipe, false); /* skip remaining processing on color fill */ return; @@ -1102,8 +1092,7 @@ static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, _dpu_plane_set_danger_lut(plane, pipe, fmt); _dpu_plane_set_qos_ctrl(plane, pipe, pipe->sspp->idx != SSPP_CURSOR0 && - pipe->sspp->idx != SSPP_CURSOR1, - DPU_PLANE_QOS_PANIC_CTRL); + pipe->sspp->idx != SSPP_CURSOR1); if (pipe->sspp->idx == SSPP_CURSOR0 || pipe->sspp->idx == SSPP_CURSOR1) @@ -1222,10 +1211,10 @@ static void dpu_plane_destroy(struct drm_plane *plane) if (pdpu) { pstate = to_dpu_plane_state(plane->state); - _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, false, DPU_PLANE_QOS_PANIC_CTRL); + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, false); if (pstate->r_pipe.sspp) - _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, false, DPU_PLANE_QOS_PANIC_CTRL); + _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, false); mutex_destroy(&pdpu->lock); @@ -1382,9 +1371,9 @@ void dpu_plane_danger_signal_ctrl(struct drm_plane *plane, bool enable) return; pm_runtime_get_sync(&dpu_kms->pdev->dev); - _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable, DPU_PLANE_QOS_PANIC_CTRL); + _dpu_plane_set_qos_ctrl(plane, &pstate->pipe, enable); if (pstate->r_pipe.sspp) - _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable, DPU_PLANE_QOS_PANIC_CTRL); + _dpu_plane_set_qos_ctrl(plane, &pstate->r_pipe, enable); pm_runtime_put_sync(&dpu_kms->pdev->dev); } #endif From patchwork Sun Apr 30 20:57:09 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 678029 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 25610C7EE25 for ; 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[2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id x6-20020ac259c6000000b004db1a7e6decsm4332749lfn.205.2023.04.30.13.57.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Apr 2023 13:57:17 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 8/9] drm/msm/dpu: remove struct dpu_hw_pipe_qos_cfg Date: Sun, 30 Apr 2023 23:57:09 +0300 Message-Id: <20230430205710.3188230-9-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> References: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Now as the struct dpu_hw_pipe_qos_cfg consists of only one bool field, drop the structure and use corresponding bool directly. Signed-off-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 10 +++------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 13 ++----------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 11 +++-------- 3 files changed, 8 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 341e3a8fc927..2533c4629021 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -568,17 +568,13 @@ static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx, } static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, - struct dpu_hw_pipe_qos_cfg *cfg) + bool danger_safe_en) { - u32 qos_ctrl = 0; - if (!ctx) return; - if (cfg->danger_safe_en) - qos_ctrl |= SSPP_QOS_CTRL_DANGER_SAFE_EN; - - DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL, qos_ctrl); + DPU_REG_WRITE(&ctx->hw, SSPP_QOS_CTRL, + danger_safe_en ? SSPP_QOS_CTRL_DANGER_SAFE_EN : 0); } static void dpu_hw_sspp_setup_cdp(struct dpu_sw_pipe *pipe, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index aaf6f41d546c..4278c421b6ac 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -163,14 +163,6 @@ struct dpu_sw_pipe_cfg { struct drm_rect dst_rect; }; -/** - * struct dpu_hw_pipe_qos_cfg : Source pipe QoS configuration - * @danger_safe_en: enable danger safe generation - */ -struct dpu_hw_pipe_qos_cfg { - bool danger_safe_en; -}; - /** * struct dpu_hw_pipe_ts_cfg - traffic shaper configuration * @size: size to prefill in bytes, or zero to disable @@ -285,11 +277,10 @@ struct dpu_hw_sspp_ops { /** * setup_qos_ctrl - setup QoS control * @ctx: Pointer to pipe context - * @cfg: Pointer to pipe QoS configuration - * + * @danger_safe_en: flags controlling enabling of danger/safe QoS/LUT */ void (*setup_qos_ctrl)(struct dpu_hw_sspp *ctx, - struct dpu_hw_pipe_qos_cfg *cfg); + bool danger_safe_en); /** * setup_histogram - setup histograms diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 22273d0baf59..75fb2d2796b5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -343,22 +343,17 @@ static void _dpu_plane_set_qos_ctrl(struct drm_plane *plane, bool enable) { struct dpu_plane *pdpu = to_dpu_plane(plane); - struct dpu_hw_pipe_qos_cfg pipe_qos_cfg; - - memset(&pipe_qos_cfg, 0, sizeof(pipe_qos_cfg)); - - pipe_qos_cfg.danger_safe_en = enable; if (!pdpu->is_rt_pipe) - pipe_qos_cfg.danger_safe_en = false; + enable = false; DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", pdpu->pipe - SSPP_VIG0, - pipe_qos_cfg.danger_safe_en, + enable, pdpu->is_rt_pipe); pipe->sspp->ops.setup_qos_ctrl(pipe->sspp, - &pipe_qos_cfg); + enable); } /** From patchwork Sun Apr 30 20:57:10 2023 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Dmitry Baryshkov X-Patchwork-Id: 678028 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CEFD2C7EE26 for ; Sun, 30 Apr 2023 20:57:26 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230139AbjD3U5Z (ORCPT ); Sun, 30 Apr 2023 16:57:25 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34204 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231150AbjD3U5W (ORCPT ); Sun, 30 Apr 2023 16:57:22 -0400 Received: from mail-lf1-x130.google.com (mail-lf1-x130.google.com [IPv6:2a00:1450:4864:20::130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 42ABE12D for ; Sun, 30 Apr 2023 13:57:20 -0700 (PDT) Received: by mail-lf1-x130.google.com with SMTP id 2adb3069b0e04-4f00d3f98deso19650783e87.0 for ; Sun, 30 Apr 2023 13:57:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1682888238; x=1685480238; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3S0mBFXgQeb+45KEUrQBsgApSVoR4gMq1gusKliQtrU=; b=EngVTkbPDXWWjYu3UiOW5zmeJsXbV4VBA8QS0KF11dkRjp/p8M0zOpQtSx1gDwyQgv KqbJR4e3als7gwHllTvLqCegFv+s2gltMv1Ta/dQSF+FboIjXZcASIBQsMk4Uz4WkDHq 4r0Z13uUO6z8WYK+qCxqQ4CnzaetjfZrwsRv/JGoJVEL5SuqF558dH9Tcf/mVlBshuSl 15Z0kTJQv2hkpQa/7aCxMHn7aao0/Mq9/OQ+YJizDdvrAyVR/8VmTg095VXw7t5IDpIe aCSDrPk1F/q523KER64i0NCN/lEpj0+mf+uSBB7egwS9/rMSZoKv100krlJVqTuPYVtR zWqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1682888238; x=1685480238; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3S0mBFXgQeb+45KEUrQBsgApSVoR4gMq1gusKliQtrU=; b=k4MZUL8u61hecSlFg8/zK6/I2g4xvq7Wyh2ZEN9RTA9OuotjIcjppXZu1QQ6zbmfFE zm4yxBLLpC7hKDaiQnVyhNFKLcGJg/PdrX+x7hhaBaoARdfGDOTuA6b2r5ala2bq0EXx EDTpozPdxBjYqZatwyLuKvd9T1INqgB3KJ4+Hv/qoSGZsrqRCdnqQ9oZRpNt9x8kRW/o OEg/u/3ccdBFFT5Y3ArZgs++DEf6bsyB2t2PAhqdLiCg0HoWD4EfS1lA25EM/GH+E6IC 2q7zwTt033AxKKCsCQkp1Zb/xOzzDV94FUqp6WI5NhKWFEFyZw+Uh66Zyo5scMJ4Ez4F eKyg== X-Gm-Message-State: AC+VfDz8mLydpzpPJ/bvfCZKTPOMkM+p5QfdqWeeTtzAAAWfNtoXFLkm 0hzyCopJqcwLQNy4m6njgRQtI2L4KLWE8XMYhu4= X-Google-Smtp-Source: ACHHUZ7jqvftkEYu6K/U8TUXr1Jpd6PbgHPo5b4Cm1P66YT3gq2jsSXdeS+ksjRGGFgMwwMvJzkMjA== X-Received: by 2002:a05:6512:39c8:b0:4eb:1599:f3b7 with SMTP id k8-20020a05651239c800b004eb1599f3b7mr4557039lfu.13.1682888238526; Sun, 30 Apr 2023 13:57:18 -0700 (PDT) Received: from eriador.lan (dzdqv0yyyyyyyyyyybcwt-3.rev.dnainternet.fi. [2001:14ba:a0db:1f00::8a5]) by smtp.gmail.com with ESMTPSA id x6-20020ac259c6000000b004db1a7e6decsm4332749lfn.205.2023.04.30.13.57.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 30 Apr 2023 13:57:18 -0700 (PDT) From: Dmitry Baryshkov To: Rob Clark , Sean Paul , Abhinav Kumar , Marijn Suijten Cc: Stephen Boyd , David Airlie , Daniel Vetter , Bjorn Andersson , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org Subject: [PATCH 9/9] drm/msm/dpu: use common helper for WB and SSPP QoS setup Date: Sun, 30 Apr 2023 23:57:10 +0300 Message-Id: <20230430205710.3188230-10-dmitry.baryshkov@linaro.org> X-Mailer: git-send-email 2.39.2 In-Reply-To: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> References: <20230430205710.3188230-1-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Rework SSPP and WB code to use common helper for programming QoS settings. Signed-off-by: Dmitry Baryshkov --- .../drm/msm/disp/dpu1/dpu_encoder_phys_wb.c | 4 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 31 ++----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 19 +---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 31 +++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 21 +++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c | 29 +------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h | 16 +--- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 84 +++++++------------ 8 files changed, 100 insertions(+), 135 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c index 120141f1e5c5..f879d006de21 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_wb.c @@ -102,7 +102,7 @@ static void dpu_encoder_phys_wb_set_qos_remap( static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc) { struct dpu_hw_wb *hw_wb; - struct dpu_hw_wb_qos_cfg qos_cfg; + struct dpu_hw_qos_cfg qos_cfg; const struct dpu_mdss_cfg *catalog; const struct dpu_qos_lut_tbl *qos_lut_tb; @@ -115,7 +115,7 @@ static void dpu_encoder_phys_wb_set_qos(struct dpu_encoder_phys *phys_enc) hw_wb = phys_enc->hw_wb; - memset(&qos_cfg, 0, sizeof(struct dpu_hw_wb_qos_cfg)); + memset(&qos_cfg, 0, sizeof(struct dpu_hw_qos_cfg)); qos_cfg.danger_safe_en = true; qos_cfg.danger_lut = catalog->perf->danger_lut_tbl[DPU_QOS_LUT_USAGE_NRT]; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 2533c4629021..c35e9faf2460 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -541,30 +541,15 @@ static void dpu_hw_sspp_setup_solidfill(struct dpu_sw_pipe *pipe, u32 color) color); } -static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_sspp *ctx, - u32 danger_lut, - u32 safe_lut) +static void dpu_hw_sspp_setup_qos_lut(struct dpu_hw_sspp *ctx, + struct dpu_hw_qos_cfg *cfg) { - if (!ctx) - return; - - DPU_REG_WRITE(&ctx->hw, SSPP_DANGER_LUT, danger_lut); - DPU_REG_WRITE(&ctx->hw, SSPP_SAFE_LUT, safe_lut); -} - -static void dpu_hw_sspp_setup_creq_lut(struct dpu_hw_sspp *ctx, - u64 creq_lut) -{ - if (!ctx) + if (!ctx || !cfg) return; - if (ctx->cap && test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features)) { - DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_0, creq_lut); - DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT_1, - creq_lut >> 32); - } else { - DPU_REG_WRITE(&ctx->hw, SSPP_CREQ_LUT, creq_lut); - } + _dpu_hw_setup_qos_lut(&ctx->hw, SSPP_DANGER_LUT, + test_bit(DPU_SSPP_QOS_8LVL, &ctx->cap->features), + cfg); } static void dpu_hw_sspp_setup_qos_ctrl(struct dpu_hw_sspp *ctx, @@ -606,9 +591,7 @@ static void _setup_layer_ops(struct dpu_hw_sspp *c, c->ops.setup_pe = dpu_hw_sspp_setup_pe_config; if (test_bit(DPU_SSPP_QOS, &features)) { - c->ops.setup_danger_safe_lut = - dpu_hw_sspp_setup_danger_safe_lut; - c->ops.setup_creq_lut = dpu_hw_sspp_setup_creq_lut; + c->ops.setup_qos_lut = dpu_hw_sspp_setup_qos_lut; c->ops.setup_qos_ctrl = dpu_hw_sspp_setup_qos_ctrl; } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 4278c421b6ac..085f34bc6b88 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -254,25 +254,14 @@ struct dpu_hw_sspp_ops { void (*setup_sharpening)(struct dpu_hw_sspp *ctx, struct dpu_hw_sharp_cfg *cfg); - /** - * setup_danger_safe_lut - setup danger safe LUTs - * @ctx: Pointer to pipe context - * @danger_lut: LUT for generate danger level based on fill level - * @safe_lut: LUT for generate safe level based on fill level - * - */ - void (*setup_danger_safe_lut)(struct dpu_hw_sspp *ctx, - u32 danger_lut, - u32 safe_lut); /** - * setup_creq_lut - setup CREQ LUT + * setup_qos_lut - setup QoS LUTs * @ctx: Pointer to pipe context - * @creq_lut: LUT for generate creq level based on fill level - * + * @cfg: LUT configuration */ - void (*setup_creq_lut)(struct dpu_hw_sspp *ctx, - u64 creq_lut); + void (*setup_qos_lut)(struct dpu_hw_sspp *ctx, + struct dpu_hw_qos_cfg *cfg); /** * setup_qos_ctrl - setup QoS control diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c index 95d20b9a3f2f..9d2273fd2fed 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c @@ -73,6 +73,19 @@ static u32 dpu_hw_util_log_mask = DPU_DBG_MASK_NONE; #define QSEED3LITE_SEP_LUT_SIZE \ (QSEED3LITE_LUT_SIZE * QSEED3LITE_SEPARABLE_LUTS * sizeof(u32)) +/* QOS_LUT */ +#define QOS_DANGER_LUT 0x00 +#define QOS_SAFE_LUT 0x04 +#define QOS_CREQ_LUT 0x08 +#define QOS_QOS_CTRL 0x0C +#define QOS_CREQ_LUT_0 0x14 +#define QOS_CREQ_LUT_1 0x18 + +/* QOS_QOS_CTRL */ +#define QOS_QOS_CTRL_DANGER_SAFE_EN BIT(0) +#define QOS_QOS_CTRL_DANGER_VBLANK_MASK GENMASK(5, 4) +#define QOS_QOS_CTRL_VBLANK_EN BIT(16) +#define QOS_QOS_CTRL_CREQ_VBLANK_MASK GENMASK(21, 20) void dpu_reg_write(struct dpu_hw_blk_reg_map *c, u32 reg_off, @@ -450,6 +463,24 @@ u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, return 0; } +void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset, + bool qos_8lvl, + const struct dpu_hw_qos_cfg *cfg) +{ + DPU_REG_WRITE(c, offset + QOS_DANGER_LUT, cfg->danger_lut); + DPU_REG_WRITE(c, offset + QOS_SAFE_LUT, cfg->safe_lut); + + if (qos_8lvl) { + DPU_REG_WRITE(c, offset + QOS_CREQ_LUT_0, cfg->creq_lut); + DPU_REG_WRITE(c, offset + QOS_CREQ_LUT_1, cfg->creq_lut >> 32); + } else { + DPU_REG_WRITE(c, offset + QOS_CREQ_LUT, cfg->creq_lut); + } + + DPU_REG_WRITE(c, offset + QOS_QOS_CTRL, + cfg->danger_safe_en ? QOS_QOS_CTRL_DANGER_SAFE_EN : 0); +} + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, u32 misr_ctrl_offset, bool enable, u32 frame_count) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h index dc6e3b795aef..1f6079f47071 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h @@ -305,6 +305,23 @@ struct dpu_drm_scaler_v2 { struct dpu_drm_de_v1 de; }; +/** + * struct dpu_hw_qos_cfg: pipe QoS configuration + * @danger_lut: LUT for generate danger level based on fill level + * @safe_lut: LUT for generate safe level based on fill level + * @creq_lut: LUT for generate creq level based on fill level + * @creq_vblank: creq value generated to vbif during vertical blanking + * @danger_vblank: danger value generated during vertical blanking + * @vblank_en: enable creq_vblank and danger_vblank during vblank + * @danger_safe_en: enable danger safe generation + */ +struct dpu_hw_qos_cfg { + u32 danger_lut; + u32 safe_lut; + u64 creq_lut; + bool danger_safe_en; +}; + u32 *dpu_hw_util_get_log_mask_ptr(void); void dpu_reg_write(struct dpu_hw_blk_reg_map *c, @@ -336,6 +353,10 @@ void dpu_setup_cdp(struct dpu_hw_blk_reg_map *c, u32 offset, u64 _dpu_hw_get_qos_lut(const struct dpu_qos_lut_tbl *tbl, u32 total_fl); +void _dpu_hw_setup_qos_lut(struct dpu_hw_blk_reg_map *c, u32 offset, + bool qos_8lvl, + const struct dpu_hw_qos_cfg *cfg); + void dpu_hw_setup_misr(struct dpu_hw_blk_reg_map *c, u32 misr_ctrl_offset, bool enable, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c index a6de4b82a188..dcffd6cc47fc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c @@ -49,9 +49,6 @@ #define WB_OUT_IMAGE_SIZE 0x2C0 #define WB_OUT_XY 0x2C4 -/* WB_QOS_CTRL */ -#define WB_QOS_CTRL_DANGER_SAFE_EN BIT(0) - static void dpu_hw_wb_setup_outaddress(struct dpu_hw_wb *ctx, struct dpu_hw_wb_cfg *data) { @@ -135,32 +132,14 @@ static void dpu_hw_wb_roi(struct dpu_hw_wb *ctx, struct dpu_hw_wb_cfg *wb) } static void dpu_hw_wb_setup_qos_lut(struct dpu_hw_wb *ctx, - struct dpu_hw_wb_qos_cfg *cfg) + struct dpu_hw_qos_cfg *cfg) { - struct dpu_hw_blk_reg_map *c = &ctx->hw; - u32 qos_ctrl = 0; - if (!ctx || !cfg) return; - DPU_REG_WRITE(c, WB_DANGER_LUT, cfg->danger_lut); - DPU_REG_WRITE(c, WB_SAFE_LUT, cfg->safe_lut); - - /* - * for chipsets not using DPU_WB_QOS_8LVL but still using DPU - * driver such as msm8998, the reset value of WB_CREQ_LUT is - * sufficient for writeback to work. SW doesn't need to explicitly - * program a value. - */ - if (ctx->caps && test_bit(DPU_WB_QOS_8LVL, &ctx->caps->features)) { - DPU_REG_WRITE(c, WB_CREQ_LUT_0, cfg->creq_lut); - DPU_REG_WRITE(c, WB_CREQ_LUT_1, cfg->creq_lut >> 32); - } - - if (cfg->danger_safe_en) - qos_ctrl |= WB_QOS_CTRL_DANGER_SAFE_EN; - - DPU_REG_WRITE(c, WB_QOS_CTRL, qos_ctrl); + _dpu_hw_setup_qos_lut(&ctx->hw, WB_DANGER_LUT, + test_bit(DPU_WB_QOS_8LVL, &ctx->caps->features), + cfg); } static void dpu_hw_wb_setup_cdp(struct dpu_hw_wb *ctx, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h index ab3541856258..c7f792eeb55c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h @@ -21,20 +21,6 @@ struct dpu_hw_wb_cfg { struct drm_rect crop; }; -/** - * struct dpu_hw_wb_qos_cfg : Writeback pipe QoS configuration - * @danger_lut: LUT for generate danger level based on fill level - * @safe_lut: LUT for generate safe level based on fill level - * @creq_lut: LUT for generate creq level based on fill level - * @danger_safe_en: enable danger safe generation - */ -struct dpu_hw_wb_qos_cfg { - u32 danger_lut; - u32 safe_lut; - u64 creq_lut; - bool danger_safe_en; -}; - /** * * struct dpu_hw_wb_ops : Interface to the wb hw driver functions @@ -56,7 +42,7 @@ struct dpu_hw_wb_ops { struct dpu_hw_wb_cfg *wb); void (*setup_qos_lut)(struct dpu_hw_wb *ctx, - struct dpu_hw_wb_qos_cfg *cfg); + struct dpu_hw_qos_cfg *cfg); void (*setup_cdp)(struct dpu_hw_wb *ctx, const struct dpu_format *fmt, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 75fb2d2796b5..f91b433d5be6 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -190,12 +190,14 @@ static u64 _dpu_plane_calc_clk(const struct drm_display_mode *mode, * _dpu_plane_calc_fill_level - calculate fill level of the given source format * @plane: Pointer to drm plane * @pipe: Pointer to software pipe + * @lut_usage LUT usecase * @fmt: Pointer to source buffer format * @src_width: width of source buffer * Return: fill level corresponding to the source buffer/format or 0 if error */ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, struct dpu_sw_pipe *pipe, + enum dpu_qos_lut_usage lut_usage, const struct dpu_format *fmt, u32 src_width) { struct dpu_plane *pdpu; @@ -207,6 +209,9 @@ static int _dpu_plane_calc_fill_level(struct drm_plane *plane, return 0; } + if (lut_usage == DPU_QOS_LUT_USAGE_NRT) + return 0; + pdpu = to_dpu_plane(plane); fixed_buff_size = pdpu->catalog->caps->pixel_ram_size; @@ -252,83 +257,58 @@ static void _dpu_plane_set_qos_lut(struct drm_plane *plane, const struct dpu_format *fmt, struct dpu_sw_pipe_cfg *pipe_cfg) { struct dpu_plane *pdpu = to_dpu_plane(plane); - u64 qos_lut; - u32 total_fl = 0, lut_usage; + struct dpu_hw_qos_cfg cfg; + u32 total_fl, lut_usage; if (!pdpu->is_rt_pipe) { lut_usage = DPU_QOS_LUT_USAGE_NRT; } else { - total_fl = _dpu_plane_calc_fill_level(plane, pipe, fmt, - drm_rect_width(&pipe_cfg->src_rect)); - if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) lut_usage = DPU_QOS_LUT_USAGE_LINEAR; else lut_usage = DPU_QOS_LUT_USAGE_MACROTILE; } - qos_lut = _dpu_hw_get_qos_lut( - &pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); + total_fl = _dpu_plane_calc_fill_level(plane, pipe, lut_usage, fmt, + drm_rect_width(&pipe_cfg->src_rect)); + + cfg.creq_lut = _dpu_hw_get_qos_lut(&pdpu->catalog->perf->qos_lut_tbl[lut_usage], total_fl); + cfg.danger_lut = pdpu->catalog->perf->danger_lut_tbl[lut_usage]; + cfg.safe_lut = pdpu->catalog->perf->safe_lut_tbl[lut_usage]; + + if (pipe->sspp->idx != SSPP_CURSOR0 && + pipe->sspp->idx != SSPP_CURSOR1 && + !pdpu->is_rt_pipe) + cfg.danger_safe_en = true; + + DPU_DEBUG_PLANE(pdpu, "pnum:%d ds:%d is_rt:%d\n", + pdpu->pipe - SSPP_VIG0, + cfg.danger_safe_en, + pdpu->is_rt_pipe); trace_dpu_perf_set_qos_luts(pipe->sspp->idx - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0, - pdpu->is_rt_pipe, total_fl, qos_lut, lut_usage); + pdpu->is_rt_pipe, total_fl, cfg.creq_lut, lut_usage); DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s rt:%d fl:%u lut:0x%llx\n", pdpu->pipe - SSPP_VIG0, fmt ? (char *)&fmt->base.pixel_format : NULL, - pdpu->is_rt_pipe, total_fl, qos_lut); - - pipe->sspp->ops.setup_creq_lut(pipe->sspp, qos_lut); -} - -/** - * _dpu_plane_set_danger_lut - set danger/safe LUT of the given plane - * @plane: Pointer to drm plane - * @pipe: Pointer to software pipe - * @fmt: Pointer to source buffer format - */ -static void _dpu_plane_set_danger_lut(struct drm_plane *plane, - struct dpu_sw_pipe *pipe, - const struct dpu_format *fmt) -{ - struct dpu_plane *pdpu = to_dpu_plane(plane); - u32 danger_lut, safe_lut; - - if (!pdpu->is_rt_pipe) { - danger_lut = pdpu->catalog->perf->danger_lut_tbl - [DPU_QOS_LUT_USAGE_NRT]; - safe_lut = pdpu->catalog->perf->safe_lut_tbl - [DPU_QOS_LUT_USAGE_NRT]; - } else { - if (fmt && DPU_FORMAT_IS_LINEAR(fmt)) { - danger_lut = pdpu->catalog->perf->danger_lut_tbl - [DPU_QOS_LUT_USAGE_LINEAR]; - safe_lut = pdpu->catalog->perf->safe_lut_tbl - [DPU_QOS_LUT_USAGE_LINEAR]; - } else { - danger_lut = pdpu->catalog->perf->danger_lut_tbl - [DPU_QOS_LUT_USAGE_MACROTILE]; - safe_lut = pdpu->catalog->perf->safe_lut_tbl - [DPU_QOS_LUT_USAGE_MACROTILE]; - } - } + pdpu->is_rt_pipe, total_fl, cfg.creq_lut); trace_dpu_perf_set_danger_luts(pdpu->pipe - SSPP_VIG0, (fmt) ? fmt->base.pixel_format : 0, (fmt) ? fmt->fetch_mode : 0, - danger_lut, - safe_lut); + cfg.danger_lut, + cfg.safe_lut); DPU_DEBUG_PLANE(pdpu, "pnum:%d fmt: %4.4s mode:%d luts[0x%x, 0x%x]\n", pdpu->pipe - SSPP_VIG0, fmt ? (char *)&fmt->base.pixel_format : NULL, fmt ? fmt->fetch_mode : -1, - danger_lut, - safe_lut); + cfg.danger_lut, + cfg.safe_lut); - pipe->sspp->ops.setup_danger_safe_lut(pipe->sspp, - danger_lut, safe_lut); + pipe->sspp->ops.setup_qos_lut(pipe->sspp, &cfg); } /** @@ -1084,10 +1064,6 @@ static void dpu_plane_sspp_update_pipe(struct drm_plane *plane, } _dpu_plane_set_qos_lut(plane, pipe, fmt, pipe_cfg); - _dpu_plane_set_danger_lut(plane, pipe, fmt); - _dpu_plane_set_qos_ctrl(plane, pipe, - pipe->sspp->idx != SSPP_CURSOR0 && - pipe->sspp->idx != SSPP_CURSOR1); if (pipe->sspp->idx == SSPP_CURSOR0 || pipe->sspp->idx == SSPP_CURSOR1)