From patchwork Tue Jun 4 13:14:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165768 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5842134ili; Tue, 4 Jun 2019 06:17:27 -0700 (PDT) X-Google-Smtp-Source: APXvYqw2doXmkcU6peFDX8mtaVs5N5f3RqBQ60a8dPMoKZ2kuodd8vN36PRemNvKQewRSuGrHgUa X-Received: by 2002:a63:445b:: with SMTP id t27mr12307496pgk.56.1559654247712; Tue, 04 Jun 2019 06:17:27 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654247; cv=none; d=google.com; s=arc-20160816; b=Pu0VeGO/zRZqHwc5NdfVJkwQqv3DUr1Jfm7rwzJX28hGtd7hCZO/bLoopD9B1bsYm4 OQB4iZjCTSleoKL1I82MbK9CvFMO5bfyxxQxdTaES5cej+dJu9Yf6reTOEYIZPpEeL+/ nzU1E7qrU6dQStEagaarLAlSaSEzvl7hh7BxqpPV8Ii2QwNtvKpCalhNM0x5bFFJsk1V jbth9UMLzaqWEUHiUM3sS5opHKIm5fdBqEtarcN+QRTrj23GAsiSYgxdUuvJx549MkiQ 9MgzjXzBJFCJGh9KdAFlued6WBMe2bqHMD+5UXS2xGxuLNjIS8skHN9QTURuWa0VSb7M cQdQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=e/EjQX9i/htBJzCijizT4bdAgxYEeQVCmIjqYfmHN98=; b=zm3t5HPECEebWWC1z1KlBaQzNmTJ9MP5/EpRXWLD1q7VeBegEXEeSJujwZ22YJc7SC 5fRhJWjYI897p5Wc9lrP1bghXNFv9C/oUlpscuIdDn16BwuTWU05wPcIS934jB/431ZH UD1nRj1AdiSunX8nesiIH7XTQsDuPQ3keTAe7TAKhS0zzYmzZG0HwW+RZHbIqMf/sRoq a8a9eT9OE7ZKXeFRbDiUCuaLcEbk1+u4MMgAwCWLNhUow82AJMNv5eYjqkM+TiS8lP9U 06NCGoWv5ZqW5+hDuVokPMAtK2VCk0XwTWfRAaI1DFzXtJ/93QzWcq5nGxCqFVnTB57C X58Q== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="A/b5AGKl"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id m9si22125445pjv.68.2019.06.04.06.17.27; Tue, 04 Jun 2019 06:17:27 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b="A/b5AGKl"; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727491AbfFDNR1 (ORCPT + 8 others); Tue, 4 Jun 2019 09:17:27 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:50242 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727480AbfFDNR0 (ORCPT ); Tue, 4 Jun 2019 09:17:26 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DH7VO082207; Tue, 4 Jun 2019 08:17:07 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654227; bh=e/EjQX9i/htBJzCijizT4bdAgxYEeQVCmIjqYfmHN98=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=A/b5AGKll5b1g3p8YiRGH+nJa/6KNgdYLR+OlRQrOvNzuc6vOJtURGSBfW3vwnG3F d9ZIht57qyQqXJMjurt0mTkAb0/JmrxFNNaN75pKycq+VADfJmQfN9tBPgaSZNoRD4 1nHjUmh2OGtlHs7C4htJEroOPxhCVyZabYLAC4AM= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DH7f6042336 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:17:07 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:17:07 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:17:07 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGK098972; Tue, 4 Jun 2019 08:17:02 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I Subject: [RFC PATCH 04/30] dt-bindings: PCI: cadence: Update EP DT bindings with TI specific compatible Date: Tue, 4 Jun 2019 18:44:50 +0530 Message-ID: <20190604131516.13596-5-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Update DT bindings for Cadence PCIe Endpoint controller with TI specific compatible. Signed-off-by: Kishon Vijay Abraham I --- Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt index 4a0475e2ba7e..536aa4bf6ce3 100644 --- a/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt +++ b/Documentation/devicetree/bindings/pci/cdns,cdns-pcie-ep.txt @@ -2,6 +2,7 @@ Required properties: - compatible: Should contain "cdns,cdns-pcie-ep" to identify the IP used. + Should contain "ti,j721e-cdns-pcie-ep" for TI platforms. - reg: Should contain the controller register base address and AXI interface region base address respectively. - reg-names: Must be "reg" and "mem" respectively. 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This is useful to get an aligned register address when a device allows only word access and doesn't allow half word or byte access. Signed-off-by: Kishon Vijay Abraham I --- include/linux/kernel.h | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/include/linux/kernel.h b/include/linux/kernel.h index 74b1ee9027f5..f5be987f1f95 100644 --- a/include/linux/kernel.h +++ b/include/linux/kernel.h @@ -34,6 +34,7 @@ #define ALIGN_DOWN(x, a) __ALIGN_KERNEL((x) - ((a) - 1), (a)) #define __ALIGN_MASK(x, mask) __ALIGN_KERNEL_MASK((x), (mask)) #define PTR_ALIGN(p, a) ((typeof(p))ALIGN((unsigned long)(p), (a))) +#define PTR_ALIGN_DOWN(p, a) ((typeof(p))ALIGN_DOWN((unsigned long)(p), (a))) #define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0) /* generic data direction definitions */ From patchwork Tue Jun 4 13:14:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165770 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5842694ili; Tue, 4 Jun 2019 06:17:50 -0700 (PDT) X-Google-Smtp-Source: APXvYqzUtJn+tjT1wiYmRNa/CH0Ofa08oWeQZFKA2cRnvsT4cbsYQjzkRScLC9MKFnlPrFaK/Sbg X-Received: by 2002:a17:902:aa8a:: with SMTP id d10mr879023plr.159.1559654270316; Tue, 04 Jun 2019 06:17:50 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654270; cv=none; d=google.com; s=arc-20160816; b=Iklzgu24k2JLDCEqe7XCYsnkRAjP/OyaZIvgVCM+BQ8+yqAdWBhL0R02X6WWzN6GdT A1dRC4l4OAqjRKvGzSbL1GWiP084nmXOlHxQdZ7HJFkO0aP7UPURC+GA6ke1cXYFeTWB v4NAbt4mDdVNeMqcoYyNBaKDRb1HRuF8GIXE5BB71DfMgk22aGSRmCvR6QcOkTd8weer sjbMxP1i20I9NgSax+5sKuzgFumbDS4OooAv8r9egGFRzyg75apLoiPkjMM/9A0Ydl6o ByfmRegdf+XV5a1cLQn61k/Rk+5FKrXGEGU710eRYCCJPMMmRUVP5y6e2nTK7dE2xaQn SZsQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=6qczyjN8xDIHWDWNCCCPX1hAyvFx0bkZdv1sjzIpsVk=; b=q9R/rw4nZI6T7mbZjmswc7AUQ68AN31+arglJ4Mi99tlitWKSEvXzgvAWrNYILsWH/ 1bxVN5tr9Q06qQeB9jAvQNtvekTTZrSa1+oBy5er8u6T0yKTxIHEtHyzjo/W/fANVuQn CZm+EQOnMGxW2l1SgdHFuhj6iL6Shd6s89/EMQgcGA5t7qfEBpK6mriMRI9zH0Pm1rl8 CEgm4IVq3NrR0fdWwyUaA3Mg3W/8TrMPV+hamLgXU07KEvt2nLGSrPC5/aEwg133Rv+6 0HFdMWhZhmaoFnvCTyKrj5ymf7MU9sPkZBHcPa0tpzGt1s2GU6KopWKhiKWkM/PGcu2l 0dPA== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qCmO322i; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id bh2si24269828plb.430.2019.06.04.06.17.48; Tue, 04 Jun 2019 06:17:50 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=qCmO322i; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727480AbfFDNRs (ORCPT + 8 others); Tue, 4 Jun 2019 09:17:48 -0400 Received: from fllv0016.ext.ti.com ([198.47.19.142]:50328 "EHLO fllv0016.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727149AbfFDNRr (ORCPT ); Tue, 4 Jun 2019 09:17:47 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DHI06082244; Tue, 4 Jun 2019 08:17:18 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654238; bh=6qczyjN8xDIHWDWNCCCPX1hAyvFx0bkZdv1sjzIpsVk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=qCmO322is04juakmYwOIY/3vblkjd2nBtFEsDOJ9gUoxnzpAnkB/+P3cJsueJdPzB uVxeSG/PZ1hhgjz2vcJkNEs+BocHvvtOo/CuqyuXzWcWjDHg9XLbEM3UQFsxh7eP79 O/t3m1hhG2x+Fg9S4Hu6pVaViSUrFa9g+Sbe6teU= Received: from DFLE107.ent.ti.com (dfle107.ent.ti.com [10.64.6.28]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DHIhQ042574 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:17:18 -0500 Received: from DFLE104.ent.ti.com (10.64.6.25) by DFLE107.ent.ti.com (10.64.6.28) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:17:18 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:17:18 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGM098972; Tue, 4 Jun 2019 08:17:13 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I Subject: [RFC PATCH 06/30] PCI: cadence: Add support to use custom read and write accessors Date: Tue, 4 Jun 2019 18:44:52 +0530 Message-ID: <20190604131516.13596-7-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support to use custom read and write accessors. Platforms that doesn't support half word or byte access or any other constraint while accessing registers can use this feature to populate custom read and write accessors. These custom accessors are used for both standard register access and configuration space register access. This is in preparation for adding PCIe support in TI's J721E SoC which uses Cadence PCIe core. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/pcie-cadence-ep.c | 15 +++ drivers/pci/controller/pcie-cadence-host.c | 20 +++- drivers/pci/controller/pcie-cadence.h | 105 +++++++++++++++++++-- 3 files changed, 131 insertions(+), 9 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c index def7820cb824..64ab5c53afb1 100644 --- a/drivers/pci/controller/pcie-cadence-ep.c +++ b/drivers/pci/controller/pcie-cadence-ep.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -434,6 +435,8 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) { struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; + const struct cdns_pcie_ep_data *data; + const struct of_device_id *match; struct cdns_pcie_ep *ep; struct cdns_pcie *pcie; struct pci_epc *epc; @@ -441,6 +444,10 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) int ret; int phy_count; + match = of_match_device(of_match_ptr(cdns_pcie_ep_of_match), dev); + if (!match) + return -EINVAL; + ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL); if (!ep) return -ENOMEM; @@ -448,6 +455,14 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) pcie = &ep->pcie; pcie->is_rc = false; + data = (struct cdns_pcie_ep_data *)match->data; + if (data) { + if (data->read) + pcie->read = data->read; + if (data->write) + pcie->write = data->write; + } + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg"); pcie->reg_base = devm_ioremap_resource(dev, res); if (IS_ERR(pcie->reg_base)) { diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c index 97e251090b4f..75cf3c312ed2 100644 --- a/drivers/pci/controller/pcie-cadence-host.c +++ b/drivers/pci/controller/pcie-cadence-host.c @@ -5,6 +5,7 @@ #include #include +#include #include #include #include @@ -235,8 +236,11 @@ static int cdns_pcie_host_init(struct device *dev, static int cdns_pcie_host_probe(struct platform_device *pdev) { + struct pci_ops *ops = &cdns_pcie_host_ops; + const struct cdns_pcie_host_data *data; struct device *dev = &pdev->dev; struct device_node *np = dev->of_node; + const struct of_device_id *match; struct pci_host_bridge *bridge; struct list_head resources; struct cdns_pcie_rc *rc; @@ -245,6 +249,10 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) int ret; int phy_count; + match = of_match_device(of_match_ptr(cdns_pcie_host_of_match), dev); + if (!match) + return -EINVAL; + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); if (!bridge) return -ENOMEM; @@ -255,6 +263,16 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) pcie = &rc->pcie; pcie->is_rc = true; + data = (struct cdns_pcie_host_data *)match->data; + if (data) { + if (data->read) + pcie->read = data->read; + if (data->write) + pcie->write = data->write; + if (data->ops) + ops = data->ops; + } + rc->max_regions = 32; of_property_read_u32(np, "cdns,max-outbound-regions", &rc->max_regions); @@ -310,7 +328,7 @@ static int cdns_pcie_host_probe(struct platform_device *pdev) list_splice_init(&resources, &bridge->windows); bridge->dev.parent = dev; bridge->busnr = pcie->bus; - bridge->ops = &cdns_pcie_host_ops; + bridge->ops = ops; bridge->map_irq = of_irq_parse_and_map_pci; bridge->swizzle_irq = pci_common_swizzle; diff --git a/drivers/pci/controller/pcie-cadence.h b/drivers/pci/controller/pcie-cadence.h index ae6bf2a2b3d3..0134c1b1ad65 100644 --- a/drivers/pci/controller/pcie-cadence.h +++ b/drivers/pci/controller/pcie-cadence.h @@ -236,26 +236,65 @@ struct cdns_pcie { int phy_count; struct phy **phy; struct device_link **link; + u32 (*read)(void __iomem *addr, int size); + void (*write)(void __iomem *addr, int size, u32 value); +}; + +struct cdns_pcie_host_data { + struct pci_ops *ops; + u32 (*read)(void __iomem *addr, int size); + void (*write)(void __iomem *addr, int size, u32 value); +}; + +struct cdns_pcie_ep_data { + u32 (*read)(void __iomem *addr, int size); + void (*write)(void __iomem *addr, int size, u32 value); }; /* Register access */ static inline void cdns_pcie_writeb(struct cdns_pcie *pcie, u32 reg, u8 value) { + void __iomem *addr = pcie->reg_base + reg; + + if (pcie->write) { + pcie->write(addr, 0x1, value); + return; + } + writeb(value, pcie->reg_base + reg); } static inline void cdns_pcie_writew(struct cdns_pcie *pcie, u32 reg, u16 value) { + void __iomem *addr = pcie->reg_base + reg; + + if (pcie->write) { + pcie->write(addr, 0x2, value); + return; + } + writew(value, pcie->reg_base + reg); } static inline void cdns_pcie_writel(struct cdns_pcie *pcie, u32 reg, u32 value) { + void __iomem *addr = pcie->reg_base + reg; + + if (pcie->write) { + pcie->write(addr, 0x4, value); + return; + } + writel(value, pcie->reg_base + reg); } static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) { + void __iomem *addr = pcie->reg_base + reg; + + if (pcie->read) + return pcie->read(addr, 0x4); + return readl(pcie->reg_base + reg); } @@ -263,47 +302,97 @@ static inline u32 cdns_pcie_readl(struct cdns_pcie *pcie, u32 reg) static inline void cdns_pcie_rp_writeb(struct cdns_pcie *pcie, u32 reg, u8 value) { - writeb(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + if (pcie->write) { + pcie->write(addr, 0x1, value); + return; + } + + writeb(value, addr); } static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, u32 reg, u16 value) { - writew(value, pcie->reg_base + CDNS_PCIE_RP_BASE + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; + + if (pcie->write) { + pcie->write(addr, 0x2, value); + return; + } + + writew(value, addr); } /* Endpoint Function register access */ static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, u32 reg, u8 value) { - writeb(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + if (pcie->write) { + pcie->write(addr, 0x1, value); + return; + } + + writeb(value, addr); } static inline void cdns_pcie_ep_fn_writew(struct cdns_pcie *pcie, u8 fn, u32 reg, u16 value) { - writew(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + if (pcie->write) { + pcie->write(addr, 0x2, value); + return; + } + + writew(value, addr); } static inline void cdns_pcie_ep_fn_writel(struct cdns_pcie *pcie, u8 fn, u32 reg, u32 value) { - writel(value, pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + if (pcie->write) { + pcie->write(addr, 0x4, value); + return; + } + + writel(value, addr); } static inline u8 cdns_pcie_ep_fn_readb(struct cdns_pcie *pcie, u8 fn, u32 reg) { - return readb(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + if (pcie->read) + return pcie->read(addr, 0x1); + + return readb(addr); } static inline u16 cdns_pcie_ep_fn_readw(struct cdns_pcie *pcie, u8 fn, u32 reg) { - return readw(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + if (pcie->read) + return pcie->read(addr, 0x2); + + return readw(addr); } static inline u32 cdns_pcie_ep_fn_readl(struct cdns_pcie *pcie, u8 fn, u32 reg) { - return readl(pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg); + void __iomem *addr = pcie->reg_base + CDNS_PCIE_EP_FUNC_BASE(fn) + reg; + + if (pcie->read) + return pcie->read(addr, 0x4); + + return readl(addr); } void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn, From patchwork Tue Jun 4 13:14:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165774 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5843045ili; Tue, 4 Jun 2019 06:18:07 -0700 (PDT) X-Google-Smtp-Source: APXvYqw9Ml5rRjcTaJbS4/iAkcPODYe3EGfTcphc6FDjmxbEWcKEgTfwKXkob+JVhO8ZEAGygPyh X-Received: by 2002:a63:2a06:: with SMTP id q6mr34979775pgq.290.1559654287519; Tue, 04 Jun 2019 06:18:07 -0700 (PDT) ARC-Seal: i=1; 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[209.132.180.67]) by mx.google.com with ESMTP id w2si7942257pgr.396.2019.06.04.06.18.07; Tue, 04 Jun 2019 06:18:07 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=R+8zqLax; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727671AbfFDNSG (ORCPT + 8 others); Tue, 4 Jun 2019 09:18:06 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:54960 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727654AbfFDNSF (ORCPT ); Tue, 4 Jun 2019 09:18:05 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DHqo6028086; Tue, 4 Jun 2019 08:17:52 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654272; bh=tBDM4Tz2keIVpXtq26vbu3y4+Vw3eoGfX9HaWTYVoeQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=R+8zqLaxd2c02V5uk6F4Sppd2D+1gsFYEkhM62sv+mxRho62Gx4HsxMmbgDSTsIG7 2KQHA8NCWHr299PML9hkzkXL402hArTl9rKprSd4RFTVcHr5T6xwtloib6PitOt4U3 v1gZhJGxWsVfEk/FMed58unQBaGz0DF2Sx8860bM= Received: from DLEE103.ent.ti.com (dlee103.ent.ti.com [157.170.170.33]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DHqGl052946 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:17:52 -0500 Received: from DLEE112.ent.ti.com (157.170.170.23) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:17:51 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:17:51 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGS098972; Tue, 4 Jun 2019 08:17:46 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I Subject: [RFC PATCH 12/30] PCI: cadence: Make "mem" an optional memory resource Date: Tue, 4 Jun 2019 18:44:58 +0530 Message-ID: <20190604131516.13596-13-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Cadence driver uses "mem" memory resource to obtain the offset of configuration space address region, memory space address region and message space address region. The obtained offset is used to program the Address Translation Unit (ATU). However certain platforms like TI's J721E SoC require the absolute address to be programmed in the and not just the offset. Make "mem" an optional memory resource and use it only for platforms that populate it. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/pcie-cadence-ep.c | 6 ++---- drivers/pci/controller/pcie-cadence-host.c | 5 +++-- drivers/pci/controller/pcie-cadence.c | 6 ++++-- 3 files changed, 9 insertions(+), 8 deletions(-) -- 2.17.1 diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c index 825a515821c3..23aa5aba1c86 100644 --- a/drivers/pci/controller/pcie-cadence-ep.c +++ b/drivers/pci/controller/pcie-cadence-ep.c @@ -489,10 +489,8 @@ static int cdns_pcie_ep_probe(struct platform_device *pdev) } res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem"); - if (!res) { - dev_err(dev, "missing \"mem\"\n"); - return -EINVAL; - } + if (!res) + dev_dbg(dev, "missing \"mem\"\n"); pcie->mem_res = res; ret = of_property_read_u32(np, "cdns,max-outbound-regions", diff --git a/drivers/pci/controller/pcie-cadence-host.c b/drivers/pci/controller/pcie-cadence-host.c index 8b3b9827a8d6..14a54f6a11de 100644 --- a/drivers/pci/controller/pcie-cadence-host.c +++ b/drivers/pci/controller/pcie-cadence-host.c @@ -188,9 +188,9 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) struct device *dev = rc->dev; struct device_node *np = dev->of_node; struct of_pci_range_parser parser; + u64 cpu_addr = cfg_res->start; struct of_pci_range range; u32 addr0, addr1, desc1; - u64 cpu_addr; int r, err; /* @@ -203,7 +203,8 @@ static int cdns_pcie_host_init_address_translation(struct cdns_pcie_rc *rc) cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_PCI_ADDR1(0), addr1); cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(0), desc1); - cpu_addr = cfg_res->start - mem_res->start; + if (mem_res) + cpu_addr -= mem_res->start; addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(12) | (lower_32_bits(cpu_addr) & GENMASK(31, 8)); addr1 = upper_32_bits(cpu_addr); diff --git a/drivers/pci/controller/pcie-cadence.c b/drivers/pci/controller/pcie-cadence.c index 5ac42b19bb63..86282e9a26f7 100644 --- a/drivers/pci/controller/pcie-cadence.c +++ b/drivers/pci/controller/pcie-cadence.c @@ -154,7 +154,8 @@ void cdns_pcie_set_outbound_region(struct cdns_pcie *pcie, u8 fn, cdns_pcie_writel(pcie, CDNS_PCIE_AT_OB_REGION_DESC1(r), desc1); /* Set the CPU address */ - cpu_addr -= pcie->mem_res->start; + if (pcie->mem_res) + cpu_addr -= pcie->mem_res->start; addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(nbits) | (lower_32_bits(cpu_addr) & GENMASK(31, 8)); addr1 = upper_32_bits(cpu_addr); @@ -181,7 +182,8 @@ void cdns_pcie_set_outbound_region_for_normal_msg(struct cdns_pcie *pcie, u8 fn, } /* Set the CPU address */ - cpu_addr -= pcie->mem_res->start; + if (pcie->mem_res) + cpu_addr -= pcie->mem_res->start; addr0 = CDNS_PCIE_AT_OB_REGION_CPU_ADDR0_NBITS(17) | (lower_32_bits(cpu_addr) & GENMASK(31, 8)); addr1 = upper_32_bits(cpu_addr); From patchwork Tue Jun 4 13:15:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165781 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5844223ili; Tue, 4 Jun 2019 06:19:01 -0700 (PDT) X-Google-Smtp-Source: APXvYqzHONsGxsp563acCVegiznKMxB3iRrryS6DrbmP3k3fWs9+rQ278jdRZNAbQxhv8SO8wUPd X-Received: by 2002:a17:902:b696:: with SMTP id c22mr35235239pls.119.1559654341843; Tue, 04 Jun 2019 06:19:01 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654341; cv=none; d=google.com; s=arc-20160816; b=ypHuOLmsG5/Lxz8brnNnvP40zNH1ywl59vTtqVO1HeIhdkfvW2KLy2ETLjvdD/me6H PTVa/3uMD/FTsaU3gpwjWIsD5F5k5ucamVjoZByptnPQsZ3clAWUAnTyjaQjiK6/dGK2 ht6CZAQFm5kP+LrMGkYerP4roOT/RrYecMXrWGbADKnmvyw8JccMDTGpiYpnJZCQpLva oRzjbBvvWmynLc7on3+CBqzoqNBZ2I+SPciEmeTwafGHIerXm30MnIJHuHEbtoiFm0mn LgxGFcxTkzcjxOhjQoH5xYd5th/0EyhU3t7Uo92bbx8YurePxU+roVVhsULH0c9AO+nY Jxpg== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=hKZXGYlFN1fONABLyDc+vJLlvFIrfsKSse6yqM2h9dA=; b=ErAdgZ/6jPvSWMKnSSiPTo0xjH801Y+5SmgyZnIIv/hhqYGKj1itBBm3p9BBngLBb1 G/YYU9QdvEGT/1adVNK7rw5wIa83WC38HcTEFQK9Uqw5P7k4Dzx8LKGPPUBflrbbEJzg soLnN0VuE/NqDDj7Wg616O0ROOXwwAZZWZ6+3eUsZ/Gvyfsd2NnDuK7KHm/ndSPSox/3 +Ax6BSq/B3TixaeNXfPMhnkTrnKCtLJfwXR8I+s/wXna0msJg5wJ7Tp+ztAJX1tvO7PD 8lygV/L+fb77BkGF++0XPr7Z0IJWttKVHyRdN2ngqIqnAgK0vaOwAyZmrUAlvGc4/FxN VnNw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mjI62sqN; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y17si23614882pfl.172.2019.06.04.06.19.01; Tue, 04 Jun 2019 06:19:01 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=mjI62sqN; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727321AbfFDNTA (ORCPT + 8 others); Tue, 4 Jun 2019 09:19:00 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:55084 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727379AbfFDNS7 (ORCPT ); Tue, 4 Jun 2019 09:18:59 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DI4oQ028116; Tue, 4 Jun 2019 08:18:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654284; bh=hKZXGYlFN1fONABLyDc+vJLlvFIrfsKSse6yqM2h9dA=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=mjI62sqN49gPl6cFJoxDVZjHIy1szKlLsYrpK+qUK7OsUlDcarolB+Y1l0glDzmkw rCcYm5koW4668+uWqe9Ruauc15dW3/xB4kVJrO0rwJ0KOTxrRTlWPPsqqv1K4gcAIw KkBadx9sQrcMDAkmjT1R1LMMePS9cWYIjYNLXewo= Received: from DFLE115.ent.ti.com (dfle115.ent.ti.com [10.64.6.36]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DI3Y0043183 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:18:03 -0500 Received: from DFLE115.ent.ti.com (10.64.6.36) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:18:03 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE115.ent.ti.com (10.64.6.36) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:18:03 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGU098972; Tue, 4 Jun 2019 08:17:57 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I , Sekhar Nori Subject: [RFC PATCH 14/30] PCI: endpoint: Use notification chain mechanism to notify EPC events to EPF Date: Tue, 4 Jun 2019 18:45:00 +0530 Message-ID: <20190604131516.13596-15-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Use atomic_notifier_call_chain to notify EPC events like linkup to EPF instead of using linkup ops in EPF driver. This is in preparation for adding proper locking mechanism to EPF ops. This will also enable to add more events (in addition to linkup) in the future. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori --- drivers/pci/endpoint/functions/pci-epf-test.c | 13 ++++++++--- drivers/pci/endpoint/pci-epc-core.c | 9 ++------ drivers/pci/endpoint/pci-epf-core.c | 22 +------------------ include/linux/pci-epc.h | 8 +++++++ include/linux/pci-epf.h | 6 ++--- 5 files changed, 23 insertions(+), 35 deletions(-) -- 2.17.1 diff --git a/drivers/pci/endpoint/functions/pci-epf-test.c b/drivers/pci/endpoint/functions/pci-epf-test.c index 27806987e93b..6380641ccc7a 100644 --- a/drivers/pci/endpoint/functions/pci-epf-test.c +++ b/drivers/pci/endpoint/functions/pci-epf-test.c @@ -360,12 +360,16 @@ static void pci_epf_test_cmd_handler(struct work_struct *work) msecs_to_jiffies(1)); } -static void pci_epf_test_linkup(struct pci_epf *epf) +static int pci_epf_test_notifier(struct notifier_block *nb, unsigned long val, + void *data) { + struct pci_epf *epf = container_of(nb, struct pci_epf, nb); struct pci_epf_test *epf_test = epf_get_drvdata(epf); queue_delayed_work(kpcitest_workqueue, &epf_test->cmd_handler, msecs_to_jiffies(1)); + + return NOTIFY_OK; } static void pci_epf_test_unbind(struct pci_epf *epf) @@ -541,8 +545,12 @@ static int pci_epf_test_bind(struct pci_epf *epf) } } - if (!linkup_notifier) + if (linkup_notifier) { + epf->nb.notifier_call = pci_epf_test_notifier; + pci_epc_register_notifier(epc, &epf->nb); + } else { queue_work(kpcitest_workqueue, &epf_test->cmd_handler.work); + } return 0; } @@ -575,7 +583,6 @@ static int pci_epf_test_probe(struct pci_epf *epf) static struct pci_epf_ops ops = { .unbind = pci_epf_test_unbind, .bind = pci_epf_test_bind, - .linkup = pci_epf_test_linkup, }; static struct pci_epf_driver test_driver = { diff --git a/drivers/pci/endpoint/pci-epc-core.c b/drivers/pci/endpoint/pci-epc-core.c index e4712a0f249c..80831a874dbd 100644 --- a/drivers/pci/endpoint/pci-epc-core.c +++ b/drivers/pci/endpoint/pci-epc-core.c @@ -538,16 +538,10 @@ EXPORT_SYMBOL_GPL(pci_epc_remove_epf); */ void pci_epc_linkup(struct pci_epc *epc) { - unsigned long flags; - struct pci_epf *epf; - if (!epc || IS_ERR(epc)) return; - spin_lock_irqsave(&epc->lock, flags); - list_for_each_entry(epf, &epc->pci_epf, list) - pci_epf_linkup(epf); - spin_unlock_irqrestore(&epc->lock, flags); + atomic_notifier_call_chain(&epc->notifier, 0, NULL); } EXPORT_SYMBOL_GPL(pci_epc_linkup); @@ -611,6 +605,7 @@ __pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, spin_lock_init(&epc->lock); INIT_LIST_HEAD(&epc->pci_epf); + ATOMIC_INIT_NOTIFIER_HEAD(&epc->notifier); device_initialize(&epc->dev); epc->dev.class = pci_epc_class; diff --git a/drivers/pci/endpoint/pci-epf-core.c b/drivers/pci/endpoint/pci-epf-core.c index fb1306de8f40..93f28c65ace0 100644 --- a/drivers/pci/endpoint/pci-epf-core.c +++ b/drivers/pci/endpoint/pci-epf-core.c @@ -20,26 +20,6 @@ static DEFINE_MUTEX(pci_epf_mutex); static struct bus_type pci_epf_bus_type; static const struct device_type pci_epf_type; -/** - * pci_epf_linkup() - Notify the function driver that EPC device has - * established a connection with the Root Complex. - * @epf: the EPF device bound to the EPC device which has established - * the connection with the host - * - * Invoke to notify the function driver that EPC device has established - * a connection with the Root Complex. - */ -void pci_epf_linkup(struct pci_epf *epf) -{ - if (!epf->driver) { - dev_WARN(&epf->dev, "epf device not bound to driver\n"); - return; - } - - epf->driver->ops->linkup(epf); -} -EXPORT_SYMBOL_GPL(pci_epf_linkup); - /** * pci_epf_unbind() - Notify the function driver that the binding between the * EPF device and EPC device has been lost @@ -214,7 +194,7 @@ int __pci_epf_register_driver(struct pci_epf_driver *driver, if (!driver->ops) return -EINVAL; - if (!driver->ops->bind || !driver->ops->unbind || !driver->ops->linkup) + if (!driver->ops->bind || !driver->ops->unbind) return -EINVAL; driver->driver.bus = &pci_epf_bus_type; diff --git a/include/linux/pci-epc.h b/include/linux/pci-epc.h index f641badc2c61..834dfc00aa00 100644 --- a/include/linux/pci-epc.h +++ b/include/linux/pci-epc.h @@ -89,6 +89,7 @@ struct pci_epc_mem { * @max_functions: max number of functions that can be configured in this EPC * @group: configfs group representing the PCI EPC device * @lock: spinlock to protect pci_epc ops + * @notifier: used to notify EPF of any EPC events (like linkup) */ struct pci_epc { struct device dev; @@ -99,6 +100,7 @@ struct pci_epc { struct config_group *group; /* spinlock to protect against concurrent access of EP controller */ spinlock_t lock; + struct atomic_notifier_head notifier; }; /** @@ -141,6 +143,12 @@ static inline void *epc_get_drvdata(struct pci_epc *epc) return dev_get_drvdata(&epc->dev); } +static inline int +pci_epc_register_notifier(struct pci_epc *epc, struct notifier_block *nb) +{ + return atomic_notifier_chain_register(&epc->notifier, nb); +} + struct pci_epc * __devm_pci_epc_create(struct device *dev, const struct pci_epc_ops *ops, struct module *owner); diff --git a/include/linux/pci-epf.h b/include/linux/pci-epf.h index 2d6f07556682..4993f7f6439b 100644 --- a/include/linux/pci-epf.h +++ b/include/linux/pci-epf.h @@ -55,13 +55,10 @@ struct pci_epf_header { * @bind: ops to perform when a EPC device has been bound to EPF device * @unbind: ops to perform when a binding has been lost between a EPC device * and EPF device - * @linkup: ops to perform when the EPC device has established a connection with - * a host system */ struct pci_epf_ops { int (*bind)(struct pci_epf *epf); void (*unbind)(struct pci_epf *epf); - void (*linkup)(struct pci_epf *epf); }; /** @@ -112,6 +109,7 @@ struct pci_epf_bar { * @epc: the EPC device to which this EPF device is bound * @driver: the EPF driver to which this EPF device is bound * @list: to add pci_epf as a list of PCI endpoint functions to pci_epc + * @nb: notifier block to notify EPF of any EPC events (like linkup) */ struct pci_epf { struct device dev; @@ -125,6 +123,7 @@ struct pci_epf { struct pci_epc *epc; struct pci_epf_driver *driver; struct list_head list; + struct notifier_block nb; }; #define to_pci_epf(epf_dev) container_of((epf_dev), struct pci_epf, dev) @@ -154,5 +153,4 @@ void *pci_epf_alloc_space(struct pci_epf *epf, size_t size, enum pci_barno bar, void pci_epf_free_space(struct pci_epf *epf, void *addr, enum pci_barno bar); int pci_epf_bind(struct pci_epf *epf); void pci_epf_unbind(struct pci_epf *epf); -void pci_epf_linkup(struct pci_epf *epf); #endif /* __LINUX_PCI_EPF_H */ From patchwork Tue Jun 4 13:15:05 2019 Content-Type: text/plain; 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Add support to link a physical function to a virtual function in pci-ep-cfs. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/endpoint/pci-ep-cfs.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) -- 2.17.1 diff --git a/drivers/pci/endpoint/pci-ep-cfs.c b/drivers/pci/endpoint/pci-ep-cfs.c index e7e8367eead1..c18ef626ada5 100644 --- a/drivers/pci/endpoint/pci-ep-cfs.c +++ b/drivers/pci/endpoint/pci-ep-cfs.c @@ -350,6 +350,28 @@ static struct configfs_attribute *pci_epf_attrs[] = { NULL, }; +static int pci_epf_vepf_link(struct config_item *epf_pf_item, + struct config_item *epf_vf_item) +{ + struct pci_epf_group *epf_vf_group = to_pci_epf_group(epf_vf_item); + struct pci_epf_group *epf_pf_group = to_pci_epf_group(epf_pf_item); + struct pci_epf *epf_pf = epf_pf_group->epf; + struct pci_epf *epf_vf = epf_vf_group->epf; + + return pci_epf_add_vepf(epf_pf, epf_vf); +} + +static void pci_epf_vepf_unlink(struct config_item *epf_pf_item, + struct config_item *epf_vf_item) +{ + struct pci_epf_group *epf_vf_group = to_pci_epf_group(epf_vf_item); + struct pci_epf_group *epf_pf_group = to_pci_epf_group(epf_pf_item); + struct pci_epf *epf_pf = epf_pf_group->epf; + struct pci_epf *epf_vf = epf_vf_group->epf; + + pci_epf_remove_vepf(epf_pf, epf_vf); +} + static void pci_epf_release(struct config_item *item) { struct pci_epf_group *epf_group = to_pci_epf_group(item); @@ -362,6 +384,8 @@ static void pci_epf_release(struct config_item *item) } static struct configfs_item_operations pci_epf_ops = { + .allow_link = pci_epf_vepf_link, + .drop_link = pci_epf_vepf_unlink, .release = pci_epf_release, }; From patchwork Tue Jun 4 13:15:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165782 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5844231ili; Tue, 4 Jun 2019 06:19:02 -0700 (PDT) X-Google-Smtp-Source: APXvYqzK4TYIpxLaUMHzWZziLLB60D7mmQDFIpvoOGElPYlpwDsNEKR1JldRqnC5Vlusj2hxzxWs X-Received: by 2002:a17:902:b497:: with SMTP id y23mr12548479plr.309.1559654342142; Tue, 04 Jun 2019 06:19:02 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654342; cv=none; d=google.com; s=arc-20160816; b=a/oMHox6f/4ZEdb10GK3e46v4XRkSET6Bh6lU9NYABWrxRaaBO0NLY7/N3OcofvJU6 YuKbPb8EeCuAd1emE8MGYvp1RWrTKMiLFwXMIFJ+lOEmzVJgkR5N7T0huS6ms74Umogj wev79bCULuAjmVft6cXgKj4zw4stcHDtg9TLM2cACyabtfYbGqxmwmaUnbd1Eg9dvfee zQ/W9I0rJVSu2w051FTd+GMvGFe7dKGRRJ/7kuaT0ArdjOVPYHHaeUNUSX4G9XWfw/m8 QqqGHf9Ivkn6CoXuDKRmGIyd6w+a4T/gjA5nNuUAd/z1z/DCMbyRYeAzFJwjSIbWqJDZ b8vQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=A1e4i3JXTGF5KqEnqJblhBzQo0a5PhT1C6gt15QrFqM=; b=UhtCD+vpDmV2qTJ8lss0YQtSsIs3CCY+PgHmiBiGrGPuWJYOxYMrKXUatKBC6EY4JF RfGLX5+q4AEQ6Yc9M2Tln2yV2PgtdEb4frE7vDgo2xZdfGw9L7jtHdhSL+laPh1lH/Wu nTqv6kgsALWe0ERGMb+tLEumwHICG/aNmxHivVJk4rzVdVnjTnj3P+ItvW33MB7Q6tal 5PR36qTG05Rs/uycmczi8mcjiqgR2yrIF+ZizR4Lqgsvmqb7u+nRDAPnSX2oIZXx2jYj E+UFy1VC92MTknbbl0Mq60dCNOfyc6/euK/smxRIMb8PbMWxCc9qF8xVvXFqi+4nMjm8 Qonw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KEFWasOi; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id y17si23614882pfl.172.2019.06.04.06.19.01; Tue, 04 Jun 2019 06:19:02 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=KEFWasOi; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727843AbfFDNTB (ORCPT + 8 others); Tue, 4 Jun 2019 09:19:01 -0400 Received: from fllv0015.ext.ti.com ([198.47.19.141]:55094 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727381AbfFDNTA (ORCPT ); Tue, 4 Jun 2019 09:19:00 -0400 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DIlQV028229; Tue, 4 Jun 2019 08:18:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654327; bh=A1e4i3JXTGF5KqEnqJblhBzQo0a5PhT1C6gt15QrFqM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=KEFWasOiIKb8vqmQe82XGw9RwsDQAOM9j+AmROXwTFSQODUVNDgZrKFM+Q/wYkfMN aMC5++WST/g4Y/LAl7colTxb5MX0VeH4+/ldbUS/mhwYKUyU5HP1URDqe4+t4tDPtq dNFjjWVS5DmERnQ2PcM0zlqNkK1cQ9GO/J6xrTz8= Received: from DFLE101.ent.ti.com (dfle101.ent.ti.com [10.64.6.22]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DIlLx009840 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:18:47 -0500 Received: from DFLE113.ent.ti.com (10.64.6.34) by DFLE101.ent.ti.com (10.64.6.22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:18:47 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:18:47 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGc098972; Tue, 4 Jun 2019 08:18:42 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I Subject: [RFC PATCH 22/30] PCI: cadence: Configure pci_epc_features to align BAR addresses to 256 Bytes Date: Tue, 4 Jun 2019 18:45:08 +0530 Message-ID: <20190604131516.13596-23-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Cadence PCIe controller has BITS[7:0] of the Inbound Address Translation Units AXI address reserved for special purpose. In order to accommodate this constraint, BAR addresses should be aligned to 256 Byte addresses. Configure pci_epc_features to align BAR addresses to 256 Bytes here. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/pcie-cadence-ep.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/pci/controller/pcie-cadence-ep.c b/drivers/pci/controller/pcie-cadence-ep.c index 3dc1a896c1e6..25638af7c668 100644 --- a/drivers/pci/controller/pcie-cadence-ep.c +++ b/drivers/pci/controller/pcie-cadence-ep.c @@ -484,6 +484,7 @@ static const struct pci_epc_features cdns_pcie_epc_features = { .linkup_notifier = false, .msi_capable = true, .msix_capable = false, + .align = 256, }; static const struct pci_epc_features cdns_pcie_epc_vf_features = { From patchwork Tue Jun 4 13:15:11 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165786 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5844648ili; Tue, 4 Jun 2019 06:19:19 -0700 (PDT) X-Google-Smtp-Source: APXvYqzJYXvH4suBMVBmpl0gIioBWI/h61ZYDWJh3RpOEk6wWx/2xI8TTGxepPPmNEip583yhBbF X-Received: by 2002:a17:902:7c03:: with SMTP id x3mr11568563pll.242.1559654359643; Tue, 04 Jun 2019 06:19:19 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654359; cv=none; d=google.com; s=arc-20160816; b=hHEFcggWQt7o04rD3V4uDtgnTWR6/vNjacKLFkMKMiXL09mTGSNsGbAiMsHkxvog7C aM814zyCvkN4S9xr8H1VeQ+Fw1+Yq9VvOcV4QOtuklcGZLJ/5gLYUo4VdxQxpwuj/wmi BIeWaTB7Uy1V+q+zigWXox2SMyJkwvrDZnNc4AtLreGPNPBMuGGjnonWK93RV0mO4d+h 75F+d00s+t8/sAB+Jcc7fCnPhjKwd6+ffScFZnq0j/XIrcpflrS8l0Vu+TWE+gF16huL o8EVU7pd03gedreEwxhkiigbrc7YU9QkZHLaTCAyZcVpuLlCH+jPOmEOhP63bpuuwcOV /n4g== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=lbZN64a/9tqoweyvK9hrm8rB5go5BK2+LZrXyh4Pjro=; b=zIzD5oJFZ2csomJ5fZRAFWXsEzQoywsyoDCxKmD6f+fpYAM/wIZtiYF4nVH7Un6YoM VwJdf/wlZJp1vAVOJMYdmribCztagAVLkz2UzD5jBAbjVCfkpoSAgjVKiioD18hZtR7r fVQs2SHGPwl48Ih7OJ4odFKjNf1g8HPfDn3gFB3BsMqZMEHcJ/5oRt6FttDLWoy5kBtA Z0bwQ4xuLYR52c9O8SENNkaeYwe0Rjcp/nEMxTTS7MrjZOUw+5L/zt5aTrD4QnIB2dys +x+6dNva3oo+megCAX3YZAvPoQpO/F77zOuTWNu8PlhKW9bj7pVW5UZOykIcieobuz2F mHJQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ZF58jGpQ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. [209.132.180.67]) by mx.google.com with ESMTP id b13si4955306pgk.19.2019.06.04.06.19.19; Tue, 04 Jun 2019 06:19:19 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=ZF58jGpQ; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727928AbfFDNTS (ORCPT + 8 others); Tue, 4 Jun 2019 09:19:18 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:35456 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727920AbfFDNTQ (ORCPT ); Tue, 4 Jun 2019 09:19:16 -0400 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DJ4cN092255; Tue, 4 Jun 2019 08:19:04 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654344; bh=lbZN64a/9tqoweyvK9hrm8rB5go5BK2+LZrXyh4Pjro=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=ZF58jGpQeMMKe5XC8XHueSfh/d5XfgdN9rZAUJVDoCiXKhFffVMZ/MI1tsM6gsgcf LArH2+g7M7cNNTHPWtBmKwMqvKwoojt4AAp4k+0cF3aB6L8Apdqj5Xz/KhgnEWoKA3 0beJetxBWfUxX1EBm2cQDn+kdeNN4I/IbgGStBuI= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DJ4dn003582 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:19:04 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:19:03 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:19:03 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGf098972; Tue, 4 Jun 2019 08:18:59 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I Subject: [RFC PATCH 25/30] PCI: j721e: Add TI J721E PCIe driver Date: Tue, 4 Jun 2019 18:45:11 +0530 Message-ID: <20190604131516.13596-26-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add support for PCIe controller in J721E SoC. The controller uses the Cadence PCIe core programmed by pcie-cadence*.c. The PCIe controller will work in both host mode and device mode. Some of the features of the controller are: *) Supports both RC mode and EP mode *) Supports Legacy, MSI and MSI-X support *) Supports upto GEN4 speed mode *) Supports SR-IOV *) Ability to route all transactions via SMMU The J721E PCIe wrapper has VMAP block which should be configured for routing all transactions via SMMU. Add j721e_pcie_quirk() which gets invoked whenever a new PCIe device is registered and configures the VMAP block. Signed-off-by: Kishon Vijay Abraham I --- drivers/pci/controller/Kconfig | 9 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pci-j721e.c | 431 +++++++++++++++++++++++++++++ 3 files changed, 441 insertions(+) create mode 100644 drivers/pci/controller/pci-j721e.c -- 2.17.1 diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 011c57cae4b0..f706aa940f18 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -50,6 +50,15 @@ config PCIE_CADENCE_EP endmenu +config PCI_J721E + bool "J721E PCIe host controller using Cadence PCIe core" + depends on PCIE_CADENCE + help + Say Y here if you want to support the J721E PCIe controller in host + mode or device mode. This PCIe controller uses the Cadence PCIe core. + This driver also handles legacy interrupts when operating in host + mode. + config PCIE_XILINX_NWL bool "NWL PCIe Core" depends on ARCH_ZYNQMP || COMPILE_TEST diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makefile index d56a507495c5..9fdefff5283c 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_PCIE_CADENCE) += pcie-cadence.o obj-$(CONFIG_PCIE_CADENCE_HOST) += pcie-cadence-host.o obj-$(CONFIG_PCIE_CADENCE_EP) += pcie-cadence-ep.o +obj-$(CONFIG_PCI_J721E) += pci-j721e.o obj-$(CONFIG_PCI_FTPCI100) += pci-ftpci100.o obj-$(CONFIG_PCI_HYPERV) += pci-hyperv.o obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o diff --git a/drivers/pci/controller/pci-j721e.c b/drivers/pci/controller/pci-j721e.c new file mode 100644 index 000000000000..712cc6a2dd41 --- /dev/null +++ b/drivers/pci/controller/pci-j721e.c @@ -0,0 +1,431 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * pci-j721e - PCIe controller driver for TI's J721E SoCs + * + * Copyright (C) 2018-2019 Texas Instruments Incorporated - http://www.ti.com + * + * Author: Kishon Vijay Abraham I + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "../pci.h" +#include "pcie-cadence.h" + +#define J721E_PCIE_USER_CMD_STATUS 0x4 +#define LINK_TRAINING_ENABLE BIT(0) + +#define J721E_PCIE_USER_LINKSTATUS 0x14 +#define LINK_STATUS GENMASK(1, 0) +enum link_status { + NO_RECIEVERS_DETECTED, + LINK_TRAINING_IN_PROGRESS, + LINK_UP_DL_IN_PROGRESS, + LINK_UP_DL_COMPLETED, +}; + +#define J721E_TRANS_CTRL(a) ((a) * 0xc) +#define J721E_TRANS_REQ_ID(a) (((a) * 0xc) + 0x4) +#define J721E_TRANS_VIRT_ID(a) (((a) * 0xc) + 0x8) + +#define J721E_REQID_MASK 0xffff +#define J721E_REQID_SHIFT 16 + +#define J721E_EN BIT(0) +#define J721E_ATYPE_SHIFT 16 + +#define J721E_MODE_RC BIT(7) +#define LANE_COUNT_MASK BIT(8) +#define LANE_COUNT(n) ((n) << 8) + +#define GENERATION_SEL_MASK GENMASK(1, 0) + +#define MAX_LANES 2 + +enum j721e_atype { + PHYS_ADDR, + INT_ADDR, + VIRT_ADDR, + TRANS_ADDR, +}; + +#define to_j721e_pcie(x) container_of((x), struct j721e_pcie, plat_data) + +struct j721e_pcie { + struct device *dev; + struct device_node *node; + u32 mode; + u32 num_lanes; + struct cdns_pcie_plat_data plat_data; + void __iomem *intd_cfg_base; + void __iomem *user_cfg_base; + void __iomem *vmap_lp_base; + u8 vmap_lp_index; + bool enable_smmu; +}; + +static inline u32 j721e_pcie_vmap_readl(struct j721e_pcie *pcie, u32 offset) +{ + return readl(pcie->vmap_lp_base + offset); +} + +static inline void j721e_pcie_vmap_writel(struct j721e_pcie *pcie, u32 offset, + u32 value) +{ + writel(value, pcie->vmap_lp_base + offset); +} + +static inline u32 j721e_pcie_intd_readl(struct j721e_pcie *pcie, u32 offset) +{ + return readl(pcie->intd_cfg_base + offset); +} + +static inline void j721e_pcie_intd_writel(struct j721e_pcie *pcie, u32 offset, + u32 value) +{ + writel(value, pcie->intd_cfg_base + offset); +} + +static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) +{ + return readl(pcie->user_cfg_base + offset); +} + +static inline void j721e_pcie_user_writel(struct j721e_pcie *pcie, u32 offset, + u32 value) +{ + writel(value, pcie->user_cfg_base + offset); +} + +static void j721e_pcie_quirk(struct pci_dev *pci_dev) +{ + struct pci_bus *root_bus; + struct pci_dev *bridge; + struct j721e_pcie *pcie; + struct pci_bus *bus; + struct device *dev; + int index; + u32 val; + + static const struct pci_device_id rc_pci_devids[] = { + { PCI_DEVICE(0x104c, 0xb00d), + .class = PCI_CLASS_BRIDGE_PCI << 8, .class_mask = ~0, }, + { 0, }, + }; + + dev = pci_get_host_bridge_device(pci_dev); + pcie = dev_get_drvdata(dev->parent->parent); + bus = pci_dev->bus; + index = pcie->vmap_lp_index; + + if (!pcie->enable_smmu) + return; + + if (index >= 32) + return; + + if (pci_is_root_bus(bus)) + return; + + root_bus = bus; + while (!pci_is_root_bus(root_bus)) { + bridge = root_bus->self; + root_bus = root_bus->parent; + } + + if (pci_match_id(rc_pci_devids, bridge)) { + val = J721E_REQID_MASK << J721E_REQID_SHIFT | + (bus->number << 8 | pci_dev->devfn); + j721e_pcie_vmap_writel(pcie, J721E_TRANS_REQ_ID(index), val); + val = VIRT_ADDR << J721E_ATYPE_SHIFT; + j721e_pcie_vmap_writel(pcie, J721E_TRANS_VIRT_ID(index), val); + j721e_pcie_vmap_writel(pcie, J721E_TRANS_CTRL(index), J721E_EN); + } + + pcie->vmap_lp_index++; +} +DECLARE_PCI_FIXUP_ENABLE(PCI_ANY_ID, PCI_ANY_ID, j721e_pcie_quirk); + +static int j721e_pcie_start_link(struct cdns_pcie_plat_data *data, bool start) +{ + struct j721e_pcie *pcie = to_j721e_pcie(data); + u32 reg; + + reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_CMD_STATUS); + if (start) + reg |= LINK_TRAINING_ENABLE; + else + reg &= ~LINK_TRAINING_ENABLE; + j721e_pcie_user_writel(pcie, J721E_PCIE_USER_CMD_STATUS, reg); + + return 0; +} + +static bool j721e_pcie_is_link_up(struct cdns_pcie_plat_data *data) +{ + struct j721e_pcie *pcie = to_j721e_pcie(data); + u32 reg; + + reg = j721e_pcie_user_readl(pcie, J721E_PCIE_USER_LINKSTATUS); + reg &= LINK_STATUS; + if (reg == LINK_UP_DL_COMPLETED) + return true; + + return false; +} + +static int j721e_pcie_set_mode(struct j721e_pcie *pcie, struct regmap *syscon) +{ + struct device *dev = pcie->dev; + u32 mask = J721E_MODE_RC; + u32 mode = pcie->mode; + u32 val = 0; + int ret = 0; + + if (mode == PCI_MODE_RC) + val = J721E_MODE_RC; + + ret = regmap_update_bits(syscon, 0, mask, val); + if (ret) + dev_err(dev, "failed to set pcie mode\n"); + + return ret; +} + +static int j721e_pcie_set_link_speed(struct j721e_pcie *pcie, + struct regmap *syscon) +{ + struct device *dev = pcie->dev; + struct device_node *np = dev->of_node; + int link_speed; + u32 val = 0; + int ret; + + link_speed = of_pci_get_max_link_speed(np); + if (link_speed < 2) + link_speed = 2; + + val = link_speed - 1; + ret = regmap_update_bits(syscon, 0, GENERATION_SEL_MASK, val); + if (ret) + dev_err(dev, "failed to set link speed\n"); + + return ret; +} + +static int j721e_pcie_set_lane_count(struct j721e_pcie *pcie, + struct regmap *syscon) +{ + struct device *dev = pcie->dev; + u32 lanes = pcie->num_lanes; + u32 val = 0; + int ret; + + val = LANE_COUNT(lanes - 1); + ret = regmap_update_bits(syscon, 0, LANE_COUNT_MASK, val); + if (ret) + dev_err(dev, "failed to set link count\n"); + + return ret; +} + +static int j721e_pcie_ctrl_init(struct j721e_pcie *pcie) +{ + struct device *dev = pcie->dev; + struct device_node *node = dev->of_node; + struct regmap *syscon; + int ret; + + syscon = syscon_regmap_lookup_by_phandle(node, "ti,syscon-pcie-ctrl"); + if (IS_ERR(syscon)) { + dev_err(dev, "Unable to get ti,syscon-pcie-ctrl regmap\n"); + return PTR_ERR(syscon); + } + + ret = j721e_pcie_set_mode(pcie, syscon); + if (ret < 0) { + dev_err(dev, "Failed to set pci mode\n"); + return ret; + } + + ret = j721e_pcie_set_link_speed(pcie, syscon); + if (ret < 0) { + dev_err(dev, "Failed to set link speed\n"); + return ret; + } + + ret = j721e_pcie_set_lane_count(pcie, syscon); + if (ret < 0) { + dev_err(dev, "Failed to set num-lanes\n"); + return ret; + } + + return 0; +} + +static const struct of_device_id of_j721e_pcie_match[] = { + { + .compatible = "ti,j721e-pcie", + }, + {}, +}; + +static int j721e_pcie_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + struct device_node *node = dev->of_node; + struct cdns_pcie_plat_data *plat_data; + struct platform_device *platform_dev; + struct device_node *child_node; + struct j721e_pcie *pcie; + struct resource *res; + void __iomem *base; + u32 num_lanes; + u32 mode; + int ret; + + pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); + if (!pcie) + return -ENOMEM; + + pcie->dev = dev; + pcie->node = node; + plat_data = &pcie->plat_data; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intd_cfg"); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + pcie->intd_cfg_base = base; + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "user_cfg"); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + return PTR_ERR(base); + pcie->user_cfg_base = base; + + plat_data->start_link = j721e_pcie_start_link; + plat_data->is_link_up = j721e_pcie_is_link_up; + + ret = of_property_read_u32(node, "pci-mode", &mode); + if (ret < 0) { + dev_err(dev, "Failed to get pci-mode binding\n"); + return ret; + } + pcie->mode = mode; + + ret = of_property_read_u32(node, "num-lanes", &num_lanes); + if (ret || num_lanes > MAX_LANES) + num_lanes = 1; + pcie->num_lanes = num_lanes; + + dev_set_drvdata(dev, pcie); + pm_runtime_enable(dev); + ret = pm_runtime_get_sync(dev); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; + } + + ret = j721e_pcie_ctrl_init(pcie); + if (ret < 0) { + dev_err(dev, "pm_runtime_get_sync failed\n"); + goto err_get_sync; + } + + switch (mode) { + case PCI_MODE_RC: + if (!IS_ENABLED(CONFIG_PCIE_CADENCE_HOST)) { + ret = -ENODEV; + goto err_get_sync; + } + + res = platform_get_resource_byname(pdev, IORESOURCE_MEM, + "vmap"); + base = devm_ioremap_resource(dev, res); + if (IS_ERR(base)) + goto err_get_sync; + pcie->vmap_lp_base = base; + + child_node = of_get_child_by_name(node, "pcie"); + if (!child_node) { + dev_WARN(dev, "pcie-rc node is absent\n"); + goto err_get_sync; + } + + if (of_property_read_bool(child_node, "iommu-map")) + pcie->enable_smmu = true; + + platform_dev = of_platform_device_create_pdata(child_node, NULL, + plat_data, dev); + if (!platform_dev) { + ret = -ENODEV; + dev_err(dev, "Failed to create Cadence RC device\n"); + goto err_get_sync; + } + + break; + case PCI_MODE_EP: + if (!IS_ENABLED(CONFIG_PCIE_CADENCE_EP)) { + ret = -ENODEV; + goto err_get_sync; + } + + child_node = of_get_child_by_name(node, "pcie-ep"); + if (!child_node) { + dev_WARN(dev, "pcie-ep node is absent\n"); + goto err_get_sync; + } + + platform_dev = of_platform_device_create_pdata(child_node, NULL, + plat_data, dev); + if (!platform_dev) { + ret = -ENODEV; + dev_err(dev, "Failed to create Cadence EP device\n"); + goto err_get_sync; + } + + break; + default: + dev_err(dev, "INVALID device type %d\n", mode); + } + + return 0; + +err_get_sync: + pm_runtime_put(dev); + pm_runtime_disable(dev); + + return ret; +} + +static int j721e_pcie_remove(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + + pm_runtime_put(dev); + pm_runtime_disable(dev); + of_platform_depopulate(dev); + + return 0; +} + +static struct platform_driver j721e_pcie_driver = { + .probe = j721e_pcie_probe, + .remove = j721e_pcie_remove, + .driver = { + .name = "j721e-pcie", + .of_match_table = of_j721e_pcie_match, + .suppress_bind_attrs = true, + }, +}; +builtin_platform_driver(j721e_pcie_driver); From patchwork Tue Jun 4 13:15:14 2019 Content-Type: text/plain; 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[209.132.180.67]) by mx.google.com with ESMTP id g95si23469850pje.41.2019.06.04.06.20.18; Tue, 04 Jun 2019 06:20:18 -0700 (PDT) Received-SPF: pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) client-ip=209.132.180.67; Authentication-Results: mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=gQFje2xL; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727530AbfFDNUS (ORCPT + 8 others); Tue, 4 Jun 2019 09:20:18 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:35648 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727153AbfFDNUR (ORCPT ); Tue, 4 Jun 2019 09:20:17 -0400 Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x54DJLQF092301; Tue, 4 Jun 2019 08:19:21 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1559654361; bh=wpR76pUQZD8qw+8R4/pRwOkQY9ta5s2pKOPuv5GPy44=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gQFje2xLV6IMR3s1mQL6R8PIVlNv//UIzSUzajaVG+d2jd1GH1XFlYZVEW+KPGA/s aACev+SCMDgAv7roiJxX92r9dpX0CyGcgKW8yfLIq/jgxvXnrnwwD/cEMvZh1e3DrU 6S1frA2Wewxa2WnxVF+7qAtUZUxam6eAunZ2d4z0= Received: from DFLE105.ent.ti.com (dfle105.ent.ti.com [10.64.6.26]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x54DJLtD054916 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Jun 2019 08:19:21 -0500 Received: from DFLE114.ent.ti.com (10.64.6.35) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Tue, 4 Jun 2019 08:19:20 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Tue, 4 Jun 2019 08:19:20 -0500 Received: from a0393678ub.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id x54DGdGi098972; Tue, 4 Jun 2019 08:19:15 -0500 From: Kishon Vijay Abraham I To: Tom Joseph , Bjorn Helgaas , Rob Herring , Mark Rutland , Lorenzo Pieralisi , Arnd Bergmann , Gustavo Pimentel CC: Greg Kroah-Hartman , Frank Rowand , Jingoo Han , , , , , , , Kishon Vijay Abraham I Subject: [RFC PATCH 28/30] misc: pci_endpoint_test: Avoid using module parameter to determine irqtype Date: Tue, 4 Jun 2019 18:45:14 +0530 Message-ID: <20190604131516.13596-29-kishon@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20190604131516.13596-1-kishon@ti.com> References: <20190604131516.13596-1-kishon@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org commit e03327122e2c8e6ae4565ef ("pci_endpoint_test: Add 2 ioctl commands") uses module parameter in pci_endpoint_test_set_irq() 'irqtype' to check if irq vectors of a particular type is already allocated. However with multi-function devices, irqtype will not correctly reflect the irq type of the PCI device. Fix it here by adding 'irqtype' for each PCI device to shows the irq type of that particular PCI device. Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) -- 2.17.1 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 98a60f4d45a1..632c76e33e4e 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -110,6 +110,7 @@ struct pci_endpoint_test { struct completion irq_raised; int last_irq; int num_irqs; + int irq_type; /* mutex to protect the ioctls */ struct mutex mutex; struct miscdevice miscdev; @@ -169,6 +170,7 @@ static void pci_endpoint_test_free_irq_vectors(struct pci_endpoint_test *test) struct pci_dev *pdev = test->pdev; pci_free_irq_vectors(pdev); + test->irq_type = IRQ_TYPE_UNDEFINED; } static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test, @@ -203,6 +205,8 @@ static bool pci_endpoint_test_alloc_irq_vectors(struct pci_endpoint_test *test, irq = 0; res = false; } + + test->irq_type = type; test->num_irqs = irq; return res; @@ -342,6 +346,7 @@ static bool pci_endpoint_test_copy(struct pci_endpoint_test *test, size_t size) dma_addr_t orig_dst_phys_addr; size_t offset; size_t alignment = test->alignment; + int irq_type = test->irq_type; u32 src_crc32; u32 dst_crc32; @@ -438,6 +443,7 @@ static bool pci_endpoint_test_write(struct pci_endpoint_test *test, size_t size) dma_addr_t orig_phys_addr; size_t offset; size_t alignment = test->alignment; + int irq_type = test->irq_type; u32 crc32; if (size > SIZE_MAX - alignment) @@ -506,6 +512,7 @@ static bool pci_endpoint_test_read(struct pci_endpoint_test *test, size_t size) dma_addr_t orig_phys_addr; size_t offset; size_t alignment = test->alignment; + int irq_type = test->irq_type; u32 crc32; if (size > SIZE_MAX - alignment) @@ -567,7 +574,7 @@ static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test, return false; } - if (irq_type == req_irq_type) + if (test->irq_type == req_irq_type) return true; pci_endpoint_test_release_irq(test); @@ -579,12 +586,10 @@ static bool pci_endpoint_test_set_irq(struct pci_endpoint_test *test, if (!pci_endpoint_test_request_irq(test)) goto err; - irq_type = req_irq_type; return true; err: pci_endpoint_test_free_irq_vectors(test); - irq_type = IRQ_TYPE_UNDEFINED; return false; } From patchwork Tue Jun 4 13:15:15 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165794 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5846267ili; Tue, 4 Jun 2019 06:20:31 -0700 (PDT) X-Google-Smtp-Source: APXvYqw5Y5fikjxKfhZtp6WhCG+nbcyuEP5q/oyVtY5Nfc8xNtYONgssPE9QU66x6v5X4oDy43cQ X-Received: by 2002:a17:902:74c4:: with SMTP id f4mr14709435plt.316.1559654431728; Tue, 04 Jun 2019 06:20:31 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654431; cv=none; d=google.com; s=arc-20160816; b=XtD7m2WXKqNDoxz9s6/ioNcRSMNj/icRHy2HY8/A1gsrDCSZ7skXSj4t8NgT53jX3d fOBOEpBPGev3GEhaFiNFnz3tw0l+4AX6v2YWy3c7JbZ+eSiDivFuL9K/byk+pxz3uV6D Elc8bfeEG57h38lY5YiShXXai4fSMIMS7GwaR49QTPMlcb2xVOBpCD/0nd2kZ8lVJCOk jDEBkHuGJOd4524rsPv1luNCjSv6RHfkslSJVLzmzQBwINI/cvBHjeqRsXGxjS2camhe kQoC2hJn78r7kdwBvRkUnbPF4Z1iy4nXjpES5TapqnueuqJxFdQwXKLNNg242hK08ls1 3n2Q== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=z+jOFbWUICQUg7VhFo19RU//56pD+kVMLSTrx7kpCoI=; b=JwUdTiT+mJDGIbvUEXFwUmTuE61tBGUFgphwHZZW/I2lr+Tre4C//OFI8/SJhHp1r5 IgJsN2HWyks/tVOtO+nO1Jc8+qnI/hii3854BUIMYGW06WknSCWPjcwf+K9n+Sk89pFp 1v387La+nCLifaD4im8gAyC2248OveXYJaLUk0HiSAVroSG1NcLA/Dj39BJvVXKilmgS 1Jj4wF4+EmSQ2zv2HXgLeXOI30uxvoBVHC8w8s7y6DhcBfIfxEylrYuevbaJCcMPWncd ZOhseQmifGmgSpoe3wQzPWBNTrC1YQJR0MkHQO0R3TDJ94jOE0HwP+HlUvUQr8itj0Bu umYQ== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=lr2vxfwG; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 632c76e33e4e..2a6cd9e65e67 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -831,6 +831,7 @@ static struct pci_driver pci_endpoint_test_driver = { .id_table = pci_endpoint_test_tbl, .probe = pci_endpoint_test_probe, .remove = pci_endpoint_test_remove, + .sriov_configure = pci_sriov_configure_simple, }; module_pci_driver(pci_endpoint_test_driver); From patchwork Tue Jun 4 13:15:16 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kishon Vijay Abraham I X-Patchwork-Id: 165793 Delivered-To: patch@linaro.org Received: by 2002:a92:9e1a:0:0:0:0:0 with SMTP id q26csp5846114ili; Tue, 4 Jun 2019 06:20:23 -0700 (PDT) X-Google-Smtp-Source: APXvYqxRhw/0lVKu1d5j+SAryG3fFoE1fJo4Qo5xc89jexxVkVjry2dnTabGRq5UeWaYFyUcNaWK X-Received: by 2002:a17:902:8490:: with SMTP id c16mr37527728plo.259.1559654423380; Tue, 04 Jun 2019 06:20:23 -0700 (PDT) ARC-Seal: i=1; a=rsa-sha256; t=1559654423; cv=none; d=google.com; s=arc-20160816; b=WwlcxDiRK1fCqdqLR9swCVuZgUH2KxQX87XLbaS1zcoKAxeaPZsIDQ+eLk1s0B03Pm HABRa+3uTvJTtClhf2gmrJrnAD/tFgQjANtnN61NDd62dVOY3Ht4x69anAmQ2rCR7Swx 3HBFxoubkQmAe+pVUKMBE+u0WzuxLEROSHGjdhF8Em7Q0hQ1ozP9n9ar2NNlx/MHYxmG A4WsPSZPZl6Fh4nZUtY/Aw8WdTPnLgy2LR2GGHN2So1u+uIak5pXF/+VuBGDxiq+MUcK m8vbVqDNGoM9db0+XYGU/gIfYu5WgX4g4jHzNIdHiBqlw3ntGHTa+NO8eERmUrS7Nppf TjMQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=arc-20160816; h=list-id:precedence:sender:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:dkim-signature; bh=v8mkOQlj6ZUtE+6KavYFNHYT3JmxgtDfIA3TqfNwJt8=; b=gA87MSQgZy/9C8EgLvUCCh0gZiScZJDrlMEu15bNvUT5EVF0nbNIlRFvBXr8Y2y0LV S/yebhxbNftEToje7Gy5PnY2EEviz2LyCzckmbf2y9Ur8k0RV+AiLUZl5JRaPLbKB44j t5I1xlFfqylEE6q6NxJgw6PiZb6LTwgzQ7yk7Ql59GvpQsz8SNTiMu/gYSvOQdDly6aN eqQfthdkhcjRa2bRIM9yG5hq3OxdTXont6ZkHXPZWmiD17ZPYdvxOyJPim4fwBIgoVR5 mRvzIdpMaaDA2XYjFhSv82gg/KsGkJDWR+iwPFJjdwURBu633OF0937MEvrIqCg6YySG JVIw== ARC-Authentication-Results: i=1; mx.google.com; dkim=pass header.i=@ti.com header.s=ti-com-17Q1 header.b=JS7LGnlK; spf=pass (google.com: best guess record for domain of devicetree-owner@vger.kernel.org designates 209.132.180.67 as permitted sender) smtp.mailfrom=devicetree-owner@vger.kernel.org; dmarc=pass (p=QUARANTINE sp=NONE dis=NONE) header.from=ti.com Return-Path: Received: from vger.kernel.org (vger.kernel.org. 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Explicitly enable legacy interrupt here in order to perform legacy interrupt tests. Signed-off-by: Kishon Vijay Abraham I --- drivers/misc/pci_endpoint_test.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1 diff --git a/drivers/misc/pci_endpoint_test.c b/drivers/misc/pci_endpoint_test.c index 2a6cd9e65e67..e12a3845ad2e 100644 --- a/drivers/misc/pci_endpoint_test.c +++ b/drivers/misc/pci_endpoint_test.c @@ -697,6 +697,7 @@ static int pci_endpoint_test_probe(struct pci_dev *pdev, } pci_set_master(pdev); + pci_intx(pdev, true); if (!pci_endpoint_test_alloc_irq_vectors(test, irq_type)) goto err_disable_irq;